1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | // |
3 | // Copyright (c) 2009 Samsung Electronics Co., Ltd. |
4 | // Jaswinder Singh <jassi.brar@samsung.com> |
5 | |
6 | #include <linux/bitops.h> |
7 | #include <linux/bits.h> |
8 | #include <linux/clk.h> |
9 | #include <linux/delay.h> |
10 | #include <linux/dma-mapping.h> |
11 | #include <linux/dmaengine.h> |
12 | #include <linux/init.h> |
13 | #include <linux/interrupt.h> |
14 | #include <linux/io.h> |
15 | #include <linux/module.h> |
16 | #include <linux/of.h> |
17 | #include <linux/platform_data/spi-s3c64xx.h> |
18 | #include <linux/platform_device.h> |
19 | #include <linux/pm_runtime.h> |
20 | #include <linux/spi/spi.h> |
21 | #include <linux/types.h> |
22 | |
23 | #define MAX_SPI_PORTS 12 |
24 | #define S3C64XX_SPI_QUIRK_CS_AUTO (1 << 1) |
25 | #define AUTOSUSPEND_TIMEOUT 2000 |
26 | |
27 | /* Registers and bit-fields */ |
28 | |
29 | #define S3C64XX_SPI_CH_CFG 0x00 |
30 | #define S3C64XX_SPI_CLK_CFG 0x04 |
31 | #define S3C64XX_SPI_MODE_CFG 0x08 |
32 | #define S3C64XX_SPI_CS_REG 0x0C |
33 | #define S3C64XX_SPI_INT_EN 0x10 |
34 | #define S3C64XX_SPI_STATUS 0x14 |
35 | #define S3C64XX_SPI_TX_DATA 0x18 |
36 | #define S3C64XX_SPI_RX_DATA 0x1C |
37 | #define S3C64XX_SPI_PACKET_CNT 0x20 |
38 | #define S3C64XX_SPI_PENDING_CLR 0x24 |
39 | #define S3C64XX_SPI_SWAP_CFG 0x28 |
40 | #define S3C64XX_SPI_FB_CLK 0x2C |
41 | |
42 | #define S3C64XX_SPI_CH_HS_EN (1<<6) /* High Speed Enable */ |
43 | #define S3C64XX_SPI_CH_SW_RST (1<<5) |
44 | #define S3C64XX_SPI_CH_SLAVE (1<<4) |
45 | #define S3C64XX_SPI_CPOL_L (1<<3) |
46 | #define S3C64XX_SPI_CPHA_B (1<<2) |
47 | #define S3C64XX_SPI_CH_RXCH_ON (1<<1) |
48 | #define S3C64XX_SPI_CH_TXCH_ON (1<<0) |
49 | |
50 | #define S3C64XX_SPI_CLKSEL_SRCMSK (3<<9) |
51 | #define S3C64XX_SPI_CLKSEL_SRCSHFT 9 |
52 | #define S3C64XX_SPI_ENCLK_ENABLE (1<<8) |
53 | #define S3C64XX_SPI_PSR_MASK 0xff |
54 | |
55 | #define S3C64XX_SPI_MODE_CH_TSZ_BYTE (0<<29) |
56 | #define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD (1<<29) |
57 | #define S3C64XX_SPI_MODE_CH_TSZ_WORD (2<<29) |
58 | #define S3C64XX_SPI_MODE_CH_TSZ_MASK (3<<29) |
59 | #define S3C64XX_SPI_MODE_BUS_TSZ_BYTE (0<<17) |
60 | #define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD (1<<17) |
61 | #define S3C64XX_SPI_MODE_BUS_TSZ_WORD (2<<17) |
62 | #define S3C64XX_SPI_MODE_BUS_TSZ_MASK (3<<17) |
63 | #define S3C64XX_SPI_MODE_RX_RDY_LVL GENMASK(16, 11) |
64 | #define S3C64XX_SPI_MODE_RX_RDY_LVL_SHIFT 11 |
65 | #define S3C64XX_SPI_MODE_SELF_LOOPBACK (1<<3) |
66 | #define S3C64XX_SPI_MODE_RXDMA_ON (1<<2) |
67 | #define S3C64XX_SPI_MODE_TXDMA_ON (1<<1) |
68 | #define S3C64XX_SPI_MODE_4BURST (1<<0) |
69 | |
70 | #define S3C64XX_SPI_CS_NSC_CNT_2 (2<<4) |
71 | #define S3C64XX_SPI_CS_AUTO (1<<1) |
72 | #define S3C64XX_SPI_CS_SIG_INACT (1<<0) |
73 | |
74 | #define S3C64XX_SPI_INT_TRAILING_EN (1<<6) |
75 | #define S3C64XX_SPI_INT_RX_OVERRUN_EN (1<<5) |
76 | #define S3C64XX_SPI_INT_RX_UNDERRUN_EN (1<<4) |
77 | #define S3C64XX_SPI_INT_TX_OVERRUN_EN (1<<3) |
78 | #define S3C64XX_SPI_INT_TX_UNDERRUN_EN (1<<2) |
79 | #define S3C64XX_SPI_INT_RX_FIFORDY_EN (1<<1) |
80 | #define S3C64XX_SPI_INT_TX_FIFORDY_EN (1<<0) |
81 | |
82 | #define S3C64XX_SPI_ST_RX_FIFO_RDY_V2 GENMASK(23, 15) |
83 | #define S3C64XX_SPI_ST_TX_FIFO_RDY_V2 GENMASK(14, 6) |
84 | #define S3C64XX_SPI_ST_TX_FIFO_LVL_SHIFT 6 |
85 | #define S3C64XX_SPI_ST_RX_OVERRUN_ERR (1<<5) |
86 | #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR (1<<4) |
87 | #define S3C64XX_SPI_ST_TX_OVERRUN_ERR (1<<3) |
88 | #define S3C64XX_SPI_ST_TX_UNDERRUN_ERR (1<<2) |
89 | #define S3C64XX_SPI_ST_RX_FIFORDY (1<<1) |
90 | #define S3C64XX_SPI_ST_TX_FIFORDY (1<<0) |
91 | |
92 | #define S3C64XX_SPI_PACKET_CNT_EN (1<<16) |
93 | #define S3C64XX_SPI_PACKET_CNT_MASK GENMASK(15, 0) |
94 | |
95 | #define S3C64XX_SPI_PND_TX_UNDERRUN_CLR (1<<4) |
96 | #define S3C64XX_SPI_PND_TX_OVERRUN_CLR (1<<3) |
97 | #define S3C64XX_SPI_PND_RX_UNDERRUN_CLR (1<<2) |
98 | #define S3C64XX_SPI_PND_RX_OVERRUN_CLR (1<<1) |
99 | #define S3C64XX_SPI_PND_TRAILING_CLR (1<<0) |
100 | |
101 | #define S3C64XX_SPI_SWAP_RX_HALF_WORD (1<<7) |
102 | #define S3C64XX_SPI_SWAP_RX_BYTE (1<<6) |
103 | #define S3C64XX_SPI_SWAP_RX_BIT (1<<5) |
104 | #define S3C64XX_SPI_SWAP_RX_EN (1<<4) |
105 | #define S3C64XX_SPI_SWAP_TX_HALF_WORD (1<<3) |
106 | #define S3C64XX_SPI_SWAP_TX_BYTE (1<<2) |
107 | #define S3C64XX_SPI_SWAP_TX_BIT (1<<1) |
108 | #define S3C64XX_SPI_SWAP_TX_EN (1<<0) |
109 | |
110 | #define S3C64XX_SPI_FBCLK_MSK (3<<0) |
111 | |
112 | #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id]) |
113 | #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \ |
114 | (1 << (i)->port_conf->tx_st_done)) ? 1 : 0) |
115 | #define TX_FIFO_LVL(v, sdd) (((v) & (sdd)->tx_fifomask) >> \ |
116 | __ffs((sdd)->tx_fifomask)) |
117 | #define RX_FIFO_LVL(v, sdd) (((v) & (sdd)->rx_fifomask) >> \ |
118 | __ffs((sdd)->rx_fifomask)) |
119 | #define FIFO_DEPTH(i) ((FIFO_LVL_MASK(i) >> 1) + 1) |
120 | |
121 | #define S3C64XX_SPI_MAX_TRAILCNT 0x3ff |
122 | #define S3C64XX_SPI_TRAILCNT_OFF 19 |
123 | |
124 | #define S3C64XX_SPI_POLLING_SIZE 32 |
125 | |
126 | #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) |
127 | #define is_polling(x) (x->cntrlr_info->polling) |
128 | |
129 | #define RXBUSY (1<<2) |
130 | #define TXBUSY (1<<3) |
131 | |
132 | struct s3c64xx_spi_dma_data { |
133 | struct dma_chan *ch; |
134 | dma_cookie_t cookie; |
135 | enum dma_transfer_direction direction; |
136 | }; |
137 | |
138 | /** |
139 | * struct s3c64xx_spi_port_config - SPI Controller hardware info |
140 | * @fifo_lvl_mask: [DEPRECATED] use @{rx, tx}_fifomask instead. |
141 | * @rx_lvl_offset: [DEPRECATED] use @{rx,tx}_fifomask instead. |
142 | * @fifo_depth: depth of the FIFO. |
143 | * @rx_fifomask: SPI_STATUS.RX_FIFO_LVL mask. Shifted mask defining the field's |
144 | * length and position. |
145 | * @tx_fifomask: SPI_STATUS.TX_FIFO_LVL mask. Shifted mask defining the field's |
146 | * length and position. |
147 | * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter. |
148 | * @clk_div: Internal clock divider |
149 | * @quirks: Bitmask of known quirks |
150 | * @high_speed: True, if the controller supports HIGH_SPEED_EN bit. |
151 | * @clk_from_cmu: True, if the controller does not include a clock mux and |
152 | * prescaler unit. |
153 | * @clk_ioclk: True if clock is present on this device |
154 | * @has_loopback: True if loopback mode can be supported |
155 | * @use_32bit_io: True if the SoC allows only 32-bit register accesses. |
156 | * |
157 | * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but |
158 | * differ in some aspects such as the size of the fifo and spi bus clock |
159 | * setup. Such differences are specified to the driver using this structure |
160 | * which is provided as driver data to the driver. |
161 | */ |
162 | struct s3c64xx_spi_port_config { |
163 | int fifo_lvl_mask[MAX_SPI_PORTS]; |
164 | int rx_lvl_offset; |
165 | unsigned int fifo_depth; |
166 | u32 rx_fifomask; |
167 | u32 tx_fifomask; |
168 | int tx_st_done; |
169 | int quirks; |
170 | int clk_div; |
171 | bool high_speed; |
172 | bool clk_from_cmu; |
173 | bool clk_ioclk; |
174 | bool has_loopback; |
175 | bool use_32bit_io; |
176 | }; |
177 | |
178 | /** |
179 | * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver. |
180 | * @clk: Pointer to the spi clock. |
181 | * @src_clk: Pointer to the clock used to generate SPI signals. |
182 | * @ioclk: Pointer to the i/o clock between host and target |
183 | * @pdev: Pointer to device's platform device data |
184 | * @host: Pointer to the SPI Protocol host. |
185 | * @cntrlr_info: Platform specific data for the controller this driver manages. |
186 | * @lock: Controller specific lock. |
187 | * @state: Set of FLAGS to indicate status. |
188 | * @sfr_start: BUS address of SPI controller regs. |
189 | * @regs: Pointer to ioremap'ed controller registers. |
190 | * @xfer_completion: To indicate completion of xfer task. |
191 | * @cur_mode: Stores the active configuration of the controller. |
192 | * @cur_bpw: Stores the active bits per word settings. |
193 | * @cur_speed: Current clock speed |
194 | * @rx_dma: Local receive DMA data (e.g. chan and direction) |
195 | * @tx_dma: Local transmit DMA data (e.g. chan and direction) |
196 | * @port_conf: Local SPI port configuration data |
197 | * @port_id: [DEPRECATED] use @{rx,tx}_fifomask instead. |
198 | * @fifo_depth: depth of the FIFO. |
199 | * @rx_fifomask: SPI_STATUS.RX_FIFO_LVL mask. Shifted mask defining the field's |
200 | * length and position. |
201 | * @tx_fifomask: SPI_STATUS.TX_FIFO_LVL mask. Shifted mask defining the field's |
202 | * length and position. |
203 | */ |
204 | struct s3c64xx_spi_driver_data { |
205 | void __iomem *regs; |
206 | struct clk *clk; |
207 | struct clk *src_clk; |
208 | struct clk *ioclk; |
209 | struct platform_device *pdev; |
210 | struct spi_controller *host; |
211 | struct s3c64xx_spi_info *cntrlr_info; |
212 | spinlock_t lock; |
213 | unsigned long sfr_start; |
214 | struct completion xfer_completion; |
215 | unsigned state; |
216 | unsigned cur_mode, cur_bpw; |
217 | unsigned cur_speed; |
218 | struct s3c64xx_spi_dma_data rx_dma; |
219 | struct s3c64xx_spi_dma_data tx_dma; |
220 | const struct s3c64xx_spi_port_config *port_conf; |
221 | unsigned int port_id; |
222 | unsigned int fifo_depth; |
223 | u32 rx_fifomask; |
224 | u32 tx_fifomask; |
225 | }; |
226 | |
227 | static void s3c64xx_flush_fifo(struct s3c64xx_spi_driver_data *sdd) |
228 | { |
229 | void __iomem *regs = sdd->regs; |
230 | unsigned long loops; |
231 | u32 val; |
232 | |
233 | writel(val: 0, addr: regs + S3C64XX_SPI_PACKET_CNT); |
234 | |
235 | val = readl(addr: regs + S3C64XX_SPI_CH_CFG); |
236 | val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON); |
237 | writel(val, addr: regs + S3C64XX_SPI_CH_CFG); |
238 | |
239 | val = readl(addr: regs + S3C64XX_SPI_CH_CFG); |
240 | val |= S3C64XX_SPI_CH_SW_RST; |
241 | val &= ~S3C64XX_SPI_CH_HS_EN; |
242 | writel(val, addr: regs + S3C64XX_SPI_CH_CFG); |
243 | |
244 | /* Flush TxFIFO*/ |
245 | loops = msecs_to_loops(1); |
246 | do { |
247 | val = readl(addr: regs + S3C64XX_SPI_STATUS); |
248 | } while (TX_FIFO_LVL(val, sdd) && loops--); |
249 | |
250 | if (loops == 0) |
251 | dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n" ); |
252 | |
253 | /* Flush RxFIFO*/ |
254 | loops = msecs_to_loops(1); |
255 | do { |
256 | val = readl(addr: regs + S3C64XX_SPI_STATUS); |
257 | if (RX_FIFO_LVL(val, sdd)) |
258 | readl(addr: regs + S3C64XX_SPI_RX_DATA); |
259 | else |
260 | break; |
261 | } while (loops--); |
262 | |
263 | if (loops == 0) |
264 | dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n" ); |
265 | |
266 | val = readl(addr: regs + S3C64XX_SPI_CH_CFG); |
267 | val &= ~S3C64XX_SPI_CH_SW_RST; |
268 | writel(val, addr: regs + S3C64XX_SPI_CH_CFG); |
269 | |
270 | val = readl(addr: regs + S3C64XX_SPI_MODE_CFG); |
271 | val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON); |
272 | writel(val, addr: regs + S3C64XX_SPI_MODE_CFG); |
273 | } |
274 | |
275 | static void s3c64xx_spi_dmacb(void *data) |
276 | { |
277 | struct s3c64xx_spi_driver_data *sdd; |
278 | struct s3c64xx_spi_dma_data *dma = data; |
279 | unsigned long flags; |
280 | |
281 | if (dma->direction == DMA_DEV_TO_MEM) |
282 | sdd = container_of(data, |
283 | struct s3c64xx_spi_driver_data, rx_dma); |
284 | else |
285 | sdd = container_of(data, |
286 | struct s3c64xx_spi_driver_data, tx_dma); |
287 | |
288 | spin_lock_irqsave(&sdd->lock, flags); |
289 | |
290 | if (dma->direction == DMA_DEV_TO_MEM) { |
291 | sdd->state &= ~RXBUSY; |
292 | if (!(sdd->state & TXBUSY)) |
293 | complete(&sdd->xfer_completion); |
294 | } else { |
295 | sdd->state &= ~TXBUSY; |
296 | if (!(sdd->state & RXBUSY)) |
297 | complete(&sdd->xfer_completion); |
298 | } |
299 | |
300 | spin_unlock_irqrestore(lock: &sdd->lock, flags); |
301 | } |
302 | |
303 | static int s3c64xx_prepare_dma(struct s3c64xx_spi_dma_data *dma, |
304 | struct sg_table *sgt) |
305 | { |
306 | struct s3c64xx_spi_driver_data *sdd; |
307 | struct dma_slave_config config; |
308 | struct dma_async_tx_descriptor *desc; |
309 | int ret; |
310 | |
311 | memset(&config, 0, sizeof(config)); |
312 | |
313 | if (dma->direction == DMA_DEV_TO_MEM) { |
314 | sdd = container_of((void *)dma, |
315 | struct s3c64xx_spi_driver_data, rx_dma); |
316 | config.src_addr = sdd->sfr_start + S3C64XX_SPI_RX_DATA; |
317 | config.src_addr_width = sdd->cur_bpw / 8; |
318 | config.src_maxburst = 1; |
319 | } else { |
320 | sdd = container_of((void *)dma, |
321 | struct s3c64xx_spi_driver_data, tx_dma); |
322 | config.dst_addr = sdd->sfr_start + S3C64XX_SPI_TX_DATA; |
323 | config.dst_addr_width = sdd->cur_bpw / 8; |
324 | config.dst_maxburst = 1; |
325 | } |
326 | config.direction = dma->direction; |
327 | ret = dmaengine_slave_config(chan: dma->ch, config: &config); |
328 | if (ret) |
329 | return ret; |
330 | |
331 | desc = dmaengine_prep_slave_sg(chan: dma->ch, sgl: sgt->sgl, sg_len: sgt->nents, |
332 | dir: dma->direction, flags: DMA_PREP_INTERRUPT); |
333 | if (!desc) { |
334 | dev_err(&sdd->pdev->dev, "unable to prepare %s scatterlist" , |
335 | dma->direction == DMA_DEV_TO_MEM ? "rx" : "tx" ); |
336 | return -ENOMEM; |
337 | } |
338 | |
339 | desc->callback = s3c64xx_spi_dmacb; |
340 | desc->callback_param = dma; |
341 | |
342 | dma->cookie = dmaengine_submit(desc); |
343 | ret = dma_submit_error(cookie: dma->cookie); |
344 | if (ret) { |
345 | dev_err(&sdd->pdev->dev, "DMA submission failed" ); |
346 | return ret; |
347 | } |
348 | |
349 | dma_async_issue_pending(chan: dma->ch); |
350 | return 0; |
351 | } |
352 | |
353 | static void s3c64xx_spi_set_cs(struct spi_device *spi, bool enable) |
354 | { |
355 | struct s3c64xx_spi_driver_data *sdd = |
356 | spi_controller_get_devdata(ctlr: spi->controller); |
357 | |
358 | if (sdd->cntrlr_info->no_cs) |
359 | return; |
360 | |
361 | if (enable) { |
362 | if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) { |
363 | writel(val: 0, addr: sdd->regs + S3C64XX_SPI_CS_REG); |
364 | } else { |
365 | u32 ssel = readl(addr: sdd->regs + S3C64XX_SPI_CS_REG); |
366 | |
367 | ssel |= (S3C64XX_SPI_CS_AUTO | |
368 | S3C64XX_SPI_CS_NSC_CNT_2); |
369 | writel(val: ssel, addr: sdd->regs + S3C64XX_SPI_CS_REG); |
370 | } |
371 | } else { |
372 | if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) |
373 | writel(S3C64XX_SPI_CS_SIG_INACT, |
374 | addr: sdd->regs + S3C64XX_SPI_CS_REG); |
375 | } |
376 | } |
377 | |
378 | static int s3c64xx_spi_prepare_transfer(struct spi_controller *spi) |
379 | { |
380 | struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(ctlr: spi); |
381 | |
382 | if (is_polling(sdd)) |
383 | return 0; |
384 | |
385 | /* Requests DMA channels */ |
386 | sdd->rx_dma.ch = dma_request_chan(dev: &sdd->pdev->dev, name: "rx" ); |
387 | if (IS_ERR(ptr: sdd->rx_dma.ch)) { |
388 | dev_err(&sdd->pdev->dev, "Failed to get RX DMA channel\n" ); |
389 | sdd->rx_dma.ch = NULL; |
390 | return 0; |
391 | } |
392 | |
393 | sdd->tx_dma.ch = dma_request_chan(dev: &sdd->pdev->dev, name: "tx" ); |
394 | if (IS_ERR(ptr: sdd->tx_dma.ch)) { |
395 | dev_err(&sdd->pdev->dev, "Failed to get TX DMA channel\n" ); |
396 | dma_release_channel(chan: sdd->rx_dma.ch); |
397 | sdd->tx_dma.ch = NULL; |
398 | sdd->rx_dma.ch = NULL; |
399 | return 0; |
400 | } |
401 | |
402 | spi->dma_rx = sdd->rx_dma.ch; |
403 | spi->dma_tx = sdd->tx_dma.ch; |
404 | |
405 | return 0; |
406 | } |
407 | |
408 | static int s3c64xx_spi_unprepare_transfer(struct spi_controller *spi) |
409 | { |
410 | struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(ctlr: spi); |
411 | |
412 | if (is_polling(sdd)) |
413 | return 0; |
414 | |
415 | /* Releases DMA channels if they are allocated */ |
416 | if (sdd->rx_dma.ch && sdd->tx_dma.ch) { |
417 | dma_release_channel(chan: sdd->rx_dma.ch); |
418 | dma_release_channel(chan: sdd->tx_dma.ch); |
419 | sdd->rx_dma.ch = NULL; |
420 | sdd->tx_dma.ch = NULL; |
421 | } |
422 | |
423 | return 0; |
424 | } |
425 | |
426 | static bool s3c64xx_spi_can_dma(struct spi_controller *host, |
427 | struct spi_device *spi, |
428 | struct spi_transfer *xfer) |
429 | { |
430 | struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(ctlr: host); |
431 | |
432 | if (sdd->rx_dma.ch && sdd->tx_dma.ch) |
433 | return xfer->len >= sdd->fifo_depth; |
434 | |
435 | return false; |
436 | } |
437 | |
438 | static void s3c64xx_iowrite8_32_rep(volatile void __iomem *addr, |
439 | const void *buffer, unsigned int count) |
440 | { |
441 | if (count) { |
442 | const u8 *buf = buffer; |
443 | |
444 | do { |
445 | __raw_writel(val: *buf++, addr); |
446 | } while (--count); |
447 | } |
448 | } |
449 | |
450 | static void s3c64xx_iowrite16_32_rep(volatile void __iomem *addr, |
451 | const void *buffer, unsigned int count) |
452 | { |
453 | if (count) { |
454 | const u16 *buf = buffer; |
455 | |
456 | do { |
457 | __raw_writel(val: *buf++, addr); |
458 | } while (--count); |
459 | } |
460 | } |
461 | |
462 | static void s3c64xx_iowrite_rep(const struct s3c64xx_spi_driver_data *sdd, |
463 | struct spi_transfer *xfer) |
464 | { |
465 | void __iomem *addr = sdd->regs + S3C64XX_SPI_TX_DATA; |
466 | const void *buf = xfer->tx_buf; |
467 | unsigned int len = xfer->len; |
468 | |
469 | switch (sdd->cur_bpw) { |
470 | case 32: |
471 | iowrite32_rep(port: addr, buf, count: len / 4); |
472 | break; |
473 | case 16: |
474 | if (sdd->port_conf->use_32bit_io) |
475 | s3c64xx_iowrite16_32_rep(addr, buffer: buf, count: len / 2); |
476 | else |
477 | iowrite16_rep(port: addr, buf, count: len / 2); |
478 | break; |
479 | default: |
480 | if (sdd->port_conf->use_32bit_io) |
481 | s3c64xx_iowrite8_32_rep(addr, buffer: buf, count: len); |
482 | else |
483 | iowrite8_rep(port: addr, buf, count: len); |
484 | break; |
485 | } |
486 | } |
487 | |
488 | static int s3c64xx_enable_datapath(struct s3c64xx_spi_driver_data *sdd, |
489 | struct spi_transfer *xfer, int dma_mode) |
490 | { |
491 | void __iomem *regs = sdd->regs; |
492 | u32 modecfg, chcfg; |
493 | int ret = 0; |
494 | |
495 | modecfg = readl(addr: regs + S3C64XX_SPI_MODE_CFG); |
496 | modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON); |
497 | |
498 | chcfg = readl(addr: regs + S3C64XX_SPI_CH_CFG); |
499 | chcfg &= ~S3C64XX_SPI_CH_TXCH_ON; |
500 | |
501 | if (dma_mode) { |
502 | chcfg &= ~S3C64XX_SPI_CH_RXCH_ON; |
503 | } else { |
504 | /* Always shift in data in FIFO, even if xfer is Tx only, |
505 | * this helps setting PCKT_CNT value for generating clocks |
506 | * as exactly needed. |
507 | */ |
508 | chcfg |= S3C64XX_SPI_CH_RXCH_ON; |
509 | writel(val: ((xfer->len * 8 / sdd->cur_bpw) & 0xffff) |
510 | | S3C64XX_SPI_PACKET_CNT_EN, |
511 | addr: regs + S3C64XX_SPI_PACKET_CNT); |
512 | } |
513 | |
514 | if (xfer->tx_buf != NULL) { |
515 | sdd->state |= TXBUSY; |
516 | chcfg |= S3C64XX_SPI_CH_TXCH_ON; |
517 | if (dma_mode) { |
518 | modecfg |= S3C64XX_SPI_MODE_TXDMA_ON; |
519 | ret = s3c64xx_prepare_dma(dma: &sdd->tx_dma, sgt: &xfer->tx_sg); |
520 | } else { |
521 | s3c64xx_iowrite_rep(sdd, xfer); |
522 | } |
523 | } |
524 | |
525 | if (xfer->rx_buf != NULL) { |
526 | sdd->state |= RXBUSY; |
527 | |
528 | if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL |
529 | && !(sdd->cur_mode & SPI_CPHA)) |
530 | chcfg |= S3C64XX_SPI_CH_HS_EN; |
531 | |
532 | if (dma_mode) { |
533 | modecfg |= S3C64XX_SPI_MODE_RXDMA_ON; |
534 | chcfg |= S3C64XX_SPI_CH_RXCH_ON; |
535 | writel(val: ((xfer->len * 8 / sdd->cur_bpw) & 0xffff) |
536 | | S3C64XX_SPI_PACKET_CNT_EN, |
537 | addr: regs + S3C64XX_SPI_PACKET_CNT); |
538 | ret = s3c64xx_prepare_dma(dma: &sdd->rx_dma, sgt: &xfer->rx_sg); |
539 | } |
540 | } |
541 | |
542 | if (ret) |
543 | return ret; |
544 | |
545 | writel(val: modecfg, addr: regs + S3C64XX_SPI_MODE_CFG); |
546 | writel(val: chcfg, addr: regs + S3C64XX_SPI_CH_CFG); |
547 | |
548 | return 0; |
549 | } |
550 | |
551 | static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd, |
552 | int timeout_ms) |
553 | { |
554 | void __iomem *regs = sdd->regs; |
555 | unsigned long val = 1; |
556 | u32 status; |
557 | u32 max_fifo = sdd->fifo_depth; |
558 | |
559 | if (timeout_ms) |
560 | val = msecs_to_loops(timeout_ms); |
561 | |
562 | do { |
563 | status = readl(addr: regs + S3C64XX_SPI_STATUS); |
564 | } while (RX_FIFO_LVL(status, sdd) < max_fifo && --val); |
565 | |
566 | /* return the actual received data length */ |
567 | return RX_FIFO_LVL(status, sdd); |
568 | } |
569 | |
570 | static int s3c64xx_wait_for_dma(struct s3c64xx_spi_driver_data *sdd, |
571 | struct spi_transfer *xfer) |
572 | { |
573 | void __iomem *regs = sdd->regs; |
574 | unsigned long val; |
575 | u32 status; |
576 | int ms; |
577 | |
578 | /* millisecs to xfer 'len' bytes @ 'cur_speed' */ |
579 | ms = xfer->len * 8 * 1000 / sdd->cur_speed; |
580 | ms += 30; /* some tolerance */ |
581 | ms = max(ms, 100); /* minimum timeout */ |
582 | |
583 | val = msecs_to_jiffies(m: ms) + 10; |
584 | val = wait_for_completion_timeout(x: &sdd->xfer_completion, timeout: val); |
585 | |
586 | /* |
587 | * If the previous xfer was completed within timeout, then |
588 | * proceed further else return -ETIMEDOUT. |
589 | * DmaTx returns after simply writing data in the FIFO, |
590 | * w/o waiting for real transmission on the bus to finish. |
591 | * DmaRx returns only after Dma read data from FIFO which |
592 | * needs bus transmission to finish, so we don't worry if |
593 | * Xfer involved Rx(with or without Tx). |
594 | */ |
595 | if (val && !xfer->rx_buf) { |
596 | val = msecs_to_loops(10); |
597 | status = readl(addr: regs + S3C64XX_SPI_STATUS); |
598 | while ((TX_FIFO_LVL(status, sdd) |
599 | || !S3C64XX_SPI_ST_TX_DONE(status, sdd)) |
600 | && --val) { |
601 | cpu_relax(); |
602 | status = readl(addr: regs + S3C64XX_SPI_STATUS); |
603 | } |
604 | |
605 | } |
606 | |
607 | /* If timed out while checking rx/tx status return error */ |
608 | if (!val) |
609 | return -ETIMEDOUT; |
610 | |
611 | return 0; |
612 | } |
613 | |
614 | static int s3c64xx_wait_for_pio(struct s3c64xx_spi_driver_data *sdd, |
615 | struct spi_transfer *xfer, bool use_irq) |
616 | { |
617 | void __iomem *regs = sdd->regs; |
618 | unsigned long val; |
619 | u32 status; |
620 | int loops; |
621 | u32 cpy_len; |
622 | u8 *buf; |
623 | int ms; |
624 | unsigned long time_us; |
625 | |
626 | /* microsecs to xfer 'len' bytes @ 'cur_speed' */ |
627 | time_us = (xfer->len * 8 * 1000 * 1000) / sdd->cur_speed; |
628 | ms = (time_us / 1000); |
629 | ms += 10; /* some tolerance */ |
630 | |
631 | /* sleep during signal transfer time */ |
632 | status = readl(addr: regs + S3C64XX_SPI_STATUS); |
633 | if (RX_FIFO_LVL(status, sdd) < xfer->len) |
634 | usleep_range(min: time_us / 2, max: time_us); |
635 | |
636 | if (use_irq) { |
637 | val = msecs_to_jiffies(m: ms); |
638 | if (!wait_for_completion_timeout(x: &sdd->xfer_completion, timeout: val)) |
639 | return -ETIMEDOUT; |
640 | } |
641 | |
642 | val = msecs_to_loops(ms); |
643 | do { |
644 | status = readl(addr: regs + S3C64XX_SPI_STATUS); |
645 | } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val); |
646 | |
647 | if (!val) |
648 | return -EIO; |
649 | |
650 | /* If it was only Tx */ |
651 | if (!xfer->rx_buf) { |
652 | sdd->state &= ~TXBUSY; |
653 | return 0; |
654 | } |
655 | |
656 | /* |
657 | * If the receive length is bigger than the controller fifo |
658 | * size, calculate the loops and read the fifo as many times. |
659 | * loops = length / max fifo size (calculated by using the |
660 | * fifo mask). |
661 | * For any size less than the fifo size the below code is |
662 | * executed atleast once. |
663 | */ |
664 | loops = xfer->len / sdd->fifo_depth; |
665 | buf = xfer->rx_buf; |
666 | do { |
667 | /* wait for data to be received in the fifo */ |
668 | cpy_len = s3c64xx_spi_wait_for_timeout(sdd, |
669 | timeout_ms: (loops ? ms : 0)); |
670 | |
671 | switch (sdd->cur_bpw) { |
672 | case 32: |
673 | ioread32_rep(port: regs + S3C64XX_SPI_RX_DATA, |
674 | buf, count: cpy_len / 4); |
675 | break; |
676 | case 16: |
677 | ioread16_rep(port: regs + S3C64XX_SPI_RX_DATA, |
678 | buf, count: cpy_len / 2); |
679 | break; |
680 | default: |
681 | ioread8_rep(port: regs + S3C64XX_SPI_RX_DATA, |
682 | buf, count: cpy_len); |
683 | break; |
684 | } |
685 | |
686 | buf = buf + cpy_len; |
687 | } while (loops--); |
688 | sdd->state &= ~RXBUSY; |
689 | |
690 | return 0; |
691 | } |
692 | |
693 | static int s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) |
694 | { |
695 | void __iomem *regs = sdd->regs; |
696 | int ret; |
697 | u32 val; |
698 | int div = sdd->port_conf->clk_div; |
699 | |
700 | /* Disable Clock */ |
701 | if (!sdd->port_conf->clk_from_cmu) { |
702 | val = readl(addr: regs + S3C64XX_SPI_CLK_CFG); |
703 | val &= ~S3C64XX_SPI_ENCLK_ENABLE; |
704 | writel(val, addr: regs + S3C64XX_SPI_CLK_CFG); |
705 | } |
706 | |
707 | /* Set Polarity and Phase */ |
708 | val = readl(addr: regs + S3C64XX_SPI_CH_CFG); |
709 | val &= ~(S3C64XX_SPI_CH_SLAVE | |
710 | S3C64XX_SPI_CPOL_L | |
711 | S3C64XX_SPI_CPHA_B); |
712 | |
713 | if (sdd->cur_mode & SPI_CPOL) |
714 | val |= S3C64XX_SPI_CPOL_L; |
715 | |
716 | if (sdd->cur_mode & SPI_CPHA) |
717 | val |= S3C64XX_SPI_CPHA_B; |
718 | |
719 | writel(val, addr: regs + S3C64XX_SPI_CH_CFG); |
720 | |
721 | /* Set Channel & DMA Mode */ |
722 | val = readl(addr: regs + S3C64XX_SPI_MODE_CFG); |
723 | val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK |
724 | | S3C64XX_SPI_MODE_CH_TSZ_MASK); |
725 | |
726 | switch (sdd->cur_bpw) { |
727 | case 32: |
728 | val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD; |
729 | val |= S3C64XX_SPI_MODE_CH_TSZ_WORD; |
730 | break; |
731 | case 16: |
732 | val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD; |
733 | val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD; |
734 | break; |
735 | default: |
736 | val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE; |
737 | val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE; |
738 | break; |
739 | } |
740 | |
741 | if ((sdd->cur_mode & SPI_LOOP) && sdd->port_conf->has_loopback) |
742 | val |= S3C64XX_SPI_MODE_SELF_LOOPBACK; |
743 | else |
744 | val &= ~S3C64XX_SPI_MODE_SELF_LOOPBACK; |
745 | |
746 | writel(val, addr: regs + S3C64XX_SPI_MODE_CFG); |
747 | |
748 | if (sdd->port_conf->clk_from_cmu) { |
749 | ret = clk_set_rate(clk: sdd->src_clk, rate: sdd->cur_speed * div); |
750 | if (ret) |
751 | return ret; |
752 | sdd->cur_speed = clk_get_rate(clk: sdd->src_clk) / div; |
753 | } else { |
754 | /* Configure Clock */ |
755 | val = readl(addr: regs + S3C64XX_SPI_CLK_CFG); |
756 | val &= ~S3C64XX_SPI_PSR_MASK; |
757 | val |= ((clk_get_rate(clk: sdd->src_clk) / sdd->cur_speed / div - 1) |
758 | & S3C64XX_SPI_PSR_MASK); |
759 | writel(val, addr: regs + S3C64XX_SPI_CLK_CFG); |
760 | |
761 | /* Enable Clock */ |
762 | val = readl(addr: regs + S3C64XX_SPI_CLK_CFG); |
763 | val |= S3C64XX_SPI_ENCLK_ENABLE; |
764 | writel(val, addr: regs + S3C64XX_SPI_CLK_CFG); |
765 | } |
766 | |
767 | return 0; |
768 | } |
769 | |
770 | #define XFER_DMAADDR_INVALID DMA_BIT_MASK(32) |
771 | |
772 | static int s3c64xx_spi_prepare_message(struct spi_controller *host, |
773 | struct spi_message *msg) |
774 | { |
775 | struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(ctlr: host); |
776 | struct spi_device *spi = msg->spi; |
777 | struct s3c64xx_spi_csinfo *cs = spi->controller_data; |
778 | |
779 | /* Configure feedback delay */ |
780 | if (!cs) |
781 | /* No delay if not defined */ |
782 | writel(val: 0, addr: sdd->regs + S3C64XX_SPI_FB_CLK); |
783 | else |
784 | writel(val: cs->fb_delay & 0x3, addr: sdd->regs + S3C64XX_SPI_FB_CLK); |
785 | |
786 | return 0; |
787 | } |
788 | |
789 | static size_t s3c64xx_spi_max_transfer_size(struct spi_device *spi) |
790 | { |
791 | struct spi_controller *ctlr = spi->controller; |
792 | |
793 | return ctlr->can_dma ? S3C64XX_SPI_PACKET_CNT_MASK : SIZE_MAX; |
794 | } |
795 | |
796 | static int s3c64xx_spi_transfer_one(struct spi_controller *host, |
797 | struct spi_device *spi, |
798 | struct spi_transfer *xfer) |
799 | { |
800 | struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(ctlr: host); |
801 | const unsigned int fifo_len = sdd->fifo_depth; |
802 | const void *tx_buf = NULL; |
803 | void *rx_buf = NULL; |
804 | int target_len = 0, origin_len = 0; |
805 | int use_dma = 0; |
806 | bool use_irq = false; |
807 | int status; |
808 | u32 speed; |
809 | u8 bpw; |
810 | unsigned long flags; |
811 | u32 rdy_lv; |
812 | u32 val; |
813 | |
814 | reinit_completion(x: &sdd->xfer_completion); |
815 | |
816 | /* Only BPW and Speed may change across transfers */ |
817 | bpw = xfer->bits_per_word; |
818 | speed = xfer->speed_hz; |
819 | |
820 | if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) { |
821 | sdd->cur_bpw = bpw; |
822 | sdd->cur_speed = speed; |
823 | sdd->cur_mode = spi->mode; |
824 | status = s3c64xx_spi_config(sdd); |
825 | if (status) |
826 | return status; |
827 | } |
828 | |
829 | if (!is_polling(sdd) && xfer->len >= fifo_len && |
830 | sdd->rx_dma.ch && sdd->tx_dma.ch) { |
831 | use_dma = 1; |
832 | } else if (xfer->len >= fifo_len) { |
833 | tx_buf = xfer->tx_buf; |
834 | rx_buf = xfer->rx_buf; |
835 | origin_len = xfer->len; |
836 | target_len = xfer->len; |
837 | xfer->len = fifo_len - 1; |
838 | } |
839 | |
840 | do { |
841 | /* transfer size is greater than 32, change to IRQ mode */ |
842 | if (!use_dma && xfer->len > S3C64XX_SPI_POLLING_SIZE) |
843 | use_irq = true; |
844 | |
845 | if (use_irq) { |
846 | reinit_completion(x: &sdd->xfer_completion); |
847 | |
848 | rdy_lv = xfer->len; |
849 | /* Setup RDY_FIFO trigger Level |
850 | * RDY_LVL = |
851 | * fifo_lvl up to 64 byte -> N bytes |
852 | * 128 byte -> RDY_LVL * 2 bytes |
853 | * 256 byte -> RDY_LVL * 4 bytes |
854 | */ |
855 | if (fifo_len == 128) |
856 | rdy_lv /= 2; |
857 | else if (fifo_len == 256) |
858 | rdy_lv /= 4; |
859 | |
860 | val = readl(addr: sdd->regs + S3C64XX_SPI_MODE_CFG); |
861 | val &= ~S3C64XX_SPI_MODE_RX_RDY_LVL; |
862 | val |= (rdy_lv << S3C64XX_SPI_MODE_RX_RDY_LVL_SHIFT); |
863 | writel(val, addr: sdd->regs + S3C64XX_SPI_MODE_CFG); |
864 | |
865 | /* Enable FIFO_RDY_EN IRQ */ |
866 | val = readl(addr: sdd->regs + S3C64XX_SPI_INT_EN); |
867 | writel(val: (val | S3C64XX_SPI_INT_RX_FIFORDY_EN), |
868 | addr: sdd->regs + S3C64XX_SPI_INT_EN); |
869 | |
870 | } |
871 | |
872 | spin_lock_irqsave(&sdd->lock, flags); |
873 | |
874 | /* Pending only which is to be done */ |
875 | sdd->state &= ~RXBUSY; |
876 | sdd->state &= ~TXBUSY; |
877 | |
878 | /* Start the signals */ |
879 | s3c64xx_spi_set_cs(spi, enable: true); |
880 | |
881 | status = s3c64xx_enable_datapath(sdd, xfer, dma_mode: use_dma); |
882 | |
883 | spin_unlock_irqrestore(lock: &sdd->lock, flags); |
884 | |
885 | if (status) { |
886 | dev_err(&spi->dev, "failed to enable data path for transfer: %d\n" , status); |
887 | break; |
888 | } |
889 | |
890 | if (use_dma) |
891 | status = s3c64xx_wait_for_dma(sdd, xfer); |
892 | else |
893 | status = s3c64xx_wait_for_pio(sdd, xfer, use_irq); |
894 | |
895 | if (status) { |
896 | dev_err(&spi->dev, |
897 | "I/O Error: rx-%d tx-%d rx-%c tx-%c len-%d dma-%d res-(%d)\n" , |
898 | xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0, |
899 | (sdd->state & RXBUSY) ? 'f' : 'p', |
900 | (sdd->state & TXBUSY) ? 'f' : 'p', |
901 | xfer->len, use_dma ? 1 : 0, status); |
902 | |
903 | if (use_dma) { |
904 | struct dma_tx_state s; |
905 | |
906 | if (xfer->tx_buf && (sdd->state & TXBUSY)) { |
907 | dmaengine_pause(chan: sdd->tx_dma.ch); |
908 | dmaengine_tx_status(chan: sdd->tx_dma.ch, cookie: sdd->tx_dma.cookie, state: &s); |
909 | dmaengine_terminate_all(chan: sdd->tx_dma.ch); |
910 | dev_err(&spi->dev, "TX residue: %d\n" , s.residue); |
911 | |
912 | } |
913 | if (xfer->rx_buf && (sdd->state & RXBUSY)) { |
914 | dmaengine_pause(chan: sdd->rx_dma.ch); |
915 | dmaengine_tx_status(chan: sdd->rx_dma.ch, cookie: sdd->rx_dma.cookie, state: &s); |
916 | dmaengine_terminate_all(chan: sdd->rx_dma.ch); |
917 | dev_err(&spi->dev, "RX residue: %d\n" , s.residue); |
918 | } |
919 | } |
920 | } else { |
921 | s3c64xx_flush_fifo(sdd); |
922 | } |
923 | if (target_len > 0) { |
924 | target_len -= xfer->len; |
925 | |
926 | if (xfer->tx_buf) |
927 | xfer->tx_buf += xfer->len; |
928 | |
929 | if (xfer->rx_buf) |
930 | xfer->rx_buf += xfer->len; |
931 | |
932 | if (target_len >= fifo_len) |
933 | xfer->len = fifo_len - 1; |
934 | else |
935 | xfer->len = target_len; |
936 | } |
937 | } while (target_len > 0); |
938 | |
939 | if (origin_len) { |
940 | /* Restore original xfer buffers and length */ |
941 | xfer->tx_buf = tx_buf; |
942 | xfer->rx_buf = rx_buf; |
943 | xfer->len = origin_len; |
944 | } |
945 | |
946 | return status; |
947 | } |
948 | |
949 | static struct s3c64xx_spi_csinfo *s3c64xx_get_target_ctrldata( |
950 | struct spi_device *spi) |
951 | { |
952 | struct s3c64xx_spi_csinfo *cs; |
953 | struct device_node *target_np, *data_np = NULL; |
954 | u32 fb_delay = 0; |
955 | |
956 | target_np = spi->dev.of_node; |
957 | if (!target_np) { |
958 | dev_err(&spi->dev, "device node not found\n" ); |
959 | return ERR_PTR(error: -EINVAL); |
960 | } |
961 | |
962 | cs = kzalloc(size: sizeof(*cs), GFP_KERNEL); |
963 | if (!cs) |
964 | return ERR_PTR(error: -ENOMEM); |
965 | |
966 | data_np = of_get_child_by_name(node: target_np, name: "controller-data" ); |
967 | if (!data_np) { |
968 | dev_info(&spi->dev, "feedback delay set to default (0)\n" ); |
969 | return cs; |
970 | } |
971 | |
972 | of_property_read_u32(np: data_np, propname: "samsung,spi-feedback-delay" , out_value: &fb_delay); |
973 | cs->fb_delay = fb_delay; |
974 | of_node_put(node: data_np); |
975 | return cs; |
976 | } |
977 | |
978 | /* |
979 | * Here we only check the validity of requested configuration |
980 | * and save the configuration in a local data-structure. |
981 | * The controller is actually configured only just before we |
982 | * get a message to transfer. |
983 | */ |
984 | static int s3c64xx_spi_setup(struct spi_device *spi) |
985 | { |
986 | struct s3c64xx_spi_csinfo *cs = spi->controller_data; |
987 | struct s3c64xx_spi_driver_data *sdd; |
988 | int err; |
989 | int div; |
990 | |
991 | sdd = spi_controller_get_devdata(ctlr: spi->controller); |
992 | if (spi->dev.of_node) { |
993 | cs = s3c64xx_get_target_ctrldata(spi); |
994 | spi->controller_data = cs; |
995 | } |
996 | |
997 | /* NULL is fine, we just avoid using the FB delay (=0) */ |
998 | if (IS_ERR(ptr: cs)) { |
999 | dev_err(&spi->dev, "No CS for SPI(%d)\n" , spi_get_chipselect(spi, 0)); |
1000 | return -ENODEV; |
1001 | } |
1002 | |
1003 | if (!spi_get_ctldata(spi)) |
1004 | spi_set_ctldata(spi, state: cs); |
1005 | |
1006 | pm_runtime_get_sync(dev: &sdd->pdev->dev); |
1007 | |
1008 | div = sdd->port_conf->clk_div; |
1009 | |
1010 | /* Check if we can provide the requested rate */ |
1011 | if (!sdd->port_conf->clk_from_cmu) { |
1012 | u32 psr, speed; |
1013 | |
1014 | /* Max possible */ |
1015 | speed = clk_get_rate(clk: sdd->src_clk) / div / (0 + 1); |
1016 | |
1017 | if (spi->max_speed_hz > speed) |
1018 | spi->max_speed_hz = speed; |
1019 | |
1020 | psr = clk_get_rate(clk: sdd->src_clk) / div / spi->max_speed_hz - 1; |
1021 | psr &= S3C64XX_SPI_PSR_MASK; |
1022 | if (psr == S3C64XX_SPI_PSR_MASK) |
1023 | psr--; |
1024 | |
1025 | speed = clk_get_rate(clk: sdd->src_clk) / div / (psr + 1); |
1026 | if (spi->max_speed_hz < speed) { |
1027 | if (psr+1 < S3C64XX_SPI_PSR_MASK) { |
1028 | psr++; |
1029 | } else { |
1030 | err = -EINVAL; |
1031 | goto setup_exit; |
1032 | } |
1033 | } |
1034 | |
1035 | speed = clk_get_rate(clk: sdd->src_clk) / div / (psr + 1); |
1036 | if (spi->max_speed_hz >= speed) { |
1037 | spi->max_speed_hz = speed; |
1038 | } else { |
1039 | dev_err(&spi->dev, "Can't set %dHz transfer speed\n" , |
1040 | spi->max_speed_hz); |
1041 | err = -EINVAL; |
1042 | goto setup_exit; |
1043 | } |
1044 | } |
1045 | |
1046 | pm_runtime_mark_last_busy(dev: &sdd->pdev->dev); |
1047 | pm_runtime_put_autosuspend(dev: &sdd->pdev->dev); |
1048 | s3c64xx_spi_set_cs(spi, enable: false); |
1049 | |
1050 | return 0; |
1051 | |
1052 | setup_exit: |
1053 | pm_runtime_mark_last_busy(dev: &sdd->pdev->dev); |
1054 | pm_runtime_put_autosuspend(dev: &sdd->pdev->dev); |
1055 | /* setup() returns with device de-selected */ |
1056 | s3c64xx_spi_set_cs(spi, enable: false); |
1057 | |
1058 | spi_set_ctldata(spi, NULL); |
1059 | |
1060 | /* This was dynamically allocated on the DT path */ |
1061 | if (spi->dev.of_node) |
1062 | kfree(objp: cs); |
1063 | |
1064 | return err; |
1065 | } |
1066 | |
1067 | static void s3c64xx_spi_cleanup(struct spi_device *spi) |
1068 | { |
1069 | struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi); |
1070 | |
1071 | /* This was dynamically allocated on the DT path */ |
1072 | if (spi->dev.of_node) |
1073 | kfree(objp: cs); |
1074 | |
1075 | spi_set_ctldata(spi, NULL); |
1076 | } |
1077 | |
1078 | static irqreturn_t s3c64xx_spi_irq(int irq, void *data) |
1079 | { |
1080 | struct s3c64xx_spi_driver_data *sdd = data; |
1081 | struct spi_controller *spi = sdd->host; |
1082 | unsigned int val, clr = 0; |
1083 | |
1084 | val = readl(addr: sdd->regs + S3C64XX_SPI_STATUS); |
1085 | |
1086 | if (val & S3C64XX_SPI_ST_RX_OVERRUN_ERR) { |
1087 | clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR; |
1088 | dev_err(&spi->dev, "RX overrun\n" ); |
1089 | } |
1090 | if (val & S3C64XX_SPI_ST_RX_UNDERRUN_ERR) { |
1091 | clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR; |
1092 | dev_err(&spi->dev, "RX underrun\n" ); |
1093 | } |
1094 | if (val & S3C64XX_SPI_ST_TX_OVERRUN_ERR) { |
1095 | clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR; |
1096 | dev_err(&spi->dev, "TX overrun\n" ); |
1097 | } |
1098 | if (val & S3C64XX_SPI_ST_TX_UNDERRUN_ERR) { |
1099 | clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR; |
1100 | dev_err(&spi->dev, "TX underrun\n" ); |
1101 | } |
1102 | |
1103 | if (val & S3C64XX_SPI_ST_RX_FIFORDY) { |
1104 | complete(&sdd->xfer_completion); |
1105 | /* No pending clear irq, turn-off INT_EN_RX_FIFO_RDY */ |
1106 | val = readl(addr: sdd->regs + S3C64XX_SPI_INT_EN); |
1107 | writel(val: (val & ~S3C64XX_SPI_INT_RX_FIFORDY_EN), |
1108 | addr: sdd->regs + S3C64XX_SPI_INT_EN); |
1109 | } |
1110 | |
1111 | /* Clear the pending irq by setting and then clearing it */ |
1112 | writel(val: clr, addr: sdd->regs + S3C64XX_SPI_PENDING_CLR); |
1113 | writel(val: 0, addr: sdd->regs + S3C64XX_SPI_PENDING_CLR); |
1114 | |
1115 | return IRQ_HANDLED; |
1116 | } |
1117 | |
1118 | static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd) |
1119 | { |
1120 | struct s3c64xx_spi_info *sci = sdd->cntrlr_info; |
1121 | void __iomem *regs = sdd->regs; |
1122 | unsigned int val; |
1123 | |
1124 | sdd->cur_speed = 0; |
1125 | |
1126 | if (sci->no_cs) |
1127 | writel(val: 0, addr: sdd->regs + S3C64XX_SPI_CS_REG); |
1128 | else if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) |
1129 | writel(S3C64XX_SPI_CS_SIG_INACT, addr: sdd->regs + S3C64XX_SPI_CS_REG); |
1130 | |
1131 | /* Disable Interrupts - we use Polling if not DMA mode */ |
1132 | writel(val: 0, addr: regs + S3C64XX_SPI_INT_EN); |
1133 | |
1134 | if (!sdd->port_conf->clk_from_cmu) |
1135 | writel(val: sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT, |
1136 | addr: regs + S3C64XX_SPI_CLK_CFG); |
1137 | writel(val: 0, addr: regs + S3C64XX_SPI_MODE_CFG); |
1138 | writel(val: 0, addr: regs + S3C64XX_SPI_PACKET_CNT); |
1139 | |
1140 | /* Clear any irq pending bits, should set and clear the bits */ |
1141 | val = S3C64XX_SPI_PND_RX_OVERRUN_CLR | |
1142 | S3C64XX_SPI_PND_RX_UNDERRUN_CLR | |
1143 | S3C64XX_SPI_PND_TX_OVERRUN_CLR | |
1144 | S3C64XX_SPI_PND_TX_UNDERRUN_CLR; |
1145 | writel(val, addr: regs + S3C64XX_SPI_PENDING_CLR); |
1146 | writel(val: 0, addr: regs + S3C64XX_SPI_PENDING_CLR); |
1147 | |
1148 | writel(val: 0, addr: regs + S3C64XX_SPI_SWAP_CFG); |
1149 | |
1150 | val = readl(addr: regs + S3C64XX_SPI_MODE_CFG); |
1151 | val &= ~S3C64XX_SPI_MODE_4BURST; |
1152 | val |= (S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF); |
1153 | writel(val, addr: regs + S3C64XX_SPI_MODE_CFG); |
1154 | |
1155 | s3c64xx_flush_fifo(sdd); |
1156 | } |
1157 | |
1158 | #ifdef CONFIG_OF |
1159 | static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev) |
1160 | { |
1161 | struct s3c64xx_spi_info *sci; |
1162 | u32 temp; |
1163 | |
1164 | sci = devm_kzalloc(dev, size: sizeof(*sci), GFP_KERNEL); |
1165 | if (!sci) |
1166 | return ERR_PTR(error: -ENOMEM); |
1167 | |
1168 | if (of_property_read_u32(np: dev->of_node, propname: "samsung,spi-src-clk" , out_value: &temp)) { |
1169 | dev_dbg(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n" ); |
1170 | sci->src_clk_nr = 0; |
1171 | } else { |
1172 | sci->src_clk_nr = temp; |
1173 | } |
1174 | |
1175 | if (of_property_read_u32(np: dev->of_node, propname: "num-cs" , out_value: &temp)) { |
1176 | dev_dbg(dev, "number of chip select lines not specified, assuming 1 chip select line\n" ); |
1177 | sci->num_cs = 1; |
1178 | } else { |
1179 | sci->num_cs = temp; |
1180 | } |
1181 | |
1182 | sci->no_cs = of_property_read_bool(np: dev->of_node, propname: "no-cs-readback" ); |
1183 | sci->polling = !of_property_present(np: dev->of_node, propname: "dmas" ); |
1184 | |
1185 | return sci; |
1186 | } |
1187 | #else |
1188 | static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev) |
1189 | { |
1190 | return dev_get_platdata(dev); |
1191 | } |
1192 | #endif |
1193 | |
1194 | static inline const struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config( |
1195 | struct platform_device *pdev) |
1196 | { |
1197 | #ifdef CONFIG_OF |
1198 | if (pdev->dev.of_node) |
1199 | return of_device_get_match_data(dev: &pdev->dev); |
1200 | #endif |
1201 | return (const struct s3c64xx_spi_port_config *)platform_get_device_id(pdev)->driver_data; |
1202 | } |
1203 | |
1204 | static int s3c64xx_spi_set_port_id(struct platform_device *pdev, |
1205 | struct s3c64xx_spi_driver_data *sdd) |
1206 | { |
1207 | const struct s3c64xx_spi_port_config *port_conf = sdd->port_conf; |
1208 | int ret; |
1209 | |
1210 | if (port_conf->rx_fifomask && port_conf->tx_fifomask) |
1211 | return 0; |
1212 | |
1213 | if (pdev->dev.of_node) { |
1214 | ret = of_alias_get_id(np: pdev->dev.of_node, stem: "spi" ); |
1215 | if (ret < 0) |
1216 | return dev_err_probe(dev: &pdev->dev, err: ret, |
1217 | fmt: "Failed to get alias id\n" ); |
1218 | sdd->port_id = ret; |
1219 | } else { |
1220 | if (pdev->id < 0) |
1221 | return dev_err_probe(dev: &pdev->dev, err: -EINVAL, |
1222 | fmt: "Negative platform ID is not allowed\n" ); |
1223 | sdd->port_id = pdev->id; |
1224 | } |
1225 | |
1226 | return 0; |
1227 | } |
1228 | |
1229 | static void s3c64xx_spi_set_fifomask(struct s3c64xx_spi_driver_data *sdd) |
1230 | { |
1231 | const struct s3c64xx_spi_port_config *port_conf = sdd->port_conf; |
1232 | |
1233 | if (port_conf->rx_fifomask) |
1234 | sdd->rx_fifomask = port_conf->rx_fifomask; |
1235 | else |
1236 | sdd->rx_fifomask = FIFO_LVL_MASK(sdd) << |
1237 | port_conf->rx_lvl_offset; |
1238 | |
1239 | if (port_conf->tx_fifomask) |
1240 | sdd->tx_fifomask = port_conf->tx_fifomask; |
1241 | else |
1242 | sdd->tx_fifomask = FIFO_LVL_MASK(sdd) << |
1243 | S3C64XX_SPI_ST_TX_FIFO_LVL_SHIFT; |
1244 | } |
1245 | |
1246 | static int s3c64xx_spi_probe(struct platform_device *pdev) |
1247 | { |
1248 | struct resource *mem_res; |
1249 | struct s3c64xx_spi_driver_data *sdd; |
1250 | struct s3c64xx_spi_info *sci = dev_get_platdata(dev: &pdev->dev); |
1251 | struct spi_controller *host; |
1252 | int ret, irq; |
1253 | char clk_name[16]; |
1254 | |
1255 | if (!sci && pdev->dev.of_node) { |
1256 | sci = s3c64xx_spi_parse_dt(dev: &pdev->dev); |
1257 | if (IS_ERR(ptr: sci)) |
1258 | return PTR_ERR(ptr: sci); |
1259 | } |
1260 | |
1261 | if (!sci) |
1262 | return dev_err_probe(dev: &pdev->dev, err: -ENODEV, |
1263 | fmt: "Platform_data missing!\n" ); |
1264 | |
1265 | irq = platform_get_irq(pdev, 0); |
1266 | if (irq < 0) |
1267 | return irq; |
1268 | |
1269 | host = devm_spi_alloc_host(dev: &pdev->dev, size: sizeof(*sdd)); |
1270 | if (!host) |
1271 | return dev_err_probe(dev: &pdev->dev, err: -ENOMEM, |
1272 | fmt: "Unable to allocate SPI Host\n" ); |
1273 | |
1274 | platform_set_drvdata(pdev, data: host); |
1275 | |
1276 | sdd = spi_controller_get_devdata(ctlr: host); |
1277 | sdd->port_conf = s3c64xx_spi_get_port_config(pdev); |
1278 | sdd->host = host; |
1279 | sdd->cntrlr_info = sci; |
1280 | sdd->pdev = pdev; |
1281 | |
1282 | ret = s3c64xx_spi_set_port_id(pdev, sdd); |
1283 | if (ret) |
1284 | return ret; |
1285 | |
1286 | if (sdd->port_conf->fifo_depth) |
1287 | sdd->fifo_depth = sdd->port_conf->fifo_depth; |
1288 | else if (of_property_read_u32(np: pdev->dev.of_node, propname: "fifo-depth" , |
1289 | out_value: &sdd->fifo_depth)) |
1290 | sdd->fifo_depth = FIFO_DEPTH(sdd); |
1291 | |
1292 | s3c64xx_spi_set_fifomask(sdd); |
1293 | |
1294 | sdd->cur_bpw = 8; |
1295 | |
1296 | sdd->tx_dma.direction = DMA_MEM_TO_DEV; |
1297 | sdd->rx_dma.direction = DMA_DEV_TO_MEM; |
1298 | |
1299 | host->dev.of_node = pdev->dev.of_node; |
1300 | host->bus_num = -1; |
1301 | host->setup = s3c64xx_spi_setup; |
1302 | host->cleanup = s3c64xx_spi_cleanup; |
1303 | host->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer; |
1304 | host->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer; |
1305 | host->prepare_message = s3c64xx_spi_prepare_message; |
1306 | host->transfer_one = s3c64xx_spi_transfer_one; |
1307 | host->max_transfer_size = s3c64xx_spi_max_transfer_size; |
1308 | host->num_chipselect = sci->num_cs; |
1309 | host->use_gpio_descriptors = true; |
1310 | host->dma_alignment = 8; |
1311 | host->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) | |
1312 | SPI_BPW_MASK(8); |
1313 | /* the spi->mode bits understood by this driver: */ |
1314 | host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; |
1315 | if (sdd->port_conf->has_loopback) |
1316 | host->mode_bits |= SPI_LOOP; |
1317 | host->auto_runtime_pm = true; |
1318 | if (!is_polling(sdd)) |
1319 | host->can_dma = s3c64xx_spi_can_dma; |
1320 | |
1321 | sdd->regs = devm_platform_get_and_ioremap_resource(pdev, index: 0, res: &mem_res); |
1322 | if (IS_ERR(ptr: sdd->regs)) |
1323 | return PTR_ERR(ptr: sdd->regs); |
1324 | sdd->sfr_start = mem_res->start; |
1325 | |
1326 | if (sci->cfg_gpio && sci->cfg_gpio()) |
1327 | return dev_err_probe(dev: &pdev->dev, err: -EBUSY, |
1328 | fmt: "Unable to config gpio\n" ); |
1329 | |
1330 | /* Setup clocks */ |
1331 | sdd->clk = devm_clk_get_enabled(dev: &pdev->dev, id: "spi" ); |
1332 | if (IS_ERR(ptr: sdd->clk)) |
1333 | return dev_err_probe(dev: &pdev->dev, err: PTR_ERR(ptr: sdd->clk), |
1334 | fmt: "Unable to acquire clock 'spi'\n" ); |
1335 | |
1336 | sprintf(buf: clk_name, fmt: "spi_busclk%d" , sci->src_clk_nr); |
1337 | sdd->src_clk = devm_clk_get_enabled(dev: &pdev->dev, id: clk_name); |
1338 | if (IS_ERR(ptr: sdd->src_clk)) |
1339 | return dev_err_probe(dev: &pdev->dev, err: PTR_ERR(ptr: sdd->src_clk), |
1340 | fmt: "Unable to acquire clock '%s'\n" , |
1341 | clk_name); |
1342 | |
1343 | if (sdd->port_conf->clk_ioclk) { |
1344 | sdd->ioclk = devm_clk_get_enabled(dev: &pdev->dev, id: "spi_ioclk" ); |
1345 | if (IS_ERR(ptr: sdd->ioclk)) |
1346 | return dev_err_probe(dev: &pdev->dev, err: PTR_ERR(ptr: sdd->ioclk), |
1347 | fmt: "Unable to acquire 'ioclk'\n" ); |
1348 | } |
1349 | |
1350 | pm_runtime_set_autosuspend_delay(dev: &pdev->dev, AUTOSUSPEND_TIMEOUT); |
1351 | pm_runtime_use_autosuspend(dev: &pdev->dev); |
1352 | pm_runtime_set_active(dev: &pdev->dev); |
1353 | pm_runtime_enable(dev: &pdev->dev); |
1354 | pm_runtime_get_sync(dev: &pdev->dev); |
1355 | |
1356 | /* Setup Deufult Mode */ |
1357 | s3c64xx_spi_hwinit(sdd); |
1358 | |
1359 | spin_lock_init(&sdd->lock); |
1360 | init_completion(x: &sdd->xfer_completion); |
1361 | |
1362 | ret = devm_request_irq(dev: &pdev->dev, irq, handler: s3c64xx_spi_irq, irqflags: 0, |
1363 | devname: "spi-s3c64xx" , dev_id: sdd); |
1364 | if (ret != 0) { |
1365 | dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n" , |
1366 | irq, ret); |
1367 | goto err_pm_put; |
1368 | } |
1369 | |
1370 | writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN | |
1371 | S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN, |
1372 | addr: sdd->regs + S3C64XX_SPI_INT_EN); |
1373 | |
1374 | ret = devm_spi_register_controller(dev: &pdev->dev, ctlr: host); |
1375 | if (ret != 0) { |
1376 | dev_err(&pdev->dev, "cannot register SPI host: %d\n" , ret); |
1377 | goto err_pm_put; |
1378 | } |
1379 | |
1380 | dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Targets attached\n" , |
1381 | host->bus_num, host->num_chipselect); |
1382 | dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tFIFO %dbytes\n" , |
1383 | mem_res, sdd->fifo_depth); |
1384 | |
1385 | pm_runtime_mark_last_busy(dev: &pdev->dev); |
1386 | pm_runtime_put_autosuspend(dev: &pdev->dev); |
1387 | |
1388 | return 0; |
1389 | |
1390 | err_pm_put: |
1391 | pm_runtime_put_noidle(dev: &pdev->dev); |
1392 | pm_runtime_disable(dev: &pdev->dev); |
1393 | pm_runtime_set_suspended(dev: &pdev->dev); |
1394 | |
1395 | return ret; |
1396 | } |
1397 | |
1398 | static void s3c64xx_spi_remove(struct platform_device *pdev) |
1399 | { |
1400 | struct spi_controller *host = platform_get_drvdata(pdev); |
1401 | struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(ctlr: host); |
1402 | |
1403 | pm_runtime_get_sync(dev: &pdev->dev); |
1404 | |
1405 | writel(val: 0, addr: sdd->regs + S3C64XX_SPI_INT_EN); |
1406 | |
1407 | if (!is_polling(sdd)) { |
1408 | dma_release_channel(chan: sdd->rx_dma.ch); |
1409 | dma_release_channel(chan: sdd->tx_dma.ch); |
1410 | } |
1411 | |
1412 | pm_runtime_put_noidle(dev: &pdev->dev); |
1413 | pm_runtime_disable(dev: &pdev->dev); |
1414 | pm_runtime_set_suspended(dev: &pdev->dev); |
1415 | } |
1416 | |
1417 | #ifdef CONFIG_PM_SLEEP |
1418 | static int s3c64xx_spi_suspend(struct device *dev) |
1419 | { |
1420 | struct spi_controller *host = dev_get_drvdata(dev); |
1421 | struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(ctlr: host); |
1422 | int ret; |
1423 | |
1424 | ret = spi_controller_suspend(ctlr: host); |
1425 | if (ret) |
1426 | return ret; |
1427 | |
1428 | ret = pm_runtime_force_suspend(dev); |
1429 | if (ret < 0) |
1430 | return ret; |
1431 | |
1432 | sdd->cur_speed = 0; /* Output Clock is stopped */ |
1433 | |
1434 | return 0; |
1435 | } |
1436 | |
1437 | static int s3c64xx_spi_resume(struct device *dev) |
1438 | { |
1439 | struct spi_controller *host = dev_get_drvdata(dev); |
1440 | struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(ctlr: host); |
1441 | struct s3c64xx_spi_info *sci = sdd->cntrlr_info; |
1442 | int ret; |
1443 | |
1444 | if (sci->cfg_gpio) |
1445 | sci->cfg_gpio(); |
1446 | |
1447 | ret = pm_runtime_force_resume(dev); |
1448 | if (ret < 0) |
1449 | return ret; |
1450 | |
1451 | return spi_controller_resume(ctlr: host); |
1452 | } |
1453 | #endif /* CONFIG_PM_SLEEP */ |
1454 | |
1455 | #ifdef CONFIG_PM |
1456 | static int s3c64xx_spi_runtime_suspend(struct device *dev) |
1457 | { |
1458 | struct spi_controller *host = dev_get_drvdata(dev); |
1459 | struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(ctlr: host); |
1460 | |
1461 | clk_disable_unprepare(clk: sdd->clk); |
1462 | clk_disable_unprepare(clk: sdd->src_clk); |
1463 | clk_disable_unprepare(clk: sdd->ioclk); |
1464 | |
1465 | return 0; |
1466 | } |
1467 | |
1468 | static int s3c64xx_spi_runtime_resume(struct device *dev) |
1469 | { |
1470 | struct spi_controller *host = dev_get_drvdata(dev); |
1471 | struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(ctlr: host); |
1472 | int ret; |
1473 | |
1474 | if (sdd->port_conf->clk_ioclk) { |
1475 | ret = clk_prepare_enable(clk: sdd->ioclk); |
1476 | if (ret != 0) |
1477 | return ret; |
1478 | } |
1479 | |
1480 | ret = clk_prepare_enable(clk: sdd->src_clk); |
1481 | if (ret != 0) |
1482 | goto err_disable_ioclk; |
1483 | |
1484 | ret = clk_prepare_enable(clk: sdd->clk); |
1485 | if (ret != 0) |
1486 | goto err_disable_src_clk; |
1487 | |
1488 | s3c64xx_spi_hwinit(sdd); |
1489 | |
1490 | writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN | |
1491 | S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN, |
1492 | addr: sdd->regs + S3C64XX_SPI_INT_EN); |
1493 | |
1494 | return 0; |
1495 | |
1496 | err_disable_src_clk: |
1497 | clk_disable_unprepare(clk: sdd->src_clk); |
1498 | err_disable_ioclk: |
1499 | clk_disable_unprepare(clk: sdd->ioclk); |
1500 | |
1501 | return ret; |
1502 | } |
1503 | #endif /* CONFIG_PM */ |
1504 | |
1505 | static const struct dev_pm_ops s3c64xx_spi_pm = { |
1506 | SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume) |
1507 | SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend, |
1508 | s3c64xx_spi_runtime_resume, NULL) |
1509 | }; |
1510 | |
1511 | static const struct s3c64xx_spi_port_config s3c2443_spi_port_config = { |
1512 | /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ |
1513 | .fifo_lvl_mask = { 0x7f }, |
1514 | /* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */ |
1515 | .rx_lvl_offset = 13, |
1516 | .tx_st_done = 21, |
1517 | .clk_div = 2, |
1518 | .high_speed = true, |
1519 | }; |
1520 | |
1521 | static const struct s3c64xx_spi_port_config s3c6410_spi_port_config = { |
1522 | /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ |
1523 | .fifo_lvl_mask = { 0x7f, 0x7F }, |
1524 | /* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */ |
1525 | .rx_lvl_offset = 13, |
1526 | .tx_st_done = 21, |
1527 | .clk_div = 2, |
1528 | }; |
1529 | |
1530 | static const struct s3c64xx_spi_port_config s5pv210_spi_port_config = { |
1531 | /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ |
1532 | .fifo_lvl_mask = { 0x1ff, 0x7F }, |
1533 | /* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */ |
1534 | .rx_lvl_offset = 15, |
1535 | .tx_st_done = 25, |
1536 | .clk_div = 2, |
1537 | .high_speed = true, |
1538 | }; |
1539 | |
1540 | static const struct s3c64xx_spi_port_config exynos4_spi_port_config = { |
1541 | /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ |
1542 | .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F }, |
1543 | /* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */ |
1544 | .rx_lvl_offset = 15, |
1545 | .tx_st_done = 25, |
1546 | .clk_div = 2, |
1547 | .high_speed = true, |
1548 | .clk_from_cmu = true, |
1549 | .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, |
1550 | }; |
1551 | |
1552 | static const struct s3c64xx_spi_port_config exynos7_spi_port_config = { |
1553 | /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ |
1554 | .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F, 0x7F, 0x7F, 0x1ff}, |
1555 | /* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */ |
1556 | .rx_lvl_offset = 15, |
1557 | .tx_st_done = 25, |
1558 | .clk_div = 2, |
1559 | .high_speed = true, |
1560 | .clk_from_cmu = true, |
1561 | .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, |
1562 | }; |
1563 | |
1564 | static const struct s3c64xx_spi_port_config exynos5433_spi_port_config = { |
1565 | /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ |
1566 | .fifo_lvl_mask = { 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff}, |
1567 | /* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */ |
1568 | .rx_lvl_offset = 15, |
1569 | .tx_st_done = 25, |
1570 | .clk_div = 2, |
1571 | .high_speed = true, |
1572 | .clk_from_cmu = true, |
1573 | .clk_ioclk = true, |
1574 | .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, |
1575 | }; |
1576 | |
1577 | static const struct s3c64xx_spi_port_config exynos850_spi_port_config = { |
1578 | .fifo_depth = 64, |
1579 | .rx_fifomask = S3C64XX_SPI_ST_RX_FIFO_RDY_V2, |
1580 | .tx_fifomask = S3C64XX_SPI_ST_TX_FIFO_RDY_V2, |
1581 | .tx_st_done = 25, |
1582 | .clk_div = 4, |
1583 | .high_speed = true, |
1584 | .clk_from_cmu = true, |
1585 | .has_loopback = true, |
1586 | .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, |
1587 | }; |
1588 | |
1589 | static const struct s3c64xx_spi_port_config exynosautov9_spi_port_config = { |
1590 | /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ |
1591 | .fifo_lvl_mask = { 0x1ff, 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff, 0x7f, |
1592 | 0x7f, 0x7f, 0x7f, 0x7f}, |
1593 | /* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */ |
1594 | .rx_lvl_offset = 15, |
1595 | .tx_st_done = 25, |
1596 | .clk_div = 4, |
1597 | .high_speed = true, |
1598 | .clk_from_cmu = true, |
1599 | .clk_ioclk = true, |
1600 | .has_loopback = true, |
1601 | .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, |
1602 | }; |
1603 | |
1604 | static const struct s3c64xx_spi_port_config fsd_spi_port_config = { |
1605 | /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ |
1606 | .fifo_lvl_mask = { 0x7f, 0x7f, 0x7f, 0x7f, 0x7f}, |
1607 | /* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */ |
1608 | .rx_lvl_offset = 15, |
1609 | .tx_st_done = 25, |
1610 | .clk_div = 2, |
1611 | .high_speed = true, |
1612 | .clk_from_cmu = true, |
1613 | .clk_ioclk = false, |
1614 | .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, |
1615 | }; |
1616 | |
1617 | static const struct s3c64xx_spi_port_config gs101_spi_port_config = { |
1618 | .fifo_depth = 64, |
1619 | .rx_fifomask = S3C64XX_SPI_ST_RX_FIFO_RDY_V2, |
1620 | .tx_fifomask = S3C64XX_SPI_ST_TX_FIFO_RDY_V2, |
1621 | .tx_st_done = 25, |
1622 | .clk_div = 4, |
1623 | .high_speed = true, |
1624 | .clk_from_cmu = true, |
1625 | .has_loopback = true, |
1626 | .use_32bit_io = true, |
1627 | .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, |
1628 | }; |
1629 | |
1630 | static const struct platform_device_id s3c64xx_spi_driver_ids[] = { |
1631 | { |
1632 | .name = "s3c2443-spi" , |
1633 | .driver_data = (kernel_ulong_t)&s3c2443_spi_port_config, |
1634 | }, { |
1635 | .name = "s3c6410-spi" , |
1636 | .driver_data = (kernel_ulong_t)&s3c6410_spi_port_config, |
1637 | }, |
1638 | { }, |
1639 | }; |
1640 | |
1641 | static const struct of_device_id s3c64xx_spi_dt_match[] = { |
1642 | { .compatible = "google,gs101-spi" , |
1643 | .data = &gs101_spi_port_config, |
1644 | }, |
1645 | { .compatible = "samsung,s3c2443-spi" , |
1646 | .data = &s3c2443_spi_port_config, |
1647 | }, |
1648 | { .compatible = "samsung,s3c6410-spi" , |
1649 | .data = &s3c6410_spi_port_config, |
1650 | }, |
1651 | { .compatible = "samsung,s5pv210-spi" , |
1652 | .data = &s5pv210_spi_port_config, |
1653 | }, |
1654 | { .compatible = "samsung,exynos4210-spi" , |
1655 | .data = &exynos4_spi_port_config, |
1656 | }, |
1657 | { .compatible = "samsung,exynos7-spi" , |
1658 | .data = &exynos7_spi_port_config, |
1659 | }, |
1660 | { .compatible = "samsung,exynos5433-spi" , |
1661 | .data = &exynos5433_spi_port_config, |
1662 | }, |
1663 | { .compatible = "samsung,exynos850-spi" , |
1664 | .data = &exynos850_spi_port_config, |
1665 | }, |
1666 | { .compatible = "samsung,exynosautov9-spi" , |
1667 | .data = &exynosautov9_spi_port_config, |
1668 | }, |
1669 | { .compatible = "tesla,fsd-spi" , |
1670 | .data = &fsd_spi_port_config, |
1671 | }, |
1672 | { }, |
1673 | }; |
1674 | MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match); |
1675 | |
1676 | static struct platform_driver s3c64xx_spi_driver = { |
1677 | .driver = { |
1678 | .name = "s3c64xx-spi" , |
1679 | .pm = &s3c64xx_spi_pm, |
1680 | .of_match_table = of_match_ptr(s3c64xx_spi_dt_match), |
1681 | }, |
1682 | .probe = s3c64xx_spi_probe, |
1683 | .remove_new = s3c64xx_spi_remove, |
1684 | .id_table = s3c64xx_spi_driver_ids, |
1685 | }; |
1686 | MODULE_ALIAS("platform:s3c64xx-spi" ); |
1687 | |
1688 | module_platform_driver(s3c64xx_spi_driver); |
1689 | |
1690 | MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>" ); |
1691 | MODULE_DESCRIPTION("S3C64XX SPI Controller Driver" ); |
1692 | MODULE_LICENSE("GPL" ); |
1693 | |