1//===- llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h -----------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file This file declares the GIMatchTableExecutor API, the opcodes supported
10/// by the match table, and some associated data structures used by the
11/// executor's implementation (see `GIMatchTableExecutorImpl.h`).
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_CODEGEN_GLOBALISEL_GIMATCHTABLEEXECUTOR_H
16#define LLVM_CODEGEN_GLOBALISEL_GIMATCHTABLEEXECUTOR_H
17
18#include "llvm/ADT/Bitset.h"
19#include "llvm/ADT/DenseMap.h"
20#include "llvm/ADT/SmallVector.h"
21#include "llvm/CodeGen/GlobalISel/Utils.h"
22#include "llvm/CodeGen/MachineFunction.h"
23#include "llvm/CodeGenTypes/LowLevelType.h"
24#include "llvm/IR/Function.h"
25#include <bitset>
26#include <cstddef>
27#include <cstdint>
28#include <functional>
29#include <initializer_list>
30#include <optional>
31#include <vector>
32
33namespace llvm {
34
35class BlockFrequencyInfo;
36class CodeGenCoverage;
37class MachineBasicBlock;
38class ProfileSummaryInfo;
39class APInt;
40class APFloat;
41class GISelKnownBits;
42class MachineInstr;
43class MachineIRBuilder;
44class MachineInstrBuilder;
45class MachineFunction;
46class MachineOperand;
47class MachineRegisterInfo;
48class RegisterBankInfo;
49class TargetInstrInfo;
50class TargetRegisterInfo;
51
52enum {
53 GICXXPred_Invalid = 0,
54 GICXXCustomAction_Invalid = 0,
55};
56
57/// The MatchTable is encoded as an array of bytes.
58/// Thus, opcodes are expected to be <255.
59///
60/// Operands can be variable-sized, their size is always after their name
61/// in the docs, e.g. "Foo(4)" means that "Foo" takes 4 entries in the table,
62/// so 4 bytes. "Foo()"
63///
64/// As a general rule of thumb:
65/// - Instruction & Operand IDs are ULEB128
66/// - LLT IDs are 1 byte
67/// - Predicates and target opcodes, register and register class IDs are 2
68/// bytes.
69/// - Indexes into the table are 4 bytes.
70/// - Inline constants are 8 bytes
71///
72/// Design notes:
73/// - Inst/Op IDs have to be LEB128 because some targets generate
74/// extremely long patterns which need more than 255 temporaries.
75/// We could just use 2 bytes everytime, but then some targets like
76/// X86/AMDGPU that have no need for it will pay the price all the time.
77enum {
78 /// Begin a try-block to attempt a match and jump to OnFail if it is
79 /// unsuccessful.
80 /// - OnFail(4) - The MatchTable entry at which to resume if the match fails.
81 ///
82 /// FIXME: This ought to take an argument indicating the number of try-blocks
83 /// to exit on failure. It's usually one but the last match attempt of
84 /// a block will need more. The (implemented) alternative is to tack a
85 /// GIM_Reject on the end of each try-block which is simpler but
86 /// requires an extra opcode and iteration in the interpreter on each
87 /// failed match.
88 GIM_Try,
89
90 /// Switch over the opcode on the specified instruction
91 /// - InsnID(ULEB128) - Instruction ID
92 /// - LowerBound(2) - numerically minimum opcode supported
93 /// - UpperBound(2) - numerically maximum + 1 opcode supported
94 /// - Default(4) - failure jump target
95 /// - JumpTable(4)... - (UpperBound - LowerBound) (at least 2) jump targets
96 GIM_SwitchOpcode,
97
98 /// Switch over the LLT on the specified instruction operand
99 /// - InsnID(ULEB128) - Instruction ID
100 /// - OpIdx(ULEB128) - Operand index
101 /// - LowerBound(2) - numerically minimum Type ID supported
102 /// - UpperBound(2) - numerically maximum + 1 Type ID supported
103 /// - Default(4) - failure jump target
104 /// - JumpTable(4)... - (UpperBound - LowerBound) (at least 2) jump targets
105 GIM_SwitchType,
106
107 /// Record the specified instruction.
108 /// The IgnoreCopies variant ignores COPY instructions.
109 /// - NewInsnID(ULEB128) - Instruction ID to define
110 /// - InsnID(ULEB128) - Instruction ID
111 /// - OpIdx(ULEB128) - Operand index
112 GIM_RecordInsn,
113 GIM_RecordInsnIgnoreCopies,
114
115 /// Check the feature bits
116 /// Feature(2) - Expected features
117 GIM_CheckFeatures,
118
119 /// Check the opcode on the specified instruction
120 /// - InsnID(ULEB128) - Instruction ID
121 /// - Opc(2) - Expected opcode
122 GIM_CheckOpcode,
123
124 /// Check the opcode on the specified instruction, checking 2 acceptable
125 /// alternatives.
126 /// - InsnID(ULEB128) - Instruction ID
127 /// - Opc(2) - Expected opcode
128 /// - Opc(2) - Alternative expected opcode
129 GIM_CheckOpcodeIsEither,
130
131 /// Check the instruction has the right number of operands
132 /// - InsnID(ULEB128) - Instruction ID
133 /// - Ops(ULEB128) - Expected number of operands
134 GIM_CheckNumOperands,
135
136 /// Check an immediate predicate on the specified instruction
137 /// - InsnID(ULEB128) - Instruction ID
138 /// - Pred(2) - The predicate to test
139 GIM_CheckI64ImmPredicate,
140 /// Check an immediate predicate on the specified instruction via an APInt.
141 /// - InsnID(ULEB128) - Instruction ID
142 /// - Pred(2) - The predicate to test
143 GIM_CheckAPIntImmPredicate,
144 /// Check a floating point immediate predicate on the specified instruction.
145 /// - InsnID(ULEB128) - Instruction ID
146 /// - Pred(2) - The predicate to test
147 GIM_CheckAPFloatImmPredicate,
148 /// Check an immediate predicate on the specified instruction
149 /// - InsnID(ULEB128) - Instruction ID
150 /// - OpIdx(ULEB128) - Operand index
151 /// - Pred(2) - The predicate to test
152 GIM_CheckImmOperandPredicate,
153
154 /// Check a memory operation has the specified atomic ordering.
155 /// - InsnID(ULEB128) - Instruction ID
156 /// - Ordering(ULEB128) - The AtomicOrdering value
157 GIM_CheckAtomicOrdering,
158 GIM_CheckAtomicOrderingOrStrongerThan,
159 GIM_CheckAtomicOrderingWeakerThan,
160
161 /// Check the size of the memory access for the given machine memory operand.
162 /// - InsnID(ULEB128) - Instruction ID
163 /// - MMOIdx(ULEB128) - MMO index
164 /// - Size(4) - The size in bytes of the memory access
165 GIM_CheckMemorySizeEqualTo,
166
167 /// Check the address space of the memory access for the given machine memory
168 /// operand.
169 /// - InsnID(ULEB128) - Instruction ID
170 /// - MMOIdx(ULEB128) - MMO index
171 /// - NumAddrSpace(ULEB128) - Number of valid address spaces
172 /// - AddrSpaceN(ULEB128) - An allowed space of the memory access
173 /// - AddrSpaceN+1 ...
174 GIM_CheckMemoryAddressSpace,
175
176 /// Check the minimum alignment of the memory access for the given machine
177 /// memory operand.
178 /// - InsnID(ULEB128) - Instruction ID
179 /// - MMOIdx(ULEB128) - MMO index
180 /// - MinAlign(ULEB128) - Minimum acceptable alignment
181 GIM_CheckMemoryAlignment,
182
183 /// Check the size of the memory access for the given machine memory operand
184 /// against the size of an operand.
185 /// - InsnID(ULEB128) - Instruction ID
186 /// - MMOIdx(ULEB128) - MMO index
187 /// - OpIdx(ULEB128) - The operand index to compare the MMO against
188 GIM_CheckMemorySizeEqualToLLT,
189 GIM_CheckMemorySizeLessThanLLT,
190 GIM_CheckMemorySizeGreaterThanLLT,
191
192 /// Check if this is a vector that can be treated as a vector splat
193 /// constant. This is valid for both G_BUILD_VECTOR as well as
194 /// G_BUILD_VECTOR_TRUNC. For AllOnes refers to individual bits, so a -1
195 /// element.
196 /// - InsnID(ULEB128) - Instruction ID
197 GIM_CheckIsBuildVectorAllOnes,
198 GIM_CheckIsBuildVectorAllZeros,
199
200 /// Check a trivial predicate which takes no arguments.
201 /// This can be used by executors to implement custom flags that don't fit in
202 /// target features.
203 /// - Pred(2) - Predicate ID to check.
204 GIM_CheckSimplePredicate,
205
206 /// Check a generic C++ instruction predicate
207 /// - InsnID(ULEB128) - Instruction ID
208 /// - PredicateID(2) - The ID of the predicate function to call
209 GIM_CheckCxxInsnPredicate,
210
211 /// Check if there's no use of the first result.
212 /// - InsnID(ULEB128) - Instruction ID
213 GIM_CheckHasNoUse,
214
215 /// Check the type for the specified operand
216 /// - InsnID(ULEB128) - Instruction ID
217 /// - OpIdx(ULEB128) - Operand index
218 /// - Ty(1) - Expected type
219 GIM_CheckType,
220 /// GIM_CheckType but InsnID is omitted and defaults to zero.
221 GIM_RootCheckType,
222
223 /// Check the type of a pointer to any address space.
224 /// - InsnID(ULEB128) - Instruction ID
225 /// - OpIdx(ULEB128) - Operand index
226 /// - SizeInBits(ULEB128) - The size of the pointer value in bits.
227 GIM_CheckPointerToAny,
228
229 /// Check the register bank for the specified operand
230 /// - InsnID(ULEB128) - Instruction ID
231 /// - OpIdx(ULEB128) - Operand index
232 /// - RC(2) - Expected register bank (specified as a register class)
233 GIM_CheckRegBankForClass,
234 /// GIM_CheckRegBankForClass but InsnID is omitted and defaults to zero.
235 GIM_RootCheckRegBankForClass,
236
237 /// Check the operand matches a complex predicate
238 /// - InsnID(ULEB128) - Instruction ID
239 /// - OpIdx(ULEB128) - Operand index
240 /// - RendererID(2) - The renderer to hold the result
241 /// - Pred(2) - Complex predicate ID
242 GIM_CheckComplexPattern,
243
244 /// Check the operand is a specific integer
245 /// - InsnID(ULEB128) - Instruction ID
246 /// - OpIdx(ULEB128) - Operand index
247 /// - Val(8) Expected integer
248 GIM_CheckConstantInt,
249
250 /// Check the operand is a specific 8-bit signed integer
251 /// - InsnID(ULEB128) - Instruction ID
252 /// - OpIdx(ULEB128) - Operand index
253 /// - Val(1) Expected integer
254 GIM_CheckConstantInt8,
255
256 /// Check the operand is a specific literal integer (i.e. MO.isImm() or
257 /// MO.isCImm() is true).
258 /// - InsnID(ULEB128) - Instruction ID
259 /// - OpIdx(ULEB128) - Operand index
260 /// - Val(8) - Expected integer
261 GIM_CheckLiteralInt,
262
263 /// Check the operand is a specific intrinsic ID
264 /// - InsnID(ULEB128) - Instruction ID
265 /// - OpIdx(ULEB128) - Operand index
266 /// - IID(2) - Expected Intrinsic ID
267 GIM_CheckIntrinsicID,
268
269 /// Check the operand is a specific predicate
270 /// - InsnID(ULEB128) - Instruction ID
271 /// - OpIdx(ULEB128) - Operand index
272 /// - Pred(2) - Expected predicate
273 GIM_CheckCmpPredicate,
274
275 /// Check the specified operand is an MBB
276 /// - InsnID(ULEB128) - Instruction ID
277 /// - OpIdx(ULEB128) - Operand index
278 GIM_CheckIsMBB,
279
280 /// Check the specified operand is an Imm
281 /// - InsnID(ULEB128) - Instruction ID
282 /// - OpIdx(ULEB128) - Operand index
283 GIM_CheckIsImm,
284
285 /// Checks if the matched instructions numbered [1, 1+N) can
286 /// be folded into the root (inst 0).
287 /// - Num(1)
288 GIM_CheckIsSafeToFold,
289
290 /// Check the specified operands are identical.
291 /// The IgnoreCopies variant looks through COPY instructions before
292 /// comparing the operands.
293 /// - InsnID(ULEB128) - Instruction ID
294 /// - OpIdx(ULEB128) - Operand index
295 /// - OtherInsnID(ULEB128) - Other instruction ID
296 /// - OtherOpIdx(ULEB128) - Other operand index
297 GIM_CheckIsSameOperand,
298 GIM_CheckIsSameOperandIgnoreCopies,
299
300 /// Check we can replace all uses of a register with another.
301 /// - OldInsnID(ULEB128)
302 /// - OldOpIdx(ULEB128)
303 /// - NewInsnID(ULEB128)
304 /// - NewOpIdx(ULEB128)
305 GIM_CheckCanReplaceReg,
306
307 /// Check that a matched instruction has, or doesn't have a MIFlag.
308 ///
309 /// - InsnID(ULEB128) - Instruction to check.
310 /// - Flags(4) - (can be one or more flags OR'd together)
311 GIM_MIFlags,
312 GIM_MIFlagsNot,
313
314 /// Predicates with 'let PredicateCodeUsesOperands = 1' need to examine some
315 /// named operands that will be recorded in RecordedOperands. Names of these
316 /// operands are referenced in predicate argument list. Emitter determines
317 /// StoreIdx(corresponds to the order in which names appear in argument list).
318 /// - InsnID(ULEB128) - Instruction ID
319 /// - OpIdx(ULEB128) - Operand index
320 /// - StoreIdx(ULEB128) - Store location in RecordedOperands.
321 GIM_RecordNamedOperand,
322
323 /// Records an operand's register type into the set of temporary types.
324 /// - InsnID(ULEB128) - Instruction ID
325 /// - OpIdx(ULEB128) - Operand index
326 /// - TempTypeIdx(1) - Temp Type Index, always negative.
327 GIM_RecordRegType,
328
329 /// Fail the current try-block, or completely fail to match if there is no
330 /// current try-block.
331 GIM_Reject,
332
333 //=== Renderers ===
334
335 /// Mutate an instruction
336 /// - NewInsnID(ULEB128) - Instruction ID to define
337 /// - OldInsnID(ULEB128) - Instruction ID to mutate
338 /// - NewOpcode(2) - The new opcode to use
339 GIR_MutateOpcode,
340
341 /// Build a new instruction
342 /// - InsnID(ULEB128) - Instruction ID to define
343 /// - Opcode(2) - The new opcode to use
344 GIR_BuildMI,
345 /// GIR_BuildMI but InsnID is omitted and defaults to zero.
346 GIR_BuildRootMI,
347
348 /// Builds a constant and stores its result in a TempReg.
349 /// - TempRegID(ULEB128) - Temp Register to define.
350 /// - Imm(8) - The immediate to add
351 GIR_BuildConstant,
352
353 /// Copy an operand to the specified instruction
354 /// - NewInsnID(ULEB128) - Instruction ID to modify
355 /// - OldInsnID(ULEB128) - Instruction ID to copy from
356 /// - OpIdx(ULEB128) - The operand to copy
357 GIR_Copy,
358 /// GIR_Copy but with both New/OldInsnIDs omitted and defaulting to zero.
359 GIR_RootToRootCopy,
360
361 /// Copy an operand to the specified instruction or add a zero register if the
362 /// operand is a zero immediate.
363 /// - NewInsnID(ULEB128) - Instruction ID to modify
364 /// - OldInsnID(ULEB128) - Instruction ID to copy from
365 /// - OpIdx(ULEB128) - The operand to copy
366 /// - ZeroReg(2) - The zero register to use
367 GIR_CopyOrAddZeroReg,
368 /// Copy an operand to the specified instruction
369 /// - NewInsnID(ULEB128) - Instruction ID to modify
370 /// - OldInsnID(ULEB128) - Instruction ID to copy from
371 /// - OpIdx(ULEB128) - The operand to copy
372 /// - SubRegIdx(2) - The subregister to copy
373 GIR_CopySubReg,
374
375 /// Add an implicit register def to the specified instruction
376 /// - InsnID(ULEB128) - Instruction ID to modify
377 /// - RegNum(2) - The register to add
378 /// - Flags(2) - Register Flags
379 GIR_AddImplicitDef,
380 /// Add an implicit register use to the specified instruction
381 /// - InsnID(ULEB128) - Instruction ID to modify
382 /// - RegNum(2) - The register to add
383 GIR_AddImplicitUse,
384 /// Add an register to the specified instruction
385 /// - InsnID(ULEB128) - Instruction ID to modify
386 /// - RegNum(2) - The register to add
387 /// - Flags(2) - Register Flags
388 GIR_AddRegister,
389
390 /// Adds an intrinsic ID to the specified instruction.
391 /// - InsnID(ULEB128) - Instruction ID to modify
392 /// - IID(2) - Intrinsic ID
393 GIR_AddIntrinsicID,
394
395 /// Marks the implicit def of a register as dead.
396 /// - InsnID(ULEB128) - Instruction ID to modify
397 /// - OpIdx(ULEB128) - The implicit def operand index
398 ///
399 /// OpIdx starts at 0 for the first implicit def.
400 GIR_SetImplicitDefDead,
401
402 /// Set or unset a MIFlag on an instruction.
403 ///
404 /// - InsnID(ULEB128) - Instruction to modify.
405 /// - Flags(4) - (can be one or more flags OR'd together)
406 GIR_SetMIFlags,
407 GIR_UnsetMIFlags,
408
409 /// Copy the MIFlags of a matched instruction into an
410 /// output instruction. The flags are OR'd together.
411 ///
412 /// - InsnID(ULEB128) - Instruction to modify.
413 /// - OldInsnID(ULEB128) - Matched instruction to copy flags from.
414 GIR_CopyMIFlags,
415
416 /// Add a temporary register to the specified instruction
417 /// - InsnID(ULEB128) - Instruction ID to modify
418 /// - TempRegID(ULEB128) - The temporary register ID to add
419 /// - TempRegFlags(2) - The register flags to set
420 GIR_AddTempRegister,
421
422 /// Add a temporary register to the specified instruction without
423 /// setting any flags.
424 /// - InsnID(ULEB128) - Instruction ID to modify
425 /// - TempRegID(ULEB128) - The temporary register ID to add
426 GIR_AddSimpleTempRegister,
427
428 /// Add a temporary register to the specified instruction
429 /// - InsnID(ULEB128) - Instruction ID to modify
430 /// - TempRegID(ULEB128) - The temporary register ID to add
431 /// - TempRegFlags(2) - The register flags to set
432 /// - SubRegIndex(2) - The subregister index to set
433 GIR_AddTempSubRegister,
434
435 /// Add an immediate to the specified instruction
436 /// - InsnID(ULEB128) - Instruction ID to modify
437 /// - Imm(8) - The immediate to add
438 GIR_AddImm,
439
440 /// Add signed 8 bit immediate to the specified instruction
441 /// - InsnID(ULEB128) - Instruction ID to modify
442 /// - Imm(1) - The immediate to add
443 GIR_AddImm8,
444
445 /// Add an CImm to the specified instruction
446 /// - InsnID(ULEB128) - Instruction ID to modify
447 /// - Ty(1) - Type of the constant immediate.
448 /// - Imm(8) - The immediate to add
449 GIR_AddCImm,
450
451 /// Render complex operands to the specified instruction
452 /// - InsnID(ULEB128) - Instruction ID to modify
453 /// - RendererID(2) - The renderer to call
454 GIR_ComplexRenderer,
455 /// Render sub-operands of complex operands to the specified instruction
456 /// - InsnID(ULEB128) - Instruction ID to modify
457 /// - RendererID(2) - The renderer to call
458 /// - RenderOpID(ULEB128) - The suboperand to render.
459 GIR_ComplexSubOperandRenderer,
460 /// Render subregisters of suboperands of complex operands to the
461 /// specified instruction
462 /// - InsnID(ULEB128) - Instruction ID to modify
463 /// - RendererID(2) - The renderer to call
464 /// - RenderOpID(ULEB128) - The suboperand to render
465 /// - SubRegIdx(2) - The subregister to extract
466 GIR_ComplexSubOperandSubRegRenderer,
467
468 /// Render operands to the specified instruction using a custom function
469 /// - InsnID(ULEB128) - Instruction ID to modify
470 /// - OldInsnID(ULEB128) - Instruction ID to get the matched operand from
471 /// - RendererFnID(2) - Custom renderer function to call
472 GIR_CustomRenderer,
473
474 /// Calls a C++ function to perform an action when a match is complete.
475 /// The MatcherState is passed to the function to allow it to modify
476 /// instructions.
477 /// This is less constrained than a custom renderer and can update
478 /// instructions
479 /// in the state.
480 /// - FnID(2) - The function to call.
481 /// TODO: Remove this at some point when combiners aren't reliant on it. It's
482 /// a bit of a hack.
483 GIR_CustomAction,
484
485 /// Render operands to the specified instruction using a custom function,
486 /// reading from a specific operand.
487 /// - InsnID(ULEB128) - Instruction ID to modify
488 /// - OldInsnID(ULEB128) - Instruction ID to get the matched operand from
489 /// - OpIdx(ULEB128) - Operand index in OldInsnID the render function should
490 /// read
491 /// from..
492 /// - RendererFnID(2) - Custom renderer function to call
493 GIR_CustomOperandRenderer,
494
495 /// Render a G_CONSTANT operator as a sign-extended immediate.
496 /// - NewInsnID(ULEB128) - Instruction ID to modify
497 /// - OldInsnID(ULEB128) - Instruction ID to copy from
498 /// The operand index is implicitly 1.
499 GIR_CopyConstantAsSImm,
500
501 /// Render a G_FCONSTANT operator as a sign-extended immediate.
502 /// - NewInsnID(ULEB128) - Instruction ID to modify
503 /// - OldInsnID(ULEB128) - Instruction ID to copy from
504 /// The operand index is implicitly 1.
505 GIR_CopyFConstantAsFPImm,
506
507 /// Constrain an instruction operand to a register class.
508 /// - InsnID(ULEB128) - Instruction ID to modify
509 /// - OpIdx(ULEB128) - Operand index
510 /// - RCEnum(2) - Register class enumeration value
511 GIR_ConstrainOperandRC,
512
513 /// Constrain an instructions operands according to the instruction
514 /// description.
515 /// - InsnID(ULEB128) - Instruction ID to modify
516 GIR_ConstrainSelectedInstOperands,
517 /// GIR_ConstrainSelectedInstOperands but InsnID is omitted and defaults to
518 /// zero.
519 GIR_RootConstrainSelectedInstOperands,
520
521 /// Merge all memory operands into instruction.
522 /// - InsnID(ULEB128) - Instruction ID to modify
523 /// - NumInsnID(1) - Number of instruction IDs following this argument
524 /// - MergeInsnID(ULEB128)... - One or more Instruction ID to merge into the
525 /// result.
526 GIR_MergeMemOperands,
527
528 /// Erase from parent.
529 /// - InsnID(ULEB128) - Instruction ID to erase
530 GIR_EraseFromParent,
531
532 /// Combines both a GIR_EraseFromParent 0 + GIR_Done
533 GIR_EraseRootFromParent_Done,
534
535 /// Create a new temporary register that's not constrained.
536 /// - TempRegID(ULEB128) - The temporary register ID to initialize.
537 /// - Ty(1) - Expected type
538 GIR_MakeTempReg,
539
540 /// Replaces all references to a register from an instruction
541 /// with another register from another instruction.
542 /// - OldInsnID(ULEB128)
543 /// - OldOpIdx(ULEB128)
544 /// - NewInsnID(ULEB128)
545 /// - NewOpIdx(ULEB128)
546 GIR_ReplaceReg,
547
548 /// Replaces all references to a register with a temporary register.
549 /// - OldInsnID(ULEB128)
550 /// - OldOpIdx(ULEB128)
551 /// - TempRegIdx(ULEB128)
552 GIR_ReplaceRegWithTempReg,
553
554 /// A successful emission
555 GIR_Done,
556
557 /// Increment the rule coverage counter.
558 /// - RuleID(4) - The ID of the rule that was covered.
559 GIR_Coverage,
560
561 /// Keeping track of the number of the GI opcodes. Must be the last entry.
562 GIU_NumOpcodes,
563};
564
565/// Provides the logic to execute GlobalISel match tables, which are used by the
566/// instruction selector and instruction combiners as their engine to match and
567/// apply MIR patterns.
568class GIMatchTableExecutor {
569public:
570 virtual ~GIMatchTableExecutor() = default;
571
572 CodeGenCoverage *CoverageInfo = nullptr;
573 GISelKnownBits *KB = nullptr;
574 MachineFunction *MF = nullptr;
575 ProfileSummaryInfo *PSI = nullptr;
576 BlockFrequencyInfo *BFI = nullptr;
577 // For some predicates, we need to track the current MBB.
578 MachineBasicBlock *CurMBB = nullptr;
579
580 virtual void setupGeneratedPerFunctionState(MachineFunction &MF) = 0;
581
582 /// Setup per-MF executor state.
583 virtual void setupMF(MachineFunction &mf, GISelKnownBits *kb,
584 CodeGenCoverage *covinfo = nullptr,
585 ProfileSummaryInfo *psi = nullptr,
586 BlockFrequencyInfo *bfi = nullptr) {
587 CoverageInfo = covinfo;
588 KB = kb;
589 MF = &mf;
590 PSI = psi;
591 BFI = bfi;
592 CurMBB = nullptr;
593 setupGeneratedPerFunctionState(mf);
594 }
595
596protected:
597 using ComplexRendererFns =
598 std::optional<SmallVector<std::function<void(MachineInstrBuilder &)>, 4>>;
599 using RecordedMIVector = SmallVector<MachineInstr *, 4>;
600 using NewMIVector = SmallVector<MachineInstrBuilder, 4>;
601
602 struct MatcherState {
603 std::vector<ComplexRendererFns::value_type> Renderers;
604 RecordedMIVector MIs;
605 DenseMap<unsigned, unsigned> TempRegisters;
606 /// Named operands that predicate with 'let PredicateCodeUsesOperands = 1'
607 /// referenced in its argument list. Operands are inserted at index set by
608 /// emitter, it corresponds to the order in which names appear in argument
609 /// list. Currently such predicates don't have more then 3 arguments.
610 std::array<const MachineOperand *, 3> RecordedOperands;
611
612 /// Types extracted from an instruction's operand.
613 /// Whenever a type index is negative, we look here instead.
614 SmallVector<LLT, 4> RecordedTypes;
615
616 MatcherState(unsigned MaxRenderers);
617 };
618
619 bool shouldOptForSize(const MachineFunction *MF) const {
620 const auto &F = MF->getFunction();
621 return F.hasOptSize() || F.hasMinSize() ||
622 (PSI && BFI && CurMBB && llvm::shouldOptForSize(MBB: *CurMBB, PSI, BFI));
623 }
624
625public:
626 template <class PredicateBitset, class ComplexMatcherMemFn,
627 class CustomRendererFn>
628 struct ExecInfoTy {
629 ExecInfoTy(const LLT *TypeObjects, size_t NumTypeObjects,
630 const PredicateBitset *FeatureBitsets,
631 const ComplexMatcherMemFn *ComplexPredicates,
632 const CustomRendererFn *CustomRenderers)
633 : TypeObjects(TypeObjects), FeatureBitsets(FeatureBitsets),
634 ComplexPredicates(ComplexPredicates),
635 CustomRenderers(CustomRenderers) {
636
637 for (size_t I = 0; I < NumTypeObjects; ++I)
638 TypeIDMap[TypeObjects[I]] = I;
639 }
640 const LLT *TypeObjects;
641 const PredicateBitset *FeatureBitsets;
642 const ComplexMatcherMemFn *ComplexPredicates;
643 const CustomRendererFn *CustomRenderers;
644
645 SmallDenseMap<LLT, unsigned, 64> TypeIDMap;
646 };
647
648protected:
649 GIMatchTableExecutor();
650
651 /// Execute a given matcher table and return true if the match was successful
652 /// and false otherwise.
653 template <class TgtExecutor, class PredicateBitset, class ComplexMatcherMemFn,
654 class CustomRendererFn>
655 bool executeMatchTable(TgtExecutor &Exec, MatcherState &State,
656 const ExecInfoTy<PredicateBitset, ComplexMatcherMemFn,
657 CustomRendererFn> &ExecInfo,
658 MachineIRBuilder &Builder, const uint8_t *MatchTable,
659 const TargetInstrInfo &TII, MachineRegisterInfo &MRI,
660 const TargetRegisterInfo &TRI,
661 const RegisterBankInfo &RBI,
662 const PredicateBitset &AvailableFeatures,
663 CodeGenCoverage *CoverageInfo) const;
664
665 virtual const uint8_t *getMatchTable() const {
666 llvm_unreachable("Should have been overridden by tablegen if used");
667 }
668
669 virtual bool testImmPredicate_I64(unsigned, int64_t) const {
670 llvm_unreachable(
671 "Subclasses must override this with a tablegen-erated function");
672 }
673 virtual bool testImmPredicate_APInt(unsigned, const APInt &) const {
674 llvm_unreachable(
675 "Subclasses must override this with a tablegen-erated function");
676 }
677 virtual bool testImmPredicate_APFloat(unsigned, const APFloat &) const {
678 llvm_unreachable(
679 "Subclasses must override this with a tablegen-erated function");
680 }
681 virtual bool testMIPredicate_MI(unsigned, const MachineInstr &,
682 const MatcherState &State) const {
683 llvm_unreachable(
684 "Subclasses must override this with a tablegen-erated function");
685 }
686
687 virtual bool testSimplePredicate(unsigned) const {
688 llvm_unreachable("Subclass does not implement testSimplePredicate!");
689 }
690
691 virtual void runCustomAction(unsigned, const MatcherState &State,
692 NewMIVector &OutMIs) const {
693 llvm_unreachable("Subclass does not implement runCustomAction!");
694 }
695
696 bool isOperandImmEqual(const MachineOperand &MO, int64_t Value,
697 const MachineRegisterInfo &MRI,
698 bool Splat = false) const;
699
700 /// Return true if the specified operand is a G_PTR_ADD with a G_CONSTANT on
701 /// the right-hand side. GlobalISel's separation of pointer and integer types
702 /// means that we don't need to worry about G_OR with equivalent semantics.
703 bool isBaseWithConstantOffset(const MachineOperand &Root,
704 const MachineRegisterInfo &MRI) const;
705
706 /// Return true if MI can obviously be folded into IntoMI.
707 /// MI and IntoMI do not need to be in the same basic blocks, but MI must
708 /// preceed IntoMI.
709 bool isObviouslySafeToFold(MachineInstr &MI, MachineInstr &IntoMI) const;
710
711 template <typename Ty> static Ty readBytesAs(const uint8_t *MatchTable) {
712 Ty Ret;
713 memcpy(&Ret, MatchTable, sizeof(Ret));
714 return Ret;
715 }
716};
717
718} // end namespace llvm
719
720#endif // LLVM_CODEGEN_GLOBALISEL_GIMATCHTABLEEXECUTOR_H
721

source code of llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h