1 | //===- RegisterScavenging.h - Machine register scavenging -------*- C++ -*-===// |
2 | // |
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | // See https://llvm.org/LICENSE.txt for license information. |
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | // |
7 | //===----------------------------------------------------------------------===// |
8 | // |
9 | /// \file |
10 | /// This file declares the machine register scavenger class. It can provide |
11 | /// information such as unused register at any point in a machine basic block. |
12 | /// It also provides a mechanism to make registers available by evicting them |
13 | /// to spill slots. |
14 | // |
15 | //===----------------------------------------------------------------------===// |
16 | |
17 | #ifndef LLVM_CODEGEN_REGISTERSCAVENGING_H |
18 | #define LLVM_CODEGEN_REGISTERSCAVENGING_H |
19 | |
20 | #include "llvm/ADT/BitVector.h" |
21 | #include "llvm/ADT/SmallVector.h" |
22 | #include "llvm/CodeGen/LiveRegUnits.h" |
23 | #include "llvm/CodeGen/MachineBasicBlock.h" |
24 | #include "llvm/CodeGen/MachineRegisterInfo.h" |
25 | #include "llvm/MC/LaneBitmask.h" |
26 | |
27 | namespace llvm { |
28 | |
29 | class MachineInstr; |
30 | class TargetInstrInfo; |
31 | class TargetRegisterClass; |
32 | class TargetRegisterInfo; |
33 | |
34 | class RegScavenger { |
35 | const TargetRegisterInfo *TRI = nullptr; |
36 | const TargetInstrInfo *TII = nullptr; |
37 | MachineRegisterInfo *MRI = nullptr; |
38 | MachineBasicBlock *MBB = nullptr; |
39 | MachineBasicBlock::iterator MBBI; |
40 | |
41 | /// Information on scavenged registers (held in a spill slot). |
42 | struct ScavengedInfo { |
43 | ScavengedInfo(int FI = -1) : FrameIndex(FI) {} |
44 | |
45 | /// A spill slot used for scavenging a register post register allocation. |
46 | int FrameIndex; |
47 | |
48 | /// If non-zero, the specific register is currently being |
49 | /// scavenged. That is, it is spilled to this scavenging stack slot. |
50 | Register Reg; |
51 | |
52 | /// The instruction that restores the scavenged register from stack. |
53 | const MachineInstr *Restore = nullptr; |
54 | }; |
55 | |
56 | /// A vector of information on scavenged registers. |
57 | SmallVector<ScavengedInfo, 2> Scavenged; |
58 | |
59 | LiveRegUnits LiveUnits; |
60 | |
61 | public: |
62 | RegScavenger() = default; |
63 | |
64 | /// Record that \p Reg is in use at scavenging index \p FI. This is for |
65 | /// targets which need to directly manage the spilling process, and need to |
66 | /// update the scavenger's internal state. It's expected this be called a |
67 | /// second time with \p Restore set to a non-null value, so that the |
68 | /// externally inserted restore instruction resets the scavenged slot |
69 | /// liveness when encountered. |
70 | void assignRegToScavengingIndex(int FI, Register Reg, |
71 | MachineInstr *Restore = nullptr) { |
72 | for (ScavengedInfo &Slot : Scavenged) { |
73 | if (Slot.FrameIndex == FI) { |
74 | assert(!Slot.Reg || Slot.Reg == Reg); |
75 | Slot.Reg = Reg; |
76 | Slot.Restore = Restore; |
77 | return; |
78 | } |
79 | } |
80 | |
81 | llvm_unreachable("did not find scavenging index" ); |
82 | } |
83 | |
84 | /// Start tracking liveness from the begin of basic block \p MBB. |
85 | void enterBasicBlock(MachineBasicBlock &MBB); |
86 | |
87 | /// Start tracking liveness from the end of basic block \p MBB. |
88 | /// Use backward() to move towards the beginning of the block. |
89 | void enterBasicBlockEnd(MachineBasicBlock &MBB); |
90 | |
91 | /// Update internal register state and move MBB iterator backwards. This |
92 | /// method gives precise results even in the absence of kill flags. |
93 | void backward(); |
94 | |
95 | /// Call backward() to update internal register state to just before \p *I. |
96 | void backward(MachineBasicBlock::iterator I) { |
97 | while (MBBI != I) |
98 | backward(); |
99 | } |
100 | |
101 | /// Return if a specific register is currently used. |
102 | bool isRegUsed(Register Reg, bool includeReserved = true) const; |
103 | |
104 | /// Return all available registers in the register class in Mask. |
105 | BitVector getRegsAvailable(const TargetRegisterClass *RC); |
106 | |
107 | /// Find an unused register of the specified register class. |
108 | /// Return 0 if none is found. |
109 | Register FindUnusedReg(const TargetRegisterClass *RC) const; |
110 | |
111 | /// Add a scavenging frame index. |
112 | void addScavengingFrameIndex(int FI) { |
113 | Scavenged.push_back(Elt: ScavengedInfo(FI)); |
114 | } |
115 | |
116 | /// Query whether a frame index is a scavenging frame index. |
117 | bool isScavengingFrameIndex(int FI) const { |
118 | for (const ScavengedInfo &SI : Scavenged) |
119 | if (SI.FrameIndex == FI) |
120 | return true; |
121 | |
122 | return false; |
123 | } |
124 | |
125 | /// Get an array of scavenging frame indices. |
126 | void getScavengingFrameIndices(SmallVectorImpl<int> &A) const { |
127 | for (const ScavengedInfo &I : Scavenged) |
128 | if (I.FrameIndex >= 0) |
129 | A.push_back(Elt: I.FrameIndex); |
130 | } |
131 | |
132 | /// Make a register of the specific register class available from the current |
133 | /// position backwards to the place before \p To. If \p RestoreAfter is true |
134 | /// this includes the instruction following the current position. |
135 | /// SPAdj is the stack adjustment due to call frame, it's passed along to |
136 | /// eliminateFrameIndex(). |
137 | /// Returns the scavenged register. |
138 | /// |
139 | /// If \p AllowSpill is false, fail if a spill is required to make the |
140 | /// register available, and return NoRegister. |
141 | Register scavengeRegisterBackwards(const TargetRegisterClass &RC, |
142 | MachineBasicBlock::iterator To, |
143 | bool RestoreAfter, int SPAdj, |
144 | bool AllowSpill = true); |
145 | |
146 | /// Tell the scavenger a register is used. |
147 | void setRegUsed(Register Reg, LaneBitmask LaneMask = LaneBitmask::getAll()); |
148 | |
149 | private: |
150 | /// Returns true if a register is reserved. It is never "unused". |
151 | bool isReserved(Register Reg) const { return MRI->isReserved(PhysReg: Reg); } |
152 | |
153 | /// Initialize RegisterScavenger. |
154 | void init(MachineBasicBlock &MBB); |
155 | |
156 | /// Spill a register after position \p After and reload it before position |
157 | /// \p UseMI. |
158 | ScavengedInfo &spill(Register Reg, const TargetRegisterClass &RC, int SPAdj, |
159 | MachineBasicBlock::iterator Before, |
160 | MachineBasicBlock::iterator &UseMI); |
161 | }; |
162 | |
163 | /// Replaces all frame index virtual registers with physical registers. Uses the |
164 | /// register scavenger to find an appropriate register to use. |
165 | void scavengeFrameVirtualRegs(MachineFunction &MF, RegScavenger &RS); |
166 | |
167 | } // end namespace llvm |
168 | |
169 | #endif // LLVM_CODEGEN_REGISTERSCAVENGING_H |
170 | |