1 | //===-- LiveVariables.cpp - Live Variable Analysis for Machine Code -------===// |
2 | // |
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | // See https://llvm.org/LICENSE.txt for license information. |
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | // |
7 | //===----------------------------------------------------------------------===// |
8 | // |
9 | // This file implements the LiveVariable analysis pass. For each machine |
10 | // instruction in the function, this pass calculates the set of registers that |
11 | // are immediately dead after the instruction (i.e., the instruction calculates |
12 | // the value, but it is never used) and the set of registers that are used by |
13 | // the instruction, but are never used after the instruction (i.e., they are |
14 | // killed). |
15 | // |
16 | // This class computes live variables using a sparse implementation based on |
17 | // the machine code SSA form. This class computes live variable information for |
18 | // each virtual and _register allocatable_ physical register in a function. It |
19 | // uses the dominance properties of SSA form to efficiently compute live |
20 | // variables for virtual registers, and assumes that physical registers are only |
21 | // live within a single basic block (allowing it to do a single local analysis |
22 | // to resolve physical register lifetimes in each basic block). If a physical |
23 | // register is not register allocatable, it is not tracked. This is useful for |
24 | // things like the stack pointer and condition codes. |
25 | // |
26 | //===----------------------------------------------------------------------===// |
27 | |
28 | #include "llvm/CodeGen/LiveVariables.h" |
29 | #include "llvm/ADT/DenseSet.h" |
30 | #include "llvm/ADT/DepthFirstIterator.h" |
31 | #include "llvm/ADT/STLExtras.h" |
32 | #include "llvm/ADT/SmallPtrSet.h" |
33 | #include "llvm/ADT/SmallSet.h" |
34 | #include "llvm/CodeGen/MachineInstr.h" |
35 | #include "llvm/CodeGen/MachineRegisterInfo.h" |
36 | #include "llvm/CodeGen/Passes.h" |
37 | #include "llvm/Config/llvm-config.h" |
38 | #include "llvm/Support/Debug.h" |
39 | #include "llvm/Support/ErrorHandling.h" |
40 | #include "llvm/Support/raw_ostream.h" |
41 | #include <algorithm> |
42 | using namespace llvm; |
43 | |
44 | char LiveVariables::ID = 0; |
45 | char &llvm::LiveVariablesID = LiveVariables::ID; |
46 | INITIALIZE_PASS_BEGIN(LiveVariables, "livevars" , |
47 | "Live Variable Analysis" , false, false) |
48 | INITIALIZE_PASS_DEPENDENCY(UnreachableMachineBlockElim) |
49 | INITIALIZE_PASS_END(LiveVariables, "livevars" , |
50 | "Live Variable Analysis" , false, false) |
51 | |
52 | |
53 | void LiveVariables::getAnalysisUsage(AnalysisUsage &AU) const { |
54 | AU.addRequiredID(ID&: UnreachableMachineBlockElimID); |
55 | AU.setPreservesAll(); |
56 | MachineFunctionPass::getAnalysisUsage(AU); |
57 | } |
58 | |
59 | MachineInstr * |
60 | LiveVariables::VarInfo::findKill(const MachineBasicBlock *MBB) const { |
61 | for (MachineInstr *MI : Kills) |
62 | if (MI->getParent() == MBB) |
63 | return MI; |
64 | return nullptr; |
65 | } |
66 | |
67 | #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) |
68 | LLVM_DUMP_METHOD void LiveVariables::VarInfo::dump() const { |
69 | dbgs() << " Alive in blocks: " ; |
70 | for (unsigned AB : AliveBlocks) |
71 | dbgs() << AB << ", " ; |
72 | dbgs() << "\n Killed by:" ; |
73 | if (Kills.empty()) |
74 | dbgs() << " No instructions.\n" ; |
75 | else { |
76 | for (unsigned i = 0, e = Kills.size(); i != e; ++i) |
77 | dbgs() << "\n #" << i << ": " << *Kills[i]; |
78 | dbgs() << "\n" ; |
79 | } |
80 | } |
81 | #endif |
82 | |
83 | /// getVarInfo - Get (possibly creating) a VarInfo object for the given vreg. |
84 | LiveVariables::VarInfo &LiveVariables::getVarInfo(Register Reg) { |
85 | assert(Reg.isVirtual() && "getVarInfo: not a virtual register!" ); |
86 | VirtRegInfo.grow(n: Reg); |
87 | return VirtRegInfo[Reg]; |
88 | } |
89 | |
90 | void LiveVariables::MarkVirtRegAliveInBlock( |
91 | VarInfo &VRInfo, MachineBasicBlock *DefBlock, MachineBasicBlock *MBB, |
92 | SmallVectorImpl<MachineBasicBlock *> &WorkList) { |
93 | unsigned BBNum = MBB->getNumber(); |
94 | |
95 | // Check to see if this basic block is one of the killing blocks. If so, |
96 | // remove it. |
97 | for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i) |
98 | if (VRInfo.Kills[i]->getParent() == MBB) { |
99 | VRInfo.Kills.erase(position: VRInfo.Kills.begin()+i); // Erase entry |
100 | break; |
101 | } |
102 | |
103 | if (MBB == DefBlock) return; // Terminate recursion |
104 | |
105 | if (VRInfo.AliveBlocks.test(Idx: BBNum)) |
106 | return; // We already know the block is live |
107 | |
108 | // Mark the variable known alive in this bb |
109 | VRInfo.AliveBlocks.set(BBNum); |
110 | |
111 | assert(MBB != &MF->front() && "Can't find reaching def for virtreg" ); |
112 | WorkList.insert(I: WorkList.end(), From: MBB->pred_rbegin(), To: MBB->pred_rend()); |
113 | } |
114 | |
115 | void LiveVariables::MarkVirtRegAliveInBlock(VarInfo &VRInfo, |
116 | MachineBasicBlock *DefBlock, |
117 | MachineBasicBlock *MBB) { |
118 | SmallVector<MachineBasicBlock *, 16> WorkList; |
119 | MarkVirtRegAliveInBlock(VRInfo, DefBlock, MBB, WorkList); |
120 | |
121 | while (!WorkList.empty()) { |
122 | MachineBasicBlock *Pred = WorkList.pop_back_val(); |
123 | MarkVirtRegAliveInBlock(VRInfo, DefBlock, MBB: Pred, WorkList); |
124 | } |
125 | } |
126 | |
127 | void LiveVariables::HandleVirtRegUse(Register Reg, MachineBasicBlock *MBB, |
128 | MachineInstr &MI) { |
129 | assert(MRI->getVRegDef(Reg) && "Register use before def!" ); |
130 | |
131 | unsigned BBNum = MBB->getNumber(); |
132 | |
133 | VarInfo &VRInfo = getVarInfo(Reg); |
134 | |
135 | // Check to see if this basic block is already a kill block. |
136 | if (!VRInfo.Kills.empty() && VRInfo.Kills.back()->getParent() == MBB) { |
137 | // Yes, this register is killed in this basic block already. Increase the |
138 | // live range by updating the kill instruction. |
139 | VRInfo.Kills.back() = &MI; |
140 | return; |
141 | } |
142 | |
143 | #ifndef NDEBUG |
144 | for (MachineInstr *Kill : VRInfo.Kills) |
145 | assert(Kill->getParent() != MBB && "entry should be at end!" ); |
146 | #endif |
147 | |
148 | // This situation can occur: |
149 | // |
150 | // ,------. |
151 | // | | |
152 | // | v |
153 | // | t2 = phi ... t1 ... |
154 | // | | |
155 | // | v |
156 | // | t1 = ... |
157 | // | ... = ... t1 ... |
158 | // | | |
159 | // `------' |
160 | // |
161 | // where there is a use in a PHI node that's a predecessor to the defining |
162 | // block. We don't want to mark all predecessors as having the value "alive" |
163 | // in this case. |
164 | if (MBB == MRI->getVRegDef(Reg)->getParent()) |
165 | return; |
166 | |
167 | // Add a new kill entry for this basic block. If this virtual register is |
168 | // already marked as alive in this basic block, that means it is alive in at |
169 | // least one of the successor blocks, it's not a kill. |
170 | if (!VRInfo.AliveBlocks.test(Idx: BBNum)) |
171 | VRInfo.Kills.push_back(x: &MI); |
172 | |
173 | // Update all dominating blocks to mark them as "known live". |
174 | for (MachineBasicBlock *Pred : MBB->predecessors()) |
175 | MarkVirtRegAliveInBlock(VRInfo, DefBlock: MRI->getVRegDef(Reg)->getParent(), MBB: Pred); |
176 | } |
177 | |
178 | void LiveVariables::HandleVirtRegDef(Register Reg, MachineInstr &MI) { |
179 | VarInfo &VRInfo = getVarInfo(Reg); |
180 | |
181 | if (VRInfo.AliveBlocks.empty()) |
182 | // If vr is not alive in any block, then defaults to dead. |
183 | VRInfo.Kills.push_back(x: &MI); |
184 | } |
185 | |
186 | /// FindLastPartialDef - Return the last partial def of the specified register. |
187 | /// Also returns the sub-registers that're defined by the instruction. |
188 | MachineInstr * |
189 | LiveVariables::FindLastPartialDef(Register Reg, |
190 | SmallSet<unsigned, 4> &PartDefRegs) { |
191 | unsigned LastDefReg = 0; |
192 | unsigned LastDefDist = 0; |
193 | MachineInstr *LastDef = nullptr; |
194 | for (MCPhysReg SubReg : TRI->subregs(Reg)) { |
195 | MachineInstr *Def = PhysRegDef[SubReg]; |
196 | if (!Def) |
197 | continue; |
198 | unsigned Dist = DistanceMap[Def]; |
199 | if (Dist > LastDefDist) { |
200 | LastDefReg = SubReg; |
201 | LastDef = Def; |
202 | LastDefDist = Dist; |
203 | } |
204 | } |
205 | |
206 | if (!LastDef) |
207 | return nullptr; |
208 | |
209 | PartDefRegs.insert(V: LastDefReg); |
210 | for (MachineOperand &MO : LastDef->all_defs()) { |
211 | if (MO.getReg() == 0) |
212 | continue; |
213 | Register DefReg = MO.getReg(); |
214 | if (TRI->isSubRegister(RegA: Reg, RegB: DefReg)) { |
215 | for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg: DefReg)) |
216 | PartDefRegs.insert(V: SubReg); |
217 | } |
218 | } |
219 | return LastDef; |
220 | } |
221 | |
222 | /// HandlePhysRegUse - Turn previous partial def's into read/mod/writes. Add |
223 | /// implicit defs to a machine instruction if there was an earlier def of its |
224 | /// super-register. |
225 | void LiveVariables::HandlePhysRegUse(Register Reg, MachineInstr &MI) { |
226 | MachineInstr *LastDef = PhysRegDef[Reg]; |
227 | // If there was a previous use or a "full" def all is well. |
228 | if (!LastDef && !PhysRegUse[Reg]) { |
229 | // Otherwise, the last sub-register def implicitly defines this register. |
230 | // e.g. |
231 | // AH = |
232 | // AL = ... implicit-def EAX, implicit killed AH |
233 | // = AH |
234 | // ... |
235 | // = EAX |
236 | // All of the sub-registers must have been defined before the use of Reg! |
237 | SmallSet<unsigned, 4> PartDefRegs; |
238 | MachineInstr *LastPartialDef = FindLastPartialDef(Reg, PartDefRegs); |
239 | // If LastPartialDef is NULL, it must be using a livein register. |
240 | if (LastPartialDef) { |
241 | LastPartialDef->addOperand(Op: MachineOperand::CreateReg(Reg, isDef: true/*IsDef*/, |
242 | isImp: true/*IsImp*/)); |
243 | PhysRegDef[Reg] = LastPartialDef; |
244 | SmallSet<unsigned, 8> Processed; |
245 | for (MCPhysReg SubReg : TRI->subregs(Reg)) { |
246 | if (Processed.count(V: SubReg)) |
247 | continue; |
248 | if (PartDefRegs.count(V: SubReg)) |
249 | continue; |
250 | // This part of Reg was defined before the last partial def. It's killed |
251 | // here. |
252 | LastPartialDef->addOperand(Op: MachineOperand::CreateReg(Reg: SubReg, |
253 | isDef: false/*IsDef*/, |
254 | isImp: true/*IsImp*/)); |
255 | PhysRegDef[SubReg] = LastPartialDef; |
256 | for (MCPhysReg SS : TRI->subregs(Reg: SubReg)) |
257 | Processed.insert(V: SS); |
258 | } |
259 | } |
260 | } else if (LastDef && !PhysRegUse[Reg] && |
261 | !LastDef->findRegisterDefOperand(Reg, /*TRI=*/nullptr)) |
262 | // Last def defines the super register, add an implicit def of reg. |
263 | LastDef->addOperand(Op: MachineOperand::CreateReg(Reg, isDef: true/*IsDef*/, |
264 | isImp: true/*IsImp*/)); |
265 | |
266 | // Remember this use. |
267 | for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg)) |
268 | PhysRegUse[SubReg] = &MI; |
269 | } |
270 | |
271 | /// FindLastRefOrPartRef - Return the last reference or partial reference of |
272 | /// the specified register. |
273 | MachineInstr *LiveVariables::FindLastRefOrPartRef(Register Reg) { |
274 | MachineInstr *LastDef = PhysRegDef[Reg]; |
275 | MachineInstr *LastUse = PhysRegUse[Reg]; |
276 | if (!LastDef && !LastUse) |
277 | return nullptr; |
278 | |
279 | MachineInstr *LastRefOrPartRef = LastUse ? LastUse : LastDef; |
280 | unsigned LastRefOrPartRefDist = DistanceMap[LastRefOrPartRef]; |
281 | unsigned LastPartDefDist = 0; |
282 | for (MCPhysReg SubReg : TRI->subregs(Reg)) { |
283 | MachineInstr *Def = PhysRegDef[SubReg]; |
284 | if (Def && Def != LastDef) { |
285 | // There was a def of this sub-register in between. This is a partial |
286 | // def, keep track of the last one. |
287 | unsigned Dist = DistanceMap[Def]; |
288 | if (Dist > LastPartDefDist) |
289 | LastPartDefDist = Dist; |
290 | } else if (MachineInstr *Use = PhysRegUse[SubReg]) { |
291 | unsigned Dist = DistanceMap[Use]; |
292 | if (Dist > LastRefOrPartRefDist) { |
293 | LastRefOrPartRefDist = Dist; |
294 | LastRefOrPartRef = Use; |
295 | } |
296 | } |
297 | } |
298 | |
299 | return LastRefOrPartRef; |
300 | } |
301 | |
302 | bool LiveVariables::HandlePhysRegKill(Register Reg, MachineInstr *MI) { |
303 | MachineInstr *LastDef = PhysRegDef[Reg]; |
304 | MachineInstr *LastUse = PhysRegUse[Reg]; |
305 | if (!LastDef && !LastUse) |
306 | return false; |
307 | |
308 | MachineInstr *LastRefOrPartRef = LastUse ? LastUse : LastDef; |
309 | unsigned LastRefOrPartRefDist = DistanceMap[LastRefOrPartRef]; |
310 | // The whole register is used. |
311 | // AL = |
312 | // AH = |
313 | // |
314 | // = AX |
315 | // = AL, implicit killed AX |
316 | // AX = |
317 | // |
318 | // Or whole register is defined, but not used at all. |
319 | // dead AX = |
320 | // ... |
321 | // AX = |
322 | // |
323 | // Or whole register is defined, but only partly used. |
324 | // dead AX = implicit-def AL |
325 | // = killed AL |
326 | // AX = |
327 | MachineInstr *LastPartDef = nullptr; |
328 | unsigned LastPartDefDist = 0; |
329 | SmallSet<unsigned, 8> PartUses; |
330 | for (MCPhysReg SubReg : TRI->subregs(Reg)) { |
331 | MachineInstr *Def = PhysRegDef[SubReg]; |
332 | if (Def && Def != LastDef) { |
333 | // There was a def of this sub-register in between. This is a partial |
334 | // def, keep track of the last one. |
335 | unsigned Dist = DistanceMap[Def]; |
336 | if (Dist > LastPartDefDist) { |
337 | LastPartDefDist = Dist; |
338 | LastPartDef = Def; |
339 | } |
340 | continue; |
341 | } |
342 | if (MachineInstr *Use = PhysRegUse[SubReg]) { |
343 | for (MCPhysReg SS : TRI->subregs_inclusive(Reg: SubReg)) |
344 | PartUses.insert(V: SS); |
345 | unsigned Dist = DistanceMap[Use]; |
346 | if (Dist > LastRefOrPartRefDist) { |
347 | LastRefOrPartRefDist = Dist; |
348 | LastRefOrPartRef = Use; |
349 | } |
350 | } |
351 | } |
352 | |
353 | if (!PhysRegUse[Reg]) { |
354 | // Partial uses. Mark register def dead and add implicit def of |
355 | // sub-registers which are used. |
356 | // dead EAX = op implicit-def AL |
357 | // That is, EAX def is dead but AL def extends pass it. |
358 | PhysRegDef[Reg]->addRegisterDead(Reg, RegInfo: TRI, AddIfNotFound: true); |
359 | for (MCPhysReg SubReg : TRI->subregs(Reg)) { |
360 | if (!PartUses.count(V: SubReg)) |
361 | continue; |
362 | bool NeedDef = true; |
363 | if (PhysRegDef[Reg] == PhysRegDef[SubReg]) { |
364 | MachineOperand *MO = |
365 | PhysRegDef[Reg]->findRegisterDefOperand(Reg: SubReg, /*TRI=*/nullptr); |
366 | if (MO) { |
367 | NeedDef = false; |
368 | assert(!MO->isDead()); |
369 | } |
370 | } |
371 | if (NeedDef) |
372 | PhysRegDef[Reg]->addOperand(Op: MachineOperand::CreateReg(Reg: SubReg, |
373 | isDef: true/*IsDef*/, isImp: true/*IsImp*/)); |
374 | MachineInstr *LastSubRef = FindLastRefOrPartRef(Reg: SubReg); |
375 | if (LastSubRef) |
376 | LastSubRef->addRegisterKilled(IncomingReg: SubReg, RegInfo: TRI, AddIfNotFound: true); |
377 | else { |
378 | LastRefOrPartRef->addRegisterKilled(IncomingReg: SubReg, RegInfo: TRI, AddIfNotFound: true); |
379 | for (MCPhysReg SS : TRI->subregs_inclusive(Reg: SubReg)) |
380 | PhysRegUse[SS] = LastRefOrPartRef; |
381 | } |
382 | for (MCPhysReg SS : TRI->subregs(Reg: SubReg)) |
383 | PartUses.erase(V: SS); |
384 | } |
385 | } else if (LastRefOrPartRef == PhysRegDef[Reg] && LastRefOrPartRef != MI) { |
386 | if (LastPartDef) |
387 | // The last partial def kills the register. |
388 | LastPartDef->addOperand(Op: MachineOperand::CreateReg(Reg, isDef: false/*IsDef*/, |
389 | isImp: true/*IsImp*/, isKill: true/*IsKill*/)); |
390 | else { |
391 | MachineOperand *MO = |
392 | LastRefOrPartRef->findRegisterDefOperand(Reg, TRI, isDead: false, Overlap: false); |
393 | bool NeedEC = MO->isEarlyClobber() && MO->getReg() != Reg; |
394 | // If the last reference is the last def, then it's not used at all. |
395 | // That is, unless we are currently processing the last reference itself. |
396 | LastRefOrPartRef->addRegisterDead(Reg, RegInfo: TRI, AddIfNotFound: true); |
397 | if (NeedEC) { |
398 | // If we are adding a subreg def and the superreg def is marked early |
399 | // clobber, add an early clobber marker to the subreg def. |
400 | MO = LastRefOrPartRef->findRegisterDefOperand(Reg, /*TRI=*/nullptr); |
401 | if (MO) |
402 | MO->setIsEarlyClobber(); |
403 | } |
404 | } |
405 | } else |
406 | LastRefOrPartRef->addRegisterKilled(IncomingReg: Reg, RegInfo: TRI, AddIfNotFound: true); |
407 | return true; |
408 | } |
409 | |
410 | void LiveVariables::HandleRegMask(const MachineOperand &MO, unsigned NumRegs) { |
411 | // Call HandlePhysRegKill() for all live registers clobbered by Mask. |
412 | // Clobbered registers are always dead, sp there is no need to use |
413 | // HandlePhysRegDef(). |
414 | for (unsigned Reg = 1; Reg != NumRegs; ++Reg) { |
415 | // Skip dead regs. |
416 | if (!PhysRegDef[Reg] && !PhysRegUse[Reg]) |
417 | continue; |
418 | // Skip mask-preserved regs. |
419 | if (!MO.clobbersPhysReg(PhysReg: Reg)) |
420 | continue; |
421 | // Kill the largest clobbered super-register. |
422 | // This avoids needless implicit operands. |
423 | unsigned Super = Reg; |
424 | for (MCPhysReg SR : TRI->superregs(Reg)) |
425 | if (SR < NumRegs && (PhysRegDef[SR] || PhysRegUse[SR]) && |
426 | MO.clobbersPhysReg(PhysReg: SR)) |
427 | Super = SR; |
428 | HandlePhysRegKill(Reg: Super, MI: nullptr); |
429 | } |
430 | } |
431 | |
432 | void LiveVariables::HandlePhysRegDef(Register Reg, MachineInstr *MI, |
433 | SmallVectorImpl<unsigned> &Defs) { |
434 | // What parts of the register are previously defined? |
435 | SmallSet<unsigned, 32> Live; |
436 | if (PhysRegDef[Reg] || PhysRegUse[Reg]) { |
437 | for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg)) |
438 | Live.insert(V: SubReg); |
439 | } else { |
440 | for (MCPhysReg SubReg : TRI->subregs(Reg)) { |
441 | // If a register isn't itself defined, but all parts that make up of it |
442 | // are defined, then consider it also defined. |
443 | // e.g. |
444 | // AL = |
445 | // AH = |
446 | // = AX |
447 | if (Live.count(V: SubReg)) |
448 | continue; |
449 | if (PhysRegDef[SubReg] || PhysRegUse[SubReg]) { |
450 | for (MCPhysReg SS : TRI->subregs_inclusive(Reg: SubReg)) |
451 | Live.insert(V: SS); |
452 | } |
453 | } |
454 | } |
455 | |
456 | // Start from the largest piece, find the last time any part of the register |
457 | // is referenced. |
458 | HandlePhysRegKill(Reg, MI); |
459 | // Only some of the sub-registers are used. |
460 | for (MCPhysReg SubReg : TRI->subregs(Reg)) { |
461 | if (!Live.count(V: SubReg)) |
462 | // Skip if this sub-register isn't defined. |
463 | continue; |
464 | HandlePhysRegKill(Reg: SubReg, MI); |
465 | } |
466 | |
467 | if (MI) |
468 | Defs.push_back(Elt: Reg); // Remember this def. |
469 | } |
470 | |
471 | void LiveVariables::UpdatePhysRegDefs(MachineInstr &MI, |
472 | SmallVectorImpl<unsigned> &Defs) { |
473 | while (!Defs.empty()) { |
474 | Register Reg = Defs.pop_back_val(); |
475 | for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg)) { |
476 | PhysRegDef[SubReg] = &MI; |
477 | PhysRegUse[SubReg] = nullptr; |
478 | } |
479 | } |
480 | } |
481 | |
482 | void LiveVariables::runOnInstr(MachineInstr &MI, |
483 | SmallVectorImpl<unsigned> &Defs, |
484 | unsigned NumRegs) { |
485 | assert(!MI.isDebugOrPseudoInstr()); |
486 | // Process all of the operands of the instruction... |
487 | unsigned NumOperandsToProcess = MI.getNumOperands(); |
488 | |
489 | // Unless it is a PHI node. In this case, ONLY process the DEF, not any |
490 | // of the uses. They will be handled in other basic blocks. |
491 | if (MI.isPHI()) |
492 | NumOperandsToProcess = 1; |
493 | |
494 | // Clear kill and dead markers. LV will recompute them. |
495 | SmallVector<unsigned, 4> UseRegs; |
496 | SmallVector<unsigned, 4> DefRegs; |
497 | SmallVector<unsigned, 1> RegMasks; |
498 | for (unsigned i = 0; i != NumOperandsToProcess; ++i) { |
499 | MachineOperand &MO = MI.getOperand(i); |
500 | if (MO.isRegMask()) { |
501 | RegMasks.push_back(Elt: i); |
502 | continue; |
503 | } |
504 | if (!MO.isReg() || MO.getReg() == 0) |
505 | continue; |
506 | Register MOReg = MO.getReg(); |
507 | if (MO.isUse()) { |
508 | if (!(MOReg.isPhysical() && MRI->isReserved(PhysReg: MOReg))) |
509 | MO.setIsKill(false); |
510 | if (MO.readsReg()) |
511 | UseRegs.push_back(Elt: MOReg); |
512 | } else { |
513 | assert(MO.isDef()); |
514 | // FIXME: We should not remove any dead flags. However the MIPS RDDSP |
515 | // instruction needs it at the moment: http://llvm.org/PR27116. |
516 | if (MOReg.isPhysical() && !MRI->isReserved(PhysReg: MOReg)) |
517 | MO.setIsDead(false); |
518 | DefRegs.push_back(Elt: MOReg); |
519 | } |
520 | } |
521 | |
522 | MachineBasicBlock *MBB = MI.getParent(); |
523 | // Process all uses. |
524 | for (unsigned MOReg : UseRegs) { |
525 | if (Register::isVirtualRegister(Reg: MOReg)) |
526 | HandleVirtRegUse(Reg: MOReg, MBB, MI); |
527 | else if (!MRI->isReserved(PhysReg: MOReg)) |
528 | HandlePhysRegUse(Reg: MOReg, MI); |
529 | } |
530 | |
531 | // Process all masked registers. (Call clobbers). |
532 | for (unsigned Mask : RegMasks) |
533 | HandleRegMask(MO: MI.getOperand(i: Mask), NumRegs); |
534 | |
535 | // Process all defs. |
536 | for (unsigned MOReg : DefRegs) { |
537 | if (Register::isVirtualRegister(Reg: MOReg)) |
538 | HandleVirtRegDef(Reg: MOReg, MI); |
539 | else if (!MRI->isReserved(PhysReg: MOReg)) |
540 | HandlePhysRegDef(Reg: MOReg, MI: &MI, Defs); |
541 | } |
542 | UpdatePhysRegDefs(MI, Defs); |
543 | } |
544 | |
545 | void LiveVariables::runOnBlock(MachineBasicBlock *MBB, unsigned NumRegs) { |
546 | // Mark live-in registers as live-in. |
547 | SmallVector<unsigned, 4> Defs; |
548 | for (const auto &LI : MBB->liveins()) { |
549 | assert(Register::isPhysicalRegister(LI.PhysReg) && |
550 | "Cannot have a live-in virtual register!" ); |
551 | HandlePhysRegDef(Reg: LI.PhysReg, MI: nullptr, Defs); |
552 | } |
553 | |
554 | // Loop over all of the instructions, processing them. |
555 | DistanceMap.clear(); |
556 | unsigned Dist = 0; |
557 | for (MachineInstr &MI : *MBB) { |
558 | if (MI.isDebugOrPseudoInstr()) |
559 | continue; |
560 | DistanceMap.insert(KV: std::make_pair(x: &MI, y: Dist++)); |
561 | |
562 | runOnInstr(MI, Defs, NumRegs); |
563 | } |
564 | |
565 | // Handle any virtual assignments from PHI nodes which might be at the |
566 | // bottom of this basic block. We check all of our successor blocks to see |
567 | // if they have PHI nodes, and if so, we simulate an assignment at the end |
568 | // of the current block. |
569 | if (!PHIVarInfo[MBB->getNumber()].empty()) { |
570 | SmallVectorImpl<unsigned> &VarInfoVec = PHIVarInfo[MBB->getNumber()]; |
571 | |
572 | for (unsigned I : VarInfoVec) |
573 | // Mark it alive only in the block we are representing. |
574 | MarkVirtRegAliveInBlock(VRInfo&: getVarInfo(Reg: I), DefBlock: MRI->getVRegDef(Reg: I)->getParent(), |
575 | MBB); |
576 | } |
577 | |
578 | // MachineCSE may CSE instructions which write to non-allocatable physical |
579 | // registers across MBBs. Remember if any reserved register is liveout. |
580 | SmallSet<unsigned, 4> LiveOuts; |
581 | for (const MachineBasicBlock *SuccMBB : MBB->successors()) { |
582 | if (SuccMBB->isEHPad()) |
583 | continue; |
584 | for (const auto &LI : SuccMBB->liveins()) { |
585 | if (!TRI->isInAllocatableClass(RegNo: LI.PhysReg)) |
586 | // Ignore other live-ins, e.g. those that are live into landing pads. |
587 | LiveOuts.insert(V: LI.PhysReg); |
588 | } |
589 | } |
590 | |
591 | // Loop over PhysRegDef / PhysRegUse, killing any registers that are |
592 | // available at the end of the basic block. |
593 | for (unsigned i = 0; i != NumRegs; ++i) |
594 | if ((PhysRegDef[i] || PhysRegUse[i]) && !LiveOuts.count(V: i)) |
595 | HandlePhysRegDef(Reg: i, MI: nullptr, Defs); |
596 | } |
597 | |
598 | bool LiveVariables::runOnMachineFunction(MachineFunction &mf) { |
599 | MF = &mf; |
600 | MRI = &mf.getRegInfo(); |
601 | TRI = MF->getSubtarget().getRegisterInfo(); |
602 | |
603 | const unsigned NumRegs = TRI->getNumSupportedRegs(mf); |
604 | PhysRegDef.assign(n: NumRegs, val: nullptr); |
605 | PhysRegUse.assign(n: NumRegs, val: nullptr); |
606 | PHIVarInfo.resize(new_size: MF->getNumBlockIDs()); |
607 | |
608 | // FIXME: LiveIntervals will be updated to remove its dependence on |
609 | // LiveVariables to improve compilation time and eliminate bizarre pass |
610 | // dependencies. Until then, we can't change much in -O0. |
611 | if (!MRI->isSSA()) |
612 | report_fatal_error(reason: "regalloc=... not currently supported with -O0" ); |
613 | |
614 | analyzePHINodes(Fn: mf); |
615 | |
616 | // Calculate live variable information in depth first order on the CFG of the |
617 | // function. This guarantees that we will see the definition of a virtual |
618 | // register before its uses due to dominance properties of SSA (except for PHI |
619 | // nodes, which are treated as a special case). |
620 | MachineBasicBlock *Entry = &MF->front(); |
621 | df_iterator_default_set<MachineBasicBlock*,16> Visited; |
622 | |
623 | for (MachineBasicBlock *MBB : depth_first_ext(G: Entry, S&: Visited)) { |
624 | runOnBlock(MBB, NumRegs); |
625 | |
626 | PhysRegDef.assign(n: NumRegs, val: nullptr); |
627 | PhysRegUse.assign(n: NumRegs, val: nullptr); |
628 | } |
629 | |
630 | // Convert and transfer the dead / killed information we have gathered into |
631 | // VirtRegInfo onto MI's. |
632 | for (unsigned i = 0, e1 = VirtRegInfo.size(); i != e1; ++i) { |
633 | const Register Reg = Register::index2VirtReg(Index: i); |
634 | for (unsigned j = 0, e2 = VirtRegInfo[Reg].Kills.size(); j != e2; ++j) |
635 | if (VirtRegInfo[Reg].Kills[j] == MRI->getVRegDef(Reg)) |
636 | VirtRegInfo[Reg].Kills[j]->addRegisterDead(Reg, RegInfo: TRI); |
637 | else |
638 | VirtRegInfo[Reg].Kills[j]->addRegisterKilled(IncomingReg: Reg, RegInfo: TRI); |
639 | } |
640 | |
641 | // Check to make sure there are no unreachable blocks in the MC CFG for the |
642 | // function. If so, it is due to a bug in the instruction selector or some |
643 | // other part of the code generator if this happens. |
644 | #ifndef NDEBUG |
645 | for (const MachineBasicBlock &MBB : *MF) |
646 | assert(Visited.contains(&MBB) && "unreachable basic block found" ); |
647 | #endif |
648 | |
649 | PhysRegDef.clear(); |
650 | PhysRegUse.clear(); |
651 | PHIVarInfo.clear(); |
652 | |
653 | return false; |
654 | } |
655 | |
656 | void LiveVariables::recomputeForSingleDefVirtReg(Register Reg) { |
657 | assert(Reg.isVirtual()); |
658 | |
659 | VarInfo &VI = getVarInfo(Reg); |
660 | VI.AliveBlocks.clear(); |
661 | VI.Kills.clear(); |
662 | |
663 | MachineInstr &DefMI = *MRI->getUniqueVRegDef(Reg); |
664 | MachineBasicBlock &DefBB = *DefMI.getParent(); |
665 | |
666 | // Initialize a worklist of BBs that Reg is live-to-end of. (Here |
667 | // "live-to-end" means Reg is live at the end of a block even if it is only |
668 | // live because of phi uses in a successor. This is different from isLiveOut() |
669 | // which does not consider phi uses.) |
670 | SmallVector<MachineBasicBlock *> LiveToEndBlocks; |
671 | SparseBitVector<> UseBlocks; |
672 | unsigned NumRealUses = 0; |
673 | for (auto &UseMO : MRI->use_nodbg_operands(Reg)) { |
674 | UseMO.setIsKill(false); |
675 | if (!UseMO.readsReg()) |
676 | continue; |
677 | ++NumRealUses; |
678 | MachineInstr &UseMI = *UseMO.getParent(); |
679 | MachineBasicBlock &UseBB = *UseMI.getParent(); |
680 | UseBlocks.set(UseBB.getNumber()); |
681 | if (UseMI.isPHI()) { |
682 | // If Reg is used in a phi then it is live-to-end of the corresponding |
683 | // predecessor. |
684 | unsigned Idx = UseMO.getOperandNo(); |
685 | LiveToEndBlocks.push_back(Elt: UseMI.getOperand(i: Idx + 1).getMBB()); |
686 | } else if (&UseBB == &DefBB) { |
687 | // A non-phi use in the same BB as the single def must come after the def. |
688 | } else { |
689 | // Otherwise Reg must be live-to-end of all predecessors. |
690 | LiveToEndBlocks.append(in_start: UseBB.pred_begin(), in_end: UseBB.pred_end()); |
691 | } |
692 | } |
693 | |
694 | // Handle the case where all uses have been removed. |
695 | if (NumRealUses == 0) { |
696 | VI.Kills.push_back(x: &DefMI); |
697 | DefMI.addRegisterDead(Reg, RegInfo: nullptr); |
698 | return; |
699 | } |
700 | DefMI.clearRegisterDeads(Reg); |
701 | |
702 | // Iterate over the worklist adding blocks to AliveBlocks. |
703 | bool LiveToEndOfDefBB = false; |
704 | while (!LiveToEndBlocks.empty()) { |
705 | MachineBasicBlock &BB = *LiveToEndBlocks.pop_back_val(); |
706 | if (&BB == &DefBB) { |
707 | LiveToEndOfDefBB = true; |
708 | continue; |
709 | } |
710 | if (VI.AliveBlocks.test(Idx: BB.getNumber())) |
711 | continue; |
712 | VI.AliveBlocks.set(BB.getNumber()); |
713 | LiveToEndBlocks.append(in_start: BB.pred_begin(), in_end: BB.pred_end()); |
714 | } |
715 | |
716 | // Recompute kill flags. For each block in which Reg is used but is not |
717 | // live-through, find the last instruction that uses Reg. Ignore phi nodes |
718 | // because they should not be included in Kills. |
719 | for (unsigned UseBBNum : UseBlocks) { |
720 | if (VI.AliveBlocks.test(Idx: UseBBNum)) |
721 | continue; |
722 | MachineBasicBlock &UseBB = *MF->getBlockNumbered(N: UseBBNum); |
723 | if (&UseBB == &DefBB && LiveToEndOfDefBB) |
724 | continue; |
725 | for (auto &MI : reverse(C&: UseBB)) { |
726 | if (MI.isDebugOrPseudoInstr()) |
727 | continue; |
728 | if (MI.isPHI()) |
729 | break; |
730 | if (MI.readsVirtualRegister(Reg)) { |
731 | assert(!MI.killsRegister(Reg, /*TRI=*/nullptr)); |
732 | MI.addRegisterKilled(IncomingReg: Reg, RegInfo: nullptr); |
733 | VI.Kills.push_back(x: &MI); |
734 | break; |
735 | } |
736 | } |
737 | } |
738 | } |
739 | |
740 | /// replaceKillInstruction - Update register kill info by replacing a kill |
741 | /// instruction with a new one. |
742 | void LiveVariables::replaceKillInstruction(Register Reg, MachineInstr &OldMI, |
743 | MachineInstr &NewMI) { |
744 | VarInfo &VI = getVarInfo(Reg); |
745 | std::replace(first: VI.Kills.begin(), last: VI.Kills.end(), old_value: &OldMI, new_value: &NewMI); |
746 | } |
747 | |
748 | /// removeVirtualRegistersKilled - Remove all killed info for the specified |
749 | /// instruction. |
750 | void LiveVariables::removeVirtualRegistersKilled(MachineInstr &MI) { |
751 | for (MachineOperand &MO : MI.operands()) { |
752 | if (MO.isReg() && MO.isKill()) { |
753 | MO.setIsKill(false); |
754 | Register Reg = MO.getReg(); |
755 | if (Reg.isVirtual()) { |
756 | bool removed = getVarInfo(Reg).removeKill(MI); |
757 | assert(removed && "kill not in register's VarInfo?" ); |
758 | (void)removed; |
759 | } |
760 | } |
761 | } |
762 | } |
763 | |
764 | /// analyzePHINodes - Gather information about the PHI nodes in here. In |
765 | /// particular, we want to map the variable information of a virtual register |
766 | /// which is used in a PHI node. We map that to the BB the vreg is coming from. |
767 | /// |
768 | void LiveVariables::analyzePHINodes(const MachineFunction& Fn) { |
769 | for (const auto &MBB : Fn) |
770 | for (const auto &BBI : MBB) { |
771 | if (!BBI.isPHI()) |
772 | break; |
773 | for (unsigned i = 1, e = BBI.getNumOperands(); i != e; i += 2) |
774 | if (BBI.getOperand(i).readsReg()) |
775 | PHIVarInfo[BBI.getOperand(i: i + 1).getMBB()->getNumber()] |
776 | .push_back(Elt: BBI.getOperand(i).getReg()); |
777 | } |
778 | } |
779 | |
780 | bool LiveVariables::VarInfo::isLiveIn(const MachineBasicBlock &MBB, |
781 | Register Reg, MachineRegisterInfo &MRI) { |
782 | unsigned Num = MBB.getNumber(); |
783 | |
784 | // Reg is live-through. |
785 | if (AliveBlocks.test(Idx: Num)) |
786 | return true; |
787 | |
788 | // Registers defined in MBB cannot be live in. |
789 | const MachineInstr *Def = MRI.getVRegDef(Reg); |
790 | if (Def && Def->getParent() == &MBB) |
791 | return false; |
792 | |
793 | // Reg was not defined in MBB, was it killed here? |
794 | return findKill(MBB: &MBB); |
795 | } |
796 | |
797 | bool LiveVariables::isLiveOut(Register Reg, const MachineBasicBlock &MBB) { |
798 | LiveVariables::VarInfo &VI = getVarInfo(Reg); |
799 | |
800 | SmallPtrSet<const MachineBasicBlock *, 8> Kills; |
801 | for (MachineInstr *MI : VI.Kills) |
802 | Kills.insert(Ptr: MI->getParent()); |
803 | |
804 | // Loop over all of the successors of the basic block, checking to see if |
805 | // the value is either live in the block, or if it is killed in the block. |
806 | for (const MachineBasicBlock *SuccMBB : MBB.successors()) { |
807 | // Is it alive in this successor? |
808 | unsigned SuccIdx = SuccMBB->getNumber(); |
809 | if (VI.AliveBlocks.test(Idx: SuccIdx)) |
810 | return true; |
811 | // Or is it live because there is a use in a successor that kills it? |
812 | if (Kills.count(Ptr: SuccMBB)) |
813 | return true; |
814 | } |
815 | |
816 | return false; |
817 | } |
818 | |
819 | /// addNewBlock - Add a new basic block BB as an empty succcessor to DomBB. All |
820 | /// variables that are live out of DomBB will be marked as passing live through |
821 | /// BB. |
822 | void LiveVariables::addNewBlock(MachineBasicBlock *BB, |
823 | MachineBasicBlock *DomBB, |
824 | MachineBasicBlock *SuccBB) { |
825 | const unsigned NumNew = BB->getNumber(); |
826 | |
827 | DenseSet<unsigned> Defs, Kills; |
828 | |
829 | MachineBasicBlock::iterator BBI = SuccBB->begin(), BBE = SuccBB->end(); |
830 | for (; BBI != BBE && BBI->isPHI(); ++BBI) { |
831 | // Record the def of the PHI node. |
832 | Defs.insert(V: BBI->getOperand(i: 0).getReg()); |
833 | |
834 | // All registers used by PHI nodes in SuccBB must be live through BB. |
835 | for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) |
836 | if (BBI->getOperand(i: i+1).getMBB() == BB) |
837 | getVarInfo(Reg: BBI->getOperand(i).getReg()).AliveBlocks.set(NumNew); |
838 | } |
839 | |
840 | // Record all vreg defs and kills of all instructions in SuccBB. |
841 | for (; BBI != BBE; ++BBI) { |
842 | for (const MachineOperand &Op : BBI->operands()) { |
843 | if (Op.isReg() && Op.getReg().isVirtual()) { |
844 | if (Op.isDef()) |
845 | Defs.insert(V: Op.getReg()); |
846 | else if (Op.isKill()) |
847 | Kills.insert(V: Op.getReg()); |
848 | } |
849 | } |
850 | } |
851 | |
852 | // Update info for all live variables |
853 | for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) { |
854 | Register Reg = Register::index2VirtReg(Index: i); |
855 | |
856 | // If the Defs is defined in the successor it can't be live in BB. |
857 | if (Defs.count(V: Reg)) |
858 | continue; |
859 | |
860 | // If the register is either killed in or live through SuccBB it's also live |
861 | // through BB. |
862 | VarInfo &VI = getVarInfo(Reg); |
863 | if (Kills.count(V: Reg) || VI.AliveBlocks.test(Idx: SuccBB->getNumber())) |
864 | VI.AliveBlocks.set(NumNew); |
865 | } |
866 | } |
867 | |
868 | /// addNewBlock - Add a new basic block BB as an empty succcessor to DomBB. All |
869 | /// variables that are live out of DomBB will be marked as passing live through |
870 | /// BB. LiveInSets[BB] is *not* updated (because it is not needed during |
871 | /// PHIElimination). |
872 | void LiveVariables::addNewBlock(MachineBasicBlock *BB, |
873 | MachineBasicBlock *DomBB, |
874 | MachineBasicBlock *SuccBB, |
875 | std::vector<SparseBitVector<>> &LiveInSets) { |
876 | const unsigned NumNew = BB->getNumber(); |
877 | |
878 | SparseBitVector<> &BV = LiveInSets[SuccBB->getNumber()]; |
879 | for (unsigned R : BV) { |
880 | Register VirtReg = Register::index2VirtReg(Index: R); |
881 | LiveVariables::VarInfo &VI = getVarInfo(Reg: VirtReg); |
882 | VI.AliveBlocks.set(NumNew); |
883 | } |
884 | // All registers used by PHI nodes in SuccBB must be live through BB. |
885 | for (MachineBasicBlock::iterator BBI = SuccBB->begin(), |
886 | BBE = SuccBB->end(); |
887 | BBI != BBE && BBI->isPHI(); ++BBI) { |
888 | for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) |
889 | if (BBI->getOperand(i: i + 1).getMBB() == BB && |
890 | BBI->getOperand(i).readsReg()) |
891 | getVarInfo(Reg: BBI->getOperand(i).getReg()) |
892 | .AliveBlocks.set(NumNew); |
893 | } |
894 | } |
895 | |