1// SPDX-License-Identifier: MIT
2/*
3 * Copyright 2014 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24#include "amdgpu_amdkfd.h"
25#include "amd_pcie.h"
26#include "amd_shared.h"
27
28#include "amdgpu.h"
29#include "amdgpu_gfx.h"
30#include "amdgpu_dma_buf.h"
31#include <drm/ttm/ttm_tt.h>
32#include <linux/module.h>
33#include <linux/dma-buf.h>
34#include "amdgpu_xgmi.h"
35#include <uapi/linux/kfd_ioctl.h>
36#include "amdgpu_ras.h"
37#include "amdgpu_umc.h"
38#include "amdgpu_reset.h"
39
40/* Total memory size in system memory and all GPU VRAM. Used to
41 * estimate worst case amount of memory to reserve for page tables
42 */
43uint64_t amdgpu_amdkfd_total_mem_size;
44
45static bool kfd_initialized;
46
47int amdgpu_amdkfd_init(void)
48{
49 struct sysinfo si;
50 int ret;
51
52 si_meminfo(val: &si);
53 amdgpu_amdkfd_total_mem_size = si.freeram - si.freehigh;
54 amdgpu_amdkfd_total_mem_size *= si.mem_unit;
55
56 ret = kgd2kfd_init();
57 kfd_initialized = !ret;
58
59 return ret;
60}
61
62void amdgpu_amdkfd_fini(void)
63{
64 if (kfd_initialized) {
65 kgd2kfd_exit();
66 kfd_initialized = false;
67 }
68}
69
70void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev)
71{
72 bool vf = amdgpu_sriov_vf(adev);
73
74 if (!kfd_initialized)
75 return;
76
77 adev->kfd.dev = kgd2kfd_probe(adev, vf);
78}
79
80/**
81 * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
82 * setup amdkfd
83 *
84 * @adev: amdgpu_device pointer
85 * @aperture_base: output returning doorbell aperture base physical address
86 * @aperture_size: output returning doorbell aperture size in bytes
87 * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
88 *
89 * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
90 * takes doorbells required for its own rings and reports the setup to amdkfd.
91 * amdgpu reserved doorbells are at the start of the doorbell aperture.
92 */
93static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
94 phys_addr_t *aperture_base,
95 size_t *aperture_size,
96 size_t *start_offset)
97{
98 /*
99 * The first num_kernel_doorbells are used by amdgpu.
100 * amdkfd takes whatever's left in the aperture.
101 */
102 if (adev->enable_mes) {
103 /*
104 * With MES enabled, we only need to initialize
105 * the base address. The size and offset are
106 * not initialized as AMDGPU manages the whole
107 * doorbell space.
108 */
109 *aperture_base = adev->doorbell.base;
110 *aperture_size = 0;
111 *start_offset = 0;
112 } else if (adev->doorbell.size > adev->doorbell.num_kernel_doorbells *
113 sizeof(u32)) {
114 *aperture_base = adev->doorbell.base;
115 *aperture_size = adev->doorbell.size;
116 *start_offset = adev->doorbell.num_kernel_doorbells * sizeof(u32);
117 } else {
118 *aperture_base = 0;
119 *aperture_size = 0;
120 *start_offset = 0;
121 }
122}
123
124
125static void amdgpu_amdkfd_reset_work(struct work_struct *work)
126{
127 struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
128 kfd.reset_work);
129
130 struct amdgpu_reset_context reset_context;
131
132 memset(&reset_context, 0, sizeof(reset_context));
133
134 reset_context.method = AMD_RESET_METHOD_NONE;
135 reset_context.reset_req_dev = adev;
136 reset_context.src = adev->enable_mes ?
137 AMDGPU_RESET_SRC_MES :
138 AMDGPU_RESET_SRC_HWS;
139 clear_bit(nr: AMDGPU_NEED_FULL_RESET, addr: &reset_context.flags);
140
141 amdgpu_device_gpu_recover(adev, NULL, reset_context: &reset_context);
142}
143
144static const struct drm_client_funcs kfd_client_funcs = {
145 .unregister = drm_client_release,
146};
147
148int amdgpu_amdkfd_drm_client_create(struct amdgpu_device *adev)
149{
150 int ret;
151
152 if (!adev->kfd.init_complete || adev->kfd.client.dev)
153 return 0;
154
155 ret = drm_client_init(dev: &adev->ddev, client: &adev->kfd.client, name: "kfd",
156 funcs: &kfd_client_funcs);
157 if (ret) {
158 dev_err(adev->dev, "Failed to init DRM client: %d\n",
159 ret);
160 return ret;
161 }
162
163 drm_client_register(client: &adev->kfd.client);
164
165 return 0;
166}
167
168void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
169{
170 int i;
171 int last_valid_bit;
172
173 amdgpu_amdkfd_gpuvm_init_mem_limits();
174
175 if (adev->kfd.dev) {
176 struct kgd2kfd_shared_resources gpu_resources = {
177 .compute_vmid_bitmap =
178 ((1 << AMDGPU_NUM_VMID) - 1) -
179 ((1 << adev->vm_manager.first_kfd_vmid) - 1),
180 .num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec,
181 .num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe,
182 .gpuvm_size = min(adev->vm_manager.max_pfn
183 << AMDGPU_GPU_PAGE_SHIFT,
184 AMDGPU_GMC_HOLE_START),
185 .drm_render_minor = adev_to_drm(adev)->render->index,
186 .sdma_doorbell_idx = adev->doorbell_index.sdma_engine,
187 .enable_mes = adev->enable_mes,
188 };
189
190 /* this is going to have a few of the MSBs set that we need to
191 * clear
192 */
193 bitmap_complement(dst: gpu_resources.cp_queue_bitmap,
194 src: adev->gfx.mec_bitmap[0].queue_bitmap,
195 AMDGPU_MAX_QUEUES);
196
197 /* According to linux/bitmap.h we shouldn't use bitmap_clear if
198 * nbits is not compile time constant
199 */
200 last_valid_bit = 1 /* only first MEC can have compute queues */
201 * adev->gfx.mec.num_pipe_per_mec
202 * adev->gfx.mec.num_queue_per_pipe;
203 for (i = last_valid_bit; i < AMDGPU_MAX_QUEUES; ++i)
204 clear_bit(nr: i, addr: gpu_resources.cp_queue_bitmap);
205
206 amdgpu_doorbell_get_kfd_info(adev,
207 aperture_base: &gpu_resources.doorbell_physical_address,
208 aperture_size: &gpu_resources.doorbell_aperture_size,
209 start_offset: &gpu_resources.doorbell_start_offset);
210
211 /* Since SOC15, BIF starts to statically use the
212 * lower 12 bits of doorbell addresses for routing
213 * based on settings in registers like
214 * SDMA0_DOORBELL_RANGE etc..
215 * In order to route a doorbell to CP engine, the lower
216 * 12 bits of its address has to be outside the range
217 * set for SDMA, VCN, and IH blocks.
218 */
219 if (adev->asic_type >= CHIP_VEGA10) {
220 gpu_resources.non_cp_doorbells_start =
221 adev->doorbell_index.first_non_cp;
222 gpu_resources.non_cp_doorbells_end =
223 adev->doorbell_index.last_non_cp;
224 }
225
226 adev->kfd.init_complete = kgd2kfd_device_init(kfd: adev->kfd.dev,
227 gpu_resources: &gpu_resources);
228
229 amdgpu_amdkfd_total_mem_size += adev->gmc.real_vram_size;
230
231 INIT_WORK(&adev->kfd.reset_work, amdgpu_amdkfd_reset_work);
232 }
233}
234
235void amdgpu_amdkfd_device_fini_sw(struct amdgpu_device *adev)
236{
237 if (adev->kfd.dev) {
238 kgd2kfd_device_exit(kfd: adev->kfd.dev);
239 adev->kfd.dev = NULL;
240 amdgpu_amdkfd_total_mem_size -= adev->gmc.real_vram_size;
241 }
242}
243
244void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev,
245 const void *ih_ring_entry)
246{
247 if (adev->kfd.dev)
248 kgd2kfd_interrupt(kfd: adev->kfd.dev, ih_ring_entry);
249}
250
251void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool suspend_proc)
252{
253 if (adev->kfd.dev) {
254 if (adev->in_s0ix)
255 kgd2kfd_stop_sched_all_nodes(kfd: adev->kfd.dev);
256 else
257 kgd2kfd_suspend(kfd: adev->kfd.dev, suspend_proc);
258 }
259}
260
261int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool resume_proc)
262{
263 int r = 0;
264
265 if (adev->kfd.dev) {
266 if (adev->in_s0ix)
267 r = kgd2kfd_start_sched_all_nodes(kfd: adev->kfd.dev);
268 else
269 r = kgd2kfd_resume(kfd: adev->kfd.dev, resume_proc);
270 }
271
272 return r;
273}
274
275void amdgpu_amdkfd_suspend_process(struct amdgpu_device *adev)
276{
277 if (adev->kfd.dev)
278 kgd2kfd_suspend_process(kfd: adev->kfd.dev);
279}
280
281int amdgpu_amdkfd_resume_process(struct amdgpu_device *adev)
282{
283 int r = 0;
284
285 if (adev->kfd.dev)
286 r = kgd2kfd_resume_process(kfd: adev->kfd.dev);
287
288 return r;
289}
290
291int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev,
292 struct amdgpu_reset_context *reset_context)
293{
294 int r = 0;
295
296 if (adev->kfd.dev)
297 r = kgd2kfd_pre_reset(kfd: adev->kfd.dev, reset_context);
298
299 return r;
300}
301
302int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev)
303{
304 int r = 0;
305
306 if (adev->kfd.dev)
307 r = kgd2kfd_post_reset(kfd: adev->kfd.dev);
308
309 return r;
310}
311
312void amdgpu_amdkfd_gpu_reset(struct amdgpu_device *adev)
313{
314 if (amdgpu_device_should_recover_gpu(adev))
315 amdgpu_reset_domain_schedule(domain: adev->reset_domain,
316 work: &adev->kfd.reset_work);
317}
318
319int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size,
320 void **mem_obj, uint64_t *gpu_addr,
321 void **cpu_ptr, bool cp_mqd_gfx9)
322{
323 struct amdgpu_bo *bo = NULL;
324 struct amdgpu_bo_param bp;
325 int r;
326 void *cpu_ptr_tmp = NULL;
327
328 memset(&bp, 0, sizeof(bp));
329 bp.size = size;
330 bp.byte_align = PAGE_SIZE;
331 bp.domain = AMDGPU_GEM_DOMAIN_GTT;
332 bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
333 bp.type = ttm_bo_type_kernel;
334 bp.resv = NULL;
335 bp.bo_ptr_size = sizeof(struct amdgpu_bo);
336
337 if (cp_mqd_gfx9)
338 bp.flags |= AMDGPU_GEM_CREATE_CP_MQD_GFX9;
339
340 r = amdgpu_bo_create(adev, bp: &bp, bo_ptr: &bo);
341 if (r) {
342 dev_err(adev->dev,
343 "failed to allocate BO for amdkfd (%d)\n", r);
344 return r;
345 }
346
347 /* map the buffer */
348 r = amdgpu_bo_reserve(bo, no_intr: true);
349 if (r) {
350 dev_err(adev->dev, "(%d) failed to reserve bo for amdkfd\n", r);
351 goto allocate_mem_reserve_bo_failed;
352 }
353
354 r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
355 if (r) {
356 dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r);
357 goto allocate_mem_pin_bo_failed;
358 }
359
360 r = amdgpu_ttm_alloc_gart(bo: &bo->tbo);
361 if (r) {
362 dev_err(adev->dev, "%p bind failed\n", bo);
363 goto allocate_mem_kmap_bo_failed;
364 }
365
366 r = amdgpu_bo_kmap(bo, ptr: &cpu_ptr_tmp);
367 if (r) {
368 dev_err(adev->dev,
369 "(%d) failed to map bo to kernel for amdkfd\n", r);
370 goto allocate_mem_kmap_bo_failed;
371 }
372
373 *mem_obj = bo;
374 *gpu_addr = amdgpu_bo_gpu_offset(bo);
375 *cpu_ptr = cpu_ptr_tmp;
376
377 amdgpu_bo_unreserve(bo);
378
379 return 0;
380
381allocate_mem_kmap_bo_failed:
382 amdgpu_bo_unpin(bo);
383allocate_mem_pin_bo_failed:
384 amdgpu_bo_unreserve(bo);
385allocate_mem_reserve_bo_failed:
386 amdgpu_bo_unref(bo: &bo);
387
388 return r;
389}
390
391void amdgpu_amdkfd_free_gtt_mem(struct amdgpu_device *adev, void **mem_obj)
392{
393 struct amdgpu_bo **bo = (struct amdgpu_bo **) mem_obj;
394
395 if (!bo || !*bo)
396 return;
397
398 (void)amdgpu_bo_reserve(bo: *bo, no_intr: true);
399 amdgpu_bo_kunmap(bo: *bo);
400 amdgpu_bo_unpin(bo: *bo);
401 amdgpu_bo_unreserve(bo: *bo);
402 amdgpu_bo_unref(bo);
403}
404
405int amdgpu_amdkfd_alloc_gws(struct amdgpu_device *adev, size_t size,
406 void **mem_obj)
407{
408 struct amdgpu_bo *bo = NULL;
409 struct amdgpu_bo_user *ubo;
410 struct amdgpu_bo_param bp;
411 int r;
412
413 memset(&bp, 0, sizeof(bp));
414 bp.size = size;
415 bp.byte_align = 1;
416 bp.domain = AMDGPU_GEM_DOMAIN_GWS;
417 bp.flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
418 bp.type = ttm_bo_type_device;
419 bp.resv = NULL;
420 bp.bo_ptr_size = sizeof(struct amdgpu_bo);
421
422 r = amdgpu_bo_create_user(adev, bp: &bp, ubo_ptr: &ubo);
423 if (r) {
424 dev_err(adev->dev,
425 "failed to allocate gws BO for amdkfd (%d)\n", r);
426 return r;
427 }
428
429 bo = &ubo->bo;
430 *mem_obj = bo;
431 return 0;
432}
433
434void amdgpu_amdkfd_free_gws(struct amdgpu_device *adev, void *mem_obj)
435{
436 struct amdgpu_bo *bo = (struct amdgpu_bo *)mem_obj;
437
438 amdgpu_bo_unref(bo: &bo);
439}
440
441uint32_t amdgpu_amdkfd_get_fw_version(struct amdgpu_device *adev,
442 enum kgd_engine_type type)
443{
444 switch (type) {
445 case KGD_ENGINE_PFP:
446 return adev->gfx.pfp_fw_version;
447
448 case KGD_ENGINE_ME:
449 return adev->gfx.me_fw_version;
450
451 case KGD_ENGINE_CE:
452 return adev->gfx.ce_fw_version;
453
454 case KGD_ENGINE_MEC1:
455 return adev->gfx.mec_fw_version;
456
457 case KGD_ENGINE_MEC2:
458 return adev->gfx.mec2_fw_version;
459
460 case KGD_ENGINE_RLC:
461 return adev->gfx.rlc_fw_version;
462
463 case KGD_ENGINE_SDMA1:
464 return adev->sdma.instance[0].fw_version;
465
466 case KGD_ENGINE_SDMA2:
467 return adev->sdma.instance[1].fw_version;
468
469 default:
470 return 0;
471 }
472
473 return 0;
474}
475
476void amdgpu_amdkfd_get_local_mem_info(struct amdgpu_device *adev,
477 struct kfd_local_mem_info *mem_info,
478 struct amdgpu_xcp *xcp)
479{
480 memset(mem_info, 0, sizeof(*mem_info));
481
482 if (xcp) {
483 if (adev->gmc.real_vram_size == adev->gmc.visible_vram_size)
484 mem_info->local_mem_size_public =
485 KFD_XCP_MEMORY_SIZE(adev, xcp->id);
486 else
487 mem_info->local_mem_size_private =
488 KFD_XCP_MEMORY_SIZE(adev, xcp->id);
489 } else if (adev->apu_prefer_gtt) {
490 mem_info->local_mem_size_public = (ttm_tt_pages_limit() << PAGE_SHIFT);
491 mem_info->local_mem_size_private = 0;
492 } else {
493 mem_info->local_mem_size_public = adev->gmc.visible_vram_size;
494 mem_info->local_mem_size_private = adev->gmc.real_vram_size -
495 adev->gmc.visible_vram_size;
496 }
497 mem_info->vram_width = adev->gmc.vram_width;
498
499 pr_debug("Address base: %pap public 0x%llx private 0x%llx\n",
500 &adev->gmc.aper_base,
501 mem_info->local_mem_size_public,
502 mem_info->local_mem_size_private);
503
504 if (adev->pm.dpm_enabled) {
505 if (amdgpu_emu_mode == 1)
506 mem_info->mem_clk_max = 0;
507 else
508 mem_info->mem_clk_max = amdgpu_dpm_get_mclk(adev, low: false) / 100;
509 } else
510 mem_info->mem_clk_max = 100;
511}
512
513uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct amdgpu_device *adev)
514{
515 if (adev->gfx.funcs->get_gpu_clock_counter)
516 return adev->gfx.funcs->get_gpu_clock_counter(adev);
517 return 0;
518}
519
520uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct amdgpu_device *adev)
521{
522 /* the sclk is in quantas of 10kHz */
523 if (adev->pm.dpm_enabled)
524 return amdgpu_dpm_get_sclk(adev, low: false) / 100;
525 else
526 return 100;
527}
528
529int amdgpu_amdkfd_get_dmabuf_info(struct amdgpu_device *adev, int dma_buf_fd,
530 struct amdgpu_device **dmabuf_adev,
531 uint64_t *bo_size, void *metadata_buffer,
532 size_t buffer_size, uint32_t *metadata_size,
533 uint32_t *flags, int8_t *xcp_id)
534{
535 struct dma_buf *dma_buf;
536 struct drm_gem_object *obj;
537 struct amdgpu_bo *bo;
538 uint64_t metadata_flags;
539 int r = -EINVAL;
540
541 dma_buf = dma_buf_get(fd: dma_buf_fd);
542 if (IS_ERR(ptr: dma_buf))
543 return PTR_ERR(ptr: dma_buf);
544
545 if (dma_buf->ops != &amdgpu_dmabuf_ops)
546 /* Can't handle non-graphics buffers */
547 goto out_put;
548
549 obj = dma_buf->priv;
550 if (obj->dev->driver != adev_to_drm(adev)->driver)
551 /* Can't handle buffers from different drivers */
552 goto out_put;
553
554 adev = drm_to_adev(ddev: obj->dev);
555 bo = gem_to_amdgpu_bo(obj);
556 if (!(bo->preferred_domains & (AMDGPU_GEM_DOMAIN_VRAM |
557 AMDGPU_GEM_DOMAIN_GTT)))
558 /* Only VRAM and GTT BOs are supported */
559 goto out_put;
560
561 r = 0;
562 if (dmabuf_adev)
563 *dmabuf_adev = adev;
564 if (bo_size)
565 *bo_size = amdgpu_bo_size(bo);
566 if (metadata_buffer)
567 r = amdgpu_bo_get_metadata(bo, buffer: metadata_buffer, buffer_size,
568 metadata_size, flags: &metadata_flags);
569 if (flags) {
570 *flags = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ?
571 KFD_IOC_ALLOC_MEM_FLAGS_VRAM
572 : KFD_IOC_ALLOC_MEM_FLAGS_GTT;
573
574 if (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
575 *flags |= KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC;
576 }
577 if (xcp_id)
578 *xcp_id = bo->xcp_id;
579
580out_put:
581 dma_buf_put(dmabuf: dma_buf);
582 return r;
583}
584
585int amdgpu_amdkfd_get_pcie_bandwidth_mbytes(struct amdgpu_device *adev, bool is_min)
586{
587 int num_lanes_shift = (is_min ? ffs(adev->pm.pcie_mlw_mask) :
588 fls(x: adev->pm.pcie_mlw_mask)) - 1;
589 int gen_speed_shift = (is_min ? ffs(adev->pm.pcie_gen_mask &
590 CAIL_PCIE_LINK_SPEED_SUPPORT_MASK) :
591 fls(x: adev->pm.pcie_gen_mask &
592 CAIL_PCIE_LINK_SPEED_SUPPORT_MASK)) - 1;
593 uint32_t num_lanes_mask = 1 << num_lanes_shift;
594 uint32_t gen_speed_mask = 1 << gen_speed_shift;
595 int num_lanes_factor = 0, gen_speed_mbits_factor = 0;
596
597 switch (num_lanes_mask) {
598 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X1:
599 num_lanes_factor = 1;
600 break;
601 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X2:
602 num_lanes_factor = 2;
603 break;
604 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X4:
605 num_lanes_factor = 4;
606 break;
607 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X8:
608 num_lanes_factor = 8;
609 break;
610 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X12:
611 num_lanes_factor = 12;
612 break;
613 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X16:
614 num_lanes_factor = 16;
615 break;
616 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X32:
617 num_lanes_factor = 32;
618 break;
619 }
620
621 switch (gen_speed_mask) {
622 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1:
623 gen_speed_mbits_factor = 2500;
624 break;
625 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2:
626 gen_speed_mbits_factor = 5000;
627 break;
628 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3:
629 gen_speed_mbits_factor = 8000;
630 break;
631 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4:
632 gen_speed_mbits_factor = 16000;
633 break;
634 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5:
635 gen_speed_mbits_factor = 32000;
636 break;
637 }
638
639 return (num_lanes_factor * gen_speed_mbits_factor)/BITS_PER_BYTE;
640}
641
642int amdgpu_amdkfd_submit_ib(struct amdgpu_device *adev,
643 enum kgd_engine_type engine,
644 uint32_t vmid, uint64_t gpu_addr,
645 uint32_t *ib_cmd, uint32_t ib_len)
646{
647 struct amdgpu_job *job;
648 struct amdgpu_ib *ib;
649 struct amdgpu_ring *ring;
650 struct dma_fence *f = NULL;
651 int ret;
652
653 switch (engine) {
654 case KGD_ENGINE_MEC1:
655 ring = &adev->gfx.compute_ring[0];
656 break;
657 case KGD_ENGINE_SDMA1:
658 ring = &adev->sdma.instance[0].ring;
659 break;
660 case KGD_ENGINE_SDMA2:
661 ring = &adev->sdma.instance[1].ring;
662 break;
663 default:
664 pr_err("Invalid engine in IB submission: %d\n", engine);
665 ret = -EINVAL;
666 goto err;
667 }
668
669 ret = amdgpu_job_alloc(adev, NULL, NULL, NULL, num_ibs: 1, job: &job, drm_client_id: 0);
670 if (ret)
671 goto err;
672
673 ib = &job->ibs[0];
674 memset(ib, 0, sizeof(struct amdgpu_ib));
675
676 ib->gpu_addr = gpu_addr;
677 ib->ptr = ib_cmd;
678 ib->length_dw = ib_len;
679 /* This works for NO_HWS. TODO: need to handle without knowing VMID */
680 job->vmid = vmid;
681 job->num_ibs = 1;
682
683 ret = amdgpu_ib_schedule(ring, num_ibs: 1, ibs: ib, job, f: &f);
684
685 if (ret) {
686 DRM_ERROR("amdgpu: failed to schedule IB.\n");
687 goto err_ib_sched;
688 }
689
690 /* Drop the initial kref_init count (see drm_sched_main as example) */
691 dma_fence_put(fence: f);
692 ret = dma_fence_wait(fence: f, intr: false);
693
694err_ib_sched:
695 amdgpu_job_free(job);
696err:
697 return ret;
698}
699
700void amdgpu_amdkfd_set_compute_idle(struct amdgpu_device *adev, bool idle)
701{
702 enum amd_powergating_state state = idle ? AMD_PG_STATE_GATE : AMD_PG_STATE_UNGATE;
703 if ((IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) == 11 &&
704 ((adev->mes.kiq_version & AMDGPU_MES_VERSION_MASK) <= 64)) ||
705 (IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) == 12)) {
706 pr_debug("GFXOFF is %s\n", idle ? "enabled" : "disabled");
707 amdgpu_gfx_off_ctrl(adev, enable: idle);
708 } else if ((IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) == 9) &&
709 (adev->flags & AMD_IS_APU)) {
710 /* Disable GFXOFF and PG. Temporary workaround
711 * to fix some compute applications issue on GFX9.
712 */
713 struct amdgpu_ip_block *gfx_block = amdgpu_device_ip_get_ip_block(adev, type: AMD_IP_BLOCK_TYPE_GFX);
714 if (gfx_block != NULL)
715 gfx_block->version->funcs->set_powergating_state((void *)gfx_block, state);
716 }
717 amdgpu_dpm_switch_power_profile(adev,
718 type: PP_SMC_POWER_PROFILE_COMPUTE,
719 en: !idle);
720}
721
722bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid)
723{
724 if (adev->kfd.dev)
725 return vmid >= adev->vm_manager.first_kfd_vmid;
726
727 return false;
728}
729
730bool amdgpu_amdkfd_have_atomics_support(struct amdgpu_device *adev)
731{
732 return adev->have_atomics_support;
733}
734
735void amdgpu_amdkfd_debug_mem_fence(struct amdgpu_device *adev)
736{
737 amdgpu_device_flush_hdp(adev, NULL);
738}
739
740bool amdgpu_amdkfd_is_fed(struct amdgpu_device *adev)
741{
742 return amdgpu_ras_get_fed_status(adev);
743}
744
745void amdgpu_amdkfd_ras_pasid_poison_consumption_handler(struct amdgpu_device *adev,
746 enum amdgpu_ras_block block, uint16_t pasid,
747 pasid_notify pasid_fn, void *data, uint32_t reset)
748{
749 amdgpu_umc_pasid_poison_handler(adev, block, pasid, pasid_fn, data, reset);
750}
751
752void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev,
753 enum amdgpu_ras_block block, uint32_t reset)
754{
755 amdgpu_umc_pasid_poison_handler(adev, block, pasid: 0, NULL, NULL, reset);
756}
757
758int amdgpu_amdkfd_send_close_event_drain_irq(struct amdgpu_device *adev,
759 uint32_t *payload)
760{
761 int ret;
762
763 /* Device or IH ring is not ready so bail. */
764 ret = amdgpu_ih_wait_on_checkpoint_process_ts(adev, ih: &adev->irq.ih);
765 if (ret)
766 return ret;
767
768 /* Send payload to fence KFD interrupts */
769 amdgpu_amdkfd_interrupt(adev, ih_ring_entry: payload);
770
771 return 0;
772}
773
774int amdgpu_amdkfd_check_and_lock_kfd(struct amdgpu_device *adev)
775{
776 return kgd2kfd_check_and_lock_kfd(kfd: adev->kfd.dev);
777}
778
779void amdgpu_amdkfd_unlock_kfd(struct amdgpu_device *adev)
780{
781 kgd2kfd_unlock_kfd(kfd: adev->kfd.dev);
782}
783
784
785u64 amdgpu_amdkfd_xcp_memory_size(struct amdgpu_device *adev, int xcp_id)
786{
787 s8 mem_id = KFD_XCP_MEM_ID(adev, xcp_id);
788 u64 tmp;
789
790 if (adev->gmc.num_mem_partitions && xcp_id >= 0 && mem_id >= 0) {
791 if (adev->gmc.is_app_apu && adev->gmc.num_mem_partitions == 1) {
792 /* In NPS1 mode, we should restrict the vram reporting
793 * tied to the ttm_pages_limit which is 1/2 of the system
794 * memory. For other partition modes, the HBM is uniformly
795 * divided already per numa node reported. If user wants to
796 * go beyond the default ttm limit and maximize the ROCm
797 * allocations, they can go up to max ttm and sysmem limits.
798 */
799
800 tmp = (ttm_tt_pages_limit() << PAGE_SHIFT) / num_online_nodes();
801 } else {
802 tmp = adev->gmc.mem_partitions[mem_id].size;
803 }
804 do_div(tmp, adev->xcp_mgr->num_xcp_per_mem_partition);
805 return ALIGN_DOWN(tmp, PAGE_SIZE);
806 } else if (adev->apu_prefer_gtt) {
807 return (ttm_tt_pages_limit() << PAGE_SHIFT);
808 } else {
809 return adev->gmc.real_vram_size;
810 }
811}
812
813int amdgpu_amdkfd_unmap_hiq(struct amdgpu_device *adev, u32 doorbell_off,
814 u32 inst)
815{
816 struct amdgpu_kiq *kiq = &adev->gfx.kiq[inst];
817 struct amdgpu_ring *kiq_ring = &kiq->ring;
818 struct amdgpu_ring_funcs *ring_funcs;
819 struct amdgpu_ring *ring;
820 int r = 0;
821
822 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
823 return -EINVAL;
824
825 if (!kiq_ring->sched.ready || amdgpu_in_reset(adev))
826 return 0;
827
828 ring_funcs = kzalloc(sizeof(*ring_funcs), GFP_KERNEL);
829 if (!ring_funcs)
830 return -ENOMEM;
831
832 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
833 if (!ring) {
834 r = -ENOMEM;
835 goto free_ring_funcs;
836 }
837
838 ring_funcs->type = AMDGPU_RING_TYPE_COMPUTE;
839 ring->doorbell_index = doorbell_off;
840 ring->funcs = ring_funcs;
841
842 spin_lock(lock: &kiq->ring_lock);
843
844 if (amdgpu_ring_alloc(ring: kiq_ring, ndw: kiq->pmf->unmap_queues_size)) {
845 spin_unlock(lock: &kiq->ring_lock);
846 r = -ENOMEM;
847 goto free_ring;
848 }
849
850 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, RESET_QUEUES, 0, 0);
851
852 /* Submit unmap queue packet */
853 amdgpu_ring_commit(ring: kiq_ring);
854 /*
855 * Ring test will do a basic scratch register change check. Just run
856 * this to ensure that unmap queues that is submitted before got
857 * processed successfully before returning.
858 */
859 r = amdgpu_ring_test_helper(ring: kiq_ring);
860
861 spin_unlock(lock: &kiq->ring_lock);
862
863free_ring:
864 kfree(objp: ring);
865
866free_ring_funcs:
867 kfree(objp: ring_funcs);
868
869 return r;
870}
871
872/* Stop scheduling on KFD */
873int amdgpu_amdkfd_stop_sched(struct amdgpu_device *adev, uint32_t node_id)
874{
875 if (!adev->kfd.init_complete)
876 return 0;
877
878 return kgd2kfd_stop_sched(kfd: adev->kfd.dev, node_id);
879}
880
881/* Start scheduling on KFD */
882int amdgpu_amdkfd_start_sched(struct amdgpu_device *adev, uint32_t node_id)
883{
884 if (!adev->kfd.init_complete)
885 return 0;
886
887 return kgd2kfd_start_sched(kfd: adev->kfd.dev, node_id);
888}
889
890/* check if there are KFD queues active */
891bool amdgpu_amdkfd_compute_active(struct amdgpu_device *adev, uint32_t node_id)
892{
893 if (!adev->kfd.init_complete)
894 return false;
895
896 return kgd2kfd_compute_active(kfd: adev->kfd.dev, node_id);
897}
898
899/* Config CGTT_SQ_CLK_CTRL */
900int amdgpu_amdkfd_config_sq_perfmon(struct amdgpu_device *adev, uint32_t xcp_id,
901 bool core_override_enable, bool reg_override_enable, bool perfmon_override_enable)
902{
903 int r;
904
905 if (!adev->kfd.init_complete)
906 return 0;
907
908 r = psp_config_sq_perfmon(psp: &adev->psp, xcp_id, core_override_enable,
909 reg_override_enable, perfmon_override_enable);
910
911 return r;
912}
913

source code of linux/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c