1 | // SPDX-License-Identifier: GPL-2.0-or-later |
2 | /* |
3 | * A driver for the ARM PL022 PrimeCell SSP/SPI bus master. |
4 | * |
5 | * Copyright (C) 2008-2012 ST-Ericsson AB |
6 | * Copyright (C) 2006 STMicroelectronics Pvt. Ltd. |
7 | * |
8 | * Author: Linus Walleij <linus.walleij@stericsson.com> |
9 | * |
10 | * Initial version inspired by: |
11 | * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c |
12 | * Initial adoption to PL022 by: |
13 | * Sachin Verma <sachin.verma@st.com> |
14 | */ |
15 | |
16 | #include <linux/init.h> |
17 | #include <linux/module.h> |
18 | #include <linux/device.h> |
19 | #include <linux/ioport.h> |
20 | #include <linux/errno.h> |
21 | #include <linux/interrupt.h> |
22 | #include <linux/spi/spi.h> |
23 | #include <linux/delay.h> |
24 | #include <linux/clk.h> |
25 | #include <linux/err.h> |
26 | #include <linux/amba/bus.h> |
27 | #include <linux/amba/pl022.h> |
28 | #include <linux/io.h> |
29 | #include <linux/slab.h> |
30 | #include <linux/dmaengine.h> |
31 | #include <linux/dma-mapping.h> |
32 | #include <linux/scatterlist.h> |
33 | #include <linux/pm_runtime.h> |
34 | #include <linux/of.h> |
35 | #include <linux/pinctrl/consumer.h> |
36 | |
37 | /* |
38 | * This macro is used to define some register default values. |
39 | * reg is masked with mask, the OR:ed with an (again masked) |
40 | * val shifted sb steps to the left. |
41 | */ |
42 | #define SSP_WRITE_BITS(reg, val, mask, sb) \ |
43 | ((reg) = (((reg) & ~(mask)) | (((val)<<(sb)) & (mask)))) |
44 | |
45 | /* |
46 | * This macro is also used to define some default values. |
47 | * It will just shift val by sb steps to the left and mask |
48 | * the result with mask. |
49 | */ |
50 | #define GEN_MASK_BITS(val, mask, sb) \ |
51 | (((val)<<(sb)) & (mask)) |
52 | |
53 | #define DRIVE_TX 0 |
54 | #define DO_NOT_DRIVE_TX 1 |
55 | |
56 | #define DO_NOT_QUEUE_DMA 0 |
57 | #define QUEUE_DMA 1 |
58 | |
59 | #define RX_TRANSFER 1 |
60 | #define TX_TRANSFER 2 |
61 | |
62 | /* |
63 | * Macros to access SSP Registers with their offsets |
64 | */ |
65 | #define SSP_CR0(r) (r + 0x000) |
66 | #define SSP_CR1(r) (r + 0x004) |
67 | #define SSP_DR(r) (r + 0x008) |
68 | #define SSP_SR(r) (r + 0x00C) |
69 | #define SSP_CPSR(r) (r + 0x010) |
70 | #define SSP_IMSC(r) (r + 0x014) |
71 | #define SSP_RIS(r) (r + 0x018) |
72 | #define SSP_MIS(r) (r + 0x01C) |
73 | #define SSP_ICR(r) (r + 0x020) |
74 | #define SSP_DMACR(r) (r + 0x024) |
75 | #define SSP_CSR(r) (r + 0x030) /* vendor extension */ |
76 | #define SSP_ITCR(r) (r + 0x080) |
77 | #define SSP_ITIP(r) (r + 0x084) |
78 | #define SSP_ITOP(r) (r + 0x088) |
79 | #define SSP_TDR(r) (r + 0x08C) |
80 | |
81 | #define SSP_PID0(r) (r + 0xFE0) |
82 | #define SSP_PID1(r) (r + 0xFE4) |
83 | #define SSP_PID2(r) (r + 0xFE8) |
84 | #define SSP_PID3(r) (r + 0xFEC) |
85 | |
86 | #define SSP_CID0(r) (r + 0xFF0) |
87 | #define SSP_CID1(r) (r + 0xFF4) |
88 | #define SSP_CID2(r) (r + 0xFF8) |
89 | #define SSP_CID3(r) (r + 0xFFC) |
90 | |
91 | /* |
92 | * SSP Control Register 0 - SSP_CR0 |
93 | */ |
94 | #define SSP_CR0_MASK_DSS (0x0FUL << 0) |
95 | #define SSP_CR0_MASK_FRF (0x3UL << 4) |
96 | #define SSP_CR0_MASK_SPO (0x1UL << 6) |
97 | #define SSP_CR0_MASK_SPH (0x1UL << 7) |
98 | #define SSP_CR0_MASK_SCR (0xFFUL << 8) |
99 | |
100 | /* |
101 | * The ST version of this block moves som bits |
102 | * in SSP_CR0 and extends it to 32 bits |
103 | */ |
104 | #define SSP_CR0_MASK_DSS_ST (0x1FUL << 0) |
105 | #define SSP_CR0_MASK_HALFDUP_ST (0x1UL << 5) |
106 | #define SSP_CR0_MASK_CSS_ST (0x1FUL << 16) |
107 | #define SSP_CR0_MASK_FRF_ST (0x3UL << 21) |
108 | |
109 | /* |
110 | * SSP Control Register 0 - SSP_CR1 |
111 | */ |
112 | #define SSP_CR1_MASK_LBM (0x1UL << 0) |
113 | #define SSP_CR1_MASK_SSE (0x1UL << 1) |
114 | #define SSP_CR1_MASK_MS (0x1UL << 2) |
115 | #define SSP_CR1_MASK_SOD (0x1UL << 3) |
116 | |
117 | /* |
118 | * The ST version of this block adds some bits |
119 | * in SSP_CR1 |
120 | */ |
121 | #define SSP_CR1_MASK_RENDN_ST (0x1UL << 4) |
122 | #define SSP_CR1_MASK_TENDN_ST (0x1UL << 5) |
123 | #define SSP_CR1_MASK_MWAIT_ST (0x1UL << 6) |
124 | #define SSP_CR1_MASK_RXIFLSEL_ST (0x7UL << 7) |
125 | #define SSP_CR1_MASK_TXIFLSEL_ST (0x7UL << 10) |
126 | /* This one is only in the PL023 variant */ |
127 | #define SSP_CR1_MASK_FBCLKDEL_ST (0x7UL << 13) |
128 | |
129 | /* |
130 | * SSP Status Register - SSP_SR |
131 | */ |
132 | #define SSP_SR_MASK_TFE (0x1UL << 0) /* Transmit FIFO empty */ |
133 | #define SSP_SR_MASK_TNF (0x1UL << 1) /* Transmit FIFO not full */ |
134 | #define SSP_SR_MASK_RNE (0x1UL << 2) /* Receive FIFO not empty */ |
135 | #define SSP_SR_MASK_RFF (0x1UL << 3) /* Receive FIFO full */ |
136 | #define SSP_SR_MASK_BSY (0x1UL << 4) /* Busy Flag */ |
137 | |
138 | /* |
139 | * SSP Clock Prescale Register - SSP_CPSR |
140 | */ |
141 | #define SSP_CPSR_MASK_CPSDVSR (0xFFUL << 0) |
142 | |
143 | /* |
144 | * SSP Interrupt Mask Set/Clear Register - SSP_IMSC |
145 | */ |
146 | #define SSP_IMSC_MASK_RORIM (0x1UL << 0) /* Receive Overrun Interrupt mask */ |
147 | #define SSP_IMSC_MASK_RTIM (0x1UL << 1) /* Receive timeout Interrupt mask */ |
148 | #define SSP_IMSC_MASK_RXIM (0x1UL << 2) /* Receive FIFO Interrupt mask */ |
149 | #define SSP_IMSC_MASK_TXIM (0x1UL << 3) /* Transmit FIFO Interrupt mask */ |
150 | |
151 | /* |
152 | * SSP Raw Interrupt Status Register - SSP_RIS |
153 | */ |
154 | /* Receive Overrun Raw Interrupt status */ |
155 | #define SSP_RIS_MASK_RORRIS (0x1UL << 0) |
156 | /* Receive Timeout Raw Interrupt status */ |
157 | #define SSP_RIS_MASK_RTRIS (0x1UL << 1) |
158 | /* Receive FIFO Raw Interrupt status */ |
159 | #define SSP_RIS_MASK_RXRIS (0x1UL << 2) |
160 | /* Transmit FIFO Raw Interrupt status */ |
161 | #define SSP_RIS_MASK_TXRIS (0x1UL << 3) |
162 | |
163 | /* |
164 | * SSP Masked Interrupt Status Register - SSP_MIS |
165 | */ |
166 | /* Receive Overrun Masked Interrupt status */ |
167 | #define SSP_MIS_MASK_RORMIS (0x1UL << 0) |
168 | /* Receive Timeout Masked Interrupt status */ |
169 | #define SSP_MIS_MASK_RTMIS (0x1UL << 1) |
170 | /* Receive FIFO Masked Interrupt status */ |
171 | #define SSP_MIS_MASK_RXMIS (0x1UL << 2) |
172 | /* Transmit FIFO Masked Interrupt status */ |
173 | #define SSP_MIS_MASK_TXMIS (0x1UL << 3) |
174 | |
175 | /* |
176 | * SSP Interrupt Clear Register - SSP_ICR |
177 | */ |
178 | /* Receive Overrun Raw Clear Interrupt bit */ |
179 | #define SSP_ICR_MASK_RORIC (0x1UL << 0) |
180 | /* Receive Timeout Clear Interrupt bit */ |
181 | #define SSP_ICR_MASK_RTIC (0x1UL << 1) |
182 | |
183 | /* |
184 | * SSP DMA Control Register - SSP_DMACR |
185 | */ |
186 | /* Receive DMA Enable bit */ |
187 | #define SSP_DMACR_MASK_RXDMAE (0x1UL << 0) |
188 | /* Transmit DMA Enable bit */ |
189 | #define SSP_DMACR_MASK_TXDMAE (0x1UL << 1) |
190 | |
191 | /* |
192 | * SSP Chip Select Control Register - SSP_CSR |
193 | * (vendor extension) |
194 | */ |
195 | #define SSP_CSR_CSVALUE_MASK (0x1FUL << 0) |
196 | |
197 | /* |
198 | * SSP Integration Test control Register - SSP_ITCR |
199 | */ |
200 | #define SSP_ITCR_MASK_ITEN (0x1UL << 0) |
201 | #define SSP_ITCR_MASK_TESTFIFO (0x1UL << 1) |
202 | |
203 | /* |
204 | * SSP Integration Test Input Register - SSP_ITIP |
205 | */ |
206 | #define ITIP_MASK_SSPRXD (0x1UL << 0) |
207 | #define ITIP_MASK_SSPFSSIN (0x1UL << 1) |
208 | #define ITIP_MASK_SSPCLKIN (0x1UL << 2) |
209 | #define ITIP_MASK_RXDMAC (0x1UL << 3) |
210 | #define ITIP_MASK_TXDMAC (0x1UL << 4) |
211 | #define ITIP_MASK_SSPTXDIN (0x1UL << 5) |
212 | |
213 | /* |
214 | * SSP Integration Test output Register - SSP_ITOP |
215 | */ |
216 | #define ITOP_MASK_SSPTXD (0x1UL << 0) |
217 | #define ITOP_MASK_SSPFSSOUT (0x1UL << 1) |
218 | #define ITOP_MASK_SSPCLKOUT (0x1UL << 2) |
219 | #define ITOP_MASK_SSPOEn (0x1UL << 3) |
220 | #define ITOP_MASK_SSPCTLOEn (0x1UL << 4) |
221 | #define ITOP_MASK_RORINTR (0x1UL << 5) |
222 | #define ITOP_MASK_RTINTR (0x1UL << 6) |
223 | #define ITOP_MASK_RXINTR (0x1UL << 7) |
224 | #define ITOP_MASK_TXINTR (0x1UL << 8) |
225 | #define ITOP_MASK_INTR (0x1UL << 9) |
226 | #define ITOP_MASK_RXDMABREQ (0x1UL << 10) |
227 | #define ITOP_MASK_RXDMASREQ (0x1UL << 11) |
228 | #define ITOP_MASK_TXDMABREQ (0x1UL << 12) |
229 | #define ITOP_MASK_TXDMASREQ (0x1UL << 13) |
230 | |
231 | /* |
232 | * SSP Test Data Register - SSP_TDR |
233 | */ |
234 | #define TDR_MASK_TESTDATA (0xFFFFFFFF) |
235 | |
236 | /* |
237 | * Message State |
238 | * we use the spi_message.state (void *) pointer to |
239 | * hold a single state value, that's why all this |
240 | * (void *) casting is done here. |
241 | */ |
242 | #define STATE_START ((void *) 0) |
243 | #define STATE_RUNNING ((void *) 1) |
244 | #define STATE_DONE ((void *) 2) |
245 | #define STATE_ERROR ((void *) -1) |
246 | #define STATE_TIMEOUT ((void *) -2) |
247 | |
248 | /* |
249 | * SSP State - Whether Enabled or Disabled |
250 | */ |
251 | #define SSP_DISABLED (0) |
252 | #define SSP_ENABLED (1) |
253 | |
254 | /* |
255 | * SSP DMA State - Whether DMA Enabled or Disabled |
256 | */ |
257 | #define SSP_DMA_DISABLED (0) |
258 | #define SSP_DMA_ENABLED (1) |
259 | |
260 | /* |
261 | * SSP Clock Defaults |
262 | */ |
263 | #define SSP_DEFAULT_CLKRATE 0x2 |
264 | #define SSP_DEFAULT_PRESCALE 0x40 |
265 | |
266 | /* |
267 | * SSP Clock Parameter ranges |
268 | */ |
269 | #define CPSDVR_MIN 0x02 |
270 | #define CPSDVR_MAX 0xFE |
271 | #define SCR_MIN 0x00 |
272 | #define SCR_MAX 0xFF |
273 | |
274 | /* |
275 | * SSP Interrupt related Macros |
276 | */ |
277 | #define DEFAULT_SSP_REG_IMSC 0x0UL |
278 | #define DISABLE_ALL_INTERRUPTS DEFAULT_SSP_REG_IMSC |
279 | #define ENABLE_ALL_INTERRUPTS ( \ |
280 | SSP_IMSC_MASK_RORIM | \ |
281 | SSP_IMSC_MASK_RTIM | \ |
282 | SSP_IMSC_MASK_RXIM | \ |
283 | SSP_IMSC_MASK_TXIM \ |
284 | ) |
285 | |
286 | #define CLEAR_ALL_INTERRUPTS 0x3 |
287 | |
288 | #define SPI_POLLING_TIMEOUT 1000 |
289 | |
290 | /* |
291 | * The type of reading going on this chip |
292 | */ |
293 | enum ssp_reading { |
294 | READING_NULL, |
295 | READING_U8, |
296 | READING_U16, |
297 | READING_U32 |
298 | }; |
299 | |
300 | /* |
301 | * The type of writing going on this chip |
302 | */ |
303 | enum ssp_writing { |
304 | WRITING_NULL, |
305 | WRITING_U8, |
306 | WRITING_U16, |
307 | WRITING_U32 |
308 | }; |
309 | |
310 | /** |
311 | * struct vendor_data - vendor-specific config parameters |
312 | * for PL022 derivates |
313 | * @fifodepth: depth of FIFOs (both) |
314 | * @max_bpw: maximum number of bits per word |
315 | * @unidir: supports unidirection transfers |
316 | * @extended_cr: 32 bit wide control register 0 with extra |
317 | * features and extra features in CR1 as found in the ST variants |
318 | * @pl023: supports a subset of the ST extensions called "PL023" |
319 | * @loopback: supports loopback mode |
320 | * @internal_cs_ctrl: supports chip select control register |
321 | */ |
322 | struct vendor_data { |
323 | int fifodepth; |
324 | int max_bpw; |
325 | bool unidir; |
326 | bool extended_cr; |
327 | bool pl023; |
328 | bool loopback; |
329 | bool internal_cs_ctrl; |
330 | }; |
331 | |
332 | /** |
333 | * struct pl022 - This is the private SSP driver data structure |
334 | * @adev: AMBA device model hookup |
335 | * @vendor: vendor data for the IP block |
336 | * @phybase: the physical memory where the SSP device resides |
337 | * @virtbase: the virtual memory where the SSP is mapped |
338 | * @clk: outgoing clock "SPICLK" for the SPI bus |
339 | * @host: SPI framework hookup |
340 | * @host_info: controller-specific data from machine setup |
341 | * @cur_transfer: Pointer to current spi_transfer |
342 | * @cur_chip: pointer to current clients chip(assigned from controller_state) |
343 | * @tx: current position in TX buffer to be read |
344 | * @tx_end: end position in TX buffer to be read |
345 | * @rx: current position in RX buffer to be written |
346 | * @rx_end: end position in RX buffer to be written |
347 | * @read: the type of read currently going on |
348 | * @write: the type of write currently going on |
349 | * @exp_fifo_level: expected FIFO level |
350 | * @rx_lev_trig: receive FIFO watermark level which triggers IRQ |
351 | * @tx_lev_trig: transmit FIFO watermark level which triggers IRQ |
352 | * @dma_rx_channel: optional channel for RX DMA |
353 | * @dma_tx_channel: optional channel for TX DMA |
354 | * @sgt_rx: scattertable for the RX transfer |
355 | * @sgt_tx: scattertable for the TX transfer |
356 | * @dummypage: a dummy page used for driving data on the bus with DMA |
357 | * @dma_running: indicates whether DMA is in operation |
358 | * @cur_cs: current chip select index |
359 | */ |
360 | struct pl022 { |
361 | struct amba_device *adev; |
362 | struct vendor_data *vendor; |
363 | resource_size_t phybase; |
364 | void __iomem *virtbase; |
365 | struct clk *clk; |
366 | struct spi_controller *host; |
367 | struct pl022_ssp_controller *host_info; |
368 | struct spi_transfer *cur_transfer; |
369 | struct chip_data *cur_chip; |
370 | void *tx; |
371 | void *tx_end; |
372 | void *rx; |
373 | void *rx_end; |
374 | enum ssp_reading read; |
375 | enum ssp_writing write; |
376 | u32 exp_fifo_level; |
377 | enum ssp_rx_level_trig rx_lev_trig; |
378 | enum ssp_tx_level_trig tx_lev_trig; |
379 | /* DMA settings */ |
380 | #ifdef CONFIG_DMA_ENGINE |
381 | struct dma_chan *dma_rx_channel; |
382 | struct dma_chan *dma_tx_channel; |
383 | struct sg_table sgt_rx; |
384 | struct sg_table sgt_tx; |
385 | char *dummypage; |
386 | bool dma_running; |
387 | #endif |
388 | int cur_cs; |
389 | }; |
390 | |
391 | /** |
392 | * struct chip_data - To maintain runtime state of SSP for each client chip |
393 | * @cr0: Value of control register CR0 of SSP - on later ST variants this |
394 | * register is 32 bits wide rather than just 16 |
395 | * @cr1: Value of control register CR1 of SSP |
396 | * @dmacr: Value of DMA control Register of SSP |
397 | * @cpsr: Value of Clock prescale register |
398 | * @n_bytes: how many bytes(power of 2) reqd for a given data width of client |
399 | * @enable_dma: Whether to enable DMA or not |
400 | * @read: function ptr to be used to read when doing xfer for this chip |
401 | * @write: function ptr to be used to write when doing xfer for this chip |
402 | * @xfer_type: polling/interrupt/DMA |
403 | * |
404 | * Runtime state of the SSP controller, maintained per chip, |
405 | * This would be set according to the current message that would be served |
406 | */ |
407 | struct chip_data { |
408 | u32 cr0; |
409 | u16 cr1; |
410 | u16 dmacr; |
411 | u16 cpsr; |
412 | u8 n_bytes; |
413 | bool enable_dma; |
414 | enum ssp_reading read; |
415 | enum ssp_writing write; |
416 | int xfer_type; |
417 | }; |
418 | |
419 | /** |
420 | * internal_cs_control - Control chip select signals via SSP_CSR. |
421 | * @pl022: SSP driver private data structure |
422 | * @enable: select/delect the chip |
423 | * |
424 | * Used on controller with internal chip select control via SSP_CSR register |
425 | * (vendor extension). Each of the 5 LSB in the register controls one chip |
426 | * select signal. |
427 | */ |
428 | static void internal_cs_control(struct pl022 *pl022, bool enable) |
429 | { |
430 | u32 tmp; |
431 | |
432 | tmp = readw(SSP_CSR(pl022->virtbase)); |
433 | if (enable) |
434 | tmp &= ~BIT(pl022->cur_cs); |
435 | else |
436 | tmp |= BIT(pl022->cur_cs); |
437 | writew(val: tmp, SSP_CSR(pl022->virtbase)); |
438 | } |
439 | |
440 | static void pl022_cs_control(struct spi_device *spi, bool enable) |
441 | { |
442 | struct pl022 *pl022 = spi_controller_get_devdata(ctlr: spi->controller); |
443 | if (pl022->vendor->internal_cs_ctrl) |
444 | internal_cs_control(pl022, enable); |
445 | } |
446 | |
447 | /** |
448 | * flush - flush the FIFO to reach a clean state |
449 | * @pl022: SSP driver private data structure |
450 | */ |
451 | static int flush(struct pl022 *pl022) |
452 | { |
453 | unsigned long limit = loops_per_jiffy << 1; |
454 | |
455 | dev_dbg(&pl022->adev->dev, "flush\n" ); |
456 | do { |
457 | while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) |
458 | readw(SSP_DR(pl022->virtbase)); |
459 | } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--); |
460 | |
461 | pl022->exp_fifo_level = 0; |
462 | |
463 | return limit; |
464 | } |
465 | |
466 | /** |
467 | * restore_state - Load configuration of current chip |
468 | * @pl022: SSP driver private data structure |
469 | */ |
470 | static void restore_state(struct pl022 *pl022) |
471 | { |
472 | struct chip_data *chip = pl022->cur_chip; |
473 | |
474 | if (pl022->vendor->extended_cr) |
475 | writel(val: chip->cr0, SSP_CR0(pl022->virtbase)); |
476 | else |
477 | writew(val: chip->cr0, SSP_CR0(pl022->virtbase)); |
478 | writew(val: chip->cr1, SSP_CR1(pl022->virtbase)); |
479 | writew(val: chip->dmacr, SSP_DMACR(pl022->virtbase)); |
480 | writew(val: chip->cpsr, SSP_CPSR(pl022->virtbase)); |
481 | writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); |
482 | writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); |
483 | } |
484 | |
485 | /* |
486 | * Default SSP Register Values |
487 | */ |
488 | #define DEFAULT_SSP_REG_CR0 ( \ |
489 | GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS, 0) | \ |
490 | GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF, 4) | \ |
491 | GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ |
492 | GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ |
493 | GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \ |
494 | ) |
495 | |
496 | /* ST versions have slightly different bit layout */ |
497 | #define DEFAULT_SSP_REG_CR0_ST ( \ |
498 | GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \ |
499 | GEN_MASK_BITS(SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, SSP_CR0_MASK_HALFDUP_ST, 5) | \ |
500 | GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ |
501 | GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ |
502 | GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) | \ |
503 | GEN_MASK_BITS(SSP_BITS_8, SSP_CR0_MASK_CSS_ST, 16) | \ |
504 | GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF_ST, 21) \ |
505 | ) |
506 | |
507 | /* The PL023 version is slightly different again */ |
508 | #define DEFAULT_SSP_REG_CR0_ST_PL023 ( \ |
509 | GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \ |
510 | GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ |
511 | GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ |
512 | GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \ |
513 | ) |
514 | |
515 | #define DEFAULT_SSP_REG_CR1 ( \ |
516 | GEN_MASK_BITS(LOOPBACK_DISABLED, SSP_CR1_MASK_LBM, 0) | \ |
517 | GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \ |
518 | GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \ |
519 | GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) \ |
520 | ) |
521 | |
522 | /* ST versions extend this register to use all 16 bits */ |
523 | #define DEFAULT_SSP_REG_CR1_ST ( \ |
524 | DEFAULT_SSP_REG_CR1 | \ |
525 | GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \ |
526 | GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \ |
527 | GEN_MASK_BITS(SSP_MWIRE_WAIT_ZERO, SSP_CR1_MASK_MWAIT_ST, 6) |\ |
528 | GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \ |
529 | GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) \ |
530 | ) |
531 | |
532 | /* |
533 | * The PL023 variant has further differences: no loopback mode, no microwire |
534 | * support, and a new clock feedback delay setting. |
535 | */ |
536 | #define DEFAULT_SSP_REG_CR1_ST_PL023 ( \ |
537 | GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \ |
538 | GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \ |
539 | GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) | \ |
540 | GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \ |
541 | GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \ |
542 | GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \ |
543 | GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) | \ |
544 | GEN_MASK_BITS(SSP_FEEDBACK_CLK_DELAY_NONE, SSP_CR1_MASK_FBCLKDEL_ST, 13) \ |
545 | ) |
546 | |
547 | #define DEFAULT_SSP_REG_CPSR ( \ |
548 | GEN_MASK_BITS(SSP_DEFAULT_PRESCALE, SSP_CPSR_MASK_CPSDVSR, 0) \ |
549 | ) |
550 | |
551 | #define DEFAULT_SSP_REG_DMACR (\ |
552 | GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_RXDMAE, 0) | \ |
553 | GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_TXDMAE, 1) \ |
554 | ) |
555 | |
556 | /** |
557 | * load_ssp_default_config - Load default configuration for SSP |
558 | * @pl022: SSP driver private data structure |
559 | */ |
560 | static void load_ssp_default_config(struct pl022 *pl022) |
561 | { |
562 | if (pl022->vendor->pl023) { |
563 | writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase)); |
564 | writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase)); |
565 | } else if (pl022->vendor->extended_cr) { |
566 | writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase)); |
567 | writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase)); |
568 | } else { |
569 | writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase)); |
570 | writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase)); |
571 | } |
572 | writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase)); |
573 | writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase)); |
574 | writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); |
575 | writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); |
576 | } |
577 | |
578 | /* |
579 | * This will write to TX and read from RX according to the parameters |
580 | * set in pl022. |
581 | */ |
582 | static void readwriter(struct pl022 *pl022) |
583 | { |
584 | |
585 | /* |
586 | * The FIFO depth is different between primecell variants. |
587 | * I believe filling in too much in the FIFO might cause |
588 | * errons in 8bit wide transfers on ARM variants (just 8 words |
589 | * FIFO, means only 8x8 = 64 bits in FIFO) at least. |
590 | * |
591 | * To prevent this issue, the TX FIFO is only filled to the |
592 | * unused RX FIFO fill length, regardless of what the TX |
593 | * FIFO status flag indicates. |
594 | */ |
595 | dev_dbg(&pl022->adev->dev, |
596 | "%s, rx: %p, rxend: %p, tx: %p, txend: %p\n" , |
597 | __func__, pl022->rx, pl022->rx_end, pl022->tx, pl022->tx_end); |
598 | |
599 | /* Read as much as you can */ |
600 | while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) |
601 | && (pl022->rx < pl022->rx_end)) { |
602 | switch (pl022->read) { |
603 | case READING_NULL: |
604 | readw(SSP_DR(pl022->virtbase)); |
605 | break; |
606 | case READING_U8: |
607 | *(u8 *) (pl022->rx) = |
608 | readw(SSP_DR(pl022->virtbase)) & 0xFFU; |
609 | break; |
610 | case READING_U16: |
611 | *(u16 *) (pl022->rx) = |
612 | (u16) readw(SSP_DR(pl022->virtbase)); |
613 | break; |
614 | case READING_U32: |
615 | *(u32 *) (pl022->rx) = |
616 | readl(SSP_DR(pl022->virtbase)); |
617 | break; |
618 | } |
619 | pl022->rx += (pl022->cur_chip->n_bytes); |
620 | pl022->exp_fifo_level--; |
621 | } |
622 | /* |
623 | * Write as much as possible up to the RX FIFO size |
624 | */ |
625 | while ((pl022->exp_fifo_level < pl022->vendor->fifodepth) |
626 | && (pl022->tx < pl022->tx_end)) { |
627 | switch (pl022->write) { |
628 | case WRITING_NULL: |
629 | writew(val: 0x0, SSP_DR(pl022->virtbase)); |
630 | break; |
631 | case WRITING_U8: |
632 | writew(val: *(u8 *) (pl022->tx), SSP_DR(pl022->virtbase)); |
633 | break; |
634 | case WRITING_U16: |
635 | writew(val: (*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase)); |
636 | break; |
637 | case WRITING_U32: |
638 | writel(val: *(u32 *) (pl022->tx), SSP_DR(pl022->virtbase)); |
639 | break; |
640 | } |
641 | pl022->tx += (pl022->cur_chip->n_bytes); |
642 | pl022->exp_fifo_level++; |
643 | /* |
644 | * This inner reader takes care of things appearing in the RX |
645 | * FIFO as we're transmitting. This will happen a lot since the |
646 | * clock starts running when you put things into the TX FIFO, |
647 | * and then things are continuously clocked into the RX FIFO. |
648 | */ |
649 | while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) |
650 | && (pl022->rx < pl022->rx_end)) { |
651 | switch (pl022->read) { |
652 | case READING_NULL: |
653 | readw(SSP_DR(pl022->virtbase)); |
654 | break; |
655 | case READING_U8: |
656 | *(u8 *) (pl022->rx) = |
657 | readw(SSP_DR(pl022->virtbase)) & 0xFFU; |
658 | break; |
659 | case READING_U16: |
660 | *(u16 *) (pl022->rx) = |
661 | (u16) readw(SSP_DR(pl022->virtbase)); |
662 | break; |
663 | case READING_U32: |
664 | *(u32 *) (pl022->rx) = |
665 | readl(SSP_DR(pl022->virtbase)); |
666 | break; |
667 | } |
668 | pl022->rx += (pl022->cur_chip->n_bytes); |
669 | pl022->exp_fifo_level--; |
670 | } |
671 | } |
672 | /* |
673 | * When we exit here the TX FIFO should be full and the RX FIFO |
674 | * should be empty |
675 | */ |
676 | } |
677 | |
678 | /* |
679 | * This DMA functionality is only compiled in if we have |
680 | * access to the generic DMA devices/DMA engine. |
681 | */ |
682 | #ifdef CONFIG_DMA_ENGINE |
683 | static void unmap_free_dma_scatter(struct pl022 *pl022) |
684 | { |
685 | /* Unmap and free the SG tables */ |
686 | dma_unmap_sg(pl022->dma_tx_channel->device->dev, pl022->sgt_tx.sgl, |
687 | pl022->sgt_tx.nents, DMA_TO_DEVICE); |
688 | dma_unmap_sg(pl022->dma_rx_channel->device->dev, pl022->sgt_rx.sgl, |
689 | pl022->sgt_rx.nents, DMA_FROM_DEVICE); |
690 | sg_free_table(&pl022->sgt_rx); |
691 | sg_free_table(&pl022->sgt_tx); |
692 | } |
693 | |
694 | static void dma_callback(void *data) |
695 | { |
696 | struct pl022 *pl022 = data; |
697 | |
698 | BUG_ON(!pl022->sgt_rx.sgl); |
699 | |
700 | #ifdef VERBOSE_DEBUG |
701 | /* |
702 | * Optionally dump out buffers to inspect contents, this is |
703 | * good if you want to convince yourself that the loopback |
704 | * read/write contents are the same, when adopting to a new |
705 | * DMA engine. |
706 | */ |
707 | { |
708 | struct scatterlist *sg; |
709 | unsigned int i; |
710 | |
711 | dma_sync_sg_for_cpu(&pl022->adev->dev, |
712 | pl022->sgt_rx.sgl, |
713 | pl022->sgt_rx.nents, |
714 | DMA_FROM_DEVICE); |
715 | |
716 | for_each_sg(pl022->sgt_rx.sgl, sg, pl022->sgt_rx.nents, i) { |
717 | dev_dbg(&pl022->adev->dev, "SPI RX SG ENTRY: %d" , i); |
718 | print_hex_dump(KERN_ERR, "SPI RX: " , |
719 | DUMP_PREFIX_OFFSET, |
720 | 16, |
721 | 1, |
722 | sg_virt(sg), |
723 | sg_dma_len(sg), |
724 | 1); |
725 | } |
726 | for_each_sg(pl022->sgt_tx.sgl, sg, pl022->sgt_tx.nents, i) { |
727 | dev_dbg(&pl022->adev->dev, "SPI TX SG ENTRY: %d" , i); |
728 | print_hex_dump(KERN_ERR, "SPI TX: " , |
729 | DUMP_PREFIX_OFFSET, |
730 | 16, |
731 | 1, |
732 | sg_virt(sg), |
733 | sg_dma_len(sg), |
734 | 1); |
735 | } |
736 | } |
737 | #endif |
738 | |
739 | unmap_free_dma_scatter(pl022); |
740 | |
741 | spi_finalize_current_transfer(ctlr: pl022->host); |
742 | } |
743 | |
744 | static void setup_dma_scatter(struct pl022 *pl022, |
745 | void *buffer, |
746 | unsigned int length, |
747 | struct sg_table *sgtab) |
748 | { |
749 | struct scatterlist *sg; |
750 | int bytesleft = length; |
751 | void *bufp = buffer; |
752 | int mapbytes; |
753 | int i; |
754 | |
755 | if (buffer) { |
756 | for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { |
757 | /* |
758 | * If there are less bytes left than what fits |
759 | * in the current page (plus page alignment offset) |
760 | * we just feed in this, else we stuff in as much |
761 | * as we can. |
762 | */ |
763 | if (bytesleft < (PAGE_SIZE - offset_in_page(bufp))) |
764 | mapbytes = bytesleft; |
765 | else |
766 | mapbytes = PAGE_SIZE - offset_in_page(bufp); |
767 | sg_set_page(sg, virt_to_page(bufp), |
768 | len: mapbytes, offset_in_page(bufp)); |
769 | bufp += mapbytes; |
770 | bytesleft -= mapbytes; |
771 | dev_dbg(&pl022->adev->dev, |
772 | "set RX/TX target page @ %p, %d bytes, %d left\n" , |
773 | bufp, mapbytes, bytesleft); |
774 | } |
775 | } else { |
776 | /* Map the dummy buffer on every page */ |
777 | for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { |
778 | if (bytesleft < PAGE_SIZE) |
779 | mapbytes = bytesleft; |
780 | else |
781 | mapbytes = PAGE_SIZE; |
782 | sg_set_page(sg, virt_to_page(pl022->dummypage), |
783 | len: mapbytes, offset: 0); |
784 | bytesleft -= mapbytes; |
785 | dev_dbg(&pl022->adev->dev, |
786 | "set RX/TX to dummy page %d bytes, %d left\n" , |
787 | mapbytes, bytesleft); |
788 | |
789 | } |
790 | } |
791 | BUG_ON(bytesleft); |
792 | } |
793 | |
794 | /** |
795 | * configure_dma - configures the channels for the next transfer |
796 | * @pl022: SSP driver's private data structure |
797 | */ |
798 | static int configure_dma(struct pl022 *pl022) |
799 | { |
800 | struct dma_slave_config rx_conf = { |
801 | .src_addr = SSP_DR(pl022->phybase), |
802 | .direction = DMA_DEV_TO_MEM, |
803 | .device_fc = false, |
804 | }; |
805 | struct dma_slave_config tx_conf = { |
806 | .dst_addr = SSP_DR(pl022->phybase), |
807 | .direction = DMA_MEM_TO_DEV, |
808 | .device_fc = false, |
809 | }; |
810 | unsigned int pages; |
811 | int ret; |
812 | int rx_sglen, tx_sglen; |
813 | struct dma_chan *rxchan = pl022->dma_rx_channel; |
814 | struct dma_chan *txchan = pl022->dma_tx_channel; |
815 | struct dma_async_tx_descriptor *rxdesc; |
816 | struct dma_async_tx_descriptor *txdesc; |
817 | |
818 | /* Check that the channels are available */ |
819 | if (!rxchan || !txchan) |
820 | return -ENODEV; |
821 | |
822 | /* |
823 | * If supplied, the DMA burstsize should equal the FIFO trigger level. |
824 | * Notice that the DMA engine uses one-to-one mapping. Since we can |
825 | * not trigger on 2 elements this needs explicit mapping rather than |
826 | * calculation. |
827 | */ |
828 | switch (pl022->rx_lev_trig) { |
829 | case SSP_RX_1_OR_MORE_ELEM: |
830 | rx_conf.src_maxburst = 1; |
831 | break; |
832 | case SSP_RX_4_OR_MORE_ELEM: |
833 | rx_conf.src_maxburst = 4; |
834 | break; |
835 | case SSP_RX_8_OR_MORE_ELEM: |
836 | rx_conf.src_maxburst = 8; |
837 | break; |
838 | case SSP_RX_16_OR_MORE_ELEM: |
839 | rx_conf.src_maxburst = 16; |
840 | break; |
841 | case SSP_RX_32_OR_MORE_ELEM: |
842 | rx_conf.src_maxburst = 32; |
843 | break; |
844 | default: |
845 | rx_conf.src_maxburst = pl022->vendor->fifodepth >> 1; |
846 | break; |
847 | } |
848 | |
849 | switch (pl022->tx_lev_trig) { |
850 | case SSP_TX_1_OR_MORE_EMPTY_LOC: |
851 | tx_conf.dst_maxburst = 1; |
852 | break; |
853 | case SSP_TX_4_OR_MORE_EMPTY_LOC: |
854 | tx_conf.dst_maxburst = 4; |
855 | break; |
856 | case SSP_TX_8_OR_MORE_EMPTY_LOC: |
857 | tx_conf.dst_maxburst = 8; |
858 | break; |
859 | case SSP_TX_16_OR_MORE_EMPTY_LOC: |
860 | tx_conf.dst_maxburst = 16; |
861 | break; |
862 | case SSP_TX_32_OR_MORE_EMPTY_LOC: |
863 | tx_conf.dst_maxburst = 32; |
864 | break; |
865 | default: |
866 | tx_conf.dst_maxburst = pl022->vendor->fifodepth >> 1; |
867 | break; |
868 | } |
869 | |
870 | switch (pl022->read) { |
871 | case READING_NULL: |
872 | /* Use the same as for writing */ |
873 | rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; |
874 | break; |
875 | case READING_U8: |
876 | rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; |
877 | break; |
878 | case READING_U16: |
879 | rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; |
880 | break; |
881 | case READING_U32: |
882 | rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
883 | break; |
884 | } |
885 | |
886 | switch (pl022->write) { |
887 | case WRITING_NULL: |
888 | /* Use the same as for reading */ |
889 | tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; |
890 | break; |
891 | case WRITING_U8: |
892 | tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; |
893 | break; |
894 | case WRITING_U16: |
895 | tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; |
896 | break; |
897 | case WRITING_U32: |
898 | tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
899 | break; |
900 | } |
901 | |
902 | /* SPI pecularity: we need to read and write the same width */ |
903 | if (rx_conf.src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) |
904 | rx_conf.src_addr_width = tx_conf.dst_addr_width; |
905 | if (tx_conf.dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) |
906 | tx_conf.dst_addr_width = rx_conf.src_addr_width; |
907 | BUG_ON(rx_conf.src_addr_width != tx_conf.dst_addr_width); |
908 | |
909 | dmaengine_slave_config(chan: rxchan, config: &rx_conf); |
910 | dmaengine_slave_config(chan: txchan, config: &tx_conf); |
911 | |
912 | /* Create sglists for the transfers */ |
913 | pages = DIV_ROUND_UP(pl022->cur_transfer->len, PAGE_SIZE); |
914 | dev_dbg(&pl022->adev->dev, "using %d pages for transfer\n" , pages); |
915 | |
916 | ret = sg_alloc_table(&pl022->sgt_rx, pages, GFP_ATOMIC); |
917 | if (ret) |
918 | goto err_alloc_rx_sg; |
919 | |
920 | ret = sg_alloc_table(&pl022->sgt_tx, pages, GFP_ATOMIC); |
921 | if (ret) |
922 | goto err_alloc_tx_sg; |
923 | |
924 | /* Fill in the scatterlists for the RX+TX buffers */ |
925 | setup_dma_scatter(pl022, buffer: pl022->rx, |
926 | length: pl022->cur_transfer->len, sgtab: &pl022->sgt_rx); |
927 | setup_dma_scatter(pl022, buffer: pl022->tx, |
928 | length: pl022->cur_transfer->len, sgtab: &pl022->sgt_tx); |
929 | |
930 | /* Map DMA buffers */ |
931 | rx_sglen = dma_map_sg(rxchan->device->dev, pl022->sgt_rx.sgl, |
932 | pl022->sgt_rx.nents, DMA_FROM_DEVICE); |
933 | if (!rx_sglen) |
934 | goto err_rx_sgmap; |
935 | |
936 | tx_sglen = dma_map_sg(txchan->device->dev, pl022->sgt_tx.sgl, |
937 | pl022->sgt_tx.nents, DMA_TO_DEVICE); |
938 | if (!tx_sglen) |
939 | goto err_tx_sgmap; |
940 | |
941 | /* Send both scatterlists */ |
942 | rxdesc = dmaengine_prep_slave_sg(chan: rxchan, |
943 | sgl: pl022->sgt_rx.sgl, |
944 | sg_len: rx_sglen, |
945 | dir: DMA_DEV_TO_MEM, |
946 | flags: DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
947 | if (!rxdesc) |
948 | goto err_rxdesc; |
949 | |
950 | txdesc = dmaengine_prep_slave_sg(chan: txchan, |
951 | sgl: pl022->sgt_tx.sgl, |
952 | sg_len: tx_sglen, |
953 | dir: DMA_MEM_TO_DEV, |
954 | flags: DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
955 | if (!txdesc) |
956 | goto err_txdesc; |
957 | |
958 | /* Put the callback on the RX transfer only, that should finish last */ |
959 | rxdesc->callback = dma_callback; |
960 | rxdesc->callback_param = pl022; |
961 | |
962 | /* Submit and fire RX and TX with TX last so we're ready to read! */ |
963 | dmaengine_submit(desc: rxdesc); |
964 | dmaengine_submit(desc: txdesc); |
965 | dma_async_issue_pending(chan: rxchan); |
966 | dma_async_issue_pending(chan: txchan); |
967 | pl022->dma_running = true; |
968 | |
969 | return 0; |
970 | |
971 | err_txdesc: |
972 | dmaengine_terminate_all(chan: txchan); |
973 | err_rxdesc: |
974 | dmaengine_terminate_all(chan: rxchan); |
975 | dma_unmap_sg(txchan->device->dev, pl022->sgt_tx.sgl, |
976 | pl022->sgt_tx.nents, DMA_TO_DEVICE); |
977 | err_tx_sgmap: |
978 | dma_unmap_sg(rxchan->device->dev, pl022->sgt_rx.sgl, |
979 | pl022->sgt_rx.nents, DMA_FROM_DEVICE); |
980 | err_rx_sgmap: |
981 | sg_free_table(&pl022->sgt_tx); |
982 | err_alloc_tx_sg: |
983 | sg_free_table(&pl022->sgt_rx); |
984 | err_alloc_rx_sg: |
985 | return -ENOMEM; |
986 | } |
987 | |
988 | static int pl022_dma_probe(struct pl022 *pl022) |
989 | { |
990 | dma_cap_mask_t mask; |
991 | |
992 | /* Try to acquire a generic DMA engine slave channel */ |
993 | dma_cap_zero(mask); |
994 | dma_cap_set(DMA_SLAVE, mask); |
995 | /* |
996 | * We need both RX and TX channels to do DMA, else do none |
997 | * of them. |
998 | */ |
999 | pl022->dma_rx_channel = dma_request_channel(mask, |
1000 | pl022->host_info->dma_filter, |
1001 | pl022->host_info->dma_rx_param); |
1002 | if (!pl022->dma_rx_channel) { |
1003 | dev_dbg(&pl022->adev->dev, "no RX DMA channel!\n" ); |
1004 | goto err_no_rxchan; |
1005 | } |
1006 | |
1007 | pl022->dma_tx_channel = dma_request_channel(mask, |
1008 | pl022->host_info->dma_filter, |
1009 | pl022->host_info->dma_tx_param); |
1010 | if (!pl022->dma_tx_channel) { |
1011 | dev_dbg(&pl022->adev->dev, "no TX DMA channel!\n" ); |
1012 | goto err_no_txchan; |
1013 | } |
1014 | |
1015 | pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL); |
1016 | if (!pl022->dummypage) |
1017 | goto err_no_dummypage; |
1018 | |
1019 | dev_info(&pl022->adev->dev, "setup for DMA on RX %s, TX %s\n" , |
1020 | dma_chan_name(pl022->dma_rx_channel), |
1021 | dma_chan_name(pl022->dma_tx_channel)); |
1022 | |
1023 | return 0; |
1024 | |
1025 | err_no_dummypage: |
1026 | dma_release_channel(chan: pl022->dma_tx_channel); |
1027 | err_no_txchan: |
1028 | dma_release_channel(chan: pl022->dma_rx_channel); |
1029 | pl022->dma_rx_channel = NULL; |
1030 | err_no_rxchan: |
1031 | dev_err(&pl022->adev->dev, |
1032 | "Failed to work in dma mode, work without dma!\n" ); |
1033 | return -ENODEV; |
1034 | } |
1035 | |
1036 | static int pl022_dma_autoprobe(struct pl022 *pl022) |
1037 | { |
1038 | struct device *dev = &pl022->adev->dev; |
1039 | struct dma_chan *chan; |
1040 | int err; |
1041 | |
1042 | /* automatically configure DMA channels from platform, normally using DT */ |
1043 | chan = dma_request_chan(dev, name: "rx" ); |
1044 | if (IS_ERR(ptr: chan)) { |
1045 | err = PTR_ERR(ptr: chan); |
1046 | goto err_no_rxchan; |
1047 | } |
1048 | |
1049 | pl022->dma_rx_channel = chan; |
1050 | |
1051 | chan = dma_request_chan(dev, name: "tx" ); |
1052 | if (IS_ERR(ptr: chan)) { |
1053 | err = PTR_ERR(ptr: chan); |
1054 | goto err_no_txchan; |
1055 | } |
1056 | |
1057 | pl022->dma_tx_channel = chan; |
1058 | |
1059 | pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL); |
1060 | if (!pl022->dummypage) { |
1061 | err = -ENOMEM; |
1062 | goto err_no_dummypage; |
1063 | } |
1064 | |
1065 | return 0; |
1066 | |
1067 | err_no_dummypage: |
1068 | dma_release_channel(chan: pl022->dma_tx_channel); |
1069 | pl022->dma_tx_channel = NULL; |
1070 | err_no_txchan: |
1071 | dma_release_channel(chan: pl022->dma_rx_channel); |
1072 | pl022->dma_rx_channel = NULL; |
1073 | err_no_rxchan: |
1074 | return err; |
1075 | } |
1076 | |
1077 | static void terminate_dma(struct pl022 *pl022) |
1078 | { |
1079 | if (!pl022->dma_running) |
1080 | return; |
1081 | |
1082 | struct dma_chan *rxchan = pl022->dma_rx_channel; |
1083 | struct dma_chan *txchan = pl022->dma_tx_channel; |
1084 | |
1085 | dmaengine_terminate_all(chan: rxchan); |
1086 | dmaengine_terminate_all(chan: txchan); |
1087 | unmap_free_dma_scatter(pl022); |
1088 | pl022->dma_running = false; |
1089 | } |
1090 | |
1091 | static void pl022_dma_remove(struct pl022 *pl022) |
1092 | { |
1093 | terminate_dma(pl022); |
1094 | if (pl022->dma_tx_channel) |
1095 | dma_release_channel(chan: pl022->dma_tx_channel); |
1096 | if (pl022->dma_rx_channel) |
1097 | dma_release_channel(chan: pl022->dma_rx_channel); |
1098 | kfree(objp: pl022->dummypage); |
1099 | } |
1100 | |
1101 | #else |
1102 | static inline int configure_dma(struct pl022 *pl022) |
1103 | { |
1104 | return -ENODEV; |
1105 | } |
1106 | |
1107 | static inline int pl022_dma_autoprobe(struct pl022 *pl022) |
1108 | { |
1109 | return 0; |
1110 | } |
1111 | |
1112 | static inline int pl022_dma_probe(struct pl022 *pl022) |
1113 | { |
1114 | return 0; |
1115 | } |
1116 | |
1117 | static inline void terminate_dma(struct pl022 *pl022) |
1118 | { |
1119 | } |
1120 | |
1121 | static inline void pl022_dma_remove(struct pl022 *pl022) |
1122 | { |
1123 | } |
1124 | #endif |
1125 | |
1126 | /** |
1127 | * pl022_interrupt_handler - Interrupt handler for SSP controller |
1128 | * @irq: IRQ number |
1129 | * @dev_id: Local device data |
1130 | * |
1131 | * This function handles interrupts generated for an interrupt based transfer. |
1132 | * If a receive overrun (ROR) interrupt is there then we disable SSP, flag the |
1133 | * current message's state as STATE_ERROR and schedule the tasklet |
1134 | * pump_transfers which will do the postprocessing of the current message by |
1135 | * calling giveback(). Otherwise it reads data from RX FIFO till there is no |
1136 | * more data, and writes data in TX FIFO till it is not full. If we complete |
1137 | * the transfer we move to the next transfer and schedule the tasklet. |
1138 | */ |
1139 | static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id) |
1140 | { |
1141 | struct pl022 *pl022 = dev_id; |
1142 | u16 irq_status = 0; |
1143 | /* Read the Interrupt Status Register */ |
1144 | irq_status = readw(SSP_MIS(pl022->virtbase)); |
1145 | |
1146 | if (unlikely(!irq_status)) |
1147 | return IRQ_NONE; |
1148 | |
1149 | /* |
1150 | * This handles the FIFO interrupts, the timeout |
1151 | * interrupts are flatly ignored, they cannot be |
1152 | * trusted. |
1153 | */ |
1154 | if (unlikely(irq_status & SSP_MIS_MASK_RORMIS)) { |
1155 | /* |
1156 | * Overrun interrupt - bail out since our Data has been |
1157 | * corrupted |
1158 | */ |
1159 | dev_err(&pl022->adev->dev, "FIFO overrun\n" ); |
1160 | if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF) |
1161 | dev_err(&pl022->adev->dev, |
1162 | "RXFIFO is full\n" ); |
1163 | |
1164 | /* |
1165 | * Disable and clear interrupts, disable SSP, |
1166 | * mark message with bad status so it can be |
1167 | * retried. |
1168 | */ |
1169 | writew(DISABLE_ALL_INTERRUPTS, |
1170 | SSP_IMSC(pl022->virtbase)); |
1171 | writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); |
1172 | writew(val: (readw(SSP_CR1(pl022->virtbase)) & |
1173 | (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); |
1174 | pl022->cur_transfer->error |= SPI_TRANS_FAIL_IO; |
1175 | spi_finalize_current_transfer(ctlr: pl022->host); |
1176 | return IRQ_HANDLED; |
1177 | } |
1178 | |
1179 | readwriter(pl022); |
1180 | |
1181 | if (pl022->tx == pl022->tx_end) { |
1182 | /* Disable Transmit interrupt, enable receive interrupt */ |
1183 | writew(val: (readw(SSP_IMSC(pl022->virtbase)) & |
1184 | ~SSP_IMSC_MASK_TXIM) | SSP_IMSC_MASK_RXIM, |
1185 | SSP_IMSC(pl022->virtbase)); |
1186 | } |
1187 | |
1188 | /* |
1189 | * Since all transactions must write as much as shall be read, |
1190 | * we can conclude the entire transaction once RX is complete. |
1191 | * At this point, all TX will always be finished. |
1192 | */ |
1193 | if (pl022->rx >= pl022->rx_end) { |
1194 | writew(DISABLE_ALL_INTERRUPTS, |
1195 | SSP_IMSC(pl022->virtbase)); |
1196 | writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); |
1197 | if (unlikely(pl022->rx > pl022->rx_end)) { |
1198 | dev_warn(&pl022->adev->dev, "read %u surplus " |
1199 | "bytes (did you request an odd " |
1200 | "number of bytes on a 16bit bus?)\n" , |
1201 | (u32) (pl022->rx - pl022->rx_end)); |
1202 | } |
1203 | spi_finalize_current_transfer(ctlr: pl022->host); |
1204 | return IRQ_HANDLED; |
1205 | } |
1206 | |
1207 | return IRQ_HANDLED; |
1208 | } |
1209 | |
1210 | /* |
1211 | * This sets up the pointers to memory for the next message to |
1212 | * send out on the SPI bus. |
1213 | */ |
1214 | static int set_up_next_transfer(struct pl022 *pl022, |
1215 | struct spi_transfer *transfer) |
1216 | { |
1217 | int residue; |
1218 | |
1219 | /* Sanity check the message for this bus width */ |
1220 | residue = pl022->cur_transfer->len % pl022->cur_chip->n_bytes; |
1221 | if (unlikely(residue != 0)) { |
1222 | dev_err(&pl022->adev->dev, |
1223 | "message of %u bytes to transmit but the current " |
1224 | "chip bus has a data width of %u bytes!\n" , |
1225 | pl022->cur_transfer->len, |
1226 | pl022->cur_chip->n_bytes); |
1227 | dev_err(&pl022->adev->dev, "skipping this message\n" ); |
1228 | return -EIO; |
1229 | } |
1230 | pl022->tx = (void *)transfer->tx_buf; |
1231 | pl022->tx_end = pl022->tx + pl022->cur_transfer->len; |
1232 | pl022->rx = (void *)transfer->rx_buf; |
1233 | pl022->rx_end = pl022->rx + pl022->cur_transfer->len; |
1234 | pl022->write = |
1235 | pl022->tx ? pl022->cur_chip->write : WRITING_NULL; |
1236 | pl022->read = pl022->rx ? pl022->cur_chip->read : READING_NULL; |
1237 | return 0; |
1238 | } |
1239 | |
1240 | static int do_interrupt_dma_transfer(struct pl022 *pl022) |
1241 | { |
1242 | int ret; |
1243 | |
1244 | /* |
1245 | * Default is to enable all interrupts except RX - |
1246 | * this will be enabled once TX is complete |
1247 | */ |
1248 | u32 irqflags = (u32)(ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM); |
1249 | |
1250 | ret = set_up_next_transfer(pl022, transfer: pl022->cur_transfer); |
1251 | if (ret) |
1252 | return ret; |
1253 | |
1254 | /* If we're using DMA, set up DMA here */ |
1255 | if (pl022->cur_chip->enable_dma) { |
1256 | /* Configure DMA transfer */ |
1257 | if (configure_dma(pl022)) { |
1258 | dev_dbg(&pl022->adev->dev, |
1259 | "configuration of DMA failed, fall back to interrupt mode\n" ); |
1260 | goto err_config_dma; |
1261 | } |
1262 | /* Disable interrupts in DMA mode, IRQ from DMA controller */ |
1263 | irqflags = DISABLE_ALL_INTERRUPTS; |
1264 | } |
1265 | err_config_dma: |
1266 | /* Enable SSP, turn on interrupts */ |
1267 | writew(val: (readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), |
1268 | SSP_CR1(pl022->virtbase)); |
1269 | writew(val: irqflags, SSP_IMSC(pl022->virtbase)); |
1270 | return 1; |
1271 | } |
1272 | |
1273 | static void print_current_status(struct pl022 *pl022) |
1274 | { |
1275 | u32 read_cr0; |
1276 | u16 read_cr1, read_dmacr, read_sr; |
1277 | |
1278 | if (pl022->vendor->extended_cr) |
1279 | read_cr0 = readl(SSP_CR0(pl022->virtbase)); |
1280 | else |
1281 | read_cr0 = readw(SSP_CR0(pl022->virtbase)); |
1282 | read_cr1 = readw(SSP_CR1(pl022->virtbase)); |
1283 | read_dmacr = readw(SSP_DMACR(pl022->virtbase)); |
1284 | read_sr = readw(SSP_SR(pl022->virtbase)); |
1285 | |
1286 | dev_warn(&pl022->adev->dev, "spi-pl022 CR0: %x\n" , read_cr0); |
1287 | dev_warn(&pl022->adev->dev, "spi-pl022 CR1: %x\n" , read_cr1); |
1288 | dev_warn(&pl022->adev->dev, "spi-pl022 DMACR: %x\n" , read_dmacr); |
1289 | dev_warn(&pl022->adev->dev, "spi-pl022 SR: %x\n" , read_sr); |
1290 | dev_warn(&pl022->adev->dev, |
1291 | "spi-pl022 exp_fifo_level/fifodepth: %u/%d\n" , |
1292 | pl022->exp_fifo_level, |
1293 | pl022->vendor->fifodepth); |
1294 | |
1295 | } |
1296 | |
1297 | static int do_polling_transfer(struct pl022 *pl022) |
1298 | { |
1299 | int ret; |
1300 | unsigned long time, timeout; |
1301 | |
1302 | /* Configuration Changing Per Transfer */ |
1303 | ret = set_up_next_transfer(pl022, transfer: pl022->cur_transfer); |
1304 | if (ret) |
1305 | return ret; |
1306 | /* Flush FIFOs and enable SSP */ |
1307 | flush(pl022); |
1308 | writew(val: (readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), |
1309 | SSP_CR1(pl022->virtbase)); |
1310 | |
1311 | dev_dbg(&pl022->adev->dev, "polling transfer ongoing ...\n" ); |
1312 | |
1313 | timeout = jiffies + msecs_to_jiffies(SPI_POLLING_TIMEOUT); |
1314 | while (pl022->tx < pl022->tx_end || pl022->rx < pl022->rx_end) { |
1315 | time = jiffies; |
1316 | readwriter(pl022); |
1317 | if (time_after(time, timeout)) { |
1318 | dev_warn(&pl022->adev->dev, |
1319 | "%s: timeout!\n" , __func__); |
1320 | print_current_status(pl022); |
1321 | return -ETIMEDOUT; |
1322 | } |
1323 | cpu_relax(); |
1324 | } |
1325 | |
1326 | return 0; |
1327 | } |
1328 | |
1329 | static int pl022_transfer_one(struct spi_controller *host, struct spi_device *spi, |
1330 | struct spi_transfer *transfer) |
1331 | { |
1332 | struct pl022 *pl022 = spi_controller_get_devdata(ctlr: host); |
1333 | |
1334 | pl022->cur_transfer = transfer; |
1335 | |
1336 | /* Setup the SPI using the per chip configuration */ |
1337 | pl022->cur_chip = spi_get_ctldata(spi); |
1338 | pl022->cur_cs = spi_get_chipselect(spi, idx: 0); |
1339 | |
1340 | restore_state(pl022); |
1341 | flush(pl022); |
1342 | |
1343 | if (pl022->cur_chip->xfer_type == POLLING_TRANSFER) |
1344 | return do_polling_transfer(pl022); |
1345 | else |
1346 | return do_interrupt_dma_transfer(pl022); |
1347 | } |
1348 | |
1349 | static void pl022_handle_err(struct spi_controller *ctlr, struct spi_message *message) |
1350 | { |
1351 | struct pl022 *pl022 = spi_controller_get_devdata(ctlr); |
1352 | |
1353 | terminate_dma(pl022); |
1354 | writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); |
1355 | writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); |
1356 | } |
1357 | |
1358 | static int pl022_unprepare_transfer_hardware(struct spi_controller *host) |
1359 | { |
1360 | struct pl022 *pl022 = spi_controller_get_devdata(ctlr: host); |
1361 | |
1362 | /* nothing more to do - disable spi/ssp and power off */ |
1363 | writew(val: (readw(SSP_CR1(pl022->virtbase)) & |
1364 | (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); |
1365 | |
1366 | return 0; |
1367 | } |
1368 | |
1369 | static int verify_controller_parameters(struct pl022 *pl022, |
1370 | struct pl022_config_chip const *chip_info) |
1371 | { |
1372 | if ((chip_info->iface < SSP_INTERFACE_MOTOROLA_SPI) |
1373 | || (chip_info->iface > SSP_INTERFACE_UNIDIRECTIONAL)) { |
1374 | dev_err(&pl022->adev->dev, |
1375 | "interface is configured incorrectly\n" ); |
1376 | return -EINVAL; |
1377 | } |
1378 | if ((chip_info->iface == SSP_INTERFACE_UNIDIRECTIONAL) && |
1379 | (!pl022->vendor->unidir)) { |
1380 | dev_err(&pl022->adev->dev, |
1381 | "unidirectional mode not supported in this " |
1382 | "hardware version\n" ); |
1383 | return -EINVAL; |
1384 | } |
1385 | if ((chip_info->hierarchy != SSP_MASTER) |
1386 | && (chip_info->hierarchy != SSP_SLAVE)) { |
1387 | dev_err(&pl022->adev->dev, |
1388 | "hierarchy is configured incorrectly\n" ); |
1389 | return -EINVAL; |
1390 | } |
1391 | if ((chip_info->com_mode != INTERRUPT_TRANSFER) |
1392 | && (chip_info->com_mode != DMA_TRANSFER) |
1393 | && (chip_info->com_mode != POLLING_TRANSFER)) { |
1394 | dev_err(&pl022->adev->dev, |
1395 | "Communication mode is configured incorrectly\n" ); |
1396 | return -EINVAL; |
1397 | } |
1398 | switch (chip_info->rx_lev_trig) { |
1399 | case SSP_RX_1_OR_MORE_ELEM: |
1400 | case SSP_RX_4_OR_MORE_ELEM: |
1401 | case SSP_RX_8_OR_MORE_ELEM: |
1402 | /* These are always OK, all variants can handle this */ |
1403 | break; |
1404 | case SSP_RX_16_OR_MORE_ELEM: |
1405 | if (pl022->vendor->fifodepth < 16) { |
1406 | dev_err(&pl022->adev->dev, |
1407 | "RX FIFO Trigger Level is configured incorrectly\n" ); |
1408 | return -EINVAL; |
1409 | } |
1410 | break; |
1411 | case SSP_RX_32_OR_MORE_ELEM: |
1412 | if (pl022->vendor->fifodepth < 32) { |
1413 | dev_err(&pl022->adev->dev, |
1414 | "RX FIFO Trigger Level is configured incorrectly\n" ); |
1415 | return -EINVAL; |
1416 | } |
1417 | break; |
1418 | default: |
1419 | dev_err(&pl022->adev->dev, |
1420 | "RX FIFO Trigger Level is configured incorrectly\n" ); |
1421 | return -EINVAL; |
1422 | } |
1423 | switch (chip_info->tx_lev_trig) { |
1424 | case SSP_TX_1_OR_MORE_EMPTY_LOC: |
1425 | case SSP_TX_4_OR_MORE_EMPTY_LOC: |
1426 | case SSP_TX_8_OR_MORE_EMPTY_LOC: |
1427 | /* These are always OK, all variants can handle this */ |
1428 | break; |
1429 | case SSP_TX_16_OR_MORE_EMPTY_LOC: |
1430 | if (pl022->vendor->fifodepth < 16) { |
1431 | dev_err(&pl022->adev->dev, |
1432 | "TX FIFO Trigger Level is configured incorrectly\n" ); |
1433 | return -EINVAL; |
1434 | } |
1435 | break; |
1436 | case SSP_TX_32_OR_MORE_EMPTY_LOC: |
1437 | if (pl022->vendor->fifodepth < 32) { |
1438 | dev_err(&pl022->adev->dev, |
1439 | "TX FIFO Trigger Level is configured incorrectly\n" ); |
1440 | return -EINVAL; |
1441 | } |
1442 | break; |
1443 | default: |
1444 | dev_err(&pl022->adev->dev, |
1445 | "TX FIFO Trigger Level is configured incorrectly\n" ); |
1446 | return -EINVAL; |
1447 | } |
1448 | if (chip_info->iface == SSP_INTERFACE_NATIONAL_MICROWIRE) { |
1449 | if ((chip_info->ctrl_len < SSP_BITS_4) |
1450 | || (chip_info->ctrl_len > SSP_BITS_32)) { |
1451 | dev_err(&pl022->adev->dev, |
1452 | "CTRL LEN is configured incorrectly\n" ); |
1453 | return -EINVAL; |
1454 | } |
1455 | if ((chip_info->wait_state != SSP_MWIRE_WAIT_ZERO) |
1456 | && (chip_info->wait_state != SSP_MWIRE_WAIT_ONE)) { |
1457 | dev_err(&pl022->adev->dev, |
1458 | "Wait State is configured incorrectly\n" ); |
1459 | return -EINVAL; |
1460 | } |
1461 | /* Half duplex is only available in the ST Micro version */ |
1462 | if (pl022->vendor->extended_cr) { |
1463 | if ((chip_info->duplex != |
1464 | SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) |
1465 | && (chip_info->duplex != |
1466 | SSP_MICROWIRE_CHANNEL_HALF_DUPLEX)) { |
1467 | dev_err(&pl022->adev->dev, |
1468 | "Microwire duplex mode is configured incorrectly\n" ); |
1469 | return -EINVAL; |
1470 | } |
1471 | } else { |
1472 | if (chip_info->duplex != SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) { |
1473 | dev_err(&pl022->adev->dev, |
1474 | "Microwire half duplex mode requested," |
1475 | " but this is only available in the" |
1476 | " ST version of PL022\n" ); |
1477 | return -EINVAL; |
1478 | } |
1479 | } |
1480 | } |
1481 | return 0; |
1482 | } |
1483 | |
1484 | static inline u32 spi_rate(u32 rate, u16 cpsdvsr, u16 scr) |
1485 | { |
1486 | return rate / (cpsdvsr * (1 + scr)); |
1487 | } |
1488 | |
1489 | static int calculate_effective_freq(struct pl022 *pl022, int freq, struct |
1490 | ssp_clock_params * clk_freq) |
1491 | { |
1492 | /* Lets calculate the frequency parameters */ |
1493 | u16 cpsdvsr = CPSDVR_MIN, scr = SCR_MIN; |
1494 | u32 rate, max_tclk, min_tclk, best_freq = 0, best_cpsdvsr = 0, |
1495 | best_scr = 0, tmp, found = 0; |
1496 | |
1497 | rate = clk_get_rate(clk: pl022->clk); |
1498 | /* cpsdvscr = 2 & scr 0 */ |
1499 | max_tclk = spi_rate(rate, CPSDVR_MIN, SCR_MIN); |
1500 | /* cpsdvsr = 254 & scr = 255 */ |
1501 | min_tclk = spi_rate(rate, CPSDVR_MAX, SCR_MAX); |
1502 | |
1503 | if (freq > max_tclk) |
1504 | dev_warn(&pl022->adev->dev, |
1505 | "Max speed that can be programmed is %d Hz, you requested %d\n" , |
1506 | max_tclk, freq); |
1507 | |
1508 | if (freq < min_tclk) { |
1509 | dev_err(&pl022->adev->dev, |
1510 | "Requested frequency: %d Hz is less than minimum possible %d Hz\n" , |
1511 | freq, min_tclk); |
1512 | return -EINVAL; |
1513 | } |
1514 | |
1515 | /* |
1516 | * best_freq will give closest possible available rate (<= requested |
1517 | * freq) for all values of scr & cpsdvsr. |
1518 | */ |
1519 | while ((cpsdvsr <= CPSDVR_MAX) && !found) { |
1520 | while (scr <= SCR_MAX) { |
1521 | tmp = spi_rate(rate, cpsdvsr, scr); |
1522 | |
1523 | if (tmp > freq) { |
1524 | /* we need lower freq */ |
1525 | scr++; |
1526 | continue; |
1527 | } |
1528 | |
1529 | /* |
1530 | * If found exact value, mark found and break. |
1531 | * If found more closer value, update and break. |
1532 | */ |
1533 | if (tmp > best_freq) { |
1534 | best_freq = tmp; |
1535 | best_cpsdvsr = cpsdvsr; |
1536 | best_scr = scr; |
1537 | |
1538 | if (tmp == freq) |
1539 | found = 1; |
1540 | } |
1541 | /* |
1542 | * increased scr will give lower rates, which are not |
1543 | * required |
1544 | */ |
1545 | break; |
1546 | } |
1547 | cpsdvsr += 2; |
1548 | scr = SCR_MIN; |
1549 | } |
1550 | |
1551 | WARN(!best_freq, "pl022: Matching cpsdvsr and scr not found for %d Hz rate \n" , |
1552 | freq); |
1553 | |
1554 | clk_freq->cpsdvsr = (u8) (best_cpsdvsr & 0xFF); |
1555 | clk_freq->scr = (u8) (best_scr & 0xFF); |
1556 | dev_dbg(&pl022->adev->dev, |
1557 | "SSP Target Frequency is: %u, Effective Frequency is %u\n" , |
1558 | freq, best_freq); |
1559 | dev_dbg(&pl022->adev->dev, "SSP cpsdvsr = %d, scr = %d\n" , |
1560 | clk_freq->cpsdvsr, clk_freq->scr); |
1561 | |
1562 | return 0; |
1563 | } |
1564 | |
1565 | /* |
1566 | * A piece of default chip info unless the platform |
1567 | * supplies it. |
1568 | */ |
1569 | static const struct pl022_config_chip pl022_default_chip_info = { |
1570 | .com_mode = INTERRUPT_TRANSFER, |
1571 | .iface = SSP_INTERFACE_MOTOROLA_SPI, |
1572 | .hierarchy = SSP_MASTER, |
1573 | .slave_tx_disable = DO_NOT_DRIVE_TX, |
1574 | .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM, |
1575 | .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC, |
1576 | .ctrl_len = SSP_BITS_8, |
1577 | .wait_state = SSP_MWIRE_WAIT_ZERO, |
1578 | .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, |
1579 | }; |
1580 | |
1581 | /** |
1582 | * pl022_setup - setup function registered to SPI host framework |
1583 | * @spi: spi device which is requesting setup |
1584 | * |
1585 | * This function is registered to the SPI framework for this SPI host |
1586 | * controller. If it is the first time when setup is called by this device, |
1587 | * this function will initialize the runtime state for this chip and save |
1588 | * the same in the device structure. Else it will update the runtime info |
1589 | * with the updated chip info. Nothing is really being written to the |
1590 | * controller hardware here, that is not done until the actual transfer |
1591 | * commence. |
1592 | */ |
1593 | static int pl022_setup(struct spi_device *spi) |
1594 | { |
1595 | struct pl022_config_chip const *chip_info; |
1596 | struct pl022_config_chip chip_info_dt; |
1597 | struct chip_data *chip; |
1598 | struct ssp_clock_params clk_freq = { .cpsdvsr = 0, .scr = 0}; |
1599 | int status = 0; |
1600 | struct pl022 *pl022 = spi_controller_get_devdata(ctlr: spi->controller); |
1601 | unsigned int bits = spi->bits_per_word; |
1602 | u32 tmp; |
1603 | struct device_node *np = spi->dev.of_node; |
1604 | |
1605 | if (!spi->max_speed_hz) |
1606 | return -EINVAL; |
1607 | |
1608 | /* Get controller_state if one is supplied */ |
1609 | chip = spi_get_ctldata(spi); |
1610 | |
1611 | if (chip == NULL) { |
1612 | chip = kzalloc(size: sizeof(struct chip_data), GFP_KERNEL); |
1613 | if (!chip) |
1614 | return -ENOMEM; |
1615 | dev_dbg(&spi->dev, |
1616 | "allocated memory for controller's runtime state\n" ); |
1617 | } |
1618 | |
1619 | /* Get controller data if one is supplied */ |
1620 | chip_info = spi->controller_data; |
1621 | |
1622 | if (chip_info == NULL) { |
1623 | if (np) { |
1624 | chip_info_dt = pl022_default_chip_info; |
1625 | |
1626 | chip_info_dt.hierarchy = SSP_MASTER; |
1627 | of_property_read_u32(np, propname: "pl022,interface" , |
1628 | out_value: &chip_info_dt.iface); |
1629 | of_property_read_u32(np, propname: "pl022,com-mode" , |
1630 | out_value: &chip_info_dt.com_mode); |
1631 | of_property_read_u32(np, propname: "pl022,rx-level-trig" , |
1632 | out_value: &chip_info_dt.rx_lev_trig); |
1633 | of_property_read_u32(np, propname: "pl022,tx-level-trig" , |
1634 | out_value: &chip_info_dt.tx_lev_trig); |
1635 | of_property_read_u32(np, propname: "pl022,ctrl-len" , |
1636 | out_value: &chip_info_dt.ctrl_len); |
1637 | of_property_read_u32(np, propname: "pl022,wait-state" , |
1638 | out_value: &chip_info_dt.wait_state); |
1639 | of_property_read_u32(np, propname: "pl022,duplex" , |
1640 | out_value: &chip_info_dt.duplex); |
1641 | |
1642 | chip_info = &chip_info_dt; |
1643 | } else { |
1644 | chip_info = &pl022_default_chip_info; |
1645 | /* spi_board_info.controller_data not is supplied */ |
1646 | dev_dbg(&spi->dev, |
1647 | "using default controller_data settings\n" ); |
1648 | } |
1649 | } else |
1650 | dev_dbg(&spi->dev, |
1651 | "using user supplied controller_data settings\n" ); |
1652 | |
1653 | /* |
1654 | * We can override with custom divisors, else we use the board |
1655 | * frequency setting |
1656 | */ |
1657 | if ((0 == chip_info->clk_freq.cpsdvsr) |
1658 | && (0 == chip_info->clk_freq.scr)) { |
1659 | status = calculate_effective_freq(pl022, |
1660 | freq: spi->max_speed_hz, |
1661 | clk_freq: &clk_freq); |
1662 | if (status < 0) |
1663 | goto err_config_params; |
1664 | } else { |
1665 | memcpy(&clk_freq, &chip_info->clk_freq, sizeof(clk_freq)); |
1666 | if ((clk_freq.cpsdvsr % 2) != 0) |
1667 | clk_freq.cpsdvsr = |
1668 | clk_freq.cpsdvsr - 1; |
1669 | } |
1670 | if ((clk_freq.cpsdvsr < CPSDVR_MIN) |
1671 | || (clk_freq.cpsdvsr > CPSDVR_MAX)) { |
1672 | status = -EINVAL; |
1673 | dev_err(&spi->dev, |
1674 | "cpsdvsr is configured incorrectly\n" ); |
1675 | goto err_config_params; |
1676 | } |
1677 | |
1678 | status = verify_controller_parameters(pl022, chip_info); |
1679 | if (status) { |
1680 | dev_err(&spi->dev, "controller data is incorrect" ); |
1681 | goto err_config_params; |
1682 | } |
1683 | |
1684 | pl022->rx_lev_trig = chip_info->rx_lev_trig; |
1685 | pl022->tx_lev_trig = chip_info->tx_lev_trig; |
1686 | |
1687 | /* Now set controller state based on controller data */ |
1688 | chip->xfer_type = chip_info->com_mode; |
1689 | |
1690 | /* Check bits per word with vendor specific range */ |
1691 | if ((bits <= 3) || (bits > pl022->vendor->max_bpw)) { |
1692 | status = -ENOTSUPP; |
1693 | dev_err(&spi->dev, "illegal data size for this controller!\n" ); |
1694 | dev_err(&spi->dev, "This controller can only handle 4 <= n <= %d bit words\n" , |
1695 | pl022->vendor->max_bpw); |
1696 | goto err_config_params; |
1697 | } else if (bits <= 8) { |
1698 | dev_dbg(&spi->dev, "4 <= n <=8 bits per word\n" ); |
1699 | chip->n_bytes = 1; |
1700 | chip->read = READING_U8; |
1701 | chip->write = WRITING_U8; |
1702 | } else if (bits <= 16) { |
1703 | dev_dbg(&spi->dev, "9 <= n <= 16 bits per word\n" ); |
1704 | chip->n_bytes = 2; |
1705 | chip->read = READING_U16; |
1706 | chip->write = WRITING_U16; |
1707 | } else { |
1708 | dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n" ); |
1709 | chip->n_bytes = 4; |
1710 | chip->read = READING_U32; |
1711 | chip->write = WRITING_U32; |
1712 | } |
1713 | |
1714 | /* Now Initialize all register settings required for this chip */ |
1715 | chip->cr0 = 0; |
1716 | chip->cr1 = 0; |
1717 | chip->dmacr = 0; |
1718 | chip->cpsr = 0; |
1719 | if ((chip_info->com_mode == DMA_TRANSFER) |
1720 | && ((pl022->host_info)->enable_dma)) { |
1721 | chip->enable_dma = true; |
1722 | dev_dbg(&spi->dev, "DMA mode set in controller state\n" ); |
1723 | SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, |
1724 | SSP_DMACR_MASK_RXDMAE, 0); |
1725 | SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, |
1726 | SSP_DMACR_MASK_TXDMAE, 1); |
1727 | } else { |
1728 | chip->enable_dma = false; |
1729 | dev_dbg(&spi->dev, "DMA mode NOT set in controller state\n" ); |
1730 | SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, |
1731 | SSP_DMACR_MASK_RXDMAE, 0); |
1732 | SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, |
1733 | SSP_DMACR_MASK_TXDMAE, 1); |
1734 | } |
1735 | |
1736 | chip->cpsr = clk_freq.cpsdvsr; |
1737 | |
1738 | /* Special setup for the ST micro extended control registers */ |
1739 | if (pl022->vendor->extended_cr) { |
1740 | u32 etx; |
1741 | |
1742 | if (pl022->vendor->pl023) { |
1743 | /* These bits are only in the PL023 */ |
1744 | SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay, |
1745 | SSP_CR1_MASK_FBCLKDEL_ST, 13); |
1746 | } else { |
1747 | /* These bits are in the PL022 but not PL023 */ |
1748 | SSP_WRITE_BITS(chip->cr0, chip_info->duplex, |
1749 | SSP_CR0_MASK_HALFDUP_ST, 5); |
1750 | SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len, |
1751 | SSP_CR0_MASK_CSS_ST, 16); |
1752 | SSP_WRITE_BITS(chip->cr0, chip_info->iface, |
1753 | SSP_CR0_MASK_FRF_ST, 21); |
1754 | SSP_WRITE_BITS(chip->cr1, chip_info->wait_state, |
1755 | SSP_CR1_MASK_MWAIT_ST, 6); |
1756 | } |
1757 | SSP_WRITE_BITS(chip->cr0, bits - 1, |
1758 | SSP_CR0_MASK_DSS_ST, 0); |
1759 | |
1760 | if (spi->mode & SPI_LSB_FIRST) { |
1761 | tmp = SSP_RX_LSB; |
1762 | etx = SSP_TX_LSB; |
1763 | } else { |
1764 | tmp = SSP_RX_MSB; |
1765 | etx = SSP_TX_MSB; |
1766 | } |
1767 | SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_RENDN_ST, 4); |
1768 | SSP_WRITE_BITS(chip->cr1, etx, SSP_CR1_MASK_TENDN_ST, 5); |
1769 | SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig, |
1770 | SSP_CR1_MASK_RXIFLSEL_ST, 7); |
1771 | SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig, |
1772 | SSP_CR1_MASK_TXIFLSEL_ST, 10); |
1773 | } else { |
1774 | SSP_WRITE_BITS(chip->cr0, bits - 1, |
1775 | SSP_CR0_MASK_DSS, 0); |
1776 | SSP_WRITE_BITS(chip->cr0, chip_info->iface, |
1777 | SSP_CR0_MASK_FRF, 4); |
1778 | } |
1779 | |
1780 | /* Stuff that is common for all versions */ |
1781 | if (spi->mode & SPI_CPOL) |
1782 | tmp = SSP_CLK_POL_IDLE_HIGH; |
1783 | else |
1784 | tmp = SSP_CLK_POL_IDLE_LOW; |
1785 | SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPO, 6); |
1786 | |
1787 | if (spi->mode & SPI_CPHA) |
1788 | tmp = SSP_CLK_SECOND_EDGE; |
1789 | else |
1790 | tmp = SSP_CLK_FIRST_EDGE; |
1791 | SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPH, 7); |
1792 | |
1793 | SSP_WRITE_BITS(chip->cr0, clk_freq.scr, SSP_CR0_MASK_SCR, 8); |
1794 | /* Loopback is available on all versions except PL023 */ |
1795 | if (pl022->vendor->loopback) { |
1796 | if (spi->mode & SPI_LOOP) |
1797 | tmp = LOOPBACK_ENABLED; |
1798 | else |
1799 | tmp = LOOPBACK_DISABLED; |
1800 | SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_LBM, 0); |
1801 | } |
1802 | SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1); |
1803 | SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2); |
1804 | SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD, |
1805 | 3); |
1806 | |
1807 | /* Save controller_state */ |
1808 | spi_set_ctldata(spi, state: chip); |
1809 | return status; |
1810 | err_config_params: |
1811 | spi_set_ctldata(spi, NULL); |
1812 | kfree(objp: chip); |
1813 | return status; |
1814 | } |
1815 | |
1816 | /** |
1817 | * pl022_cleanup - cleanup function registered to SPI host framework |
1818 | * @spi: spi device which is requesting cleanup |
1819 | * |
1820 | * This function is registered to the SPI framework for this SPI host |
1821 | * controller. It will free the runtime state of chip. |
1822 | */ |
1823 | static void pl022_cleanup(struct spi_device *spi) |
1824 | { |
1825 | struct chip_data *chip = spi_get_ctldata(spi); |
1826 | |
1827 | spi_set_ctldata(spi, NULL); |
1828 | kfree(objp: chip); |
1829 | } |
1830 | |
1831 | static struct pl022_ssp_controller * |
1832 | pl022_platform_data_dt_get(struct device *dev) |
1833 | { |
1834 | struct device_node *np = dev->of_node; |
1835 | struct pl022_ssp_controller *pd; |
1836 | |
1837 | if (!np) { |
1838 | dev_err(dev, "no dt node defined\n" ); |
1839 | return NULL; |
1840 | } |
1841 | |
1842 | pd = devm_kzalloc(dev, size: sizeof(struct pl022_ssp_controller), GFP_KERNEL); |
1843 | if (!pd) |
1844 | return NULL; |
1845 | |
1846 | pd->bus_id = -1; |
1847 | of_property_read_u32(np, propname: "pl022,autosuspend-delay" , |
1848 | out_value: &pd->autosuspend_delay); |
1849 | pd->rt = of_property_read_bool(np, propname: "pl022,rt" ); |
1850 | |
1851 | return pd; |
1852 | } |
1853 | |
1854 | static int pl022_probe(struct amba_device *adev, const struct amba_id *id) |
1855 | { |
1856 | struct device *dev = &adev->dev; |
1857 | struct pl022_ssp_controller *platform_info = |
1858 | dev_get_platdata(dev: &adev->dev); |
1859 | struct spi_controller *host; |
1860 | struct pl022 *pl022 = NULL; /*Data for this driver */ |
1861 | int status = 0; |
1862 | |
1863 | dev_info(&adev->dev, |
1864 | "ARM PL022 driver, device ID: 0x%08x\n" , adev->periphid); |
1865 | if (!platform_info && IS_ENABLED(CONFIG_OF)) |
1866 | platform_info = pl022_platform_data_dt_get(dev); |
1867 | |
1868 | if (!platform_info) { |
1869 | dev_err(dev, "probe: no platform data defined\n" ); |
1870 | return -ENODEV; |
1871 | } |
1872 | |
1873 | /* Allocate host with space for data */ |
1874 | host = spi_alloc_host(dev, size: sizeof(struct pl022)); |
1875 | if (host == NULL) { |
1876 | dev_err(&adev->dev, "probe - cannot alloc SPI host\n" ); |
1877 | return -ENOMEM; |
1878 | } |
1879 | |
1880 | pl022 = spi_controller_get_devdata(ctlr: host); |
1881 | pl022->host = host; |
1882 | pl022->host_info = platform_info; |
1883 | pl022->adev = adev; |
1884 | pl022->vendor = id->data; |
1885 | |
1886 | /* |
1887 | * Bus Number Which has been Assigned to this SSP controller |
1888 | * on this board |
1889 | */ |
1890 | host->bus_num = platform_info->bus_id; |
1891 | host->cleanup = pl022_cleanup; |
1892 | host->setup = pl022_setup; |
1893 | host->auto_runtime_pm = true; |
1894 | host->transfer_one = pl022_transfer_one; |
1895 | host->set_cs = pl022_cs_control; |
1896 | host->handle_err = pl022_handle_err; |
1897 | host->unprepare_transfer_hardware = pl022_unprepare_transfer_hardware; |
1898 | host->rt = platform_info->rt; |
1899 | host->dev.of_node = dev->of_node; |
1900 | host->use_gpio_descriptors = true; |
1901 | |
1902 | /* |
1903 | * Supports mode 0-3, loopback, and active low CS. Transfers are |
1904 | * always MS bit first on the original pl022. |
1905 | */ |
1906 | host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; |
1907 | if (pl022->vendor->extended_cr) |
1908 | host->mode_bits |= SPI_LSB_FIRST; |
1909 | |
1910 | dev_dbg(&adev->dev, "BUSNO: %d\n" , host->bus_num); |
1911 | |
1912 | status = amba_request_regions(adev, NULL); |
1913 | if (status) |
1914 | goto err_no_ioregion; |
1915 | |
1916 | pl022->phybase = adev->res.start; |
1917 | pl022->virtbase = devm_ioremap(dev, offset: adev->res.start, |
1918 | size: resource_size(res: &adev->res)); |
1919 | if (pl022->virtbase == NULL) { |
1920 | status = -ENOMEM; |
1921 | goto err_no_ioremap; |
1922 | } |
1923 | dev_info(&adev->dev, "mapped registers from %pa to %p\n" , |
1924 | &adev->res.start, pl022->virtbase); |
1925 | |
1926 | pl022->clk = devm_clk_get_enabled(dev: &adev->dev, NULL); |
1927 | if (IS_ERR(ptr: pl022->clk)) { |
1928 | status = PTR_ERR(ptr: pl022->clk); |
1929 | dev_err(&adev->dev, "could not retrieve SSP/SPI bus clock\n" ); |
1930 | goto err_no_clk; |
1931 | } |
1932 | |
1933 | /* Disable SSP */ |
1934 | writew(val: (readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)), |
1935 | SSP_CR1(pl022->virtbase)); |
1936 | load_ssp_default_config(pl022); |
1937 | |
1938 | status = devm_request_irq(dev, irq: adev->irq[0], handler: pl022_interrupt_handler, |
1939 | irqflags: 0, devname: "pl022" , dev_id: pl022); |
1940 | if (status < 0) { |
1941 | dev_err(&adev->dev, "probe - cannot get IRQ (%d)\n" , status); |
1942 | goto err_no_irq; |
1943 | } |
1944 | |
1945 | /* Get DMA channels, try autoconfiguration first */ |
1946 | status = pl022_dma_autoprobe(pl022); |
1947 | if (status == -EPROBE_DEFER) { |
1948 | dev_dbg(dev, "deferring probe to get DMA channel\n" ); |
1949 | goto err_no_irq; |
1950 | } |
1951 | |
1952 | /* If that failed, use channels from platform_info */ |
1953 | if (status == 0) |
1954 | platform_info->enable_dma = 1; |
1955 | else if (platform_info->enable_dma) { |
1956 | status = pl022_dma_probe(pl022); |
1957 | if (status != 0) |
1958 | platform_info->enable_dma = 0; |
1959 | } |
1960 | |
1961 | /* Register with the SPI framework */ |
1962 | amba_set_drvdata(adev, pl022); |
1963 | status = devm_spi_register_controller(dev: &adev->dev, ctlr: host); |
1964 | if (status != 0) { |
1965 | dev_err_probe(dev: &adev->dev, err: status, |
1966 | fmt: "problem registering spi host\n" ); |
1967 | goto err_spi_register; |
1968 | } |
1969 | dev_dbg(dev, "probe succeeded\n" ); |
1970 | |
1971 | /* let runtime pm put suspend */ |
1972 | if (platform_info->autosuspend_delay > 0) { |
1973 | dev_info(&adev->dev, |
1974 | "will use autosuspend for runtime pm, delay %dms\n" , |
1975 | platform_info->autosuspend_delay); |
1976 | pm_runtime_set_autosuspend_delay(dev, |
1977 | delay: platform_info->autosuspend_delay); |
1978 | pm_runtime_use_autosuspend(dev); |
1979 | } |
1980 | pm_runtime_put(dev); |
1981 | |
1982 | return 0; |
1983 | |
1984 | err_spi_register: |
1985 | if (platform_info->enable_dma) |
1986 | pl022_dma_remove(pl022); |
1987 | err_no_irq: |
1988 | err_no_clk: |
1989 | err_no_ioremap: |
1990 | amba_release_regions(adev); |
1991 | err_no_ioregion: |
1992 | spi_controller_put(ctlr: host); |
1993 | return status; |
1994 | } |
1995 | |
1996 | static void |
1997 | pl022_remove(struct amba_device *adev) |
1998 | { |
1999 | struct pl022 *pl022 = amba_get_drvdata(adev); |
2000 | |
2001 | if (!pl022) |
2002 | return; |
2003 | |
2004 | /* |
2005 | * undo pm_runtime_put() in probe. I assume that we're not |
2006 | * accessing the primecell here. |
2007 | */ |
2008 | pm_runtime_get_noresume(dev: &adev->dev); |
2009 | |
2010 | load_ssp_default_config(pl022); |
2011 | if (pl022->host_info->enable_dma) |
2012 | pl022_dma_remove(pl022); |
2013 | |
2014 | amba_release_regions(adev); |
2015 | } |
2016 | |
2017 | #ifdef CONFIG_PM_SLEEP |
2018 | static int pl022_suspend(struct device *dev) |
2019 | { |
2020 | struct pl022 *pl022 = dev_get_drvdata(dev); |
2021 | int ret; |
2022 | |
2023 | ret = spi_controller_suspend(ctlr: pl022->host); |
2024 | if (ret) |
2025 | return ret; |
2026 | |
2027 | ret = pm_runtime_force_suspend(dev); |
2028 | if (ret) { |
2029 | spi_controller_resume(ctlr: pl022->host); |
2030 | return ret; |
2031 | } |
2032 | |
2033 | pinctrl_pm_select_sleep_state(dev); |
2034 | |
2035 | dev_dbg(dev, "suspended\n" ); |
2036 | return 0; |
2037 | } |
2038 | |
2039 | static int pl022_resume(struct device *dev) |
2040 | { |
2041 | struct pl022 *pl022 = dev_get_drvdata(dev); |
2042 | int ret; |
2043 | |
2044 | ret = pm_runtime_force_resume(dev); |
2045 | if (ret) |
2046 | dev_err(dev, "problem resuming\n" ); |
2047 | |
2048 | /* Start the queue running */ |
2049 | ret = spi_controller_resume(ctlr: pl022->host); |
2050 | if (!ret) |
2051 | dev_dbg(dev, "resumed\n" ); |
2052 | |
2053 | return ret; |
2054 | } |
2055 | #endif |
2056 | |
2057 | #ifdef CONFIG_PM |
2058 | static int pl022_runtime_suspend(struct device *dev) |
2059 | { |
2060 | struct pl022 *pl022 = dev_get_drvdata(dev); |
2061 | |
2062 | clk_disable_unprepare(clk: pl022->clk); |
2063 | pinctrl_pm_select_idle_state(dev); |
2064 | |
2065 | return 0; |
2066 | } |
2067 | |
2068 | static int pl022_runtime_resume(struct device *dev) |
2069 | { |
2070 | struct pl022 *pl022 = dev_get_drvdata(dev); |
2071 | |
2072 | pinctrl_pm_select_default_state(dev); |
2073 | clk_prepare_enable(clk: pl022->clk); |
2074 | |
2075 | return 0; |
2076 | } |
2077 | #endif |
2078 | |
2079 | static const struct dev_pm_ops pl022_dev_pm_ops = { |
2080 | SET_SYSTEM_SLEEP_PM_OPS(pl022_suspend, pl022_resume) |
2081 | SET_RUNTIME_PM_OPS(pl022_runtime_suspend, pl022_runtime_resume, NULL) |
2082 | }; |
2083 | |
2084 | static struct vendor_data vendor_arm = { |
2085 | .fifodepth = 8, |
2086 | .max_bpw = 16, |
2087 | .unidir = false, |
2088 | .extended_cr = false, |
2089 | .pl023 = false, |
2090 | .loopback = true, |
2091 | .internal_cs_ctrl = false, |
2092 | }; |
2093 | |
2094 | static struct vendor_data vendor_st = { |
2095 | .fifodepth = 32, |
2096 | .max_bpw = 32, |
2097 | .unidir = false, |
2098 | .extended_cr = true, |
2099 | .pl023 = false, |
2100 | .loopback = true, |
2101 | .internal_cs_ctrl = false, |
2102 | }; |
2103 | |
2104 | static struct vendor_data vendor_st_pl023 = { |
2105 | .fifodepth = 32, |
2106 | .max_bpw = 32, |
2107 | .unidir = false, |
2108 | .extended_cr = true, |
2109 | .pl023 = true, |
2110 | .loopback = false, |
2111 | .internal_cs_ctrl = false, |
2112 | }; |
2113 | |
2114 | static struct vendor_data vendor_lsi = { |
2115 | .fifodepth = 8, |
2116 | .max_bpw = 16, |
2117 | .unidir = false, |
2118 | .extended_cr = false, |
2119 | .pl023 = false, |
2120 | .loopback = true, |
2121 | .internal_cs_ctrl = true, |
2122 | }; |
2123 | |
2124 | static const struct amba_id pl022_ids[] = { |
2125 | { |
2126 | /* |
2127 | * ARM PL022 variant, this has a 16bit wide |
2128 | * and 8 locations deep TX/RX FIFO |
2129 | */ |
2130 | .id = 0x00041022, |
2131 | .mask = 0x000fffff, |
2132 | .data = &vendor_arm, |
2133 | }, |
2134 | { |
2135 | /* |
2136 | * ST Micro derivative, this has 32bit wide |
2137 | * and 32 locations deep TX/RX FIFO |
2138 | */ |
2139 | .id = 0x01080022, |
2140 | .mask = 0xffffffff, |
2141 | .data = &vendor_st, |
2142 | }, |
2143 | { |
2144 | /* |
2145 | * ST-Ericsson derivative "PL023" (this is not |
2146 | * an official ARM number), this is a PL022 SSP block |
2147 | * stripped to SPI mode only, it has 32bit wide |
2148 | * and 32 locations deep TX/RX FIFO but no extended |
2149 | * CR0/CR1 register |
2150 | */ |
2151 | .id = 0x00080023, |
2152 | .mask = 0xffffffff, |
2153 | .data = &vendor_st_pl023, |
2154 | }, |
2155 | { |
2156 | /* |
2157 | * PL022 variant that has a chip select control register whih |
2158 | * allows control of 5 output signals nCS[0:4]. |
2159 | */ |
2160 | .id = 0x000b6022, |
2161 | .mask = 0x000fffff, |
2162 | .data = &vendor_lsi, |
2163 | }, |
2164 | { 0, 0 }, |
2165 | }; |
2166 | |
2167 | MODULE_DEVICE_TABLE(amba, pl022_ids); |
2168 | |
2169 | static struct amba_driver pl022_driver = { |
2170 | .drv = { |
2171 | .name = "ssp-pl022" , |
2172 | .pm = &pl022_dev_pm_ops, |
2173 | }, |
2174 | .id_table = pl022_ids, |
2175 | .probe = pl022_probe, |
2176 | .remove = pl022_remove, |
2177 | }; |
2178 | |
2179 | static int __init pl022_init(void) |
2180 | { |
2181 | return amba_driver_register(drv: &pl022_driver); |
2182 | } |
2183 | subsys_initcall(pl022_init); |
2184 | |
2185 | static void __exit pl022_exit(void) |
2186 | { |
2187 | amba_driver_unregister(drv: &pl022_driver); |
2188 | } |
2189 | module_exit(pl022_exit); |
2190 | |
2191 | MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>" ); |
2192 | MODULE_DESCRIPTION("PL022 SSP Controller Driver" ); |
2193 | MODULE_LICENSE("GPL" ); |
2194 | |