1	/* IRA hard register and memory cost calculation for allocnos or pseudos.
2	Copyright (C) 2006-2025 Free Software Foundation, Inc.
3	Contributed by Vladimir Makarov <vmakarov@redhat.com>.
4
5	This file is part of GCC.
6
7	GCC is free software; you can redistribute it and/or modify it under
8	the terms of the GNU General Public License as published by the Free
9	Software Foundation; either version 3, or (at your option) any later
10	version.
11
12	GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13	WARRANTY; without even the implied warranty of MERCHANTABILITY or
14	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15	for more details.
16
17	You should have received a copy of the GNU General Public License
18	along with GCC; see the file COPYING3. If not see
19	<http://www.gnu.org/licenses/>. */
20
21	#include "config.h"
22	#include "system.h"
23	#include "coretypes.h"
24	#include "backend.h"
25	#include "target.h"
26	#include "rtl.h"
27	#include "tree.h"
28	#include "predict.h"
29	#include "memmodel.h"
30	#include "tm_p.h"
31	#include "insn-config.h"
32	#include "regs.h"
33	#include "regset.h"
34	#include "ira.h"
35	#include "ira-int.h"
36	#include "addresses.h"
37	#include "reload.h"
38	#include "print-rtl.h"
39
40	/* The flags is set up every time when we calculate pseudo register
41	classes through function ira_set_pseudo_classes. */
42	static bool pseudo_classes_defined_p = false;
43
44	/* TRUE if we work with allocnos. Otherwise we work with pseudos. */
45	static bool allocno_p;
46
47	/* Number of elements in array `costs'. */
48	static int cost_elements_num;
49
50	/* The `costs' struct records the cost of using hard registers of each
51	class considered for the calculation and of using memory for each
52	allocno or pseudo. */
53	struct costs
54	{
55	int mem_cost;
56	/* Costs for register classes start here. We process only some
57	allocno classes. */
58	int cost[1];
59	};
60
61	#define max_struct_costs_size \
62	(this_target_ira_int->x_max_struct_costs_size)
63	#define init_cost \
64	(this_target_ira_int->x_init_cost)
65	#define temp_costs \
66	(this_target_ira_int->x_temp_costs)
67	#define op_costs \
68	(this_target_ira_int->x_op_costs)
69	#define this_op_costs \
70	(this_target_ira_int->x_this_op_costs)
71
72	/* Costs of each class for each allocno or pseudo. */
73	static struct costs *costs;
74
75	/* Accumulated costs of each class for each allocno. */
76	static struct costs *total_allocno_costs;
77
78	/* It is the current size of struct costs. */
79	static size_t struct_costs_size;
80
81	/* Return pointer to structure containing costs of allocno or pseudo
82	with given NUM in array ARR. */
83	#define COSTS(arr, num) \
84	((struct costs *) ((char *) (arr) + (num) * struct_costs_size))
85
86	/* Return index in COSTS when processing reg with REGNO. */
87	#define COST_INDEX(regno) (allocno_p \
88	? ALLOCNO_NUM (ira_curr_regno_allocno_map[regno]) \
89	: (int) regno)
90
91	/* Record register class preferences of each allocno or pseudo. Null
92	value means no preferences. It happens on the 1st iteration of the
93	cost calculation. */
94	static enum reg_class *pref;
95
96	/* Allocated buffers for pref. */
97	static enum reg_class *pref_buffer;
98
99	/* Record allocno class of each allocno with the same regno. */
100	static enum reg_class *regno_aclass;
101
102	/* Record cost gains for not allocating a register with an invariant
103	equivalence. */
104	static int *regno_equiv_gains;
105
106	/* Execution frequency of the current insn. */
107	static int frequency;
108
109
110
111	/* Info about reg classes whose costs are calculated for a pseudo. */
112	struct cost_classes
113	{
114	/* Number of the cost classes in the subsequent array. */
115	int num;
116	/* Container of the cost classes. */
117	enum reg_class classes[N_REG_CLASSES];
118	/* Map reg class -> index of the reg class in the previous array.
119	-1 if it is not a cost class. */
120	int index[N_REG_CLASSES];
121	/* Map hard regno index of first class in array CLASSES containing
122	the hard regno, -1 otherwise. */
123	int hard_regno_index[FIRST_PSEUDO_REGISTER];
124	};
125
126	/* Types of pointers to the structure above. */
127	typedef struct cost_classes *cost_classes_t;
128	typedef const struct cost_classes *const_cost_classes_t;
129
130	/* Info about cost classes for each pseudo. */
131	static cost_classes_t *regno_cost_classes;
132
133	/* Helper for cost_classes hashing. */
134
135	struct cost_classes_hasher : pointer_hash <cost_classes>
136	{
137	static inline hashval_t hash (const cost_classes *);
138	static inline bool equal (const cost_classes *, const cost_classes *);
139	static inline void remove (cost_classes *);
140	};
141
142	/* Returns hash value for cost classes info HV. */
143	inline hashval_t
144	cost_classes_hasher::hash (const cost_classes *hv)
145	{
146	return iterative_hash (&hv->classes, sizeof (enum reg_class) * hv->num, 0);
147	}
148
149	/* Compares cost classes info HV1 and HV2. */
150	inline bool
151	cost_classes_hasher::equal (const cost_classes *hv1, const cost_classes *hv2)
152	{
153	return (hv1->num == hv2->num
154	&& memcmp (s1: hv1->classes, s2: hv2->classes,
155	n: sizeof (enum reg_class) * hv1->num) == 0);
156	}
157
158	/* Delete cost classes info V from the hash table. */
159	inline void
160	cost_classes_hasher::remove (cost_classes *v)
161	{
162	ira_free (addr: v);
163	}
164
165	/* Hash table of unique cost classes. */
166	static hash_table<cost_classes_hasher> *cost_classes_htab;
167
168	/* Map allocno class -> cost classes for pseudo of given allocno
169	class. */
170	static cost_classes_t cost_classes_aclass_cache[N_REG_CLASSES];
171
172	/* Map mode -> cost classes for pseudo of give mode. */
173	static cost_classes_t cost_classes_mode_cache[MAX_MACHINE_MODE];
174
175	/* Cost classes that include all classes in ira_important_classes. */
176	static cost_classes all_cost_classes;
177
178	/* Use the array of classes in CLASSES_PTR to fill out the rest of
179	the structure. */
180	static void
181	complete_cost_classes (cost_classes_t classes_ptr)
182	{
183	for (int i = 0; i < N_REG_CLASSES; i++)
184	classes_ptr->index[i] = -1;
185	for (int i = 0; i < FIRST_PSEUDO_REGISTER; i++)
186	classes_ptr->hard_regno_index[i] = -1;
187	for (int i = 0; i < classes_ptr->num; i++)
188	{
189	enum reg_class cl = classes_ptr->classes[i];
190	classes_ptr->index[cl] = i;
191	for (int j = ira_class_hard_regs_num[cl] - 1; j >= 0; j--)
192	{
193	unsigned int hard_regno = ira_class_hard_regs[cl][j];
194	if (classes_ptr->hard_regno_index[hard_regno] < 0)
195	classes_ptr->hard_regno_index[hard_regno] = i;
196	}
197	}
198	}
199
200	/* Initialize info about the cost classes for each pseudo. */
201	static void
202	initiate_regno_cost_classes (void)
203	{
204	int size = sizeof (cost_classes_t) * max_reg_num ();
205
206	regno_cost_classes = (cost_classes_t *) ira_allocate (size);
207	memset (s: regno_cost_classes, c: 0, n: size);
208	memset (s: cost_classes_aclass_cache, c: 0,
209	n: sizeof (cost_classes_t) * N_REG_CLASSES);
210	memset (s: cost_classes_mode_cache, c: 0,
211	n: sizeof (cost_classes_t) * MAX_MACHINE_MODE);
212	cost_classes_htab = new hash_table<cost_classes_hasher> (200);
213	all_cost_classes.num = ira_important_classes_num;
214	for (int i = 0; i < ira_important_classes_num; i++)
215	all_cost_classes.classes[i] = ira_important_classes[i];
216	complete_cost_classes (classes_ptr: &all_cost_classes);
217	}
218
219	/* Create new cost classes from cost classes FROM and set up members
220	index and hard_regno_index. Return the new classes. The function
221	implements some common code of two functions
222	setup_regno_cost_classes_by_aclass and
223	setup_regno_cost_classes_by_mode. */
224	static cost_classes_t
225	setup_cost_classes (cost_classes_t from)
226	{
227	cost_classes_t classes_ptr;
228
229	classes_ptr = (cost_classes_t) ira_allocate (sizeof (struct cost_classes));
230	classes_ptr->num = from->num;
231	for (int i = 0; i < from->num; i++)
232	classes_ptr->classes[i] = from->classes[i];
233	complete_cost_classes (classes_ptr);
234	return classes_ptr;
235	}
236
237	/* Return a version of FULL that only considers registers in REGS that are
238	valid for mode MODE. Both FULL and the returned class are globally
239	allocated. */
240	static cost_classes_t
241	restrict_cost_classes (cost_classes_t full, machine_mode mode,
242	const_hard_reg_set regs)
243	{
244	static struct cost_classes narrow;
245	int map[N_REG_CLASSES];
246	narrow.num = 0;
247	for (int i = 0; i < full->num; i++)
248	{
249	/* Assume that we'll drop the class. */
250	map[i] = -1;
251
252	/* Ignore classes that are too small for the mode. */
253	enum reg_class cl = full->classes[i];
254	if (!contains_reg_of_mode[cl][mode])
255	continue;
256
257	/* Calculate the set of registers in CL that belong to REGS and
258	are valid for MODE. */
259	HARD_REG_SET valid_for_cl = reg_class_contents[cl] & regs;
260	valid_for_cl &= ~(ira_prohibited_class_mode_regs[cl][mode]
261	| ira_no_alloc_regs);
262	if (hard_reg_set_empty_p (x: valid_for_cl))
263	continue;
264
265	/* Don't use this class if the set of valid registers is a subset
266	of an existing class. For example, suppose we have two classes
267	GR_REGS and FR_REGS and a union class GR_AND_FR_REGS. Suppose
268	that the mode changes allowed by FR_REGS are not as general as
269	the mode changes allowed by GR_REGS.
270
271	In this situation, the mode changes for GR_AND_FR_REGS could
272	either be seen as the union or the intersection of the mode
273	changes allowed by the two subclasses. The justification for
274	the union-based definition would be that, if you want a mode
275	change that's only allowed by GR_REGS, you can pick a register
276	from the GR_REGS subclass. The justification for the
277	intersection-based definition would be that every register
278	from the class would allow the mode change.
279
280	However, if we have a register that needs to be in GR_REGS,
281	using GR_AND_FR_REGS with the intersection-based definition
282	would be too pessimistic, since it would bring in restrictions
283	that only apply to FR_REGS. Conversely, if we have a register
284	that needs to be in FR_REGS, using GR_AND_FR_REGS with the
285	union-based definition would lose the extra restrictions
286	placed on FR_REGS. GR_AND_FR_REGS is therefore only useful
287	for cases where GR_REGS and FP_REGS are both valid. */
288	int pos;
289	for (pos = 0; pos < narrow.num; ++pos)
290	{
291	enum reg_class cl2 = narrow.classes[pos];
292	if (hard_reg_set_subset_p (x: valid_for_cl, reg_class_contents[cl2]))
293	break;
294	}
295	map[i] = pos;
296	if (pos == narrow.num)
297	{
298	/* If several classes are equivalent, prefer to use the one
299	that was chosen as the allocno class. */
300	enum reg_class cl2 = ira_allocno_class_translate[cl];
301	if (ira_class_hard_regs_num[cl] == ira_class_hard_regs_num[cl2])
302	cl = cl2;
303	narrow.classes[narrow.num++] = cl;
304	}
305	}
306	if (narrow.num == full->num)
307	return full;
308
309	cost_classes **slot = cost_classes_htab->find_slot (value: &narrow, insert: INSERT);
310	if (*slot == NULL)
311	{
312	cost_classes_t classes = setup_cost_classes (&narrow);
313	/* Map equivalent classes to the representative that we chose above. */
314	for (int i = 0; i < ira_important_classes_num; i++)
315	{
316	enum reg_class cl = ira_important_classes[i];
317	int index = full->index[cl];
318	if (index >= 0)
319	classes->index[cl] = map[index];
320	}
321	*slot = classes;
322	}
323	return *slot;
324	}
325
326	/* Setup cost classes for pseudo REGNO whose allocno class is ACLASS.
327	This function is used when we know an initial approximation of
328	allocno class of the pseudo already, e.g. on the second iteration
329	of class cost calculation or after class cost calculation in
330	register-pressure sensitive insn scheduling or register-pressure
331	sensitive loop-invariant motion. */
332	static void
333	setup_regno_cost_classes_by_aclass (int regno, enum reg_class aclass)
334	{
335	static struct cost_classes classes;
336	cost_classes_t classes_ptr;
337	enum reg_class cl;
338	int i;
339	cost_classes **slot;
340	HARD_REG_SET temp, temp2;
341	bool exclude_p;
342
343	if ((classes_ptr = cost_classes_aclass_cache[aclass]) == NULL)
344	{
345	temp = reg_class_contents[aclass] & ~ira_no_alloc_regs;
346	/* We exclude classes from consideration which are subsets of
347	ACLASS only if ACLASS is an uniform class. */
348	exclude_p = ira_uniform_class_p[aclass];
349	classes.num = 0;
350	for (i = 0; i < ira_important_classes_num; i++)
351	{
352	cl = ira_important_classes[i];
353	if (exclude_p)
354	{
355	/* Exclude non-uniform classes which are subsets of
356	ACLASS. */
357	temp2 = reg_class_contents[cl] & ~ira_no_alloc_regs;
358	if (hard_reg_set_subset_p (x: temp2, y: temp) && cl != aclass)
359	continue;
360	}
361	classes.classes[classes.num++] = cl;
362	}
363	slot = cost_classes_htab->find_slot (value: &classes, insert: INSERT);
364	if (*slot == NULL)
365	{
366	classes_ptr = setup_cost_classes (&classes);
367	*slot = classes_ptr;
368	}
369	classes_ptr = cost_classes_aclass_cache[aclass] = (cost_classes_t) *slot;
370	}
371	if (regno_reg_rtx[regno] != NULL_RTX)
372	{
373	/* Restrict the classes to those that are valid for REGNO's mode
374	(which might for example exclude singleton classes if the mode
375	requires two registers). Also restrict the classes to those that
376	are valid for subregs of REGNO. */
377	const HARD_REG_SET *valid_regs = valid_mode_changes_for_regno (regno);
378	if (!valid_regs)
379	valid_regs = &reg_class_contents[ALL_REGS];
380	classes_ptr = restrict_cost_classes (full: classes_ptr,
381	PSEUDO_REGNO_MODE (regno),
382	regs: *valid_regs);
383	}
384	regno_cost_classes[regno] = classes_ptr;
385	}
386
387	/* Setup cost classes for pseudo REGNO with MODE. Usage of MODE can
388	decrease number of cost classes for the pseudo, if hard registers
389	of some important classes cannot hold a value of MODE. So the
390	pseudo cannot get hard register of some important classes and cost
391	calculation for such important classes is only wasting CPU
392	time. */
393	static void
394	setup_regno_cost_classes_by_mode (int regno, machine_mode mode)
395	{
396	if (const HARD_REG_SET *valid_regs = valid_mode_changes_for_regno (regno))
397	regno_cost_classes[regno] = restrict_cost_classes (full: &all_cost_classes,
398	mode, regs: *valid_regs);
399	else
400	{
401	if (cost_classes_mode_cache[mode] == NULL)
402	cost_classes_mode_cache[mode]
403	= restrict_cost_classes (full: &all_cost_classes, mode,
404	reg_class_contents[ALL_REGS]);
405	regno_cost_classes[regno] = cost_classes_mode_cache[mode];
406	}
407	}
408
409	/* Finalize info about the cost classes for each pseudo. */
410	static void
411	finish_regno_cost_classes (void)
412	{
413	ira_free (addr: regno_cost_classes);
414	delete cost_classes_htab;
415	cost_classes_htab = NULL;
416	}
417
418
419
420	/* Compute the cost of loading X into (if TO_P is TRUE) or from (if
421	TO_P is FALSE) a register of class RCLASS in mode MODE. X must not
422	be a pseudo register. */
423	static int
424	copy_cost (rtx x, machine_mode mode, reg_class_t rclass, bool to_p,
425	secondary_reload_info *prev_sri)
426	{
427	secondary_reload_info sri;
428	reg_class_t secondary_class = NO_REGS;
429
430	/* If X is a SCRATCH, there is actually nothing to move since we are
431	assuming optimal allocation. */
432	if (GET_CODE (x) == SCRATCH)
433	return 0;
434
435	/* Get the class we will actually use for a reload. */
436	rclass = targetm.preferred_reload_class (x, rclass);
437
438	/* If we need a secondary reload for an intermediate, the cost is
439	that to load the input into the intermediate register, then to
440	copy it. */
441	sri.prev_sri = prev_sri;
442	sri.extra_cost = 0;
443	/* PR 68770: Secondary reload might examine the t_icode field. */
444	sri.t_icode = CODE_FOR_nothing;
445
446	secondary_class = targetm.secondary_reload (to_p, x, rclass, mode, &sri);
447
448	if (secondary_class != NO_REGS)
449	{
450	ira_init_register_move_cost_if_necessary (mode);
451	return (ira_register_move_cost[mode][(int) secondary_class][(int) rclass]
452	+ sri.extra_cost
453	+ copy_cost (x, mode, rclass: secondary_class, to_p, prev_sri: &sri));
454	}
455
456	/* For memory, use the memory move cost, for (hard) registers, use
457	the cost to move between the register classes, and use 2 for
458	everything else (constants). */
459	if (MEM_P (x) || rclass == NO_REGS)
460	return sri.extra_cost
461	+ ira_memory_move_cost[mode][(int) rclass][to_p != 0];
462	else if (REG_P (x))
463	{
464	reg_class_t x_class = REGNO_REG_CLASS (REGNO (x));
465
466	ira_init_register_move_cost_if_necessary (mode);
467	return (sri.extra_cost
468	+ ira_register_move_cost[mode][(int) x_class][(int) rclass]);
469	}
470	else
471	/* If this is a constant, we may eventually want to call rtx_cost
472	here. */
473	return sri.extra_cost + COSTS_N_INSNS (1);
474	}
475
476
477
478	/* Record the cost of using memory or hard registers of various
479	classes for the operands in INSN.
480
481	N_ALTS is the number of alternatives.
482	N_OPS is the number of operands.
483	OPS is an array of the operands.
484	MODES are the modes of the operands, in case any are VOIDmode.
485	CONSTRAINTS are the constraints to use for the operands. This array
486	is modified by this procedure.
487
488	This procedure works alternative by alternative. For each
489	alternative we assume that we will be able to allocate all allocnos
490	to their ideal register class and calculate the cost of using that
491	alternative. Then we compute, for each operand that is a
492	pseudo-register, the cost of having the allocno allocated to each
493	register class and using it in that alternative. To this cost is
494	added the cost of the alternative.
495
496	The cost of each class for this insn is its lowest cost among all
497	the alternatives. */
498	static void
499	record_reg_classes (int n_alts, int n_ops, rtx *ops,
500	machine_mode *modes, const char **constraints,
501	rtx_insn *insn, enum reg_class *pref)
502	{
503	int alt;
504	int i, j, k;
505	int insn_allows_mem[MAX_RECOG_OPERANDS];
506	move_table *move_in_cost, *move_out_cost;
507	short (*mem_cost)[2];
508	const char *p;
509
510	if (ira_dump_file != NULL && internal_flag_ira_verbose > 5)
511	{
512	fprintf (stream: ira_dump_file, format: " Processing insn %u", INSN_UID (insn));
513	if (INSN_CODE (insn) >= 0
514	&& (p = get_insn_name (INSN_CODE (insn))) != NULL)
515	fprintf (stream: ira_dump_file, format: " {%s}", p);
516	fprintf (stream: ira_dump_file, format: " (freq=%d)\n",
517	REG_FREQ_FROM_BB (BLOCK_FOR_INSN (insn)));
518	dump_insn_slim (ira_dump_file, insn);
519	}
520
521	for (i = 0; i < n_ops; i++)
522	insn_allows_mem[i] = 0;
523
524	/* Process each alternative, each time minimizing an operand's cost
525	with the cost for each operand in that alternative. */
526	alternative_mask preferred = get_preferred_alternatives (insn);
527	for (alt = 0; alt < n_alts; alt++)
528	{
529	enum reg_class classes[MAX_RECOG_OPERANDS];
530	int allows_mem[MAX_RECOG_OPERANDS];
531	enum reg_class rclass;
532	int alt_fail = 0;
533	int alt_cost = 0, op_cost_add;
534
535	if (!TEST_BIT (preferred, alt))
536	{
537	for (i = 0; i < recog_data.n_operands; i++)
538	constraints[i] = skip_alternative (p: constraints[i]);
539
540	continue;
541	}
542
543	if (ira_dump_file != NULL && internal_flag_ira_verbose > 5)
544	{
545	fprintf (stream: ira_dump_file, format: " Alt %d:", alt);
546	for (i = 0; i < n_ops; i++)
547	{
548	p = constraints[i];
549	if (*p == '\0')
550	continue;
551	fprintf (stream: ira_dump_file, format: " (%d) ", i);
552	for (; *p != '\0' && *p != ',' && *p != '#'; p++)
553	fputc (c: *p, stream: ira_dump_file);
554	}
555	fprintf (stream: ira_dump_file, format: "\n");
556	}
557
558	for (i = 0; i < n_ops; i++)
559	{
560	unsigned char c;
561	const char *p = constraints[i];
562	rtx op = ops[i];
563	machine_mode mode = modes[i];
564	int allows_addr = 0;
565	int win = 0;
566
567	/* Initially show we know nothing about the register class. */
568	classes[i] = NO_REGS;
569	allows_mem[i] = 0;
570
571	/* If this operand has no constraints at all, we can
572	conclude nothing about it since anything is valid. */
573	if (*p == 0)
574	{
575	if (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER)
576	memset (this_op_costs[i], c: 0, n: struct_costs_size);
577	continue;
578	}
579
580	/* If this alternative is only relevant when this operand
581	matches a previous operand, we do different things
582	depending on whether this operand is a allocno-reg or not.
583	We must process any modifiers for the operand before we
584	can make this test. */
585	while (*p == '%' || *p == '=' || *p == '+' || *p == '&')
586	p++;
587
588	if (p[0] >= '0' && p[0] <= '0' + i)
589	{
590	/* Copy class and whether memory is allowed from the
591	matching alternative. Then perform any needed cost
592	computations and/or adjustments. */
593	j = p[0] - '0';
594	classes[i] = classes[j];
595	allows_mem[i] = allows_mem[j];
596	if (allows_mem[i])
597	insn_allows_mem[i] = 1;
598
599	if (! REG_P (op) || REGNO (op) < FIRST_PSEUDO_REGISTER)
600	{
601	/* If this matches the other operand, we have no
602	added cost and we win. */
603	if (rtx_equal_p (ops[j], op))
604	win = 1;
605	/* If we can put the other operand into a register,
606	add to the cost of this alternative the cost to
607	copy this operand to the register used for the
608	other operand. */
609	else if (classes[j] != NO_REGS)
610	{
611	alt_cost += copy_cost (x: op, mode, rclass: classes[j], to_p: 1, NULL);
612	win = 1;
613	}
614	}
615	else if (! REG_P (ops[j])
616	|| REGNO (ops[j]) < FIRST_PSEUDO_REGISTER)
617	{
618	/* This op is an allocno but the one it matches is
619	not. */
620
621	/* If we can't put the other operand into a
622	register, this alternative can't be used. */
623
624	if (classes[j] == NO_REGS)
625	{
626	alt_fail = 1;
627	}
628	else
629	/* Otherwise, add to the cost of this alternative the cost
630	to copy the other operand to the hard register used for
631	this operand. */
632	{
633	alt_cost += copy_cost (x: ops[j], mode, rclass: classes[j], to_p: 1, NULL);
634	}
635	}
636	else
637	{
638	/* The costs of this operand are not the same as the
639	other operand since move costs are not symmetric.
640	Moreover, if we cannot tie them, this alternative
641	needs to do a copy, which is one insn. */
642	struct costs *pp = this_op_costs[i];
643	int *pp_costs = pp->cost;
644	cost_classes_t cost_classes_ptr
645	= regno_cost_classes[REGNO (op)];
646	enum reg_class *cost_classes = cost_classes_ptr->classes;
647	bool in_p = recog_data.operand_type[i] != OP_OUT;
648	bool out_p = recog_data.operand_type[i] != OP_IN;
649	enum reg_class op_class = classes[i];
650
651	ira_init_register_move_cost_if_necessary (mode);
652	if (! in_p)
653	{
654	ira_assert (out_p);
655	if (op_class == NO_REGS)
656	{
657	mem_cost = ira_memory_move_cost[mode];
658	for (k = cost_classes_ptr->num - 1; k >= 0; k--)
659	{
660	rclass = cost_classes[k];
661	pp_costs[k] = mem_cost[rclass][0] * frequency;
662	}
663	}
664	else
665	{
666	move_out_cost = ira_may_move_out_cost[mode];
667	for (k = cost_classes_ptr->num - 1; k >= 0; k--)
668	{
669	rclass = cost_classes[k];
670	pp_costs[k]
671	= move_out_cost[op_class][rclass] * frequency;
672	}
673	}
674	}
675	else if (! out_p)
676	{
677	ira_assert (in_p);
678	if (op_class == NO_REGS)
679	{
680	mem_cost = ira_memory_move_cost[mode];
681	for (k = cost_classes_ptr->num - 1; k >= 0; k--)
682	{
683	rclass = cost_classes[k];
684	pp_costs[k] = mem_cost[rclass][1] * frequency;
685	}
686	}
687	else
688	{
689	move_in_cost = ira_may_move_in_cost[mode];
690	for (k = cost_classes_ptr->num - 1; k >= 0; k--)
691	{
692	rclass = cost_classes[k];
693	pp_costs[k]
694	= move_in_cost[rclass][op_class] * frequency;
695	}
696	}
697	}
698	else
699	{
700	if (op_class == NO_REGS)
701	{
702	mem_cost = ira_memory_move_cost[mode];
703	for (k = cost_classes_ptr->num - 1; k >= 0; k--)
704	{
705	rclass = cost_classes[k];
706	pp_costs[k] = ((mem_cost[rclass][0]
707	+ mem_cost[rclass][1])
708	* frequency);
709	}
710	}
711	else
712	{
713	move_in_cost = ira_may_move_in_cost[mode];
714	move_out_cost = ira_may_move_out_cost[mode];
715	for (k = cost_classes_ptr->num - 1; k >= 0; k--)
716	{
717	rclass = cost_classes[k];
718	pp_costs[k] = ((move_in_cost[rclass][op_class]
719	+ move_out_cost[op_class][rclass])
720	* frequency);
721	}
722	}
723	}
724
725	/* If the alternative actually allows memory, make
726	things a bit cheaper since we won't need an extra
727	insn to load it. */
728	pp->mem_cost
729	= ((out_p ? ira_memory_move_cost[mode][op_class][0] : 0)
730	+ (in_p ? ira_memory_move_cost[mode][op_class][1] : 0)
731	- allows_mem[i]) * frequency;
732
733	/* If we have assigned a class to this allocno in
734	our first pass, add a cost to this alternative
735	corresponding to what we would add if this
736	allocno were not in the appropriate class. */
737	if (pref)
738	{
739	enum reg_class pref_class = pref[COST_INDEX (REGNO (op))];
740
741	if (pref_class == NO_REGS)
742	alt_cost
743	+= ((out_p
744	? ira_memory_move_cost[mode][op_class][0] : 0)
745	+ (in_p
746	? ira_memory_move_cost[mode][op_class][1]
747	: 0));
748	else if (ira_reg_class_intersect
749	[pref_class][op_class] == NO_REGS)
750	alt_cost
751	+= ira_register_move_cost[mode][pref_class][op_class];
752	}
753	if (REGNO (ops[i]) != REGNO (ops[j])
754	&& ! find_reg_note (insn, REG_DEAD, op))
755	alt_cost += 2;
756
757	p++;
758	}
759	}
760
761	/* Scan all the constraint letters. See if the operand
762	matches any of the constraints. Collect the valid
763	register classes and see if this operand accepts
764	memory. */
765	while ((c = *p))
766	{
767	switch (c)
768	{
769	case '*':
770	/* Ignore the next letter for this pass. */
771	c = *++p;
772	break;
773
774	case '^':
775	alt_cost += 2;
776	break;
777
778	case '?':
779	alt_cost += 2;
780	break;
781
782	case 'g':
783	if (MEM_P (op)
784	|| (CONSTANT_P (op)
785	&& (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))))
786	win = 1;
787	insn_allows_mem[i] = allows_mem[i] = 1;
788	classes[i] = ira_reg_class_subunion[classes[i]][GENERAL_REGS];
789	break;
790
791	default:
792	enum constraint_num cn = lookup_constraint (p);
793	enum reg_class cl;
794	switch (get_constraint_type (c: cn))
795	{
796	case CT_REGISTER:
797	cl = reg_class_for_constraint (c: cn);
798	if (cl != NO_REGS)
799	classes[i] = ira_reg_class_subunion[classes[i]][cl];
800	break;
801
802	case CT_CONST_INT:
803	if (CONST_INT_P (op)
804	&& insn_const_int_ok_for_constraint (INTVAL (op), cn))
805	win = 1;
806	break;
807
808	case CT_MEMORY:
809	case CT_RELAXED_MEMORY:
810	/* Every MEM can be reloaded to fit. */
811	insn_allows_mem[i] = allows_mem[i] = 1;
812	if (MEM_P (op))
813	win = 1;
814	break;
815
816	case CT_SPECIAL_MEMORY:
817	insn_allows_mem[i] = allows_mem[i] = 1;
818	if (MEM_P (extract_mem_from_operand (op))
819	&& constraint_satisfied_p (x: op, c: cn))
820	win = 1;
821	break;
822
823	case CT_ADDRESS:
824	/* Every address can be reloaded to fit. */
825	allows_addr = 1;
826	if (address_operand (op, GET_MODE (op))
827	|| constraint_satisfied_p (x: op, c: cn))
828	win = 1;
829	/* We know this operand is an address, so we
830	want it to be allocated to a hard register
831	that can be the base of an address,
832	i.e. BASE_REG_CLASS. */
833	classes[i]
834	= ira_reg_class_subunion[classes[i]]
835	[base_reg_class (VOIDmode, ADDR_SPACE_GENERIC,
836	outer_code: ADDRESS, index_code: SCRATCH)];
837	break;
838
839	case CT_FIXED_FORM:
840	if (constraint_satisfied_p (x: op, c: cn))
841	win = 1;
842	break;
843	}
844	break;
845	}
846	p += CONSTRAINT_LEN (c, p);
847	if (c == ',')
848	break;
849	}
850
851	constraints[i] = p;
852
853	if (alt_fail)
854	break;
855
856	/* How we account for this operand now depends on whether it
857	is a pseudo register or not. If it is, we first check if
858	any register classes are valid. If not, we ignore this
859	alternative, since we want to assume that all allocnos get
860	allocated for register preferencing. If some register
861	class is valid, compute the costs of moving the allocno
862	into that class. */
863	if (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER)
864	{
865	if (classes[i] == NO_REGS && ! allows_mem[i])
866	{
867	/* We must always fail if the operand is a REG, but
868	we did not find a suitable class and memory is
869	not allowed.
870
871	Otherwise we may perform an uninitialized read
872	from this_op_costs after the `continue' statement
873	below. */
874	alt_fail = 1;
875	}
876	else
877	{
878	unsigned int regno = REGNO (op);
879	struct costs *pp = this_op_costs[i];
880	int *pp_costs = pp->cost;
881	cost_classes_t cost_classes_ptr = regno_cost_classes[regno];
882	enum reg_class *cost_classes = cost_classes_ptr->classes;
883	bool in_p = recog_data.operand_type[i] != OP_OUT;
884	bool out_p = recog_data.operand_type[i] != OP_IN;
885	enum reg_class op_class = classes[i];
886
887	ira_init_register_move_cost_if_necessary (mode);
888	if (! in_p)
889	{
890	ira_assert (out_p);
891	if (op_class == NO_REGS)
892	{
893	mem_cost = ira_memory_move_cost[mode];
894	for (k = cost_classes_ptr->num - 1; k >= 0; k--)
895	{
896	rclass = cost_classes[k];
897	pp_costs[k] = mem_cost[rclass][0] * frequency;
898	}
899	}
900	else
901	{
902	move_out_cost = ira_may_move_out_cost[mode];
903	for (k = cost_classes_ptr->num - 1; k >= 0; k--)
904	{
905	rclass = cost_classes[k];
906	pp_costs[k]
907	= move_out_cost[op_class][rclass] * frequency;
908	}
909	}
910	}
911	else if (! out_p)
912	{
913	ira_assert (in_p);
914	if (op_class == NO_REGS)
915	{
916	mem_cost = ira_memory_move_cost[mode];
917	for (k = cost_classes_ptr->num - 1; k >= 0; k--)
918	{
919	rclass = cost_classes[k];
920	pp_costs[k] = mem_cost[rclass][1] * frequency;
921	}
922	}
923	else
924	{
925	move_in_cost = ira_may_move_in_cost[mode];
926	for (k = cost_classes_ptr->num - 1; k >= 0; k--)
927	{
928	rclass = cost_classes[k];
929	pp_costs[k]
930	= move_in_cost[rclass][op_class] * frequency;
931	}
932	}
933	}
934	else
935	{
936	if (op_class == NO_REGS)
937	{
938	mem_cost = ira_memory_move_cost[mode];
939	for (k = cost_classes_ptr->num - 1; k >= 0; k--)
940	{
941	rclass = cost_classes[k];
942	pp_costs[k] = ((mem_cost[rclass][0]
943	+ mem_cost[rclass][1])
944	* frequency);
945	}
946	}
947	else
948	{
949	move_in_cost = ira_may_move_in_cost[mode];
950	move_out_cost = ira_may_move_out_cost[mode];
951	for (k = cost_classes_ptr->num - 1; k >= 0; k--)
952	{
953	rclass = cost_classes[k];
954	pp_costs[k] = ((move_in_cost[rclass][op_class]
955	+ move_out_cost[op_class][rclass])
956	* frequency);
957	}
958	}
959	}
960
961	if (op_class == NO_REGS)
962	/* Although we don't need insn to reload from
963	memory, still accessing memory is usually more
964	expensive than a register. */
965	pp->mem_cost = frequency;
966	else
967	/* If the alternative actually allows memory, make
968	things a bit cheaper since we won't need an
969	extra insn to load it. */
970	pp->mem_cost
971	= ((out_p ? ira_memory_move_cost[mode][op_class][0] : 0)
972	+ (in_p ? ira_memory_move_cost[mode][op_class][1] : 0)
973	- allows_mem[i]) * frequency;
974	/* If we have assigned a class to this allocno in
975	our first pass, add a cost to this alternative
976	corresponding to what we would add if this
977	allocno were not in the appropriate class. */
978	if (pref)
979	{
980	enum reg_class pref_class = pref[COST_INDEX (REGNO (op))];
981
982	if (pref_class == NO_REGS)
983	{
984	if (op_class != NO_REGS)
985	alt_cost
986	+= ((out_p
987	? ira_memory_move_cost[mode][op_class][0]
988	: 0)
989	+ (in_p
990	? ira_memory_move_cost[mode][op_class][1]
991	: 0));
992	}
993	else if (op_class == NO_REGS)
994	alt_cost
995	+= ((out_p
996	? ira_memory_move_cost[mode][pref_class][1]
997	: 0)
998	+ (in_p
999	? ira_memory_move_cost[mode][pref_class][0]
1000	: 0));
1001	else if (ira_reg_class_intersect[pref_class][op_class]
1002	== NO_REGS)
1003	alt_cost += (ira_register_move_cost
1004	[mode][pref_class][op_class]);
1005	}
1006	}
1007	}
1008
1009	/* Otherwise, if this alternative wins, either because we
1010	have already determined that or if we have a hard
1011	register of the proper class, there is no cost for this
1012	alternative. */
1013	else if (win || (REG_P (op)
1014	&& reg_fits_class_p (op, classes[i],
1015	0, GET_MODE (op))))
1016	;
1017
1018	/* If registers are valid, the cost of this alternative
1019	includes copying the object to and/or from a
1020	register. */
1021	else if (classes[i] != NO_REGS)
1022	{
1023	if (recog_data.operand_type[i] != OP_OUT)
1024	alt_cost += copy_cost (x: op, mode, rclass: classes[i], to_p: 1, NULL);
1025
1026	if (recog_data.operand_type[i] != OP_IN)
1027	alt_cost += copy_cost (x: op, mode, rclass: classes[i], to_p: 0, NULL);
1028	}
1029	/* The only other way this alternative can be used is if
1030	this is a constant that could be placed into memory. */
1031	else if (CONSTANT_P (op) && (allows_addr || allows_mem[i]))
1032	alt_cost += ira_memory_move_cost[mode][classes[i]][1];
1033	else
1034	alt_fail = 1;
1035
1036	if (alt_fail)
1037	break;
1038	}
1039
1040	if (alt_fail)
1041	{
1042	/* The loop above might have exited early once the failure
1043	was seen. Skip over the constraints for the remaining
1044	operands. */
1045	i += 1;
1046	for (; i < n_ops; ++i)
1047	constraints[i] = skip_alternative (p: constraints[i]);
1048	continue;
1049	}
1050
1051	op_cost_add = alt_cost * frequency;
1052	/* Finally, update the costs with the information we've
1053	calculated about this alternative. */
1054	for (i = 0; i < n_ops; i++)
1055	if (REG_P (ops[i]) && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1056	{
1057	int old_cost;
1058	bool cost_change_p = false;
1059	struct costs *pp = op_costs[i], *qq = this_op_costs[i];
1060	int *pp_costs = pp->cost, *qq_costs = qq->cost;
1061	int scale = 1 + (recog_data.operand_type[i] == OP_INOUT);
1062	cost_classes_t cost_classes_ptr
1063	= regno_cost_classes[REGNO (ops[i])];
1064
1065	old_cost = pp->mem_cost;
1066	pp->mem_cost = MIN (old_cost,
1067	(qq->mem_cost + op_cost_add) * scale);
1068
1069	if (ira_dump_file != NULL && internal_flag_ira_verbose > 5
1070	&& pp->mem_cost < old_cost)
1071	{
1072	cost_change_p = true;
1073	fprintf (stream: ira_dump_file, format: " op %d(r=%u) new costs MEM:%d",
1074	i, REGNO(ops[i]), pp->mem_cost);
1075	}
1076	for (k = cost_classes_ptr->num - 1; k >= 0; k--)
1077	{
1078	old_cost = pp_costs[k];
1079	pp_costs[k]
1080	= MIN (old_cost, (qq_costs[k] + op_cost_add) * scale);
1081	if (ira_dump_file != NULL && internal_flag_ira_verbose > 5
1082	&& pp_costs[k] < old_cost)
1083	{
1084	if (!cost_change_p)
1085	fprintf (stream: ira_dump_file, format: " op %d(r=%u) new costs",
1086	i, REGNO(ops[i]));
1087	cost_change_p = true;
1088	fprintf (stream: ira_dump_file, format: " %s:%d",
1089	reg_class_names[cost_classes_ptr->classes[k]],
1090	pp_costs[k]);
1091	}
1092	}
1093	if (ira_dump_file != NULL && internal_flag_ira_verbose > 5
1094	&& cost_change_p)
1095	fprintf (stream: ira_dump_file, format: "\n");
1096	}
1097	}
1098
1099	if (allocno_p)
1100	for (i = 0; i < n_ops; i++)
1101	{
1102	ira_allocno_t a;
1103	rtx op = ops[i];
1104
1105	if (! REG_P (op) || REGNO (op) < FIRST_PSEUDO_REGISTER)
1106	continue;
1107	a = ira_curr_regno_allocno_map [REGNO (op)];
1108	if (! ALLOCNO_BAD_SPILL_P (a) && insn_allows_mem[i] == 0)
1109	ALLOCNO_BAD_SPILL_P (a) = true;
1110	}
1111
1112	}
1113
1114
1115
1116	/* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudo registers. */
1117	static inline bool
1118	ok_for_index_p_nonstrict (rtx reg)
1119	{
1120	unsigned regno = REGNO (reg);
1121
1122	return regno >= FIRST_PSEUDO_REGISTER || REGNO_OK_FOR_INDEX_P (regno);
1123	}
1124
1125	/* A version of regno_ok_for_base_p for use here, when all
1126	pseudo-registers should count as OK. Arguments as for
1127	regno_ok_for_base_p. */
1128	static inline bool
1129	ok_for_base_p_nonstrict (rtx reg, machine_mode mode, addr_space_t as,
1130	enum rtx_code outer_code, enum rtx_code index_code)
1131	{
1132	unsigned regno = REGNO (reg);
1133
1134	if (regno >= FIRST_PSEUDO_REGISTER)
1135	return true;
1136	return ok_for_base_p_1 (regno, mode, as, outer_code, index_code);
1137	}
1138
1139	/* Record the pseudo registers we must reload into hard registers in a
1140	subexpression of a memory address, X.
1141
1142	If CONTEXT is 0, we are looking at the base part of an address,
1143	otherwise we are looking at the index part.
1144
1145	MODE and AS are the mode and address space of the memory reference;
1146	OUTER_CODE and INDEX_CODE give the context that the rtx appears in.
1147	These four arguments are passed down to base_reg_class.
1148
1149	SCALE is twice the amount to multiply the cost by (it is twice so
1150	we can represent half-cost adjustments). */
1151	static void
1152	record_address_regs (machine_mode mode, addr_space_t as, rtx x,
1153	int context, enum rtx_code outer_code,
1154	enum rtx_code index_code, int scale)
1155	{
1156	enum rtx_code code = GET_CODE (x);
1157	enum reg_class rclass;
1158
1159	if (context == 1)
1160	rclass = INDEX_REG_CLASS;
1161	else
1162	rclass = base_reg_class (mode, as, outer_code, index_code);
1163
1164	switch (code)
1165	{
1166	case CONST_INT:
1167	case CONST:
1168	case PC:
1169	case SYMBOL_REF:
1170	case LABEL_REF:
1171	return;
1172
1173	case PLUS:
1174	/* When we have an address that is a sum, we must determine
1175	whether registers are "base" or "index" regs. If there is a
1176	sum of two registers, we must choose one to be the "base".
1177	Luckily, we can use the REG_POINTER to make a good choice
1178	most of the time. We only need to do this on machines that
1179	can have two registers in an address and where the base and
1180	index register classes are different.
1181
1182	??? This code used to set REGNO_POINTER_FLAG in some cases,
1183	but that seems bogus since it should only be set when we are
1184	sure the register is being used as a pointer. */
1185	{
1186	rtx arg0 = XEXP (x, 0);
1187	rtx arg1 = XEXP (x, 1);
1188	enum rtx_code code0 = GET_CODE (arg0);
1189	enum rtx_code code1 = GET_CODE (arg1);
1190
1191	/* Look inside subregs. */
1192	if (code0 == SUBREG)
1193	arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0);
1194	if (code1 == SUBREG)
1195	arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1);
1196
1197	/* If index registers do not appear, or coincide with base registers,
1198	just record registers in any non-constant operands. We
1199	assume here, as well as in the tests below, that all
1200	addresses are in canonical form. */
1201	if (MAX_REGS_PER_ADDRESS == 1
1202	|| INDEX_REG_CLASS == base_reg_class (VOIDmode, as, outer_code: PLUS, index_code: SCRATCH))
1203	{
1204	record_address_regs (mode, as, x: arg0, context, outer_code: PLUS, index_code: code1, scale);
1205	if (! CONSTANT_P (arg1))
1206	record_address_regs (mode, as, x: arg1, context, outer_code: PLUS, index_code: code0, scale);
1207	}
1208
1209	/* If the second operand is a constant integer, it doesn't
1210	change what class the first operand must be. */
1211	else if (CONST_SCALAR_INT_P (arg1))
1212	record_address_regs (mode, as, x: arg0, context, outer_code: PLUS, index_code: code1, scale);
1213	/* If the second operand is a symbolic constant, the first
1214	operand must be an index register. */
1215	else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF)
1216	record_address_regs (mode, as, x: arg0, context: 1, outer_code: PLUS, index_code: code1, scale);
1217	/* If both operands are registers but one is already a hard
1218	register of index or reg-base class, give the other the
1219	class that the hard register is not. */
1220	else if (code0 == REG && code1 == REG
1221	&& REGNO (arg0) < FIRST_PSEUDO_REGISTER
1222	&& (ok_for_base_p_nonstrict (reg: arg0, mode, as, outer_code: PLUS, index_code: REG)
1223	|| ok_for_index_p_nonstrict (reg: arg0)))
1224	record_address_regs (mode, as, x: arg1,
1225	context: ok_for_base_p_nonstrict (reg: arg0, mode, as,
1226	outer_code: PLUS, index_code: REG) ? 1 : 0,
1227	outer_code: PLUS, index_code: REG, scale);
1228	else if (code0 == REG && code1 == REG
1229	&& REGNO (arg1) < FIRST_PSEUDO_REGISTER
1230	&& (ok_for_base_p_nonstrict (reg: arg1, mode, as, outer_code: PLUS, index_code: REG)
1231	|| ok_for_index_p_nonstrict (reg: arg1)))
1232	record_address_regs (mode, as, x: arg0,
1233	context: ok_for_base_p_nonstrict (reg: arg1, mode, as,
1234	outer_code: PLUS, index_code: REG) ? 1 : 0,
1235	outer_code: PLUS, index_code: REG, scale);
1236	/* If one operand is known to be a pointer, it must be the
1237	base with the other operand the index. Likewise if the
1238	other operand is a MULT. */
1239	else if ((code0 == REG && REG_POINTER (arg0)) || code1 == MULT)
1240	{
1241	record_address_regs (mode, as, x: arg0, context: 0, outer_code: PLUS, index_code: code1, scale);
1242	record_address_regs (mode, as, x: arg1, context: 1, outer_code: PLUS, index_code: code0, scale);
1243	}
1244	else if ((code1 == REG && REG_POINTER (arg1)) || code0 == MULT)
1245	{
1246	record_address_regs (mode, as, x: arg0, context: 1, outer_code: PLUS, index_code: code1, scale);
1247	record_address_regs (mode, as, x: arg1, context: 0, outer_code: PLUS, index_code: code0, scale);
1248	}
1249	/* Otherwise, count equal chances that each might be a base or
1250	index register. This case should be rare. */
1251	else
1252	{
1253	record_address_regs (mode, as, x: arg0, context: 0, outer_code: PLUS, index_code: code1, scale: scale / 2);
1254	record_address_regs (mode, as, x: arg0, context: 1, outer_code: PLUS, index_code: code1, scale: scale / 2);
1255	record_address_regs (mode, as, x: arg1, context: 0, outer_code: PLUS, index_code: code0, scale: scale / 2);
1256	record_address_regs (mode, as, x: arg1, context: 1, outer_code: PLUS, index_code: code0, scale: scale / 2);
1257	}
1258	}
1259	break;
1260
1261	/* Double the importance of an allocno that is incremented or
1262	decremented, since it would take two extra insns if it ends
1263	up in the wrong place. */
1264	case POST_MODIFY:
1265	case PRE_MODIFY:
1266	record_address_regs (mode, as, XEXP (x, 0), context: 0, outer_code: code,
1267	GET_CODE (XEXP (XEXP (x, 1), 1)), scale: 2 * scale);
1268	if (REG_P (XEXP (XEXP (x, 1), 1)))
1269	record_address_regs (mode, as, XEXP (XEXP (x, 1), 1), context: 1, outer_code: code, index_code: REG,
1270	scale: 2 * scale);
1271	break;
1272
1273	case POST_INC:
1274	case PRE_INC:
1275	case POST_DEC:
1276	case PRE_DEC:
1277	/* Double the importance of an allocno that is incremented or
1278	decremented, since it would take two extra insns if it ends
1279	up in the wrong place. */
1280	record_address_regs (mode, as, XEXP (x, 0), context: 0, outer_code: code, index_code: SCRATCH, scale: 2 * scale);
1281	break;
1282
1283	case REG:
1284	{
1285	struct costs *pp;
1286	int *pp_costs;
1287	enum reg_class i;
1288	int k, regno, add_cost;
1289	cost_classes_t cost_classes_ptr;
1290	enum reg_class *cost_classes;
1291	move_table *move_in_cost;
1292
1293	if (REGNO (x) < FIRST_PSEUDO_REGISTER)
1294	break;
1295
1296	regno = REGNO (x);
1297	if (allocno_p)
1298	ALLOCNO_BAD_SPILL_P (ira_curr_regno_allocno_map[regno]) = true;
1299	pp = COSTS (costs, COST_INDEX (regno));
1300	add_cost = (ira_memory_move_cost[Pmode][rclass][1] * scale) / 2;
1301	if (INT_MAX - add_cost < pp->mem_cost)
1302	pp->mem_cost = INT_MAX;
1303	else
1304	pp->mem_cost += add_cost;
1305	cost_classes_ptr = regno_cost_classes[regno];
1306	cost_classes = cost_classes_ptr->classes;
1307	pp_costs = pp->cost;
1308	ira_init_register_move_cost_if_necessary (Pmode);
1309	move_in_cost = ira_may_move_in_cost[Pmode];
1310	for (k = cost_classes_ptr->num - 1; k >= 0; k--)
1311	{
1312	i = cost_classes[k];
1313	add_cost = (move_in_cost[i][rclass] * scale) / 2;
1314	if (INT_MAX - add_cost < pp_costs[k])
1315	pp_costs[k] = INT_MAX;
1316	else
1317	pp_costs[k] += add_cost;
1318	}
1319	}
1320	break;
1321
1322	default:
1323	{
1324	const char *fmt = GET_RTX_FORMAT (code);
1325	int i;
1326	for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1327	if (fmt[i] == 'e')
1328	record_address_regs (mode, as, XEXP (x, i), context, outer_code: code, index_code: SCRATCH,
1329	scale);
1330	}
1331	}
1332	}
1333
1334
1335
1336	/* Calculate the costs of insn operands. */
1337	static void
1338	record_operand_costs (rtx_insn *insn, enum reg_class *pref)
1339	{
1340	const char *constraints[MAX_RECOG_OPERANDS];
1341	machine_mode modes[MAX_RECOG_OPERANDS];
1342	rtx set;
1343	int i;
1344
1345	if ((set = single_set (insn)) != NULL_RTX
1346	/* In rare cases the single set insn might have less 2 operands
1347	as the source can be a fixed special reg. */
1348	&& recog_data.n_operands > 1
1349	&& recog_data.operand[0] == SET_DEST (set)
1350	&& recog_data.operand[1] == SET_SRC (set))
1351	{
1352	int regno, other_regno;
1353	rtx dest = SET_DEST (set);
1354	rtx src = SET_SRC (set);
1355
1356	if (GET_CODE (dest) == SUBREG
1357	&& known_eq (GET_MODE_SIZE (GET_MODE (dest)),
1358	GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))))
1359	dest = SUBREG_REG (dest);
1360	if (GET_CODE (src) == SUBREG
1361	&& known_eq (GET_MODE_SIZE (GET_MODE (src)),
1362	GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))))
1363	src = SUBREG_REG (src);
1364	if (REG_P (src) && REG_P (dest)
1365	&& (((regno = REGNO (src)) >= FIRST_PSEUDO_REGISTER
1366	&& (other_regno = REGNO (dest)) < FIRST_PSEUDO_REGISTER)
1367	|| ((regno = REGNO (dest)) >= FIRST_PSEUDO_REGISTER
1368	&& (other_regno = REGNO (src)) < FIRST_PSEUDO_REGISTER)))
1369	{
1370	machine_mode mode = GET_MODE (SET_SRC (set)), cost_mode = mode;
1371	machine_mode hard_reg_mode = GET_MODE(regno_reg_rtx[other_regno]);
1372	poly_int64 pmode_size = GET_MODE_SIZE (mode);
1373	poly_int64 phard_reg_mode_size = GET_MODE_SIZE (mode: hard_reg_mode);
1374	HOST_WIDE_INT mode_size, hard_reg_mode_size;
1375	cost_classes_t cost_classes_ptr = regno_cost_classes[regno];
1376	enum reg_class *cost_classes = cost_classes_ptr->classes;
1377	reg_class_t rclass, hard_reg_class, bigger_hard_reg_class;
1378	int cost_factor = 1, cost, k;
1379	move_table *move_costs;
1380	bool dead_p = find_regno_note (insn, REG_DEAD, REGNO (src));
1381
1382	hard_reg_class = REGNO_REG_CLASS (other_regno);
1383	bigger_hard_reg_class = ira_pressure_class_translate[hard_reg_class];
1384	/* Target code may return any cost for mode which does not fit the
1385	hard reg class (e.g. DImode for AREG on i386). Check this and use
1386	a bigger class to get the right cost. */
1387	if (bigger_hard_reg_class != NO_REGS
1388	&& ! ira_hard_reg_in_set_p (hard_regno: other_regno, mode,
1389	reg_class_contents[hard_reg_class]))
1390	hard_reg_class = bigger_hard_reg_class;
1391	ira_init_register_move_cost_if_necessary (mode);
1392	ira_init_register_move_cost_if_necessary (mode: hard_reg_mode);
1393	/* Use smaller movement cost for natural hard reg mode or its mode as
1394	operand. */
1395	if (pmode_size.is_constant (const_value: &mode_size)
1396	&& phard_reg_mode_size.is_constant (const_value: &hard_reg_mode_size))
1397	{
1398	/* Assume we are moving in the natural modes: */
1399	cost_factor = mode_size / hard_reg_mode_size;
1400	if (mode_size % hard_reg_mode_size != 0)
1401	cost_factor++;
1402	if (cost_factor
1403	* (ira_register_move_cost
1404	[hard_reg_mode][hard_reg_class][hard_reg_class])
1405	< (ira_register_move_cost
1406	[mode][hard_reg_class][hard_reg_class]))
1407	cost_mode = hard_reg_mode;
1408	else
1409	cost_factor = 1;
1410	}
1411	move_costs = ira_register_move_cost[cost_mode];
1412	i = regno == (int) REGNO (src) ? 1 : 0;
1413	for (k = cost_classes_ptr->num - 1; k >= 0; k--)
1414	{
1415	rclass = cost_classes[k];
1416	cost = (i == 0
1417	? move_costs[hard_reg_class][rclass]
1418	: move_costs[rclass][hard_reg_class]);
1419	cost *= cost_factor;
1420	op_costs[i]->cost[k] = cost * frequency;
1421	/* If this insn is a single set copying operand 1 to
1422	operand 0 and one operand is an allocno with the
1423	other a hard reg or an allocno that prefers a hard
1424	register that is in its own register class then we
1425	may want to adjust the cost of that register class to
1426	-1.
1427
1428	Avoid the adjustment if the source does not die to
1429	avoid stressing of register allocator by preferencing
1430	two colliding registers into single class. */
1431	if (dead_p
1432	&& TEST_HARD_REG_BIT (reg_class_contents[rclass], bit: other_regno)
1433	&& (reg_class_size[(int) rclass]
1434	== (ira_reg_class_max_nregs
1435	[(int) rclass][(int) GET_MODE(src)])))
1436	{
1437	if (reg_class_size[rclass] == 1)
1438	op_costs[i]->cost[k] = -frequency;
1439	else if (in_hard_reg_set_p (reg_class_contents[rclass],
1440	GET_MODE(src), regno: other_regno))
1441	op_costs[i]->cost[k] = -frequency;
1442	}
1443	}
1444	op_costs[i]->mem_cost
1445	= ira_memory_move_cost[mode][hard_reg_class][i] * frequency;
1446	return;
1447	}
1448	}
1449
1450	for (i = 0; i < recog_data.n_operands; i++)
1451	{
1452	constraints[i] = recog_data.constraints[i];
1453	modes[i] = recog_data.operand_mode[i];
1454	}
1455
1456	/* If we get here, we are set up to record the costs of all the
1457	operands for this insn. Start by initializing the costs. Then
1458	handle any address registers. Finally record the desired classes
1459	for any allocnos, doing it twice if some pair of operands are
1460	commutative. */
1461	for (i = 0; i < recog_data.n_operands; i++)
1462	{
1463	rtx op_mem = extract_mem_from_operand (recog_data.operand[i]);
1464	memcpy (op_costs[i], init_cost, n: struct_costs_size);
1465
1466	if (GET_CODE (recog_data.operand[i]) == SUBREG)
1467	recog_data.operand[i] = SUBREG_REG (recog_data.operand[i]);
1468
1469	if (MEM_P (op_mem))
1470	record_address_regs (GET_MODE (op_mem),
1471	MEM_ADDR_SPACE (op_mem),
1472	XEXP (op_mem, 0),
1473	context: 0, outer_code: MEM, index_code: SCRATCH, scale: frequency * 2);
1474	else if (constraints[i][0] == 'p'
1475	|| (insn_extra_address_constraint
1476	(c: lookup_constraint (p: constraints[i]))))
1477	record_address_regs (VOIDmode, ADDR_SPACE_GENERIC,
1478	x: recog_data.operand[i], context: 0, outer_code: ADDRESS, index_code: SCRATCH,
1479	scale: frequency * 2);
1480	}
1481
1482	/* Check for commutative in a separate loop so everything will have
1483	been initialized. We must do this even if one operand is a
1484	constant--see addsi3 in m68k.md. */
1485	for (i = 0; i < (int) recog_data.n_operands - 1; i++)
1486	if (constraints[i][0] == '%')
1487	{
1488	const char *xconstraints[MAX_RECOG_OPERANDS];
1489	int j;
1490
1491	/* Handle commutative operands by swapping the
1492	constraints. We assume the modes are the same. */
1493	for (j = 0; j < recog_data.n_operands; j++)
1494	xconstraints[j] = constraints[j];
1495
1496	xconstraints[i] = constraints[i+1];
1497	xconstraints[i+1] = constraints[i];
1498	record_reg_classes (n_alts: recog_data.n_alternatives, n_ops: recog_data.n_operands,
1499	ops: recog_data.operand, modes,
1500	constraints: xconstraints, insn, pref);
1501	}
1502	record_reg_classes (n_alts: recog_data.n_alternatives, n_ops: recog_data.n_operands,
1503	ops: recog_data.operand, modes,
1504	constraints, insn, pref);
1505	}
1506
1507
1508
1509	/* Process one insn INSN. Scan it and record each time it would save
1510	code to put a certain allocnos in a certain class. Return the last
1511	insn processed, so that the scan can be continued from there. */
1512	static rtx_insn *
1513	scan_one_insn (rtx_insn *insn)
1514	{
1515	enum rtx_code pat_code;
1516	rtx set, note;
1517	int i, k;
1518	bool counted_mem;
1519
1520	if (!NONDEBUG_INSN_P (insn))
1521	return insn;
1522
1523	pat_code = GET_CODE (PATTERN (insn));
1524	if (pat_code == ASM_INPUT)
1525	return insn;
1526
1527	/* If INSN is a USE/CLOBBER of a pseudo in a mode M then go ahead
1528	and initialize the register move costs of mode M.
1529
1530	The pseudo may be related to another pseudo via a copy (implicit or
1531	explicit) and if there are no mode M uses/sets of the original
1532	pseudo, then we may leave the register move costs uninitialized for
1533	mode M. */
1534	if (pat_code == USE || pat_code == CLOBBER)
1535	{
1536	rtx x = XEXP (PATTERN (insn), 0);
1537	if (GET_CODE (x) == REG
1538	&& REGNO (x) >= FIRST_PSEUDO_REGISTER
1539	&& have_regs_of_mode[GET_MODE (x)])
1540	ira_init_register_move_cost_if_necessary (GET_MODE (x));
1541	return insn;
1542	}
1543
1544	counted_mem = false;
1545	set = single_set (insn);
1546	extract_insn (insn);
1547
1548	/* If this insn loads a parameter from its stack slot, then it
1549	represents a savings, rather than a cost, if the parameter is
1550	stored in memory. Record this fact.
1551
1552	Similarly if we're loading other constants from memory (constant
1553	pool, TOC references, small data areas, etc) and this is the only
1554	assignment to the destination pseudo.
1555
1556	Don't do this if SET_SRC (set) isn't a general operand, if it is
1557	a memory requiring special instructions to load it, decreasing
1558	mem_cost might result in it being loaded using the specialized
1559	instruction into a register, then stored into stack and loaded
1560	again from the stack. See PR52208.
1561
1562	Don't do this if SET_SRC (set) has side effect. See PR56124. */
1563	if (set != 0 && REG_P (SET_DEST (set)) && MEM_P (SET_SRC (set))
1564	&& (note = find_reg_note (insn, REG_EQUIV, NULL_RTX)) != NULL_RTX
1565	&& ((MEM_P (XEXP (note, 0))
1566	&& !side_effects_p (SET_SRC (set)))
1567	|| (CONSTANT_P (XEXP (note, 0))
1568	&& targetm.legitimate_constant_p (GET_MODE (SET_DEST (set)),
1569	XEXP (note, 0))
1570	&& REG_N_SETS (REGNO (SET_DEST (set))) == 1))
1571	&& general_operand (SET_SRC (set), GET_MODE (SET_SRC (set)))
1572	/* LRA does not use equiv with a symbol for PIC code. */
1573	&& (! ira_use_lra_p || ! pic_offset_table_rtx
1574	|| ! contains_symbol_ref_p (XEXP (note, 0))))
1575	{
1576	enum reg_class cl = GENERAL_REGS;
1577	rtx reg = SET_DEST (set);
1578	int num = COST_INDEX (REGNO (reg));
1579	/* Costs for NO_REGS are used in cost calculation on the
1580	1st pass when the preferred register classes are not
1581	known yet. In this case we take the best scenario when
1582	mode can't be put into GENERAL_REGS. */
1583	if (!targetm.hard_regno_mode_ok (ira_class_hard_regs[cl][0],
1584	GET_MODE (reg)))
1585	cl = NO_REGS;
1586
1587	COSTS (costs, num)->mem_cost
1588	-= ira_memory_move_cost[GET_MODE (reg)][cl][1] * frequency;
1589	record_address_regs (GET_MODE (SET_SRC (set)),
1590	MEM_ADDR_SPACE (SET_SRC (set)),
1591	XEXP (SET_SRC (set), 0), context: 0, outer_code: MEM, index_code: SCRATCH,
1592	scale: frequency * 2);
1593	counted_mem = true;
1594	}
1595
1596	record_operand_costs (insn, pref);
1597
1598	if (ira_dump_file != NULL && internal_flag_ira_verbose > 5)
1599	{
1600	const char *p;
1601	fprintf (stream: ira_dump_file, format: " Final costs after insn %u", INSN_UID (insn));
1602	if (INSN_CODE (insn) >= 0
1603	&& (p = get_insn_name (INSN_CODE (insn))) != NULL)
1604	fprintf (stream: ira_dump_file, format: " {%s}", p);
1605	fprintf (stream: ira_dump_file, format: " (freq=%d)\n",
1606	REG_FREQ_FROM_BB (BLOCK_FOR_INSN (insn)));
1607	dump_insn_slim (ira_dump_file, insn);
1608	}
1609
1610	/* Now add the cost for each operand to the total costs for its
1611	allocno. */
1612	for (i = 0; i < recog_data.n_operands; i++)
1613	{
1614	rtx op = recog_data.operand[i];
1615
1616	if (GET_CODE (op) == SUBREG)
1617	op = SUBREG_REG (op);
1618	if (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1619	{
1620	int regno = REGNO (op);
1621	struct costs *p = COSTS (costs, COST_INDEX (regno));
1622	struct costs *q = op_costs[i];
1623	int *p_costs = p->cost, *q_costs = q->cost;
1624	cost_classes_t cost_classes_ptr = regno_cost_classes[regno];
1625	int add_cost = 0;
1626
1627	/* If the already accounted for the memory "cost" above, don't
1628	do so again. */
1629	if (!counted_mem)
1630	{
1631	add_cost = q->mem_cost;
1632	if (add_cost > 0 && INT_MAX - add_cost < p->mem_cost)
1633	p->mem_cost = INT_MAX;
1634	else
1635	p->mem_cost += add_cost;
1636	}
1637	if (ira_dump_file != NULL && internal_flag_ira_verbose > 5)
1638	{
1639	fprintf (stream: ira_dump_file, format: " op %d(r=%u) MEM:%d(+%d)",
1640	i, REGNO(op), p->mem_cost, add_cost);
1641	}
1642	for (k = cost_classes_ptr->num - 1; k >= 0; k--)
1643	{
1644	add_cost = q_costs[k];
1645	if (add_cost > 0 && INT_MAX - add_cost < p_costs[k])
1646	p_costs[k] = INT_MAX;
1647	else
1648	p_costs[k] += add_cost;
1649	if (ira_dump_file != NULL && internal_flag_ira_verbose > 5)
1650	{
1651	fprintf (stream: ira_dump_file, format: " %s:%d(+%d)",
1652	reg_class_names[cost_classes_ptr->classes[k]],
1653	p_costs[k], add_cost);
1654	}
1655	}
1656	if (ira_dump_file != NULL && internal_flag_ira_verbose > 5)
1657	fprintf (stream: ira_dump_file, format: "\n");
1658	}
1659	}
1660	return insn;
1661	}
1662
1663
1664
1665	/* Print allocnos costs to the dump file. */
1666	static void
1667	print_allocno_costs (void)
1668	{
1669	int k;
1670	ira_allocno_t a;
1671	ira_allocno_iterator ai;
1672
1673	ira_assert (allocno_p);
1674	fprintf (stream: ira_dump_file, format: "\n");
1675	FOR_EACH_ALLOCNO (a, ai)
1676	{
1677	int i, rclass;
1678	basic_block bb;
1679	int regno = ALLOCNO_REGNO (a);
1680	cost_classes_t cost_classes_ptr = regno_cost_classes[regno];
1681	enum reg_class *cost_classes = cost_classes_ptr->classes;
1682
1683	i = ALLOCNO_NUM (a);
1684	fprintf (stream: ira_dump_file, format: " a%d(r%d,", i, regno);
1685	if ((bb = ALLOCNO_LOOP_TREE_NODE (a)->bb) != NULL)
1686	fprintf (stream: ira_dump_file, format: "b%d", bb->index);
1687	else
1688	fprintf (stream: ira_dump_file, format: "l%d", ALLOCNO_LOOP_TREE_NODE (a)->loop_num);
1689	fprintf (stream: ira_dump_file, format: ") costs:");
1690	for (k = 0; k < cost_classes_ptr->num; k++)
1691	{
1692	rclass = cost_classes[k];
1693	fprintf (stream: ira_dump_file, format: " %s:%d", reg_class_names[rclass],
1694	COSTS (costs, i)->cost[k]);
1695	if (flag_ira_region == IRA_REGION_ALL
1696	|| flag_ira_region == IRA_REGION_MIXED)
1697	fprintf (stream: ira_dump_file, format: ",%d",
1698	COSTS (total_allocno_costs, i)->cost[k]);
1699	}
1700	fprintf (stream: ira_dump_file, format: " MEM:%i", COSTS (costs, i)->mem_cost);
1701	if (flag_ira_region == IRA_REGION_ALL
1702	|| flag_ira_region == IRA_REGION_MIXED)
1703	fprintf (stream: ira_dump_file, format: ",%d",
1704	COSTS (total_allocno_costs, i)->mem_cost);
1705	fprintf (stream: ira_dump_file, format: "\n");
1706	}
1707	}
1708
1709	/* Print pseudo costs to the dump file. */
1710	static void
1711	print_pseudo_costs (void)
1712	{
1713	int regno, k;
1714	int rclass;
1715	cost_classes_t cost_classes_ptr;
1716	enum reg_class *cost_classes;
1717
1718	ira_assert (! allocno_p);
1719	fprintf (stream: ira_dump_file, format: "\n");
1720	for (regno = max_reg_num () - 1; regno >= FIRST_PSEUDO_REGISTER; regno--)
1721	{
1722	if (REG_N_REFS (regno) <= 0)
1723	continue;
1724	cost_classes_ptr = regno_cost_classes[regno];
1725	cost_classes = cost_classes_ptr->classes;
1726	fprintf (stream: ira_dump_file, format: " r%d costs:", regno);
1727	for (k = 0; k < cost_classes_ptr->num; k++)
1728	{
1729	rclass = cost_classes[k];
1730	fprintf (stream: ira_dump_file, format: " %s:%d", reg_class_names[rclass],
1731	COSTS (costs, regno)->cost[k]);
1732	}
1733	fprintf (stream: ira_dump_file, format: " MEM:%i\n", COSTS (costs, regno)->mem_cost);
1734	}
1735	}
1736
1737	/* Traverse the BB represented by LOOP_TREE_NODE to update the allocno
1738	costs. */
1739	static void
1740	process_bb_for_costs (basic_block bb)
1741	{
1742	rtx_insn *insn;
1743
1744	frequency = REG_FREQ_FROM_BB (bb);
1745	if (frequency == 0)
1746	frequency = 1;
1747	FOR_BB_INSNS (bb, insn)
1748	insn = scan_one_insn (insn);
1749	}
1750
1751	/* Traverse the BB represented by LOOP_TREE_NODE to update the allocno
1752	costs. */
1753	static void
1754	process_bb_node_for_costs (ira_loop_tree_node_t loop_tree_node)
1755	{
1756	basic_block bb;
1757
1758	bb = loop_tree_node->bb;
1759	if (bb != NULL)
1760	process_bb_for_costs (bb);
1761	}
1762
1763	/* Return true if all autoinc rtx in X change only a register and memory is
1764	valid. */
1765	static bool
1766	validate_autoinc_and_mem_addr_p (rtx x)
1767	{
1768	enum rtx_code code = GET_CODE (x);
1769	if (GET_RTX_CLASS (code) == RTX_AUTOINC)
1770	return REG_P (XEXP (x, 0));
1771	const char *fmt = GET_RTX_FORMAT (code);
1772	for (int i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1773	if (fmt[i] == 'e')
1774	{
1775	if (!validate_autoinc_and_mem_addr_p (XEXP (x, i)))
1776	return false;
1777	}
1778	else if (fmt[i] == 'E')
1779	{
1780	for (int j = 0; j < XVECLEN (x, i); j++)
1781	if (!validate_autoinc_and_mem_addr_p (XVECEXP (x, i, j)))
1782	return false;
1783	}
1784	/* Check memory after checking autoinc to guarantee that autoinc is already
1785	valid for machine-dependent code checking memory address. */
1786	return (!MEM_P (x)
1787	|| memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
1788	MEM_ADDR_SPACE (x)));
1789	}
1790
1791	/* Check that reg REGNO in INSN can be changed by TO (which is an invariant
1792	equiv when INVARIANT_P is true). Return true in case the result insn would
1793	be valid one. */
1794	static bool
1795	equiv_can_be_consumed_p (int regno, rtx to, rtx_insn *insn, bool invariant_p)
1796	{
1797	validate_replace_src_group (regno_reg_rtx[regno], to, insn);
1798	/* We can change register to equivalent memory in autoinc rtl. Some code
1799	including verify_changes assumes that autoinc contains only a register.
1800	So check this first. */
1801	bool res = validate_autoinc_and_mem_addr_p (x: PATTERN (insn));
1802	if (res)
1803	res = verify_changes (0);
1804	cancel_changes (0);
1805	if (!res && invariant_p)
1806	{
1807	/* Here we use more expensive code for the invariant because we need to
1808	simplify the result insn as the invariant can be arithmetic rtx
1809	inserted into another arithmetic rtx, e.g. into memory address. */
1810	rtx pat = PATTERN (insn);
1811	int code = INSN_CODE (insn);
1812	PATTERN (insn) = copy_rtx (pat);
1813	PATTERN (insn)
1814	= simplify_replace_rtx (PATTERN (insn), regno_reg_rtx[regno], to);
1815	res = !insn_invalid_p (insn, false);
1816	PATTERN (insn) = pat;
1817	INSN_CODE (insn) = code;
1818	}
1819	return res;
1820	}
1821
1822	/* Return true if X contains a pseudo with equivalence. In this case also
1823	return the pseudo through parameter REG. If the pseudo is a part of subreg,
1824	return the subreg through parameter SUBREG. */
1825
1826	static bool
1827	get_equiv_regno (rtx x, int &regno, rtx &subreg)
1828	{
1829	subreg = NULL_RTX;
1830	if (GET_CODE (x) == SUBREG)
1831	{
1832	subreg = x;
1833	x = SUBREG_REG (x);
1834	}
1835	if (REG_P (x)
1836	&& (ira_reg_equiv[REGNO (x)].memory != NULL
1837	|| ira_reg_equiv[REGNO (x)].invariant != NULL
1838	|| ira_reg_equiv[REGNO (x)].constant != NULL))
1839	{
1840	regno = REGNO (x);
1841	return true;
1842	}
1843	RTX_CODE code = GET_CODE (x);
1844	const char *fmt = GET_RTX_FORMAT (code);
1845
1846	for (int i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1847	if (fmt[i] == 'e')
1848	{
1849	if (get_equiv_regno (XEXP (x, i), regno, subreg))
1850	return true;
1851	}
1852	else if (fmt[i] == 'E')
1853	{
1854	for (int j = 0; j < XVECLEN (x, i); j++)
1855	if (get_equiv_regno (XVECEXP (x, i, j), regno, subreg))
1856	return true;
1857	}
1858	return false;
1859	}
1860
1861	/* A pass through the current function insns. Calculate costs of using
1862	equivalences for pseudos and store them in regno_equiv_gains. */
1863
1864	static void
1865	calculate_equiv_gains (void)
1866	{
1867	basic_block bb;
1868	int regno, freq, cost;
1869	rtx subreg;
1870	rtx_insn *insn;
1871	machine_mode mode;
1872	enum reg_class rclass;
1873	bitmap_head equiv_pseudos;
1874
1875	ira_assert (allocno_p);
1876	bitmap_initialize (head: &equiv_pseudos, obstack: &reg_obstack);
1877	for (regno = max_reg_num () - 1; regno >= FIRST_PSEUDO_REGISTER; regno--)
1878	if (ira_reg_equiv[regno].init_insns != NULL
1879	&& (ira_reg_equiv[regno].memory != NULL
1880	|| ira_reg_equiv[regno].invariant != NULL
1881	|| (ira_reg_equiv[regno].constant != NULL
1882	/* Ignore complicated constants which probably will be placed
1883	in memory: */
1884	&& GET_CODE (ira_reg_equiv[regno].constant) != CONST_DOUBLE
1885	&& GET_CODE (ira_reg_equiv[regno].constant) != CONST_VECTOR
1886	&& GET_CODE (ira_reg_equiv[regno].constant) != LABEL_REF)))
1887	{
1888	rtx_insn_list *x;
1889	for (x = ira_reg_equiv[regno].init_insns; x != NULL; x = x->next ())
1890	{
1891	insn = x->insn ();
1892	rtx set = single_set (insn);
1893
1894	if (set == NULL_RTX || SET_DEST (set) != regno_reg_rtx[regno])
1895	break;
1896	bb = BLOCK_FOR_INSN (insn);
1897	ira_curr_regno_allocno_map
1898	= ira_bb_nodes[bb->index].parent->regno_allocno_map;
1899	mode = PSEUDO_REGNO_MODE (regno);
1900	rclass = pref[COST_INDEX (regno)];
1901	ira_init_register_move_cost_if_necessary (mode);
1902	if (ira_reg_equiv[regno].memory != NULL)
1903	cost = ira_memory_move_cost[mode][rclass][1];
1904	else
1905	cost = ira_register_move_cost[mode][rclass][rclass];
1906	freq = REG_FREQ_FROM_BB (bb);
1907	regno_equiv_gains[regno] += cost * freq;
1908	}
1909	if (x != NULL)
1910	/* We found complicated equiv or reverse equiv mem=reg. Ignore
1911	them. */
1912	regno_equiv_gains[regno] = 0;
1913	else
1914	bitmap_set_bit (&equiv_pseudos, regno);
1915	}
1916
1917	FOR_EACH_BB_FN (bb, cfun)
1918	{
1919	freq = REG_FREQ_FROM_BB (bb);
1920	ira_curr_regno_allocno_map
1921	= ira_bb_nodes[bb->index].parent->regno_allocno_map;
1922	FOR_BB_INSNS (bb, insn)
1923	{
1924	if (!NONDEBUG_INSN_P (insn)
1925	|| !get_equiv_regno (x: PATTERN (insn), regno, subreg)
1926	|| !bitmap_bit_p (&equiv_pseudos, regno))
1927	continue;
1928
1929	if (ira_reg_equiv[regno].invariant != NULL)
1930	{
1931	rtx_insn_list *x = ira_reg_equiv[regno].init_insns;
1932	for (; x != NULL; x = x->next ())
1933	if (insn == x->insn ())
1934	break;
1935	if (x != NULL)
1936	continue; /* skip equiv init insn for invariant */
1937	}
1938
1939	rtx subst = ira_reg_equiv[regno].memory;
1940
1941	if (subst == NULL)
1942	subst = ira_reg_equiv[regno].constant;
1943	if (subst == NULL)
1944	subst = ira_reg_equiv[regno].invariant;
1945	ira_assert (subst != NULL);
1946	mode = PSEUDO_REGNO_MODE (regno);
1947	ira_init_register_move_cost_if_necessary (mode);
1948	bool consumed_p
1949	= equiv_can_be_consumed_p (regno, to: subst, insn,
1950	invariant_p: subst == ira_reg_equiv[regno].invariant);
1951
1952	rclass = pref[COST_INDEX (regno)];
1953	if (MEM_P (subst)
1954	/* If it is a change of constant into double for example, the
1955	result constant probably will be placed in memory. */
1956	|| (ira_reg_equiv[regno].invariant == NULL
1957	&& subreg != NULL_RTX
1958	&& !INTEGRAL_MODE_P (GET_MODE (subreg))))
1959	cost = ira_memory_move_cost[mode][rclass][1] + (consumed_p ? 0 : 1);
1960	else if (consumed_p)
1961	continue;
1962	else
1963	cost = ira_register_move_cost[mode][rclass][rclass];
1964	regno_equiv_gains[regno] -= cost * freq;
1965	}
1966	}
1967	bitmap_clear (&equiv_pseudos);
1968	}
1969
1970	/* Find costs of register classes and memory for allocnos or pseudos
1971	and their best costs. Set up preferred, alternative and allocno
1972	classes for pseudos. */
1973	static void
1974	find_costs_and_classes (void)
1975	{
1976	int i, k, start, max_cost_classes_num;
1977	int pass;
1978	basic_block bb;
1979	enum reg_class *regno_best_class, new_class;
1980
1981	init_recog ();
1982	regno_best_class
1983	= (enum reg_class *) ira_allocate (max_reg_num ()
1984	* sizeof (enum reg_class));
1985	for (i = max_reg_num () - 1; i >= FIRST_PSEUDO_REGISTER; i--)
1986	regno_best_class[i] = NO_REGS;
1987	if (!resize_reg_info () && allocno_p
1988	&& pseudo_classes_defined_p && flag_expensive_optimizations)
1989	{
1990	ira_allocno_t a;
1991	ira_allocno_iterator ai;
1992
1993	pref = pref_buffer;
1994	max_cost_classes_num = 1;
1995	FOR_EACH_ALLOCNO (a, ai)
1996	{
1997	pref[ALLOCNO_NUM (a)] = reg_preferred_class (ALLOCNO_REGNO (a));
1998	setup_regno_cost_classes_by_aclass
1999	(ALLOCNO_REGNO (a), aclass: pref[ALLOCNO_NUM (a)]);
2000	max_cost_classes_num
2001	= MAX (max_cost_classes_num,
2002	regno_cost_classes[ALLOCNO_REGNO (a)]->num);
2003	}
2004	start = 1;
2005	}
2006	else
2007	{
2008	pref = NULL;
2009	max_cost_classes_num = ira_important_classes_num;
2010	for (i = max_reg_num () - 1; i >= FIRST_PSEUDO_REGISTER; i--)
2011	if (regno_reg_rtx[i] != NULL_RTX)
2012	setup_regno_cost_classes_by_mode (regno: i, PSEUDO_REGNO_MODE (i));
2013	else
2014	setup_regno_cost_classes_by_aclass (regno: i, aclass: ALL_REGS);
2015	start = 0;
2016	}
2017	if (allocno_p)
2018	/* Clear the flag for the next compiled function. */
2019	pseudo_classes_defined_p = false;
2020	/* Normally we scan the insns once and determine the best class to
2021	use for each allocno. However, if -fexpensive-optimizations are
2022	on, we do so twice, the second time using the tentative best
2023	classes to guide the selection. */
2024	for (pass = start; pass <= flag_expensive_optimizations; pass++)
2025	{
2026	if ((!allocno_p || internal_flag_ira_verbose > 0) && ira_dump_file)
2027	fprintf (stream: ira_dump_file,
2028	format: "\nPass %i for finding pseudo/allocno costs\n\n", pass);
2029
2030	if (pass != start)
2031	{
2032	max_cost_classes_num = 1;
2033	for (i = max_reg_num () - 1; i >= FIRST_PSEUDO_REGISTER; i--)
2034	{
2035	setup_regno_cost_classes_by_aclass (regno: i, aclass: regno_best_class[i]);
2036	max_cost_classes_num
2037	= MAX (max_cost_classes_num, regno_cost_classes[i]->num);
2038	}
2039	}
2040
2041	struct_costs_size
2042	= sizeof (struct costs) + sizeof (int) * (max_cost_classes_num - 1);
2043	/* Zero out our accumulation of the cost of each class for each
2044	allocno. */
2045	memset (s: costs, c: 0, n: cost_elements_num * struct_costs_size);
2046
2047	if (allocno_p)
2048	{
2049	/* Scan the instructions and record each time it would save code
2050	to put a certain allocno in a certain class. */
2051	ira_traverse_loop_tree (true, ira_loop_tree_root,
2052	process_bb_node_for_costs, NULL);
2053
2054	memcpy (dest: total_allocno_costs, src: costs,
2055	max_struct_costs_size * ira_allocnos_num);
2056	}
2057	else
2058	{
2059	basic_block bb;
2060
2061	FOR_EACH_BB_FN (bb, cfun)
2062	process_bb_for_costs (bb);
2063	}
2064
2065	if (pass == 0)
2066	pref = pref_buffer;
2067
2068	if (ira_use_lra_p && allocno_p && pass == 1)
2069	/* It is a pass through all insns. So do it once and only for RA (not
2070	for insn scheduler) when we already found preferable pseudo register
2071	classes on the previous pass. */
2072	calculate_equiv_gains ();
2073
2074	/* Now for each allocno look at how desirable each class is and
2075	find which class is preferred. */
2076	for (i = max_reg_num () - 1; i >= FIRST_PSEUDO_REGISTER; i--)
2077	{
2078	ira_allocno_t a, parent_a;
2079	int rclass, a_num, parent_a_num, add_cost;
2080	ira_loop_tree_node_t parent;
2081	int best_cost, allocno_cost;
2082	enum reg_class best, alt_class;
2083	cost_classes_t cost_classes_ptr = regno_cost_classes[i];
2084	enum reg_class *cost_classes;
2085	int *i_costs = temp_costs->cost;
2086	int i_mem_cost;
2087	int equiv_savings = regno_equiv_gains[i];
2088
2089	if (! allocno_p)
2090	{
2091	if (regno_reg_rtx[i] == NULL_RTX)
2092	continue;
2093	memcpy (temp_costs, COSTS (costs, i), n: struct_costs_size);
2094	i_mem_cost = temp_costs->mem_cost;
2095	cost_classes = cost_classes_ptr->classes;
2096	}
2097	else
2098	{
2099	if (ira_regno_allocno_map[i] == NULL)
2100	continue;
2101	memset (temp_costs, c: 0, n: struct_costs_size);
2102	i_mem_cost = 0;
2103	cost_classes = cost_classes_ptr->classes;
2104	/* Find cost of all allocnos with the same regno. */
2105	for (a = ira_regno_allocno_map[i];
2106	a != NULL;
2107	a = ALLOCNO_NEXT_REGNO_ALLOCNO (a))
2108	{
2109	int *a_costs, *p_costs;
2110
2111	a_num = ALLOCNO_NUM (a);
2112	if ((flag_ira_region == IRA_REGION_ALL
2113	|| flag_ira_region == IRA_REGION_MIXED)
2114	&& (parent = ALLOCNO_LOOP_TREE_NODE (a)->parent) != NULL
2115	&& (parent_a = parent->regno_allocno_map[i]) != NULL
2116	/* There are no caps yet. */
2117	&& bitmap_bit_p (ALLOCNO_LOOP_TREE_NODE
2118	(a)->border_allocnos,
2119	ALLOCNO_NUM (a)))
2120	{
2121	/* Propagate costs to upper levels in the region
2122	tree. */
2123	parent_a_num = ALLOCNO_NUM (parent_a);
2124	a_costs = COSTS (total_allocno_costs, a_num)->cost;
2125	p_costs = COSTS (total_allocno_costs, parent_a_num)->cost;
2126	for (k = cost_classes_ptr->num - 1; k >= 0; k--)
2127	{
2128	add_cost = a_costs[k];
2129	if (add_cost > 0 && INT_MAX - add_cost < p_costs[k])
2130	p_costs[k] = INT_MAX;
2131	else
2132	p_costs[k] += add_cost;
2133	}
2134	add_cost = COSTS (total_allocno_costs, a_num)->mem_cost;
2135	if (add_cost > 0
2136	&& (INT_MAX - add_cost
2137	< COSTS (total_allocno_costs,
2138	parent_a_num)->mem_cost))
2139	COSTS (total_allocno_costs, parent_a_num)->mem_cost
2140	= INT_MAX;
2141	else
2142	COSTS (total_allocno_costs, parent_a_num)->mem_cost
2143	+= add_cost;
2144
2145	if (i >= first_moveable_pseudo && i < last_moveable_pseudo)
2146	COSTS (total_allocno_costs, parent_a_num)->mem_cost = 0;
2147	}
2148	a_costs = COSTS (costs, a_num)->cost;
2149	for (k = cost_classes_ptr->num - 1; k >= 0; k--)
2150	{
2151	add_cost = a_costs[k];
2152	if (add_cost > 0 && INT_MAX - add_cost < i_costs[k])
2153	i_costs[k] = INT_MAX;
2154	else
2155	i_costs[k] += add_cost;
2156	}
2157	add_cost = COSTS (costs, a_num)->mem_cost;
2158	if (add_cost > 0 && INT_MAX - add_cost < i_mem_cost)
2159	i_mem_cost = INT_MAX;
2160	else
2161	i_mem_cost += add_cost;
2162	}
2163	}
2164	if (i >= first_moveable_pseudo && i < last_moveable_pseudo)
2165	i_mem_cost = 0;
2166	else if (ira_use_lra_p)
2167	{
2168	if (equiv_savings > 0)
2169	{
2170	i_mem_cost = 0;
2171	if (ira_dump_file != NULL && internal_flag_ira_verbose > 5)
2172	fprintf (stream: ira_dump_file,
2173	format: " Use MEM for r%d as the equiv savings is %d\n",
2174	i, equiv_savings);
2175	}
2176	}
2177	else if (equiv_savings < 0)
2178	i_mem_cost = -equiv_savings;
2179	else if (equiv_savings > 0)
2180	{
2181	i_mem_cost = 0;
2182	for (k = cost_classes_ptr->num - 1; k >= 0; k--)
2183	i_costs[k] += equiv_savings;
2184	}
2185
2186	best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1;
2187	best = ALL_REGS;
2188	alt_class = NO_REGS;
2189	/* Find best common class for all allocnos with the same
2190	regno. */
2191	for (k = 0; k < cost_classes_ptr->num; k++)
2192	{
2193	rclass = cost_classes[k];
2194	if (i_costs[k] < best_cost)
2195	{
2196	best_cost = i_costs[k];
2197	best = (enum reg_class) rclass;
2198	}
2199	else if (i_costs[k] == best_cost)
2200	best = ira_reg_class_subunion[best][rclass];
2201	if (pass == flag_expensive_optimizations
2202	/* We still prefer registers to memory even at this
2203	stage if their costs are the same. We will make
2204	a final decision during assigning hard registers
2205	when we have all info including more accurate
2206	costs which might be affected by assigning hard
2207	registers to other pseudos because the pseudos
2208	involved in moves can be coalesced. */
2209	&& i_costs[k] <= i_mem_cost
2210	&& (reg_class_size[reg_class_subunion[alt_class][rclass]]
2211	> reg_class_size[alt_class]))
2212	alt_class = reg_class_subunion[alt_class][rclass];
2213	}
2214	alt_class = ira_allocno_class_translate[alt_class];
2215	if (best_cost > i_mem_cost
2216	&& ! non_spilled_static_chain_regno_p (regno: i))
2217	regno_aclass[i] = NO_REGS;
2218	else if (!optimize && !targetm.class_likely_spilled_p (best))
2219	/* Registers in the alternative class are likely to need
2220	longer or slower sequences than registers in the best class.
2221	When optimizing we make some effort to use the best class
2222	over the alternative class where possible, but at -O0 we
2223	effectively give the alternative class equal weight.
2224	We then run the risk of using slower alternative registers
2225	when plenty of registers from the best class are still free.
2226	This is especially true because live ranges tend to be very
2227	short in -O0 code and so register pressure tends to be low.
2228
2229	Avoid that by ignoring the alternative class if the best
2230	class has plenty of registers.
2231
2232	The union class arrays give important classes and only
2233	part of it are allocno classes. So translate them into
2234	allocno classes. */
2235	regno_aclass[i] = ira_allocno_class_translate[best];
2236	else
2237	{
2238	/* Make the common class the biggest class of best and
2239	alt_class. Translate the common class into an
2240	allocno class too. */
2241	regno_aclass[i] = (ira_allocno_class_translate
2242	[ira_reg_class_superunion[best][alt_class]]);
2243	ira_assert (regno_aclass[i] != NO_REGS
2244	&& ira_reg_allocno_class_p[regno_aclass[i]]);
2245	}
2246	if (pic_offset_table_rtx != NULL
2247	&& i == (int) REGNO (pic_offset_table_rtx))
2248	{
2249	/* For some targets, integer pseudos can be assigned to fp
2250	regs. As we don't want reload pic offset table pseudo, we
2251	should avoid using non-integer regs. */
2252	regno_aclass[i]
2253	= ira_reg_class_intersect[regno_aclass[i]][GENERAL_REGS];
2254	alt_class = ira_reg_class_intersect[alt_class][GENERAL_REGS];
2255	}
2256	if ((new_class
2257	= (reg_class) (targetm.ira_change_pseudo_allocno_class
2258	(i, regno_aclass[i], best))) != regno_aclass[i])
2259	{
2260	regno_aclass[i] = new_class;
2261	if (hard_reg_set_subset_p (reg_class_contents[new_class],
2262	reg_class_contents[best]))
2263	best = new_class;
2264	if (hard_reg_set_subset_p (reg_class_contents[new_class],
2265	reg_class_contents[alt_class]))
2266	alt_class = new_class;
2267	}
2268	if (pass == flag_expensive_optimizations)
2269	{
2270	if (best_cost > i_mem_cost
2271	/* Do not assign NO_REGS to static chain pointer
2272	pseudo when non-local goto is used. */
2273	&& ! non_spilled_static_chain_regno_p (regno: i))
2274	best = alt_class = NO_REGS;
2275	else if (best == alt_class)
2276	alt_class = NO_REGS;
2277	setup_reg_classes (i, best, alt_class, regno_aclass[i]);
2278	if ((!allocno_p || internal_flag_ira_verbose > 2)
2279	&& ira_dump_file != NULL)
2280	fprintf (stream: ira_dump_file,
2281	format: " r%d: preferred %s, alternative %s, allocno %s\n",
2282	i, reg_class_names[best], reg_class_names[alt_class],
2283	reg_class_names[regno_aclass[i]]);
2284	}
2285	regno_best_class[i] = best;
2286	if (! allocno_p)
2287	{
2288	pref[i] = (best_cost > i_mem_cost
2289	&& ! non_spilled_static_chain_regno_p (regno: i)
2290	? NO_REGS : best);
2291	continue;
2292	}
2293	for (a = ira_regno_allocno_map[i];
2294	a != NULL;
2295	a = ALLOCNO_NEXT_REGNO_ALLOCNO (a))
2296	{
2297	enum reg_class aclass = regno_aclass[i];
2298	int a_num = ALLOCNO_NUM (a);
2299	int *total_a_costs = COSTS (total_allocno_costs, a_num)->cost;
2300	int *a_costs = COSTS (costs, a_num)->cost;
2301
2302	if (aclass == NO_REGS)
2303	best = NO_REGS;
2304	else
2305	{
2306	/* Finding best class which is subset of the common
2307	class. */
2308	best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1;
2309	allocno_cost = best_cost;
2310	best = ALL_REGS;
2311	for (k = 0; k < cost_classes_ptr->num; k++)
2312	{
2313	rclass = cost_classes[k];
2314	if (! ira_class_subset_p[rclass][aclass])
2315	continue;
2316	if (total_a_costs[k] < best_cost)
2317	{
2318	best_cost = total_a_costs[k];
2319	allocno_cost = a_costs[k];
2320	best = (enum reg_class) rclass;
2321	}
2322	else if (total_a_costs[k] == best_cost)
2323	{
2324	best = ira_reg_class_subunion[best][rclass];
2325	allocno_cost = MAX (allocno_cost, a_costs[k]);
2326	}
2327	}
2328	ALLOCNO_CLASS_COST (a) = allocno_cost;
2329	}
2330	if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL
2331	&& (pass == 0 || pref[a_num] != best))
2332	{
2333	fprintf (stream: ira_dump_file, format: " a%d (r%d,", a_num, i);
2334	if ((bb = ALLOCNO_LOOP_TREE_NODE (a)->bb) != NULL)
2335	fprintf (stream: ira_dump_file, format: "b%d", bb->index);
2336	else
2337	fprintf (stream: ira_dump_file, format: "l%d",
2338	ALLOCNO_LOOP_TREE_NODE (a)->loop_num);
2339	fprintf (stream: ira_dump_file, format: ") best %s, allocno %s\n",
2340	reg_class_names[best],
2341	reg_class_names[aclass]);
2342	}
2343	pref[a_num] = best;
2344	if (pass == flag_expensive_optimizations && best != aclass
2345	&& ira_class_hard_regs_num[best] > 0
2346	&& (ira_reg_class_max_nregs[best][ALLOCNO_MODE (a)]
2347	>= ira_class_hard_regs_num[best]))
2348	{
2349	int ind = cost_classes_ptr->index[aclass];
2350
2351	ira_assert (ind >= 0);
2352	ira_init_register_move_cost_if_necessary (ALLOCNO_MODE (a));
2353	ira_add_allocno_pref (a, ira_class_hard_regs[best][0],
2354	(a_costs[ind] - ALLOCNO_CLASS_COST (a))
2355	/ (ira_register_move_cost
2356	[ALLOCNO_MODE (a)][best][aclass]));
2357	for (k = 0; k < cost_classes_ptr->num; k++)
2358	if (ira_class_subset_p[cost_classes[k]][best])
2359	a_costs[k] = a_costs[ind];
2360	}
2361	}
2362	}
2363
2364	if (internal_flag_ira_verbose > 4 && ira_dump_file)
2365	{
2366	if (allocno_p)
2367	print_allocno_costs ();
2368	else
2369	print_pseudo_costs ();
2370	fprintf (stream: ira_dump_file,format: "\n");
2371	}
2372	}
2373	ira_free (addr: regno_best_class);
2374	}
2375
2376
2377
2378	/* Process moves involving hard regs to modify allocno hard register
2379	costs. We can do this only after determining allocno class. If a
2380	hard register forms a register class, then moves with the hard
2381	register are already taken into account in class costs for the
2382	allocno. */
2383	static void
2384	process_bb_node_for_hard_reg_moves (ira_loop_tree_node_t loop_tree_node)
2385	{
2386	int i, freq, src_regno, dst_regno, hard_regno, a_regno;
2387	bool to_p;
2388	ira_allocno_t a, curr_a;
2389	ira_loop_tree_node_t curr_loop_tree_node;
2390	enum reg_class rclass;
2391	basic_block bb;
2392	rtx_insn *insn;
2393	rtx set, src, dst;
2394
2395	bb = loop_tree_node->bb;
2396	if (bb == NULL)
2397	return;
2398	freq = REG_FREQ_FROM_BB (bb);
2399	if (freq == 0)
2400	freq = 1;
2401	FOR_BB_INSNS (bb, insn)
2402	{
2403	if (!NONDEBUG_INSN_P (insn))
2404	continue;
2405	set = single_set (insn);
2406	if (set == NULL_RTX)
2407	continue;
2408	dst = SET_DEST (set);
2409	src = SET_SRC (set);
2410	if (! REG_P (dst) || ! REG_P (src))
2411	continue;
2412	dst_regno = REGNO (dst);
2413	src_regno = REGNO (src);
2414	if (dst_regno >= FIRST_PSEUDO_REGISTER
2415	&& src_regno < FIRST_PSEUDO_REGISTER)
2416	{
2417	hard_regno = src_regno;
2418	a = ira_curr_regno_allocno_map[dst_regno];
2419	to_p = true;
2420	}
2421	else if (src_regno >= FIRST_PSEUDO_REGISTER
2422	&& dst_regno < FIRST_PSEUDO_REGISTER)
2423	{
2424	hard_regno = dst_regno;
2425	a = ira_curr_regno_allocno_map[src_regno];
2426	to_p = false;
2427	}
2428	else
2429	continue;
2430	if (reg_class_size[(int) REGNO_REG_CLASS (hard_regno)]
2431	== (ira_reg_class_max_nregs
2432	[REGNO_REG_CLASS (hard_regno)][(int) ALLOCNO_MODE(a)]))
2433	/* If the class can provide only one hard reg to the allocno,
2434	we processed the insn record_operand_costs already and we
2435	actually updated the hard reg cost there. */
2436	continue;
2437	rclass = ALLOCNO_CLASS (a);
2438	if (! TEST_HARD_REG_BIT (reg_class_contents[rclass], bit: hard_regno))
2439	continue;
2440	i = ira_class_hard_reg_index[rclass][hard_regno];
2441	if (i < 0)
2442	continue;
2443	a_regno = ALLOCNO_REGNO (a);
2444	for (curr_loop_tree_node = ALLOCNO_LOOP_TREE_NODE (a);
2445	curr_loop_tree_node != NULL;
2446	curr_loop_tree_node = curr_loop_tree_node->parent)
2447	if ((curr_a = curr_loop_tree_node->regno_allocno_map[a_regno]) != NULL)
2448	ira_add_allocno_pref (curr_a, hard_regno, freq);
2449	{
2450	int cost;
2451	enum reg_class hard_reg_class;
2452	machine_mode mode;
2453
2454	mode = ALLOCNO_MODE (a);
2455	hard_reg_class = REGNO_REG_CLASS (hard_regno);
2456	ira_init_register_move_cost_if_necessary (mode);
2457	cost = (to_p ? ira_register_move_cost[mode][hard_reg_class][rclass]
2458	: ira_register_move_cost[mode][rclass][hard_reg_class]) * freq;
2459	ira_allocate_and_set_costs (vec: &ALLOCNO_HARD_REG_COSTS (a), aclass: rclass,
2460	ALLOCNO_CLASS_COST (a));
2461	ira_allocate_and_set_costs (vec: &ALLOCNO_CONFLICT_HARD_REG_COSTS (a),
2462	aclass: rclass, val: 0);
2463	ALLOCNO_HARD_REG_COSTS (a)[i] -= cost;
2464	ALLOCNO_CONFLICT_HARD_REG_COSTS (a)[i] -= cost;
2465	ALLOCNO_CLASS_COST (a) = MIN (ALLOCNO_CLASS_COST (a),
2466	ALLOCNO_HARD_REG_COSTS (a)[i]);
2467	}
2468	}
2469	}
2470
2471	/* After we find hard register and memory costs for allocnos, define
2472	its class and modify hard register cost because insns moving
2473	allocno to/from hard registers. */
2474	static void
2475	setup_allocno_class_and_costs (void)
2476	{
2477	int i, j, n, regno, hard_regno, num;
2478	int *reg_costs;
2479	enum reg_class aclass, rclass;
2480	ira_allocno_t a;
2481	ira_allocno_iterator ai;
2482	cost_classes_t cost_classes_ptr;
2483
2484	ira_assert (allocno_p);
2485	FOR_EACH_ALLOCNO (a, ai)
2486	{
2487	i = ALLOCNO_NUM (a);
2488	regno = ALLOCNO_REGNO (a);
2489	aclass = regno_aclass[regno];
2490	cost_classes_ptr = regno_cost_classes[regno];
2491	ira_assert (pref[i] == NO_REGS || aclass != NO_REGS);
2492	ALLOCNO_MEMORY_COST (a) = COSTS (costs, i)->mem_cost;
2493	ira_set_allocno_class (a, aclass);
2494	if (aclass == NO_REGS)
2495	continue;
2496	if (optimize && ALLOCNO_CLASS (a) != pref[i])
2497	{
2498	n = ira_class_hard_regs_num[aclass];
2499	ALLOCNO_HARD_REG_COSTS (a)
2500	= reg_costs = ira_allocate_cost_vector (aclass);
2501	for (j = n - 1; j >= 0; j--)
2502	{
2503	hard_regno = ira_class_hard_regs[aclass][j];
2504	if (TEST_HARD_REG_BIT (reg_class_contents[pref[i]], bit: hard_regno))
2505	reg_costs[j] = ALLOCNO_CLASS_COST (a);
2506	else
2507	{
2508	rclass = REGNO_REG_CLASS (hard_regno);
2509	num = cost_classes_ptr->index[rclass];
2510	if (num < 0)
2511	{
2512	num = cost_classes_ptr->hard_regno_index[hard_regno];
2513	ira_assert (num >= 0);
2514	}
2515	reg_costs[j] = COSTS (costs, i)->cost[num];
2516	}
2517	}
2518	}
2519	}
2520	if (optimize)
2521	ira_traverse_loop_tree (true, ira_loop_tree_root,
2522	process_bb_node_for_hard_reg_moves, NULL);
2523	}
2524
2525
2526
2527	/* Function called once during compiler work. */
2528	void
2529	ira_init_costs_once (void)
2530	{
2531	int i;
2532
2533	init_cost = NULL;
2534	for (i = 0; i < MAX_RECOG_OPERANDS; i++)
2535	{
2536	op_costs[i] = NULL;
2537	this_op_costs[i] = NULL;
2538	}
2539	temp_costs = NULL;
2540	}
2541
2542	/* Free allocated temporary cost vectors. */
2543	void
2544	target_ira_int::free_ira_costs ()
2545	{
2546	int i;
2547
2548	free (ptr: x_init_cost);
2549	x_init_cost = NULL;
2550	for (i = 0; i < MAX_RECOG_OPERANDS; i++)
2551	{
2552	free (ptr: x_op_costs[i]);
2553	free (ptr: x_this_op_costs[i]);
2554	x_op_costs[i] = x_this_op_costs[i] = NULL;
2555	}
2556	free (ptr: x_temp_costs);
2557	x_temp_costs = NULL;
2558	}
2559
2560	/* This is called each time register related information is
2561	changed. */
2562	void
2563	ira_init_costs (void)
2564	{
2565	int i;
2566
2567	this_target_ira_int->free_ira_costs ();
2568	max_struct_costs_size
2569	= sizeof (struct costs) + sizeof (int) * (ira_important_classes_num - 1);
2570	/* Don't use ira_allocate because vectors live through several IRA
2571	calls. */
2572	init_cost = (struct costs *) xmalloc (max_struct_costs_size);
2573	init_cost->mem_cost = 1000000;
2574	for (i = 0; i < ira_important_classes_num; i++)
2575	init_cost->cost[i] = 1000000;
2576	for (i = 0; i < MAX_RECOG_OPERANDS; i++)
2577	{
2578	op_costs[i] = (struct costs *) xmalloc (max_struct_costs_size);
2579	this_op_costs[i] = (struct costs *) xmalloc (max_struct_costs_size);
2580	}
2581	temp_costs = (struct costs *) xmalloc (max_struct_costs_size);
2582	}
2583
2584
2585
2586	/* Common initialization function for ira_costs and
2587	ira_set_pseudo_classes. */
2588	static void
2589	init_costs (void)
2590	{
2591	init_subregs_of_mode ();
2592	costs = (struct costs *) ira_allocate (max_struct_costs_size
2593	* cost_elements_num);
2594	pref_buffer = (enum reg_class *) ira_allocate (sizeof (enum reg_class)
2595	* cost_elements_num);
2596	regno_aclass = (enum reg_class *) ira_allocate (sizeof (enum reg_class)
2597	* max_reg_num ());
2598	regno_equiv_gains = (int *) ira_allocate (sizeof (int) * max_reg_num ());
2599	memset (s: regno_equiv_gains, c: 0, n: sizeof (int) * max_reg_num ());
2600	}
2601
2602	/* Common finalization function for ira_costs and
2603	ira_set_pseudo_classes. */
2604	static void
2605	finish_costs (void)
2606	{
2607	finish_subregs_of_mode ();
2608	ira_free (addr: regno_equiv_gains);
2609	ira_free (addr: regno_aclass);
2610	ira_free (addr: pref_buffer);
2611	ira_free (addr: costs);
2612	}
2613
2614	/* Entry function which defines register class, memory and hard
2615	register costs for each allocno. */
2616	void
2617	ira_costs (void)
2618	{
2619	allocno_p = true;
2620	cost_elements_num = ira_allocnos_num;
2621	init_costs ();
2622	total_allocno_costs = (struct costs *) ira_allocate (max_struct_costs_size
2623	* ira_allocnos_num);
2624	initiate_regno_cost_classes ();
2625	if (!ira_use_lra_p)
2626	/* Process equivs in reload to update costs through hook
2627	ira_adjust_equiv_reg_cost. */
2628	calculate_elim_costs_all_insns ();
2629	find_costs_and_classes ();
2630	setup_allocno_class_and_costs ();
2631	finish_regno_cost_classes ();
2632	finish_costs ();
2633	ira_free (addr: total_allocno_costs);
2634	}
2635
2636	/* Entry function which defines classes for pseudos.
2637	Set pseudo_classes_defined_p only if DEFINE_PSEUDO_CLASSES is true. */
2638	void
2639	ira_set_pseudo_classes (bool define_pseudo_classes, FILE *dump_file)
2640	{
2641	FILE *saved_file = ira_dump_file;
2642	allocno_p = false;
2643	internal_flag_ira_verbose = flag_ira_verbose;
2644	ira_dump_file = dump_file;
2645	cost_elements_num = max_reg_num ();
2646	init_costs ();
2647	initiate_regno_cost_classes ();
2648	find_costs_and_classes ();
2649	finish_regno_cost_classes ();
2650	if (define_pseudo_classes)
2651	pseudo_classes_defined_p = true;
2652
2653	finish_costs ();
2654	ira_dump_file = saved_file;
2655	}
2656
2657
2658
2659	/* Change hard register costs for allocnos which lives through
2660	function calls. This is called only when we found all intersected
2661	calls during building allocno live ranges. */
2662	void
2663	ira_tune_allocno_costs (void)
2664	{
2665	int j, n, regno;
2666	int cost, min_cost, *reg_costs;
2667	enum reg_class aclass;
2668	machine_mode mode;
2669	ira_allocno_t a;
2670	ira_allocno_iterator ai;
2671	ira_allocno_object_iterator oi;
2672	ira_object_t obj;
2673	bool skip_p;
2674
2675	FOR_EACH_ALLOCNO (a, ai)
2676	{
2677	aclass = ALLOCNO_CLASS (a);
2678	if (aclass == NO_REGS)
2679	continue;
2680	mode = ALLOCNO_MODE (a);
2681	n = ira_class_hard_regs_num[aclass];
2682	min_cost = INT_MAX;
2683	if (ALLOCNO_CALLS_CROSSED_NUM (a)
2684	!= ALLOCNO_CHEAP_CALLS_CROSSED_NUM (a))
2685	{
2686	ira_allocate_and_set_costs
2687	(vec: &ALLOCNO_HARD_REG_COSTS (a), aclass,
2688	ALLOCNO_CLASS_COST (a));
2689	reg_costs = ALLOCNO_HARD_REG_COSTS (a);
2690	for (j = n - 1; j >= 0; j--)
2691	{
2692	regno = ira_class_hard_regs[aclass][j];
2693	skip_p = false;
2694	FOR_EACH_ALLOCNO_OBJECT (a, obj, oi)
2695	{
2696	if (ira_hard_reg_set_intersection_p (hard_regno: regno, mode,
2697	OBJECT_CONFLICT_HARD_REGS
2698	(obj)))
2699	{
2700	skip_p = true;
2701	break;
2702	}
2703	}
2704	if (skip_p)
2705	continue;
2706	cost = 0;
2707	if (ira_need_caller_save_p (a, regno))
2708	cost += ira_caller_save_cost (a);
2709	#ifdef IRA_HARD_REGNO_ADD_COST_MULTIPLIER
2710	{
2711	auto rclass = REGNO_REG_CLASS (regno);
2712	cost += ((ira_memory_move_cost[mode][rclass][0]
2713	+ ira_memory_move_cost[mode][rclass][1])
2714	* ALLOCNO_FREQ (a)
2715	* IRA_HARD_REGNO_ADD_COST_MULTIPLIER (regno) / 2);
2716	}
2717	#endif
2718	if (INT_MAX - cost < reg_costs[j])
2719	reg_costs[j] = INT_MAX;
2720	else
2721	reg_costs[j] += cost;
2722	if (min_cost > reg_costs[j])
2723	min_cost = reg_costs[j];
2724	}
2725	}
2726	if (min_cost != INT_MAX)
2727	ALLOCNO_CLASS_COST (a) = min_cost;
2728
2729	/* Some targets allow pseudos to be allocated to unaligned sequences
2730	of hard registers. However, selecting an unaligned sequence can
2731	unnecessarily restrict later allocations. So increase the cost of
2732	unaligned hard regs to encourage the use of aligned hard regs. */
2733	{
2734	const int nregs = ira_reg_class_max_nregs[aclass][ALLOCNO_MODE (a)];
2735
2736	if (nregs > 1)
2737	{
2738	ira_allocate_and_set_costs
2739	(vec: &ALLOCNO_HARD_REG_COSTS (a), aclass, ALLOCNO_CLASS_COST (a));
2740	reg_costs = ALLOCNO_HARD_REG_COSTS (a);
2741	for (j = n - 1; j >= 0; j--)
2742	{
2743	regno = ira_non_ordered_class_hard_regs[aclass][j];
2744	if ((regno % nregs) != 0)
2745	{
2746	int index = ira_class_hard_reg_index[aclass][regno];
2747	ira_assert (index != -1);
2748	reg_costs[index] += ALLOCNO_FREQ (a);
2749	}
2750	}
2751	}
2752	}
2753	}
2754	}
2755
2756	/* A hook from the reload pass. Add COST to the estimated gain for eliminating
2757	REGNO with its equivalence. If COST is zero, record that no such
2758	elimination is possible. */
2759
2760	void
2761	ira_adjust_equiv_reg_cost (unsigned regno, int cost)
2762	{
2763	ira_assert (!ira_use_lra_p);
2764	if (cost == 0)
2765	regno_equiv_gains[regno] = 0;
2766	else
2767	regno_equiv_gains[regno] += cost;
2768	}
2769
2770	void
2771	ira_costs_cc_finalize (void)
2772	{
2773	this_target_ira_int->free_ira_costs ();
2774	}
2775