1	// SPDX-License-Identifier: GPL-2.0-or-later
2	/*
3	* PowerPC64 port by Mike Corrigan and Dave Engebretsen
4	* {mikejc|engebret}@us.ibm.com
5	*
6	* Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
7	*
8	* SMP scalability work:
9	* Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
10	*
11	* Module name: htab.c
12	*
13	* Description:
14	* PowerPC Hashed Page Table functions
15	*/
16
17	#undef DEBUG
18	#undef DEBUG_LOW
19
20	#define pr_fmt(fmt) "hash-mmu: " fmt
21	#include <linux/spinlock.h>
22	#include <linux/errno.h>
23	#include <linux/sched/mm.h>
24	#include <linux/proc_fs.h>
25	#include <linux/stat.h>
26	#include <linux/sysctl.h>
27	#include <linux/export.h>
28	#include <linux/ctype.h>
29	#include <linux/cache.h>
30	#include <linux/init.h>
31	#include <linux/signal.h>
32	#include <linux/memblock.h>
33	#include <linux/context_tracking.h>
34	#include <linux/libfdt.h>
35	#include <linux/pkeys.h>
36	#include <linux/hugetlb.h>
37	#include <linux/cpu.h>
38	#include <linux/pgtable.h>
39	#include <linux/debugfs.h>
40	#include <linux/random.h>
41	#include <linux/elf-randomize.h>
42	#include <linux/of_fdt.h>
43	#include <linux/kfence.h>
44
45	#include <asm/interrupt.h>
46	#include <asm/processor.h>
47	#include <asm/mmu.h>
48	#include <asm/mmu_context.h>
49	#include <asm/page.h>
50	#include <asm/pgalloc.h>
51	#include <asm/types.h>
52	#include <linux/uaccess.h>
53	#include <asm/machdep.h>
54	#include <asm/io.h>
55	#include <asm/eeh.h>
56	#include <asm/tlb.h>
57	#include <asm/cacheflush.h>
58	#include <asm/cputable.h>
59	#include <asm/sections.h>
60	#include <asm/spu.h>
61	#include <asm/udbg.h>
62	#include <asm/text-patching.h>
63	#include <asm/fadump.h>
64	#include <asm/firmware.h>
65	#include <asm/tm.h>
66	#include <asm/trace.h>
67	#include <asm/ps3.h>
68	#include <asm/pte-walk.h>
69	#include <asm/asm-prototypes.h>
70	#include <asm/ultravisor.h>
71	#include <asm/kfence.h>
72
73	#include <mm/mmu_decl.h>
74
75	#include "internal.h"
76
77
78	#ifdef DEBUG
79	#define DBG(fmt...) udbg_printf(fmt)
80	#else
81	#define DBG(fmt...)
82	#endif
83
84	#ifdef DEBUG_LOW
85	#define DBG_LOW(fmt...) udbg_printf(fmt)
86	#else
87	#define DBG_LOW(fmt...)
88	#endif
89
90	#define KB (1024)
91	#define MB (1024*KB)
92	#define GB (1024L*MB)
93
94	/*
95	* Note: pte --> Linux PTE
96	* HPTE --> PowerPC Hashed Page Table Entry
97	*
98	* Execution context:
99	* htab_initialize is called with the MMU off (of course), but
100	* the kernel has been copied down to zero so it can directly
101	* reference global data. At this point it is very difficult
102	* to print debug info.
103	*
104	*/
105
106	static unsigned long _SDR1;
107
108	u8 hpte_page_sizes[1 << LP_BITS];
109	EXPORT_SYMBOL_GPL(hpte_page_sizes);
110
111	struct hash_pte *htab_address;
112	unsigned long htab_size_bytes;
113	unsigned long htab_hash_mask;
114	EXPORT_SYMBOL_GPL(htab_hash_mask);
115	int mmu_linear_psize = MMU_PAGE_4K;
116	EXPORT_SYMBOL_GPL(mmu_linear_psize);
117	int mmu_virtual_psize = MMU_PAGE_4K;
118	int mmu_vmalloc_psize = MMU_PAGE_4K;
119	EXPORT_SYMBOL_GPL(mmu_vmalloc_psize);
120	int mmu_io_psize = MMU_PAGE_4K;
121	int mmu_kernel_ssize = MMU_SEGSIZE_256M;
122	EXPORT_SYMBOL_GPL(mmu_kernel_ssize);
123	int mmu_highuser_ssize = MMU_SEGSIZE_256M;
124	u16 mmu_slb_size = 64;
125	EXPORT_SYMBOL_GPL(mmu_slb_size);
126	#ifdef CONFIG_PPC_64K_PAGES
127	int mmu_ci_restrictions;
128	#endif
129	struct mmu_hash_ops mmu_hash_ops __ro_after_init;
130	EXPORT_SYMBOL(mmu_hash_ops);
131
132	/*
133	* These are definitions of page sizes arrays to be used when none
134	* is provided by the firmware.
135	*/
136
137	/*
138	* Fallback (4k pages only)
139	*/
140	static struct mmu_psize_def mmu_psize_defaults[] = {
141	[MMU_PAGE_4K] = {
142	.shift = 12,
143	.sllp = 0,
144	.penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1},
145	.avpnm = 0,
146	.tlbiel = 0,
147	},
148	};
149
150	/*
151	* POWER4, GPUL, POWER5
152	*
153	* Support for 16Mb large pages
154	*/
155	static struct mmu_psize_def mmu_psize_defaults_gp[] = {
156	[MMU_PAGE_4K] = {
157	.shift = 12,
158	.sllp = 0,
159	.penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1},
160	.avpnm = 0,
161	.tlbiel = 1,
162	},
163	[MMU_PAGE_16M] = {
164	.shift = 24,
165	.sllp = SLB_VSID_L,
166	.penc = {[0 ... MMU_PAGE_16M - 1] = -1, [MMU_PAGE_16M] = 0,
167	[MMU_PAGE_16M + 1 ... MMU_PAGE_COUNT - 1] = -1 },
168	.avpnm = 0x1UL,
169	.tlbiel = 0,
170	},
171	};
172
173	static inline void tlbiel_hash_set_isa206(unsigned int set, unsigned int is)
174	{
175	unsigned long rb;
176
177	rb = (set << PPC_BITLSHIFT(51)) | (is << PPC_BITLSHIFT(53));
178
179	asm volatile("tlbiel %0" : : "r" (rb));
180	}
181
182	/*
183	* tlbiel instruction for hash, set invalidation
184	* i.e., r=1 and is=01 or is=10 or is=11
185	*/
186	static __always_inline void tlbiel_hash_set_isa300(unsigned int set, unsigned int is,
187	unsigned int pid,
188	unsigned int ric, unsigned int prs)
189	{
190	unsigned long rb;
191	unsigned long rs;
192	unsigned int r = 0; /* hash format */
193
194	rb = (set << PPC_BITLSHIFT(51)) | (is << PPC_BITLSHIFT(53));
195	rs = ((unsigned long)pid << PPC_BITLSHIFT(31));
196
197	asm volatile(PPC_TLBIEL(%0, %1, %2, %3, %4)
198	: : "r"(rb), "r"(rs), "i"(ric), "i"(prs), "i"(r)
199	: "memory");
200	}
201
202
203	static void tlbiel_all_isa206(unsigned int num_sets, unsigned int is)
204	{
205	unsigned int set;
206
207	asm volatile("ptesync": : :"memory");
208
209	for (set = 0; set < num_sets; set++)
210	tlbiel_hash_set_isa206(set, is);
211
212	ppc_after_tlbiel_barrier();
213	}
214
215	static void tlbiel_all_isa300(unsigned int num_sets, unsigned int is)
216	{
217	unsigned int set;
218
219	asm volatile("ptesync": : :"memory");
220
221	/*
222	* Flush the partition table cache if this is HV mode.
223	*/
224	if (early_cpu_has_feature(CPU_FTR_HVMODE))
225	tlbiel_hash_set_isa300(set: 0, is, pid: 0, ric: 2, prs: 0);
226
227	/*
228	* Now invalidate the process table cache. UPRT=0 HPT modes (what
229	* current hardware implements) do not use the process table, but
230	* add the flushes anyway.
231	*
232	* From ISA v3.0B p. 1078:
233	* The following forms are invalid.
234	* * PRS=1, R=0, and RIC!=2 (The only process-scoped
235	* HPT caching is of the Process Table.)
236	*/
237	tlbiel_hash_set_isa300(set: 0, is, pid: 0, ric: 2, prs: 1);
238
239	/*
240	* Then flush the sets of the TLB proper. Hash mode uses
241	* partition scoped TLB translations, which may be flushed
242	* in !HV mode.
243	*/
244	for (set = 0; set < num_sets; set++)
245	tlbiel_hash_set_isa300(set, is, pid: 0, ric: 0, prs: 0);
246
247	ppc_after_tlbiel_barrier();
248
249	asm volatile(PPC_ISA_3_0_INVALIDATE_ERAT "; isync" : : :"memory");
250	}
251
252	void hash__tlbiel_all(unsigned int action)
253	{
254	unsigned int is;
255
256	switch (action) {
257	case TLB_INVAL_SCOPE_GLOBAL:
258	is = 3;
259	break;
260	case TLB_INVAL_SCOPE_LPID:
261	is = 2;
262	break;
263	default:
264	BUG();
265	}
266
267	if (early_cpu_has_feature(CPU_FTR_ARCH_300))
268	tlbiel_all_isa300(num_sets: POWER9_TLB_SETS_HASH, is);
269	else if (early_cpu_has_feature(CPU_FTR_ARCH_207S))
270	tlbiel_all_isa206(num_sets: POWER8_TLB_SETS, is);
271	else if (early_cpu_has_feature(CPU_FTR_ARCH_206))
272	tlbiel_all_isa206(num_sets: POWER7_TLB_SETS, is);
273	else
274	WARN(1, "%s called on pre-POWER7 CPU\n", __func__);
275	}
276
277	#if defined(CONFIG_DEBUG_PAGEALLOC) || defined(CONFIG_KFENCE)
278	static void kernel_map_linear_page(unsigned long vaddr, unsigned long idx,
279	u8 *slots, raw_spinlock_t *lock)
280	{
281	unsigned long hash;
282	unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
283	unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
284	unsigned long mode = htab_convert_pte_flags(pgprot_val(PAGE_KERNEL), HPTE_USE_KERNEL_KEY);
285	long ret;
286
287	hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize);
288
289	/* Don't create HPTE entries for bad address */
290	if (!vsid)
291	return;
292
293	if (slots[idx] & 0x80)
294	return;
295
296	ret = hpte_insert_repeating(hash, vpn, __pa(vaddr), mode,
297	HPTE_V_BOLTED,
298	mmu_linear_psize, mmu_kernel_ssize);
299
300	BUG_ON (ret < 0);
301	raw_spin_lock(lock);
302	BUG_ON(slots[idx] & 0x80);
303	slots[idx] = ret | 0x80;
304	raw_spin_unlock(lock);
305	}
306
307	static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long idx,
308	u8 *slots, raw_spinlock_t *lock)
309	{
310	unsigned long hash, hslot, slot;
311	unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
312	unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
313
314	hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize);
315	raw_spin_lock(lock);
316	if (!(slots[idx] & 0x80)) {
317	raw_spin_unlock(lock);
318	return;
319	}
320	hslot = slots[idx] & 0x7f;
321	slots[idx] = 0;
322	raw_spin_unlock(lock);
323	if (hslot & _PTEIDX_SECONDARY)
324	hash = ~hash;
325	slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
326	slot += hslot & _PTEIDX_GROUP_IX;
327	mmu_hash_ops.hpte_invalidate(slot, vpn, mmu_linear_psize,
328	mmu_linear_psize,
329	mmu_kernel_ssize, 0);
330	}
331	#endif
332
333	static inline bool hash_supports_debug_pagealloc(void)
334	{
335	unsigned long max_hash_count = ppc64_rma_size / 4;
336	unsigned long linear_map_count = memblock_end_of_DRAM() >> PAGE_SHIFT;
337
338	if (!debug_pagealloc_enabled() || linear_map_count > max_hash_count)
339	return false;
340	return true;
341	}
342
343	#ifdef CONFIG_DEBUG_PAGEALLOC
344	static u8 *linear_map_hash_slots;
345	static unsigned long linear_map_hash_count;
346	static DEFINE_RAW_SPINLOCK(linear_map_hash_lock);
347	static __init void hash_debug_pagealloc_alloc_slots(void)
348	{
349	if (!hash_supports_debug_pagealloc())
350	return;
351
352	linear_map_hash_count = memblock_end_of_DRAM() >> PAGE_SHIFT;
353	linear_map_hash_slots = memblock_alloc_try_nid(
354	size: linear_map_hash_count, align: 1, MEMBLOCK_LOW_LIMIT,
355	max_addr: ppc64_rma_size, NUMA_NO_NODE);
356	if (!linear_map_hash_slots)
357	panic(fmt: "%s: Failed to allocate %lu bytes max_addr=%pa\n",
358	__func__, linear_map_hash_count, &ppc64_rma_size);
359	}
360
361	static inline void hash_debug_pagealloc_add_slot(phys_addr_t paddr,
362	int slot)
363	{
364	if (!debug_pagealloc_enabled() || !linear_map_hash_count)
365	return;
366	if ((paddr >> PAGE_SHIFT) < linear_map_hash_count)
367	linear_map_hash_slots[paddr >> PAGE_SHIFT] = slot | 0x80;
368	}
369
370	static int hash_debug_pagealloc_map_pages(struct page *page, int numpages,
371	int enable)
372	{
373	unsigned long flags, vaddr, lmi;
374	int i;
375
376	if (!debug_pagealloc_enabled() || !linear_map_hash_count)
377	return 0;
378
379	local_irq_save(flags);
380	for (i = 0; i < numpages; i++, page++) {
381	vaddr = (unsigned long)page_address(page);
382	lmi = __pa(vaddr) >> PAGE_SHIFT;
383	if (lmi >= linear_map_hash_count)
384	continue;
385	if (enable)
386	kernel_map_linear_page(vaddr, idx: lmi,
387	slots: linear_map_hash_slots, lock: &linear_map_hash_lock);
388	else
389	kernel_unmap_linear_page(vaddr, idx: lmi,
390	slots: linear_map_hash_slots, lock: &linear_map_hash_lock);
391	}
392	local_irq_restore(flags);
393	return 0;
394	}
395
396	#else /* CONFIG_DEBUG_PAGEALLOC */
397	static inline void hash_debug_pagealloc_alloc_slots(void) {}
398	static inline void hash_debug_pagealloc_add_slot(phys_addr_t paddr, int slot) {}
399	static int __maybe_unused
400	hash_debug_pagealloc_map_pages(struct page *page, int numpages, int enable)
401	{
402	return 0;
403	}
404	#endif /* CONFIG_DEBUG_PAGEALLOC */
405
406	#ifdef CONFIG_KFENCE
407	static u8 *linear_map_kf_hash_slots;
408	static unsigned long linear_map_kf_hash_count;
409	static DEFINE_RAW_SPINLOCK(linear_map_kf_hash_lock);
410
411	static phys_addr_t kfence_pool;
412
413	static __init void hash_kfence_alloc_pool(void)
414	{
415	if (!kfence_early_init_enabled())
416	goto err;
417
418	/* allocate linear map for kfence within RMA region */
419	linear_map_kf_hash_count = KFENCE_POOL_SIZE >> PAGE_SHIFT;
420	linear_map_kf_hash_slots = memblock_alloc_try_nid(
421	size: linear_map_kf_hash_count, align: 1,
422	MEMBLOCK_LOW_LIMIT, max_addr: ppc64_rma_size,
423	NUMA_NO_NODE);
424	if (!linear_map_kf_hash_slots) {
425	pr_err("%s: memblock for linear map (%lu) failed\n", __func__,
426	linear_map_kf_hash_count);
427	goto err;
428	}
429
430	/* allocate kfence pool early */
431	kfence_pool = memblock_phys_alloc_range(KFENCE_POOL_SIZE, PAGE_SIZE,
432	MEMBLOCK_LOW_LIMIT, MEMBLOCK_ALLOC_ANYWHERE);
433	if (!kfence_pool) {
434	pr_err("%s: memblock for kfence pool (%lu) failed\n", __func__,
435	KFENCE_POOL_SIZE);
436	memblock_free(ptr: linear_map_kf_hash_slots,
437	size: linear_map_kf_hash_count);
438	linear_map_kf_hash_count = 0;
439	goto err;
440	}
441	memblock_mark_nomap(base: kfence_pool, KFENCE_POOL_SIZE);
442
443	return;
444	err:
445	pr_info("Disabling kfence\n");
446	disable_kfence();
447	}
448
449	static __init void hash_kfence_map_pool(void)
450	{
451	unsigned long kfence_pool_start, kfence_pool_end;
452	unsigned long prot = pgprot_val(PAGE_KERNEL);
453	unsigned int pshift = mmu_psize_defs[mmu_linear_psize].shift;
454
455	if (!kfence_pool)
456	return;
457
458	kfence_pool_start = (unsigned long) __va(kfence_pool);
459	kfence_pool_end = kfence_pool_start + KFENCE_POOL_SIZE;
460	__kfence_pool = (char *) kfence_pool_start;
461	BUG_ON(htab_bolt_mapping(kfence_pool_start, kfence_pool_end,
462	kfence_pool, prot, mmu_linear_psize,
463	mmu_kernel_ssize));
464	update_page_count(level: mmu_linear_psize, KFENCE_POOL_SIZE >> pshift);
465	memblock_clear_nomap(base: kfence_pool, KFENCE_POOL_SIZE);
466	}
467
468	static inline void hash_kfence_add_slot(phys_addr_t paddr, int slot)
469	{
470	unsigned long vaddr = (unsigned long) __va(paddr);
471	unsigned long lmi = (vaddr - (unsigned long)__kfence_pool)
472	>> PAGE_SHIFT;
473
474	if (!kfence_pool)
475	return;
476	BUG_ON(!is_kfence_address((void *)vaddr));
477	BUG_ON(lmi >= linear_map_kf_hash_count);
478	linear_map_kf_hash_slots[lmi] = slot | 0x80;
479	}
480
481	static int hash_kfence_map_pages(struct page *page, int numpages, int enable)
482	{
483	unsigned long flags, vaddr, lmi;
484	int i;
485
486	WARN_ON_ONCE(!linear_map_kf_hash_count);
487	local_irq_save(flags);
488	for (i = 0; i < numpages; i++, page++) {
489	vaddr = (unsigned long)page_address(page);
490	lmi = (vaddr - (unsigned long)__kfence_pool) >> PAGE_SHIFT;
491
492	/* Ideally this should never happen */
493	if (lmi >= linear_map_kf_hash_count) {
494	WARN_ON_ONCE(1);
495	continue;
496	}
497
498	if (enable)
499	kernel_map_linear_page(vaddr, idx: lmi,
500	slots: linear_map_kf_hash_slots,
501	lock: &linear_map_kf_hash_lock);
502	else
503	kernel_unmap_linear_page(vaddr, idx: lmi,
504	slots: linear_map_kf_hash_slots,
505	lock: &linear_map_kf_hash_lock);
506	}
507	local_irq_restore(flags);
508	return 0;
509	}
510	#else
511	static inline void hash_kfence_alloc_pool(void) {}
512	static inline void hash_kfence_map_pool(void) {}
513	static inline void hash_kfence_add_slot(phys_addr_t paddr, int slot) {}
514	static int __maybe_unused
515	hash_kfence_map_pages(struct page *page, int numpages, int enable)
516	{
517	return 0;
518	}
519	#endif
520
521	#if defined(CONFIG_DEBUG_PAGEALLOC) || defined(CONFIG_KFENCE)
522	int hash__kernel_map_pages(struct page *page, int numpages, int enable)
523	{
524	void *vaddr = page_address(page);
525
526	if (is_kfence_address(addr: vaddr))
527	return hash_kfence_map_pages(page, numpages, enable);
528	else
529	return hash_debug_pagealloc_map_pages(page, numpages, enable);
530	}
531
532	static void hash_linear_map_add_slot(phys_addr_t paddr, int slot)
533	{
534	if (is_kfence_address(__va(paddr)))
535	hash_kfence_add_slot(paddr, slot);
536	else
537	hash_debug_pagealloc_add_slot(paddr, slot);
538	}
539	#else
540	static void hash_linear_map_add_slot(phys_addr_t paddr, int slot) {}
541	#endif
542
543	/*
544	* 'R' and 'C' update notes:
545	* - Under pHyp or KVM, the updatepp path will not set C, thus it *will*
546	* create writeable HPTEs without C set, because the hcall H_PROTECT
547	* that we use in that case will not update C
548	* - The above is however not a problem, because we also don't do that
549	* fancy "no flush" variant of eviction and we use H_REMOVE which will
550	* do the right thing and thus we don't have the race I described earlier
551	*
552	* - Under bare metal, we do have the race, so we need R and C set
553	* - We make sure R is always set and never lost
554	* - C is _PAGE_DIRTY, and *should* always be set for a writeable mapping
555	*/
556	unsigned long htab_convert_pte_flags(unsigned long pteflags, unsigned long flags)
557	{
558	unsigned long rflags = 0;
559
560	/* _PAGE_EXEC -> NOEXEC */
561	if ((pteflags & _PAGE_EXEC) == 0)
562	rflags |= HPTE_R_N;
563	/*
564	* PPP bits:
565	* Linux uses slb key 0 for kernel and 1 for user.
566	* kernel RW areas are mapped with PPP=0b000
567	* User area is mapped with PPP=0b010 for read/write
568	* or PPP=0b011 for read-only (including writeable but clean pages).
569	*/
570	if (pteflags & _PAGE_PRIVILEGED) {
571	/*
572	* Kernel read only mapped with ppp bits 0b110
573	*/
574	if (!(pteflags & _PAGE_WRITE)) {
575	if (mmu_has_feature(MMU_FTR_KERNEL_RO))
576	rflags |= (HPTE_R_PP0 | 0x2);
577	else
578	rflags |= 0x3;
579	}
580	VM_WARN_ONCE(!(pteflags & _PAGE_RWX), "no-access mapping request");
581	} else {
582	if (pteflags & _PAGE_RWX)
583	rflags |= 0x2;
584	/*
585	* We should never hit this in normal fault handling because
586	* a permission check (check_pte_access()) will bubble this
587	* to higher level linux handler even for PAGE_NONE.
588	*/
589	VM_WARN_ONCE(!(pteflags & _PAGE_RWX), "no-access mapping request");
590	if (!((pteflags & _PAGE_WRITE) && (pteflags & _PAGE_DIRTY)))
591	rflags |= 0x1;
592	}
593	/*
594	* We can't allow hardware to update hpte bits. Hence always
595	* set 'R' bit and set 'C' if it is a write fault
596	*/
597	rflags |= HPTE_R_R;
598
599	if (pteflags & _PAGE_DIRTY)
600	rflags |= HPTE_R_C;
601	/*
602	* Add in WIG bits
603	*/
604
605	if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_TOLERANT)
606	rflags |= HPTE_R_I;
607	else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT)
608	rflags |= (HPTE_R_I | HPTE_R_G);
609	else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_SAO)
610	rflags |= (HPTE_R_W | HPTE_R_I | HPTE_R_M);
611	else
612	/*
613	* Add memory coherence if cache inhibited is not set
614	*/
615	rflags |= HPTE_R_M;
616
617	rflags |= pte_to_hpte_pkey_bits(pteflags, flags);
618	return rflags;
619	}
620
621	int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
622	unsigned long pstart, unsigned long prot,
623	int psize, int ssize)
624	{
625	unsigned long vaddr, paddr;
626	unsigned int step, shift;
627	int ret = 0;
628
629	shift = mmu_psize_defs[psize].shift;
630	step = 1 << shift;
631
632	prot = htab_convert_pte_flags(prot, HPTE_USE_KERNEL_KEY);
633
634	DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n",
635	vstart, vend, pstart, prot, psize, ssize);
636
637	/* Carefully map only the possible range */
638	vaddr = ALIGN(vstart, step);
639	paddr = ALIGN(pstart, step);
640	vend = ALIGN_DOWN(vend, step);
641
642	for (; vaddr < vend; vaddr += step, paddr += step) {
643	unsigned long hash, hpteg;
644	unsigned long vsid = get_kernel_vsid(vaddr, ssize);
645	unsigned long vpn = hpt_vpn(vaddr, vsid, ssize);
646	unsigned long tprot = prot;
647	bool secondary_hash = false;
648
649	/*
650	* If we hit a bad address return error.
651	*/
652	if (!vsid)
653	return -1;
654	/* Make kernel text executable */
655	if (overlaps_kernel_text(vaddr, vaddr + step))
656	tprot &= ~HPTE_R_N;
657
658	/*
659	* If relocatable, check if it overlaps interrupt vectors that
660	* are copied down to real 0. For relocatable kernel
661	* (e.g. kdump case) we copy interrupt vectors down to real
662	* address 0. Mark that region as executable. This is
663	* because on p8 system with relocation on exception feature
664	* enabled, exceptions are raised with MMU (IR=DR=1) ON. Hence
665	* in order to execute the interrupt handlers in virtual
666	* mode the vector region need to be marked as executable.
667	*/
668	if ((PHYSICAL_START > MEMORY_START) &&
669	overlaps_interrupt_vector_text(vaddr, vaddr + step))
670	tprot &= ~HPTE_R_N;
671
672	hash = hpt_hash(vpn, shift, ssize);
673	hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
674
675	BUG_ON(!mmu_hash_ops.hpte_insert);
676	repeat:
677	ret = mmu_hash_ops.hpte_insert(hpteg, vpn, paddr, tprot,
678	HPTE_V_BOLTED, psize, psize,
679	ssize);
680	if (ret == -1) {
681	/*
682	* Try to keep bolted entries in primary.
683	* Remove non bolted entries and try insert again
684	*/
685	ret = mmu_hash_ops.hpte_remove(hpteg);
686	if (ret != -1)
687	ret = mmu_hash_ops.hpte_insert(hpteg, vpn, paddr, tprot,
688	HPTE_V_BOLTED, psize, psize,
689	ssize);
690	if (ret == -1 && !secondary_hash) {
691	secondary_hash = true;
692	hpteg = ((~hash & htab_hash_mask) * HPTES_PER_GROUP);
693	goto repeat;
694	}
695	}
696
697	if (ret < 0)
698	break;
699
700	cond_resched();
701	/* add slot info in debug_pagealloc / kfence linear map */
702	hash_linear_map_add_slot(paddr, slot: ret);
703	}
704	return ret < 0 ? ret : 0;
705	}
706
707	int htab_remove_mapping(unsigned long vstart, unsigned long vend,
708	int psize, int ssize)
709	{
710	unsigned long vaddr, time_limit;
711	unsigned int step, shift;
712	int rc;
713	int ret = 0;
714
715	shift = mmu_psize_defs[psize].shift;
716	step = 1 << shift;
717
718	if (!mmu_hash_ops.hpte_removebolted)
719	return -ENODEV;
720
721	/* Unmap the full range specificied */
722	vaddr = ALIGN_DOWN(vstart, step);
723	time_limit = jiffies + HZ;
724
725	for (;vaddr < vend; vaddr += step) {
726	rc = mmu_hash_ops.hpte_removebolted(vaddr, psize, ssize);
727
728	/*
729	* For large number of mappings introduce a cond_resched()
730	* to prevent softlockup warnings.
731	*/
732	if (time_after(jiffies, time_limit)) {
733	cond_resched();
734	time_limit = jiffies + HZ;
735	}
736	if (rc == -ENOENT) {
737	ret = -ENOENT;
738	continue;
739	}
740	if (rc < 0)
741	return rc;
742	}
743
744	return ret;
745	}
746
747	static bool disable_1tb_segments __ro_after_init;
748
749	static int __init parse_disable_1tb_segments(char *p)
750	{
751	disable_1tb_segments = true;
752	return 0;
753	}
754	early_param("disable_1tb_segments", parse_disable_1tb_segments);
755
756	bool stress_hpt_enabled __initdata;
757
758	static int __init parse_stress_hpt(char *p)
759	{
760	stress_hpt_enabled = true;
761	return 0;
762	}
763	early_param("stress_hpt", parse_stress_hpt);
764
765	__ro_after_init DEFINE_STATIC_KEY_FALSE(stress_hpt_key);
766
767	/*
768	* per-CPU array allocated if we enable stress_hpt.
769	*/
770	#define STRESS_MAX_GROUPS 16
771	struct stress_hpt_struct {
772	unsigned long last_group[STRESS_MAX_GROUPS];
773	};
774
775	static inline int stress_nr_groups(void)
776	{
777	/*
778	* LPAR H_REMOVE flushes TLB, so need some number > 1 of entries
779	* to allow practical forward progress. Bare metal returns 1, which
780	* seems to help uncover more bugs.
781	*/
782	if (firmware_has_feature(FW_FEATURE_LPAR))
783	return STRESS_MAX_GROUPS;
784	else
785	return 1;
786	}
787
788	static struct stress_hpt_struct *stress_hpt_struct;
789
790	static int __init htab_dt_scan_seg_sizes(unsigned long node,
791	const char *uname, int depth,
792	void *data)
793	{
794	const char *type = of_get_flat_dt_prop(node, name: "device_type", NULL);
795	const __be32 *prop;
796	int size = 0;
797
798	/* We are scanning "cpu" nodes only */
799	if (type == NULL || strcmp(type, "cpu") != 0)
800	return 0;
801
802	prop = of_get_flat_dt_prop(node, name: "ibm,processor-segment-sizes", size: &size);
803	if (prop == NULL)
804	return 0;
805	for (; size >= 4; size -= 4, ++prop) {
806	if (be32_to_cpu(prop[0]) == 40) {
807	DBG("1T segment support detected\n");
808
809	if (disable_1tb_segments) {
810	DBG("1T segments disabled by command line\n");
811	break;
812	}
813
814	cur_cpu_spec->mmu_features |= MMU_FTR_1T_SEGMENT;
815	return 1;
816	}
817	}
818	cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B;
819	return 0;
820	}
821
822	static int __init get_idx_from_shift(unsigned int shift)
823	{
824	int idx = -1;
825
826	switch (shift) {
827	case 0xc:
828	idx = MMU_PAGE_4K;
829	break;
830	case 0x10:
831	idx = MMU_PAGE_64K;
832	break;
833	case 0x14:
834	idx = MMU_PAGE_1M;
835	break;
836	case 0x18:
837	idx = MMU_PAGE_16M;
838	break;
839	case 0x22:
840	idx = MMU_PAGE_16G;
841	break;
842	}
843	return idx;
844	}
845
846	static int __init htab_dt_scan_page_sizes(unsigned long node,
847	const char *uname, int depth,
848	void *data)
849	{
850	const char *type = of_get_flat_dt_prop(node, name: "device_type", NULL);
851	const __be32 *prop;
852	int size = 0;
853
854	/* We are scanning "cpu" nodes only */
855	if (type == NULL || strcmp(type, "cpu") != 0)
856	return 0;
857
858	prop = of_get_flat_dt_prop(node, name: "ibm,segment-page-sizes", size: &size);
859	if (!prop)
860	return 0;
861
862	pr_info("Page sizes from device-tree:\n");
863	size /= 4;
864	cur_cpu_spec->mmu_features &= ~(MMU_FTR_16M_PAGE);
865	while(size > 0) {
866	unsigned int base_shift = be32_to_cpu(prop[0]);
867	unsigned int slbenc = be32_to_cpu(prop[1]);
868	unsigned int lpnum = be32_to_cpu(prop[2]);
869	struct mmu_psize_def *def;
870	int idx, base_idx;
871
872	size -= 3; prop += 3;
873	base_idx = get_idx_from_shift(shift: base_shift);
874	if (base_idx < 0) {
875	/* skip the pte encoding also */
876	prop += lpnum * 2; size -= lpnum * 2;
877	continue;
878	}
879	def = &mmu_psize_defs[base_idx];
880	if (base_idx == MMU_PAGE_16M)
881	cur_cpu_spec->mmu_features |= MMU_FTR_16M_PAGE;
882
883	def->shift = base_shift;
884	if (base_shift <= 23)
885	def->avpnm = 0;
886	else
887	def->avpnm = (1 << (base_shift - 23)) - 1;
888	def->sllp = slbenc;
889	/*
890	* We don't know for sure what's up with tlbiel, so
891	* for now we only set it for 4K and 64K pages
892	*/
893	if (base_idx == MMU_PAGE_4K || base_idx == MMU_PAGE_64K)
894	def->tlbiel = 1;
895	else
896	def->tlbiel = 0;
897
898	while (size > 0 && lpnum) {
899	unsigned int shift = be32_to_cpu(prop[0]);
900	int penc = be32_to_cpu(prop[1]);
901
902	prop += 2; size -= 2;
903	lpnum--;
904
905	idx = get_idx_from_shift(shift);
906	if (idx < 0)
907	continue;
908
909	if (penc == -1)
910	pr_err("Invalid penc for base_shift=%d "
911	"shift=%d\n", base_shift, shift);
912
913	def->penc[idx] = penc;
914	pr_info("base_shift=%d: shift=%d, sllp=0x%04lx,"
915	" avpnm=0x%08lx, tlbiel=%d, penc=%d\n",
916	base_shift, shift, def->sllp,
917	def->avpnm, def->tlbiel, def->penc[idx]);
918	}
919	}
920
921	return 1;
922	}
923
924	#ifdef CONFIG_HUGETLB_PAGE
925	/*
926	* Scan for 16G memory blocks that have been set aside for huge pages
927	* and reserve those blocks for 16G huge pages.
928	*/
929	static int __init htab_dt_scan_hugepage_blocks(unsigned long node,
930	const char *uname, int depth,
931	void *data) {
932	const char *type = of_get_flat_dt_prop(node, name: "device_type", NULL);
933	const __be64 *addr_prop;
934	const __be32 *page_count_prop;
935	unsigned int expected_pages;
936	long unsigned int phys_addr;
937	long unsigned int block_size;
938
939	/* We are scanning "memory" nodes only */
940	if (type == NULL || strcmp(type, "memory") != 0)
941	return 0;
942
943	/*
944	* This property is the log base 2 of the number of virtual pages that
945	* will represent this memory block.
946	*/
947	page_count_prop = of_get_flat_dt_prop(node, name: "ibm,expected#pages", NULL);
948	if (page_count_prop == NULL)
949	return 0;
950	expected_pages = (1 << be32_to_cpu(page_count_prop[0]));
951	addr_prop = of_get_flat_dt_prop(node, name: "reg", NULL);
952	if (addr_prop == NULL)
953	return 0;
954	phys_addr = be64_to_cpu(addr_prop[0]);
955	block_size = be64_to_cpu(addr_prop[1]);
956	if (block_size != (16 * GB))
957	return 0;
958	pr_info("Huge page(16GB) memory: "
959	"addr = 0x%lX size = 0x%lX pages = %d\n",
960	phys_addr, block_size, expected_pages);
961	if (phys_addr + block_size * expected_pages <= memblock_end_of_DRAM()) {
962	memblock_reserve(base: phys_addr, size: block_size * expected_pages);
963	pseries_add_gpage(phys_addr, block_size, expected_pages);
964	}
965	return 0;
966	}
967	#endif /* CONFIG_HUGETLB_PAGE */
968
969	static void __init mmu_psize_set_default_penc(void)
970	{
971	int bpsize, apsize;
972	for (bpsize = 0; bpsize < MMU_PAGE_COUNT; bpsize++)
973	for (apsize = 0; apsize < MMU_PAGE_COUNT; apsize++)
974	mmu_psize_defs[bpsize].penc[apsize] = -1;
975	}
976
977	#ifdef CONFIG_PPC_64K_PAGES
978
979	static bool __init might_have_hea(void)
980	{
981	/*
982	* The HEA ethernet adapter requires awareness of the
983	* GX bus. Without that awareness we can easily assume
984	* we will never see an HEA ethernet device.
985	*/
986	#ifdef CONFIG_IBMEBUS
987	return !cpu_has_feature(CPU_FTR_ARCH_207S) &&
988	firmware_has_feature(FW_FEATURE_SPLPAR);
989	#else
990	return false;
991	#endif
992	}
993
994	#endif /* #ifdef CONFIG_PPC_64K_PAGES */
995
996	static void __init htab_scan_page_sizes(void)
997	{
998	int rc;
999
1000	/* se the invalid penc to -1 */
1001	mmu_psize_set_default_penc();
1002
1003	/* Default to 4K pages only */
1004	memcpy(mmu_psize_defs, mmu_psize_defaults,
1005	sizeof(mmu_psize_defaults));
1006
1007	/*
1008	* Try to find the available page sizes in the device-tree
1009	*/
1010	rc = of_scan_flat_dt(it: htab_dt_scan_page_sizes, NULL);
1011	if (rc == 0 && early_mmu_has_feature(MMU_FTR_16M_PAGE)) {
1012	/*
1013	* Nothing in the device-tree, but the CPU supports 16M pages,
1014	* so let's fallback on a known size list for 16M capable CPUs.
1015	*/
1016	memcpy(mmu_psize_defs, mmu_psize_defaults_gp,
1017	sizeof(mmu_psize_defaults_gp));
1018	}
1019
1020	#ifdef CONFIG_HUGETLB_PAGE
1021	if (!hugetlb_disabled && !early_radix_enabled() ) {
1022	/* Reserve 16G huge page memory sections for huge pages */
1023	of_scan_flat_dt(it: htab_dt_scan_hugepage_blocks, NULL);
1024	}
1025	#endif /* CONFIG_HUGETLB_PAGE */
1026	}
1027
1028	/*
1029	* Fill in the hpte_page_sizes[] array.
1030	* We go through the mmu_psize_defs[] array looking for all the
1031	* supported base/actual page size combinations. Each combination
1032	* has a unique pagesize encoding (penc) value in the low bits of
1033	* the LP field of the HPTE. For actual page sizes less than 1MB,
1034	* some of the upper LP bits are used for RPN bits, meaning that
1035	* we need to fill in several entries in hpte_page_sizes[].
1036	*
1037	* In diagrammatic form, with r = RPN bits and z = page size bits:
1038	* PTE LP actual page size
1039	* rrrr rrrz >=8KB
1040	* rrrr rrzz >=16KB
1041	* rrrr rzzz >=32KB
1042	* rrrr zzzz >=64KB
1043	* ...
1044	*
1045	* The zzzz bits are implementation-specific but are chosen so that
1046	* no encoding for a larger page size uses the same value in its
1047	* low-order N bits as the encoding for the 2^(12+N) byte page size
1048	* (if it exists).
1049	*/
1050	static void __init init_hpte_page_sizes(void)
1051	{
1052	long int ap, bp;
1053	long int shift, penc;
1054
1055	for (bp = 0; bp < MMU_PAGE_COUNT; ++bp) {
1056	if (!mmu_psize_defs[bp].shift)
1057	continue; /* not a supported page size */
1058	for (ap = bp; ap < MMU_PAGE_COUNT; ++ap) {
1059	penc = mmu_psize_defs[bp].penc[ap];
1060	if (penc == -1 || !mmu_psize_defs[ap].shift)
1061	continue;
1062	shift = mmu_psize_defs[ap].shift - LP_SHIFT;
1063	if (shift <= 0)
1064	continue; /* should never happen */
1065	/*
1066	* For page sizes less than 1MB, this loop
1067	* replicates the entry for all possible values
1068	* of the rrrr bits.
1069	*/
1070	while (penc < (1 << LP_BITS)) {
1071	hpte_page_sizes[penc] = (ap << 4) | bp;
1072	penc += 1 << shift;
1073	}
1074	}
1075	}
1076	}
1077
1078	static void __init htab_init_page_sizes(void)
1079	{
1080	bool aligned = true;
1081	init_hpte_page_sizes();
1082
1083	if (!hash_supports_debug_pagealloc() && !kfence_early_init_enabled()) {
1084	/*
1085	* Pick a size for the linear mapping. Currently, we only
1086	* support 16M, 1M and 4K which is the default
1087	*/
1088	if (IS_ENABLED(CONFIG_STRICT_KERNEL_RWX) &&
1089	(unsigned long)_stext % 0x1000000) {
1090	if (mmu_psize_defs[MMU_PAGE_16M].shift)
1091	pr_warn("Kernel not 16M aligned, disabling 16M linear map alignment\n");
1092	aligned = false;
1093	}
1094
1095	if (mmu_psize_defs[MMU_PAGE_16M].shift && aligned)
1096	mmu_linear_psize = MMU_PAGE_16M;
1097	else if (mmu_psize_defs[MMU_PAGE_1M].shift)
1098	mmu_linear_psize = MMU_PAGE_1M;
1099	}
1100
1101	#ifdef CONFIG_PPC_64K_PAGES
1102	/*
1103	* Pick a size for the ordinary pages. Default is 4K, we support
1104	* 64K for user mappings and vmalloc if supported by the processor.
1105	* We only use 64k for ioremap if the processor
1106	* (and firmware) support cache-inhibited large pages.
1107	* If not, we use 4k and set mmu_ci_restrictions so that
1108	* hash_page knows to switch processes that use cache-inhibited
1109	* mappings to 4k pages.
1110	*/
1111	if (mmu_psize_defs[MMU_PAGE_64K].shift) {
1112	mmu_virtual_psize = MMU_PAGE_64K;
1113	mmu_vmalloc_psize = MMU_PAGE_64K;
1114	if (mmu_linear_psize == MMU_PAGE_4K)
1115	mmu_linear_psize = MMU_PAGE_64K;
1116	if (mmu_has_feature(MMU_FTR_CI_LARGE_PAGE)) {
1117	/*
1118	* When running on pSeries using 64k pages for ioremap
1119	* would stop us accessing the HEA ethernet. So if we
1120	* have the chance of ever seeing one, stay at 4k.
1121	*/
1122	if (!might_have_hea())
1123	mmu_io_psize = MMU_PAGE_64K;
1124	} else
1125	mmu_ci_restrictions = 1;
1126	}
1127	#endif /* CONFIG_PPC_64K_PAGES */
1128
1129	#ifdef CONFIG_SPARSEMEM_VMEMMAP
1130	/*
1131	* We try to use 16M pages for vmemmap if that is supported
1132	* and we have at least 1G of RAM at boot
1133	*/
1134	if (mmu_psize_defs[MMU_PAGE_16M].shift &&
1135	memblock_phys_mem_size() >= 0x40000000)
1136	mmu_vmemmap_psize = MMU_PAGE_16M;
1137	else
1138	mmu_vmemmap_psize = mmu_virtual_psize;
1139	#endif /* CONFIG_SPARSEMEM_VMEMMAP */
1140
1141	pr_info("Page orders: linear mapping = %d, "
1142	"virtual = %d, io = %d"
1143	#ifdef CONFIG_SPARSEMEM_VMEMMAP
1144	", vmemmap = %d"
1145	#endif
1146	"\n",
1147	mmu_psize_defs[mmu_linear_psize].shift,
1148	mmu_psize_defs[mmu_virtual_psize].shift,
1149	mmu_psize_defs[mmu_io_psize].shift
1150	#ifdef CONFIG_SPARSEMEM_VMEMMAP
1151	,mmu_psize_defs[mmu_vmemmap_psize].shift
1152	#endif
1153	);
1154	}
1155
1156	static int __init htab_dt_scan_pftsize(unsigned long node,
1157	const char *uname, int depth,
1158	void *data)
1159	{
1160	const char *type = of_get_flat_dt_prop(node, name: "device_type", NULL);
1161	const __be32 *prop;
1162
1163	/* We are scanning "cpu" nodes only */
1164	if (type == NULL || strcmp(type, "cpu") != 0)
1165	return 0;
1166
1167	prop = of_get_flat_dt_prop(node, name: "ibm,pft-size", NULL);
1168	if (prop != NULL) {
1169	/* pft_size[0] is the NUMA CEC cookie */
1170	ppc64_pft_size = be32_to_cpu(prop[1]);
1171	return 1;
1172	}
1173	return 0;
1174	}
1175
1176	unsigned htab_shift_for_mem_size(unsigned long mem_size)
1177	{
1178	unsigned memshift = __ilog2(mem_size);
1179	unsigned pshift = mmu_psize_defs[mmu_virtual_psize].shift;
1180	unsigned pteg_shift;
1181
1182	/* round mem_size up to next power of 2 */
1183	if ((1UL << memshift) < mem_size)
1184	memshift += 1;
1185
1186	/* aim for 2 pages / pteg */
1187	pteg_shift = memshift - (pshift + 1);
1188
1189	/*
1190	* 2^11 PTEGS of 128 bytes each, ie. 2^18 bytes is the minimum htab
1191	* size permitted by the architecture.
1192	*/
1193	return max(pteg_shift + 7, 18U);
1194	}
1195
1196	static unsigned long __init htab_get_table_size(void)
1197	{
1198	/*
1199	* If hash size isn't already provided by the platform, we try to
1200	* retrieve it from the device-tree. If it's not there neither, we
1201	* calculate it now based on the total RAM size
1202	*/
1203	if (ppc64_pft_size == 0)
1204	of_scan_flat_dt(it: htab_dt_scan_pftsize, NULL);
1205	if (ppc64_pft_size)
1206	return 1UL << ppc64_pft_size;
1207
1208	return 1UL << htab_shift_for_mem_size(mem_size: memblock_phys_mem_size());
1209	}
1210
1211	#ifdef CONFIG_MEMORY_HOTPLUG
1212	static int resize_hpt_for_hotplug(unsigned long new_mem_size)
1213	{
1214	unsigned target_hpt_shift;
1215
1216	if (!mmu_hash_ops.resize_hpt)
1217	return 0;
1218
1219	target_hpt_shift = htab_shift_for_mem_size(mem_size: new_mem_size);
1220
1221	/*
1222	* To avoid lots of HPT resizes if memory size is fluctuating
1223	* across a boundary, we deliberately have some hysterisis
1224	* here: we immediately increase the HPT size if the target
1225	* shift exceeds the current shift, but we won't attempt to
1226	* reduce unless the target shift is at least 2 below the
1227	* current shift
1228	*/
1229	if (target_hpt_shift > ppc64_pft_size ||
1230	target_hpt_shift < ppc64_pft_size - 1)
1231	return mmu_hash_ops.resize_hpt(target_hpt_shift);
1232
1233	return 0;
1234	}
1235
1236	int hash__create_section_mapping(unsigned long start, unsigned long end,
1237	int nid, pgprot_t prot)
1238	{
1239	int rc;
1240	unsigned int pshift = mmu_psize_defs[mmu_linear_psize].shift;
1241
1242	if (end >= H_VMALLOC_START) {
1243	pr_warn("Outside the supported range\n");
1244	return -1;
1245	}
1246
1247	resize_hpt_for_hotplug(new_mem_size: memblock_phys_mem_size());
1248
1249	rc = htab_bolt_mapping(vstart: start, vend: end, __pa(start),
1250	pgprot_val(prot), psize: mmu_linear_psize,
1251	ssize: mmu_kernel_ssize);
1252
1253	if (rc < 0) {
1254	int rc2 = htab_remove_mapping(vstart: start, vend: end, psize: mmu_linear_psize,
1255	ssize: mmu_kernel_ssize);
1256	BUG_ON(rc2 && (rc2 != -ENOENT));
1257	}
1258	update_page_count(level: mmu_linear_psize, pages: (end - start) >> pshift);
1259	return rc;
1260	}
1261
1262	int hash__remove_section_mapping(unsigned long start, unsigned long end)
1263	{
1264	unsigned int pshift = mmu_psize_defs[mmu_linear_psize].shift;
1265
1266	int rc = htab_remove_mapping(vstart: start, vend: end, psize: mmu_linear_psize,
1267	ssize: mmu_kernel_ssize);
1268
1269	if (resize_hpt_for_hotplug(new_mem_size: memblock_phys_mem_size()) == -ENOSPC)
1270	pr_warn("Hash collision while resizing HPT\n");
1271
1272	if (!rc)
1273	update_page_count(level: mmu_linear_psize, pages: -((end - start) >> pshift));
1274	return rc;
1275	}
1276	#endif /* CONFIG_MEMORY_HOTPLUG */
1277
1278	static void __init hash_init_partition_table(phys_addr_t hash_table,
1279	unsigned long htab_size)
1280	{
1281	mmu_partition_table_init();
1282
1283	/*
1284	* PS field (VRMA page size) is not used for LPID 0, hence set to 0.
1285	* For now, UPRT is 0 and we have no segment table.
1286	*/
1287	htab_size = __ilog2(htab_size) - 18;
1288	mmu_partition_table_set_entry(0, hash_table | htab_size, 0, false);
1289	pr_info("Partition table %p\n", partition_tb);
1290	}
1291
1292	void hpt_clear_stress(void);
1293	static struct timer_list stress_hpt_timer;
1294	static void stress_hpt_timer_fn(struct timer_list *timer)
1295	{
1296	int next_cpu;
1297
1298	hpt_clear_stress();
1299	if (!firmware_has_feature(FW_FEATURE_LPAR))
1300	tlbiel_all();
1301
1302	next_cpu = cpumask_next(raw_smp_processor_id(), cpu_online_mask);
1303	if (next_cpu >= nr_cpu_ids)
1304	next_cpu = cpumask_first(cpu_online_mask);
1305	stress_hpt_timer.expires = jiffies + msecs_to_jiffies(m: 10);
1306	add_timer_on(timer: &stress_hpt_timer, cpu: next_cpu);
1307	}
1308
1309	static void __init htab_initialize(void)
1310	{
1311	unsigned long table;
1312	unsigned long pteg_count;
1313	unsigned long prot;
1314	phys_addr_t base = 0, size = 0, end, limit = MEMBLOCK_ALLOC_ANYWHERE;
1315	u64 i;
1316	unsigned int pshift = mmu_psize_defs[mmu_linear_psize].shift;
1317
1318	DBG(" -> htab_initialize()\n");
1319
1320	if (firmware_has_feature(FW_FEATURE_LPAR))
1321	limit = ppc64_rma_size;
1322
1323	if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) {
1324	mmu_kernel_ssize = MMU_SEGSIZE_1T;
1325	mmu_highuser_ssize = MMU_SEGSIZE_1T;
1326	pr_info("Using 1TB segments\n");
1327	}
1328
1329	if (stress_slb_enabled)
1330	static_branch_enable(&stress_slb_key);
1331
1332	if (no_slb_preload)
1333	static_branch_enable(&no_slb_preload_key);
1334
1335	if (stress_hpt_enabled) {
1336	unsigned long tmp;
1337	static_branch_enable(&stress_hpt_key);
1338	// Too early to use nr_cpu_ids, so use NR_CPUS
1339	tmp = memblock_phys_alloc_range(size: sizeof(struct stress_hpt_struct) * NR_CPUS,
1340	align: __alignof__(struct stress_hpt_struct),
1341	MEMBLOCK_LOW_LIMIT, end: limit);
1342	memset((void *)tmp, 0xff, sizeof(struct stress_hpt_struct) * NR_CPUS);
1343	stress_hpt_struct = __va(tmp);
1344
1345	timer_setup(&stress_hpt_timer, stress_hpt_timer_fn, 0);
1346	stress_hpt_timer.expires = jiffies + msecs_to_jiffies(m: 10);
1347	add_timer(timer: &stress_hpt_timer);
1348	}
1349
1350	/*
1351	* Calculate the required size of the htab. We want the number of
1352	* PTEGs to equal one half the number of real pages.
1353	*/
1354	htab_size_bytes = htab_get_table_size();
1355	pteg_count = htab_size_bytes >> 7;
1356
1357	htab_hash_mask = pteg_count - 1;
1358
1359	if (firmware_has_feature(FW_FEATURE_LPAR) ||
1360	firmware_has_feature(FW_FEATURE_PS3_LV1)) {
1361	/* Using a hypervisor which owns the htab */
1362	htab_address = NULL;
1363	_SDR1 = 0;
1364	#ifdef CONFIG_FA_DUMP
1365	/*
1366	* If firmware assisted dump is active firmware preserves
1367	* the contents of htab along with entire partition memory.
1368	* Clear the htab if firmware assisted dump is active so
1369	* that we dont end up using old mappings.
1370	*/
1371	if (is_fadump_active() && mmu_hash_ops.hpte_clear_all)
1372	mmu_hash_ops.hpte_clear_all();
1373	#endif
1374	} else {
1375
1376	table = memblock_phys_alloc_range(size: htab_size_bytes,
1377	align: htab_size_bytes,
1378	MEMBLOCK_LOW_LIMIT, end: limit);
1379	if (!table)
1380	panic(fmt: "ERROR: Failed to allocate %pa bytes below %pa\n",
1381	&htab_size_bytes, &limit);
1382
1383	DBG("Hash table allocated at %lx, size: %lx\n", table,
1384	htab_size_bytes);
1385
1386	htab_address = __va(table);
1387
1388	/* htab absolute addr + encoded htabsize */
1389	_SDR1 = table + __ilog2(htab_size_bytes) - 18;
1390
1391	/* Initialize the HPT with no entries */
1392	memset((void *)table, 0, htab_size_bytes);
1393
1394	if (!cpu_has_feature(CPU_FTR_ARCH_300))
1395	/* Set SDR1 */
1396	mtspr(SPRN_SDR1, _SDR1);
1397	else
1398	hash_init_partition_table(hash_table: table, htab_size: htab_size_bytes);
1399	}
1400
1401	prot = pgprot_val(PAGE_KERNEL);
1402
1403	hash_debug_pagealloc_alloc_slots();
1404	hash_kfence_alloc_pool();
1405	/* create bolted the linear mapping in the hash table */
1406	for_each_mem_range(i, &base, &end) {
1407	size = end - base;
1408	base = (unsigned long)__va(base);
1409
1410	pr_debug("creating mapping for region: 0x%pa..0x%pa (prot: %lx)\n",
1411	&base, &size, prot);
1412
1413	if ((base + size) >= H_VMALLOC_START) {
1414	pr_warn("Outside the supported range\n");
1415	continue;
1416	}
1417
1418	BUG_ON(htab_bolt_mapping(base, base + size, __pa(base),
1419	prot, mmu_linear_psize, mmu_kernel_ssize));
1420
1421	update_page_count(level: mmu_linear_psize, pages: size >> pshift);
1422	}
1423	hash_kfence_map_pool();
1424	memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
1425
1426	/*
1427	* If we have a memory_limit and we've allocated TCEs then we need to
1428	* explicitly map the TCE area at the top of RAM. We also cope with the
1429	* case that the TCEs start below memory_limit.
1430	* tce_alloc_start/end are 16MB aligned so the mapping should work
1431	* for either 4K or 16MB pages.
1432	*/
1433	if (tce_alloc_start) {
1434	tce_alloc_start = (unsigned long)__va(tce_alloc_start);
1435	tce_alloc_end = (unsigned long)__va(tce_alloc_end);
1436
1437	if (base + size >= tce_alloc_start)
1438	tce_alloc_start = base + size + 1;
1439
1440	BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end,
1441	__pa(tce_alloc_start), prot,
1442	mmu_linear_psize, mmu_kernel_ssize));
1443	update_page_count(mmu_linear_psize,
1444	(tce_alloc_end - tce_alloc_start) >> pshift);
1445	}
1446
1447
1448	DBG(" <- htab_initialize()\n");
1449	}
1450	#undef KB
1451	#undef MB
1452
1453	void __init hash__early_init_devtree(void)
1454	{
1455	/* Initialize segment sizes */
1456	of_scan_flat_dt(it: htab_dt_scan_seg_sizes, NULL);
1457
1458	/* Initialize page sizes */
1459	htab_scan_page_sizes();
1460	}
1461
1462	static struct hash_mm_context init_hash_mm_context;
1463	void __init hash__early_init_mmu(void)
1464	{
1465	#ifndef CONFIG_PPC_64K_PAGES
1466	/*
1467	* We have code in __hash_page_4K() and elsewhere, which assumes it can
1468	* do the following:
1469	* new_pte |= (slot << H_PAGE_F_GIX_SHIFT) & (H_PAGE_F_SECOND | H_PAGE_F_GIX);
1470	*
1471	* Where the slot number is between 0-15, and values of 8-15 indicate
1472	* the secondary bucket. For that code to work H_PAGE_F_SECOND and
1473	* H_PAGE_F_GIX must occupy four contiguous bits in the PTE, and
1474	* H_PAGE_F_SECOND must be placed above H_PAGE_F_GIX. Assert that here
1475	* with a BUILD_BUG_ON().
1476	*/
1477	BUILD_BUG_ON(H_PAGE_F_SECOND != (1ul << (H_PAGE_F_GIX_SHIFT + 3)));
1478	#endif /* CONFIG_PPC_64K_PAGES */
1479
1480	htab_init_page_sizes();
1481
1482	/*
1483	* initialize page table size
1484	*/
1485	__pte_frag_nr = H_PTE_FRAG_NR;
1486	__pte_frag_size_shift = H_PTE_FRAG_SIZE_SHIFT;
1487	__pmd_frag_nr = H_PMD_FRAG_NR;
1488	__pmd_frag_size_shift = H_PMD_FRAG_SIZE_SHIFT;
1489
1490	__pte_index_size = H_PTE_INDEX_SIZE;
1491	__pmd_index_size = H_PMD_INDEX_SIZE;
1492	__pud_index_size = H_PUD_INDEX_SIZE;
1493	__pgd_index_size = H_PGD_INDEX_SIZE;
1494	__pud_cache_index = H_PUD_CACHE_INDEX;
1495	__pte_table_size = H_PTE_TABLE_SIZE;
1496	__pmd_table_size = H_PMD_TABLE_SIZE;
1497	__pud_table_size = H_PUD_TABLE_SIZE;
1498	__pgd_table_size = H_PGD_TABLE_SIZE;
1499	__pmd_val_bits = HASH_PMD_VAL_BITS;
1500	__pud_val_bits = HASH_PUD_VAL_BITS;
1501	__pgd_val_bits = HASH_PGD_VAL_BITS;
1502
1503	__kernel_virt_start = H_KERN_VIRT_START;
1504	__vmalloc_start = H_VMALLOC_START;
1505	__vmalloc_end = H_VMALLOC_END;
1506	__kernel_io_start = H_KERN_IO_START;
1507	__kernel_io_end = H_KERN_IO_END;
1508	vmemmap = (struct page *)H_VMEMMAP_START;
1509	ioremap_bot = IOREMAP_BASE;
1510
1511	#ifdef CONFIG_PCI
1512	pci_io_base = ISA_IO_BASE;
1513	#endif
1514
1515	/* Select appropriate backend */
1516	if (firmware_has_feature(FW_FEATURE_PS3_LV1))
1517	ps3_early_mm_init();
1518	else if (firmware_has_feature(FW_FEATURE_LPAR))
1519	hpte_init_pseries();
1520	else if (IS_ENABLED(CONFIG_PPC_HASH_MMU_NATIVE))
1521	hpte_init_native();
1522
1523	if (!mmu_hash_ops.hpte_insert)
1524	panic(fmt: "hash__early_init_mmu: No MMU hash ops defined!\n");
1525
1526	/*
1527	* Initialize the MMU Hash table and create the linear mapping
1528	* of memory. Has to be done before SLB initialization as this is
1529	* currently where the page size encoding is obtained.
1530	*/
1531	htab_initialize();
1532
1533	init_mm.context.hash_context = &init_hash_mm_context;
1534	mm_ctx_set_slb_addr_limit(&init_mm.context, SLB_ADDR_LIMIT_DEFAULT);
1535
1536	pr_info("Initializing hash mmu with SLB\n");
1537	/* Initialize SLB management */
1538	slb_initialize();
1539
1540	if (cpu_has_feature(CPU_FTR_ARCH_206)
1541	&& cpu_has_feature(CPU_FTR_HVMODE))
1542	tlbiel_all();
1543	}
1544
1545	#ifdef CONFIG_SMP
1546	void hash__early_init_mmu_secondary(void)
1547	{
1548	/* Initialize hash table for that CPU */
1549	if (!firmware_has_feature(FW_FEATURE_LPAR)) {
1550
1551	if (!cpu_has_feature(CPU_FTR_ARCH_300))
1552	mtspr(SPRN_SDR1, _SDR1);
1553	else
1554	set_ptcr_when_no_uv(__pa(partition_tb) |
1555	(PATB_SIZE_SHIFT - 12));
1556	}
1557	/* Initialize SLB */
1558	slb_initialize();
1559
1560	if (cpu_has_feature(CPU_FTR_ARCH_206)
1561	&& cpu_has_feature(CPU_FTR_HVMODE))
1562	tlbiel_all();
1563
1564	#ifdef CONFIG_PPC_MEM_KEYS
1565	if (mmu_has_feature(MMU_FTR_PKEY))
1566	mtspr(SPRN_UAMOR, default_uamor);
1567	#endif
1568	}
1569	#endif /* CONFIG_SMP */
1570
1571	/*
1572	* Called by asm hashtable.S for doing lazy icache flush
1573	*/
1574	unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
1575	{
1576	struct folio *folio;
1577
1578	if (!pfn_valid(pfn: pte_pfn(pte)))
1579	return pp;
1580
1581	folio = page_folio(pte_page(pte));
1582
1583	/* page is dirty */
1584	if (!test_bit(PG_dcache_clean, &folio->flags.f) &&
1585	!folio_test_reserved(folio)) {
1586	if (trap == INTERRUPT_INST_STORAGE) {
1587	flush_dcache_icache_folio(folio);
1588	set_bit(PG_dcache_clean, &folio->flags.f);
1589	} else
1590	pp |= HPTE_R_N;
1591	}
1592	return pp;
1593	}
1594
1595	static unsigned int get_paca_psize(unsigned long addr)
1596	{
1597	unsigned char *psizes;
1598	unsigned long index, mask_index;
1599
1600	if (addr < SLICE_LOW_TOP) {
1601	psizes = get_paca()->mm_ctx_low_slices_psize;
1602	index = GET_LOW_SLICE_INDEX(addr);
1603	} else {
1604	psizes = get_paca()->mm_ctx_high_slices_psize;
1605	index = GET_HIGH_SLICE_INDEX(addr);
1606	}
1607	mask_index = index & 0x1;
1608	return (psizes[index >> 1] >> (mask_index * 4)) & 0xF;
1609	}
1610
1611
1612	/*
1613	* Demote a segment to using 4k pages.
1614	* For now this makes the whole process use 4k pages.
1615	*/
1616	#ifdef CONFIG_PPC_64K_PAGES
1617	void demote_segment_4k(struct mm_struct *mm, unsigned long addr)
1618	{
1619	if (get_slice_psize(mm, addr) == MMU_PAGE_4K)
1620	return;
1621	slice_set_range_psize(mm, addr, 1, MMU_PAGE_4K);
1622	#ifdef CONFIG_SPU_BASE
1623	spu_flush_all_slbs(mm);
1624	#endif
1625	if ((get_paca_psize(addr) != MMU_PAGE_4K) && (current->mm == mm)) {
1626
1627	copy_mm_to_paca(mm);
1628	slb_flush_and_restore_bolted();
1629	}
1630	}
1631	#endif /* CONFIG_PPC_64K_PAGES */
1632
1633	#ifdef CONFIG_PPC_SUBPAGE_PROT
1634	/*
1635	* This looks up a 2-bit protection code for a 4k subpage of a 64k page.
1636	* Userspace sets the subpage permissions using the subpage_prot system call.
1637	*
1638	* Result is 0: full permissions, _PAGE_RW: read-only,
1639	* _PAGE_RWX: no access.
1640	*/
1641	static int subpage_protection(struct mm_struct *mm, unsigned long ea)
1642	{
1643	struct subpage_prot_table *spt = mm_ctx_subpage_prot(&mm->context);
1644	u32 spp = 0;
1645	u32 **sbpm, *sbpp;
1646
1647	if (!spt)
1648	return 0;
1649
1650	if (ea >= spt->maxaddr)
1651	return 0;
1652	if (ea < 0x100000000UL) {
1653	/* addresses below 4GB use spt->low_prot */
1654	sbpm = spt->low_prot;
1655	} else {
1656	sbpm = spt->protptrs[ea >> SBP_L3_SHIFT];
1657	if (!sbpm)
1658	return 0;
1659	}
1660	sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)];
1661	if (!sbpp)
1662	return 0;
1663	spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)];
1664
1665	/* extract 2-bit bitfield for this 4k subpage */
1666	spp >>= 30 - 2 * ((ea >> 12) & 0xf);
1667
1668	/*
1669	* 0 -> full permission
1670	* 1 -> Read only
1671	* 2 -> no access.
1672	* We return the flag that need to be cleared.
1673	*/
1674	spp = ((spp & 2) ? _PAGE_RWX : 0) | ((spp & 1) ? _PAGE_WRITE : 0);
1675	return spp;
1676	}
1677
1678	#else /* CONFIG_PPC_SUBPAGE_PROT */
1679	static inline int subpage_protection(struct mm_struct *mm, unsigned long ea)
1680	{
1681	return 0;
1682	}
1683	#endif
1684
1685	void hash_failure_debug(unsigned long ea, unsigned long access,
1686	unsigned long vsid, unsigned long trap,
1687	int ssize, int psize, int lpsize, unsigned long pte)
1688	{
1689	if (!printk_ratelimit())
1690	return;
1691	pr_info("mm: Hashing failure ! EA=0x%lx access=0x%lx current=%s\n",
1692	ea, access, current->comm);
1693	pr_info(" trap=0x%lx vsid=0x%lx ssize=%d base psize=%d psize %d pte=0x%lx\n",
1694	trap, vsid, ssize, psize, lpsize, pte);
1695	}
1696
1697	static void check_paca_psize(unsigned long ea, struct mm_struct *mm,
1698	int psize, bool user_region)
1699	{
1700	if (user_region) {
1701	if (psize != get_paca_psize(addr: ea)) {
1702	copy_mm_to_paca(mm);
1703	slb_flush_and_restore_bolted();
1704	}
1705	} else if (get_paca()->vmalloc_sllp !=
1706	mmu_psize_defs[mmu_vmalloc_psize].sllp) {
1707	get_paca()->vmalloc_sllp =
1708	mmu_psize_defs[mmu_vmalloc_psize].sllp;
1709	slb_vmalloc_update();
1710	}
1711	}
1712
1713	/*
1714	* Result code is:
1715	* 0 - handled
1716	* 1 - normal page fault
1717	* -1 - critical hash insertion error
1718	* -2 - access not permitted by subpage protection mechanism
1719	*/
1720	int hash_page_mm(struct mm_struct *mm, unsigned long ea,
1721	unsigned long access, unsigned long trap,
1722	unsigned long flags)
1723	{
1724	bool is_thp;
1725	pgd_t *pgdir;
1726	unsigned long vsid;
1727	pte_t *ptep;
1728	unsigned hugeshift;
1729	int rc, user_region = 0;
1730	int psize, ssize;
1731
1732	DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n",
1733	ea, access, trap);
1734	trace_hash_fault(ea, access, trap);
1735
1736	/* Get region & vsid */
1737	switch (get_region_id(ea)) {
1738	case USER_REGION_ID:
1739	user_region = 1;
1740	if (! mm) {
1741	DBG_LOW(" user region with no mm !\n");
1742	rc = 1;
1743	goto bail;
1744	}
1745	psize = get_slice_psize(mm, ea);
1746	ssize = user_segment_size(ea);
1747	vsid = get_user_vsid(&mm->context, ea, ssize);
1748	break;
1749	case VMALLOC_REGION_ID:
1750	vsid = get_kernel_vsid(ea, mmu_kernel_ssize);
1751	psize = mmu_vmalloc_psize;
1752	ssize = mmu_kernel_ssize;
1753	flags |= HPTE_USE_KERNEL_KEY;
1754	break;
1755
1756	case IO_REGION_ID:
1757	vsid = get_kernel_vsid(ea, mmu_kernel_ssize);
1758	psize = mmu_io_psize;
1759	ssize = mmu_kernel_ssize;
1760	flags |= HPTE_USE_KERNEL_KEY;
1761	break;
1762	default:
1763	/*
1764	* Not a valid range
1765	* Send the problem up to do_page_fault()
1766	*/
1767	rc = 1;
1768	goto bail;
1769	}
1770	DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid);
1771
1772	/* Bad address. */
1773	if (!vsid) {
1774	DBG_LOW("Bad address!\n");
1775	rc = 1;
1776	goto bail;
1777	}
1778	/* Get pgdir */
1779	pgdir = mm->pgd;
1780	if (pgdir == NULL) {
1781	rc = 1;
1782	goto bail;
1783	}
1784
1785	/* Check CPU locality */
1786	if (user_region && mm_is_thread_local(mm))
1787	flags |= HPTE_LOCAL_UPDATE;
1788
1789	#ifndef CONFIG_PPC_64K_PAGES
1790	/*
1791	* If we use 4K pages and our psize is not 4K, then we might
1792	* be hitting a special driver mapping, and need to align the
1793	* address before we fetch the PTE.
1794	*
1795	* It could also be a hugepage mapping, in which case this is
1796	* not necessary, but it's not harmful, either.
1797	*/
1798	if (psize != MMU_PAGE_4K)
1799	ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
1800	#endif /* CONFIG_PPC_64K_PAGES */
1801
1802	/* Get PTE and page size from page tables */
1803	ptep = find_linux_pte(pgdir, ea, &is_thp, &hugeshift);
1804	if (ptep == NULL || !pte_present(a: *ptep)) {
1805	DBG_LOW(" no PTE !\n");
1806	rc = 1;
1807	goto bail;
1808	}
1809
1810	if (IS_ENABLED(CONFIG_PPC_4K_PAGES) && !radix_enabled()) {
1811	if (hugeshift == PMD_SHIFT && psize == MMU_PAGE_16M)
1812	hugeshift = mmu_psize_defs[MMU_PAGE_16M].shift;
1813	if (hugeshift == PUD_SHIFT && psize == MMU_PAGE_16G)
1814	hugeshift = mmu_psize_defs[MMU_PAGE_16G].shift;
1815	}
1816
1817	/*
1818	* Add _PAGE_PRESENT to the required access perm. If there are parallel
1819	* updates to the pte that can possibly clear _PAGE_PTE, catch that too.
1820	*
1821	* We can safely use the return pte address in rest of the function
1822	* because we do set H_PAGE_BUSY which prevents further updates to pte
1823	* from generic code.
1824	*/
1825	access |= _PAGE_PRESENT | _PAGE_PTE;
1826
1827	/*
1828	* Pre-check access permissions (will be re-checked atomically
1829	* in __hash_page_XX but this pre-check is a fast path
1830	*/
1831	if (!check_pte_access(access, pte_val(pte: *ptep))) {
1832	DBG_LOW(" no access !\n");
1833	rc = 1;
1834	goto bail;
1835	}
1836
1837	if (hugeshift) {
1838	if (is_thp)
1839	rc = __hash_page_thp(ea, access, vsid, (pmd_t *)ptep,
1840	trap, flags, ssize, psize);
1841	#ifdef CONFIG_HUGETLB_PAGE
1842	else
1843	rc = __hash_page_huge(ea, access, vsid, ptep, trap,
1844	flags, ssize, hugeshift, psize);
1845	#else
1846	else {
1847	/*
1848	* if we have hugeshift, and is not transhuge with
1849	* hugetlb disabled, something is really wrong.
1850	*/
1851	rc = 1;
1852	WARN_ON(1);
1853	}
1854	#endif
1855	if (current->mm == mm)
1856	check_paca_psize(ea, mm, psize, user_region);
1857
1858	goto bail;
1859	}
1860
1861	#ifndef CONFIG_PPC_64K_PAGES
1862	DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep));
1863	#else
1864	DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep),
1865	pte_val(*(ptep + PTRS_PER_PTE)));
1866	#endif
1867	/* Do actual hashing */
1868	#ifdef CONFIG_PPC_64K_PAGES
1869	/* If H_PAGE_4K_PFN is set, make sure this is a 4k segment */
1870	if ((pte_val(*ptep) & H_PAGE_4K_PFN) && psize == MMU_PAGE_64K) {
1871	demote_segment_4k(mm, ea);
1872	psize = MMU_PAGE_4K;
1873	}
1874
1875	/*
1876	* If this PTE is non-cacheable and we have restrictions on
1877	* using non cacheable large pages, then we switch to 4k
1878	*/
1879	if (mmu_ci_restrictions && psize == MMU_PAGE_64K && pte_ci(*ptep)) {
1880	if (user_region) {
1881	demote_segment_4k(mm, ea);
1882	psize = MMU_PAGE_4K;
1883	} else if (ea < VMALLOC_END) {
1884	/*
1885	* some driver did a non-cacheable mapping
1886	* in vmalloc space, so switch vmalloc
1887	* to 4k pages
1888	*/
1889	pr_alert("Reducing vmalloc segment "
1890	"to 4kB pages because of "
1891	"non-cacheable mapping\n");
1892	psize = mmu_vmalloc_psize = MMU_PAGE_4K;
1893	#ifdef CONFIG_SPU_BASE
1894	spu_flush_all_slbs(mm);
1895	#endif
1896	}
1897	}
1898
1899	#endif /* CONFIG_PPC_64K_PAGES */
1900
1901	if (current->mm == mm)
1902	check_paca_psize(ea, mm, psize, user_region);
1903
1904	#ifdef CONFIG_PPC_64K_PAGES
1905	if (psize == MMU_PAGE_64K)
1906	rc = __hash_page_64K(ea, access, vsid, ptep, trap,
1907	flags, ssize);
1908	else
1909	#endif /* CONFIG_PPC_64K_PAGES */
1910	{
1911	int spp = subpage_protection(mm, ea);
1912	if (access & spp)
1913	rc = -2;
1914	else
1915	rc = __hash_page_4K(ea, access, vsid, ptep, trap,
1916	flags, ssize, spp);
1917	}
1918
1919	/*
1920	* Dump some info in case of hash insertion failure, they should
1921	* never happen so it is really useful to know if/when they do
1922	*/
1923	if (rc == -1)
1924	hash_failure_debug(ea, access, vsid, trap, ssize, psize,
1925	lpsize: psize, pte: pte_val(pte: *ptep));
1926	#ifndef CONFIG_PPC_64K_PAGES
1927	DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep));
1928	#else
1929	DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep),
1930	pte_val(*(ptep + PTRS_PER_PTE)));
1931	#endif
1932	DBG_LOW(" -> rc=%d\n", rc);
1933
1934	bail:
1935	return rc;
1936	}
1937	EXPORT_SYMBOL_GPL(hash_page_mm);
1938
1939	int hash_page(unsigned long ea, unsigned long access, unsigned long trap,
1940	unsigned long dsisr)
1941	{
1942	unsigned long flags = 0;
1943	struct mm_struct *mm = current->mm;
1944
1945	if ((get_region_id(ea) == VMALLOC_REGION_ID) ||
1946	(get_region_id(ea) == IO_REGION_ID))
1947	mm = &init_mm;
1948
1949	if (dsisr & DSISR_NOHPTE)
1950	flags |= HPTE_NOHPTE_UPDATE;
1951
1952	return hash_page_mm(mm, ea, access, trap, flags);
1953	}
1954	EXPORT_SYMBOL_GPL(hash_page);
1955
1956	DEFINE_INTERRUPT_HANDLER(do_hash_fault)
1957	{
1958	unsigned long ea = regs->dar;
1959	unsigned long dsisr = regs->dsisr;
1960	unsigned long access = _PAGE_PRESENT | _PAGE_READ;
1961	unsigned long flags = 0;
1962	struct mm_struct *mm;
1963	unsigned int region_id;
1964	long err;
1965
1966	if (unlikely(dsisr & (DSISR_BAD_FAULT_64S | DSISR_KEYFAULT))) {
1967	hash__do_page_fault(regs);
1968	return;
1969	}
1970
1971	region_id = get_region_id(ea);
1972	if ((region_id == VMALLOC_REGION_ID) || (region_id == IO_REGION_ID))
1973	mm = &init_mm;
1974	else
1975	mm = current->mm;
1976
1977	if (dsisr & DSISR_NOHPTE)
1978	flags |= HPTE_NOHPTE_UPDATE;
1979
1980	if (dsisr & DSISR_ISSTORE)
1981	access |= _PAGE_WRITE;
1982	/*
1983	* We set _PAGE_PRIVILEGED only when
1984	* kernel mode access kernel space.
1985	*
1986	* _PAGE_PRIVILEGED is NOT set
1987	* 1) when kernel mode access user space
1988	* 2) user space access kernel space.
1989	*/
1990	access |= _PAGE_PRIVILEGED;
1991	if (user_mode(regs) || (region_id == USER_REGION_ID))
1992	access &= ~_PAGE_PRIVILEGED;
1993
1994	if (TRAP(regs) == INTERRUPT_INST_STORAGE)
1995	access |= _PAGE_EXEC;
1996
1997	err = hash_page_mm(mm, ea, access, TRAP(regs), flags);
1998	if (unlikely(err < 0)) {
1999	// failed to insert a hash PTE due to an hypervisor error
2000	if (user_mode(regs)) {
2001	if (IS_ENABLED(CONFIG_PPC_SUBPAGE_PROT) && err == -2)
2002	_exception(SIGSEGV, regs, SEGV_ACCERR, ea);
2003	else
2004	_exception(SIGBUS, regs, BUS_ADRERR, ea);
2005	} else {
2006	bad_page_fault(regs, SIGBUS);
2007	}
2008	err = 0;
2009
2010	} else if (err) {
2011	hash__do_page_fault(regs);
2012	}
2013	}
2014
2015	static bool should_hash_preload(struct mm_struct *mm, unsigned long ea)
2016	{
2017	int psize = get_slice_psize(mm, ea);
2018
2019	/* We only prefault standard pages for now */
2020	if (unlikely(psize != mm_ctx_user_psize(&mm->context)))
2021	return false;
2022
2023	/*
2024	* Don't prefault if subpage protection is enabled for the EA.
2025	*/
2026	if (unlikely((psize == MMU_PAGE_4K) && subpage_protection(mm, ea)))
2027	return false;
2028
2029	return true;
2030	}
2031
2032	static void hash_preload(struct mm_struct *mm, pte_t *ptep, unsigned long ea,
2033	bool is_exec, unsigned long trap)
2034	{
2035	unsigned long vsid;
2036	pgd_t *pgdir;
2037	int rc, ssize, update_flags = 0;
2038	unsigned long access = _PAGE_PRESENT | _PAGE_READ | (is_exec ? _PAGE_EXEC : 0);
2039	unsigned long flags;
2040
2041	BUG_ON(get_region_id(ea) != USER_REGION_ID);
2042
2043	if (!should_hash_preload(mm, ea))
2044	return;
2045
2046	DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx,"
2047	" trap=%lx\n", mm, mm->pgd, ea, access, trap);
2048
2049	/* Get Linux PTE if available */
2050	pgdir = mm->pgd;
2051	if (pgdir == NULL)
2052	return;
2053
2054	/* Get VSID */
2055	ssize = user_segment_size(ea);
2056	vsid = get_user_vsid(&mm->context, ea, ssize);
2057	if (!vsid)
2058	return;
2059
2060	#ifdef CONFIG_PPC_64K_PAGES
2061	/* If either H_PAGE_4K_PFN or cache inhibited is set (and we are on
2062	* a 64K kernel), then we don't preload, hash_page() will take
2063	* care of it once we actually try to access the page.
2064	* That way we don't have to duplicate all of the logic for segment
2065	* page size demotion here
2066	* Called with PTL held, hence can be sure the value won't change in
2067	* between.
2068	*/
2069	if ((pte_val(*ptep) & H_PAGE_4K_PFN) || pte_ci(*ptep))
2070	return;
2071	#endif /* CONFIG_PPC_64K_PAGES */
2072
2073	/*
2074	* __hash_page_* must run with interrupts off, including PMI interrupts
2075	* off, as it sets the H_PAGE_BUSY bit.
2076	*
2077	* It's otherwise possible for perf interrupts to hit at any time and
2078	* may take a hash fault reading the user stack, which could take a
2079	* hash miss and deadlock on the same H_PAGE_BUSY bit.
2080	*
2081	* Interrupts must also be off for the duration of the
2082	* mm_is_thread_local test and update, to prevent preempt running the
2083	* mm on another CPU (XXX: this may be racy vs kthread_use_mm).
2084	*/
2085	powerpc_local_irq_pmu_save(flags);
2086
2087	/* Is that local to this CPU ? */
2088	if (mm_is_thread_local(mm))
2089	update_flags |= HPTE_LOCAL_UPDATE;
2090
2091	/* Hash it in */
2092	#ifdef CONFIG_PPC_64K_PAGES
2093	if (mm_ctx_user_psize(&mm->context) == MMU_PAGE_64K)
2094	rc = __hash_page_64K(ea, access, vsid, ptep, trap,
2095	update_flags, ssize);
2096	else
2097	#endif /* CONFIG_PPC_64K_PAGES */
2098	rc = __hash_page_4K(ea, access, vsid, ptep, trap, update_flags,
2099	ssize, subpage_protection(mm, ea));
2100
2101	/* Dump some info in case of hash insertion failure, they should
2102	* never happen so it is really useful to know if/when they do
2103	*/
2104	if (rc == -1)
2105	hash_failure_debug(ea, access, vsid, trap, ssize,
2106	psize: mm_ctx_user_psize(&mm->context),
2107	lpsize: mm_ctx_user_psize(&mm->context),
2108	pte: pte_val(pte: *ptep));
2109
2110	powerpc_local_irq_pmu_restore(flags);
2111	}
2112
2113	/*
2114	* This is called at the end of handling a user page fault, when the
2115	* fault has been handled by updating a PTE in the linux page tables.
2116	* We use it to preload an HPTE into the hash table corresponding to
2117	* the updated linux PTE.
2118	*
2119	* This must always be called with the pte lock held.
2120	*/
2121	void __update_mmu_cache(struct vm_area_struct *vma, unsigned long address,
2122	pte_t *ptep)
2123	{
2124	/*
2125	* We don't need to worry about _PAGE_PRESENT here because we are
2126	* called with either mm->page_table_lock held or ptl lock held
2127	*/
2128	unsigned long trap;
2129	bool is_exec;
2130
2131	/* We only want HPTEs for linux PTEs that have _PAGE_ACCESSED set */
2132	if (!pte_young(pte: *ptep) || address >= TASK_SIZE)
2133	return;
2134
2135	/*
2136	* We try to figure out if we are coming from an instruction
2137	* access fault and pass that down to __hash_page so we avoid
2138	* double-faulting on execution of fresh text. We have to test
2139	* for regs NULL since init will get here first thing at boot.
2140	*
2141	* We also avoid filling the hash if not coming from a fault.
2142	*/
2143
2144	trap = current->thread.regs ? TRAP(current->thread.regs) : 0UL;
2145	switch (trap) {
2146	case 0x300:
2147	is_exec = false;
2148	break;
2149	case 0x400:
2150	is_exec = true;
2151	break;
2152	default:
2153	return;
2154	}
2155
2156	hash_preload(mm: vma->vm_mm, ptep, ea: address, is_exec, trap);
2157	}
2158
2159	#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2160	static inline void tm_flush_hash_page(int local)
2161	{
2162	/*
2163	* Transactions are not aborted by tlbiel, only tlbie. Without, syncing a
2164	* page back to a block device w/PIO could pick up transactional data
2165	* (bad!) so we force an abort here. Before the sync the page will be
2166	* made read-only, which will flush_hash_page. BIG ISSUE here: if the
2167	* kernel uses a page from userspace without unmapping it first, it may
2168	* see the speculated version.
2169	*/
2170	if (local && cpu_has_feature(CPU_FTR_TM) && current->thread.regs &&
2171	MSR_TM_ACTIVE(current->thread.regs->msr)) {
2172	tm_enable();
2173	tm_abort(TM_CAUSE_TLBI);
2174	}
2175	}
2176	#else
2177	static inline void tm_flush_hash_page(int local)
2178	{
2179	}
2180	#endif
2181
2182	/*
2183	* Return the global hash slot, corresponding to the given PTE, which contains
2184	* the HPTE.
2185	*/
2186	unsigned long pte_get_hash_gslot(unsigned long vpn, unsigned long shift,
2187	int ssize, real_pte_t rpte, unsigned int subpg_index)
2188	{
2189	unsigned long hash, gslot, hidx;
2190
2191	hash = hpt_hash(vpn, shift, ssize);
2192	hidx = __rpte_to_hidx(rpte, subpg_index);
2193	if (hidx & _PTEIDX_SECONDARY)
2194	hash = ~hash;
2195	gslot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
2196	gslot += hidx & _PTEIDX_GROUP_IX;
2197	return gslot;
2198	}
2199
2200	void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize, int ssize,
2201	unsigned long flags)
2202	{
2203	unsigned long index, shift, gslot;
2204	int local = flags & HPTE_LOCAL_UPDATE;
2205
2206	DBG_LOW("flush_hash_page(vpn=%016lx)\n", vpn);
2207	pte_iterate_hashed_subpages(pte, psize, vpn, index, shift) {
2208	gslot = pte_get_hash_gslot(vpn, shift, ssize, pte, index);
2209	DBG_LOW(" sub %ld: gslot=%lx\n", index, gslot);
2210	/*
2211	* We use same base page size and actual psize, because we don't
2212	* use these functions for hugepage
2213	*/
2214	mmu_hash_ops.hpte_invalidate(gslot, vpn, psize, psize,
2215	ssize, local);
2216	} pte_iterate_hashed_end();
2217
2218	tm_flush_hash_page(local);
2219	}
2220
2221	#ifdef CONFIG_TRANSPARENT_HUGEPAGE
2222	void flush_hash_hugepage(unsigned long vsid, unsigned long addr,
2223	pmd_t *pmdp, unsigned int psize, int ssize,
2224	unsigned long flags)
2225	{
2226	int i, max_hpte_count, valid;
2227	unsigned long s_addr;
2228	unsigned char *hpte_slot_array;
2229	unsigned long hidx, shift, vpn, hash, slot;
2230	int local = flags & HPTE_LOCAL_UPDATE;
2231
2232	s_addr = addr & HPAGE_PMD_MASK;
2233	hpte_slot_array = get_hpte_slot_array(pmdp);
2234	/*
2235	* IF we try to do a HUGE PTE update after a withdraw is done.
2236	* we will find the below NULL. This happens when we do
2237	* split_huge_pmd
2238	*/
2239	if (!hpte_slot_array)
2240	return;
2241
2242	if (mmu_hash_ops.hugepage_invalidate) {
2243	mmu_hash_ops.hugepage_invalidate(vsid, s_addr, hpte_slot_array,
2244	psize, ssize, local);
2245	goto tm_abort;
2246	}
2247	/*
2248	* No bluk hpte removal support, invalidate each entry
2249	*/
2250	shift = mmu_psize_defs[psize].shift;
2251	max_hpte_count = HPAGE_PMD_SIZE >> shift;
2252	for (i = 0; i < max_hpte_count; i++) {
2253	/*
2254	* 8 bits per each hpte entries
2255	* 000| [ secondary group (one bit) | hidx (3 bits) | valid bit]
2256	*/
2257	valid = hpte_valid(hpte_slot_array, i);
2258	if (!valid)
2259	continue;
2260	hidx = hpte_hash_index(hpte_slot_array, i);
2261
2262	/* get the vpn */
2263	addr = s_addr + (i * (1ul << shift));
2264	vpn = hpt_vpn(addr, vsid, ssize);
2265	hash = hpt_hash(vpn, shift, ssize);
2266	if (hidx & _PTEIDX_SECONDARY)
2267	hash = ~hash;
2268
2269	slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
2270	slot += hidx & _PTEIDX_GROUP_IX;
2271	mmu_hash_ops.hpte_invalidate(slot, vpn, psize,
2272	MMU_PAGE_16M, ssize, local);
2273	}
2274	tm_abort:
2275	tm_flush_hash_page(local);
2276	}
2277	#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
2278
2279	void flush_hash_range(unsigned long number, int local)
2280	{
2281	if (mmu_hash_ops.flush_hash_range)
2282	mmu_hash_ops.flush_hash_range(number, local);
2283	else {
2284	int i;
2285	struct ppc64_tlb_batch *batch =
2286	this_cpu_ptr(&ppc64_tlb_batch);
2287
2288	for (i = 0; i < number; i++)
2289	flush_hash_page(batch->vpn[i], batch->pte[i],
2290	batch->psize, batch->ssize, local);
2291	}
2292	}
2293
2294	long hpte_insert_repeating(unsigned long hash, unsigned long vpn,
2295	unsigned long pa, unsigned long rflags,
2296	unsigned long vflags, int psize, int ssize)
2297	{
2298	unsigned long hpte_group;
2299	long slot;
2300
2301	repeat:
2302	hpte_group = (hash & htab_hash_mask) * HPTES_PER_GROUP;
2303
2304	/* Insert into the hash table, primary slot */
2305	slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags, vflags,
2306	psize, psize, ssize);
2307
2308	/* Primary is full, try the secondary */
2309	if (unlikely(slot == -1)) {
2310	hpte_group = (~hash & htab_hash_mask) * HPTES_PER_GROUP;
2311	slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags,
2312	vflags | HPTE_V_SECONDARY,
2313	psize, psize, ssize);
2314	if (slot == -1) {
2315	if (mftb() & 0x1)
2316	hpte_group = (hash & htab_hash_mask) *
2317	HPTES_PER_GROUP;
2318
2319	mmu_hash_ops.hpte_remove(hpte_group);
2320	goto repeat;
2321	}
2322	}
2323
2324	return slot;
2325	}
2326
2327	void hpt_clear_stress(void)
2328	{
2329	int cpu = raw_smp_processor_id();
2330	int g;
2331
2332	for (g = 0; g < stress_nr_groups(); g++) {
2333	unsigned long last_group;
2334	last_group = stress_hpt_struct[cpu].last_group[g];
2335
2336	if (last_group != -1UL) {
2337	int i;
2338	for (i = 0; i < HPTES_PER_GROUP; i++) {
2339	if (mmu_hash_ops.hpte_remove(last_group) == -1)
2340	break;
2341	}
2342	stress_hpt_struct[cpu].last_group[g] = -1;
2343	}
2344	}
2345	}
2346
2347	void hpt_do_stress(unsigned long ea, unsigned long hpte_group)
2348	{
2349	unsigned long last_group;
2350	int cpu = raw_smp_processor_id();
2351
2352	last_group = stress_hpt_struct[cpu].last_group[stress_nr_groups() - 1];
2353	if (hpte_group == last_group)
2354	return;
2355
2356	if (last_group != -1UL) {
2357	int i;
2358	/*
2359	* Concurrent CPUs might be inserting into this group, so
2360	* give up after a number of iterations, to prevent a live
2361	* lock.
2362	*/
2363	for (i = 0; i < HPTES_PER_GROUP; i++) {
2364	if (mmu_hash_ops.hpte_remove(last_group) == -1)
2365	break;
2366	}
2367	stress_hpt_struct[cpu].last_group[stress_nr_groups() - 1] = -1;
2368	}
2369
2370	if (ea >= PAGE_OFFSET) {
2371	/*
2372	* We would really like to prefetch to get the TLB loaded, then
2373	* remove the PTE before returning from fault interrupt, to
2374	* increase the hash fault rate.
2375	*
2376	* Unfortunately QEMU TCG does not model the TLB in a way that
2377	* makes this possible, and systemsim (mambo) emulator does not
2378	* bring in TLBs with prefetches (although loads/stores do
2379	* work for non-CI PTEs).
2380	*
2381	* So remember this PTE and clear it on the next hash fault.
2382	*/
2383	memmove(&stress_hpt_struct[cpu].last_group[1],
2384	&stress_hpt_struct[cpu].last_group[0],
2385	(stress_nr_groups() - 1) * sizeof(unsigned long));
2386	stress_hpt_struct[cpu].last_group[0] = hpte_group;
2387	}
2388	}
2389
2390	void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base,
2391	phys_addr_t first_memblock_size)
2392	{
2393	/*
2394	* We don't currently support the first MEMBLOCK not mapping 0
2395	* physical on those processors
2396	*/
2397	BUG_ON(first_memblock_base != 0);
2398
2399	/*
2400	* On virtualized systems the first entry is our RMA region aka VRMA,
2401	* non-virtualized 64-bit hash MMU systems don't have a limitation
2402	* on real mode access.
2403	*
2404	* For guests on platforms before POWER9, we clamp the it limit to 1G
2405	* to avoid some funky things such as RTAS bugs etc...
2406	*
2407	* On POWER9 we limit to 1TB in case the host erroneously told us that
2408	* the RMA was >1TB. Effective address bits 0:23 are treated as zero
2409	* (meaning the access is aliased to zero i.e. addr = addr % 1TB)
2410	* for virtual real mode addressing and so it doesn't make sense to
2411	* have an area larger than 1TB as it can't be addressed.
2412	*/
2413	if (!early_cpu_has_feature(CPU_FTR_HVMODE)) {
2414	ppc64_rma_size = first_memblock_size;
2415	if (!early_cpu_has_feature(CPU_FTR_ARCH_300))
2416	ppc64_rma_size = min_t(u64, ppc64_rma_size, 0x40000000);
2417	else
2418	ppc64_rma_size = min_t(u64, ppc64_rma_size,
2419	1UL << SID_SHIFT_1T);
2420
2421	/* Finally limit subsequent allocations */
2422	memblock_set_current_limit(ppc64_rma_size);
2423	} else {
2424	ppc64_rma_size = ULONG_MAX;
2425	}
2426	}
2427
2428	#ifdef CONFIG_DEBUG_FS
2429
2430	static int hpt_order_get(void *data, u64 *val)
2431	{
2432	*val = ppc64_pft_size;
2433	return 0;
2434	}
2435
2436	static int hpt_order_set(void *data, u64 val)
2437	{
2438	int ret;
2439
2440	if (!mmu_hash_ops.resize_hpt)
2441	return -ENODEV;
2442
2443	cpus_read_lock();
2444	ret = mmu_hash_ops.resize_hpt(val);
2445	cpus_read_unlock();
2446
2447	return ret;
2448	}
2449
2450	DEFINE_DEBUGFS_ATTRIBUTE(fops_hpt_order, hpt_order_get, hpt_order_set, "%llu\n");
2451
2452	static int __init hash64_debugfs(void)
2453	{
2454	if (radix_enabled())
2455	return 0;
2456	debugfs_create_file("hpt_order", 0600, arch_debugfs_dir, NULL,
2457	&fops_hpt_order);
2458	return 0;
2459	}
2460	machine_device_initcall(pseries, hash64_debugfs);
2461	#endif /* CONFIG_DEBUG_FS */
2462
2463	void __init print_system_hash_info(void)
2464	{
2465	pr_info("ppc64_pft_size = 0x%llx\n", ppc64_pft_size);
2466
2467	if (htab_hash_mask)
2468	pr_info("htab_hash_mask = 0x%lx\n", htab_hash_mask);
2469	}
2470
2471	unsigned long arch_randomize_brk(struct mm_struct *mm)
2472	{
2473	/*
2474	* If we are using 1TB segments and we are allowed to randomise
2475	* the heap, we can put it above 1TB so it is backed by a 1TB
2476	* segment. Otherwise the heap will be in the bottom 1TB
2477	* which always uses 256MB segments and this may result in a
2478	* performance penalty.
2479	*/
2480	if (is_32bit_task())
2481	return randomize_page(start: mm->brk, SZ_32M);
2482	else if (!radix_enabled() && mmu_highuser_ssize == MMU_SEGSIZE_1T)
2483	return randomize_page(max_t(unsigned long, mm->brk, SZ_1T), SZ_1G);
2484	else
2485	return randomize_page(start: mm->brk, SZ_1G);
2486	}
2487