1	/*
2	* Copyright 2014 Advanced Micro Devices, Inc.
3	*
4	* Permission is hereby granted, free of charge, to any person obtaining a
5	* copy of this software and associated documentation files (the "Software"),
6	* to deal in the Software without restriction, including without limitation
7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8	* and/or sell copies of the Software, and to permit persons to whom the
9	* Software is furnished to do so, subject to the following conditions:
10	*
11	* The above copyright notice and this permission notice shall be included in
12	* all copies or substantial portions of the Software.
13	*
14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20	* OTHER DEALINGS IN THE SOFTWARE.
21	*
22	*/
23
24	#include <drm/drm_edid.h>
25	#include <drm/drm_fourcc.h>
26	#include <drm/drm_modeset_helper.h>
27	#include <drm/drm_modeset_helper_vtables.h>
28	#include <drm/drm_vblank.h>
29
30	#include "amdgpu.h"
31	#include "amdgpu_pm.h"
32	#include "amdgpu_i2c.h"
33	#include "vid.h"
34	#include "atom.h"
35	#include "amdgpu_atombios.h"
36	#include "atombios_crtc.h"
37	#include "atombios_encoders.h"
38	#include "amdgpu_pll.h"
39	#include "amdgpu_connectors.h"
40	#include "amdgpu_display.h"
41	#include "dce_v11_0.h"
42
43	#include "dce/dce_11_0_d.h"
44	#include "dce/dce_11_0_sh_mask.h"
45	#include "dce/dce_11_0_enum.h"
46	#include "oss/oss_3_0_d.h"
47	#include "oss/oss_3_0_sh_mask.h"
48	#include "gmc/gmc_8_1_d.h"
49	#include "gmc/gmc_8_1_sh_mask.h"
50
51	#include "ivsrcid/ivsrcid_vislands30.h"
52
53	static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev);
54	static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev);
55	static void dce_v11_0_hpd_int_ack(struct amdgpu_device *adev, int hpd);
56
57	static const u32 crtc_offsets[] =
58	{
59	CRTC0_REGISTER_OFFSET,
60	CRTC1_REGISTER_OFFSET,
61	CRTC2_REGISTER_OFFSET,
62	CRTC3_REGISTER_OFFSET,
63	CRTC4_REGISTER_OFFSET,
64	CRTC5_REGISTER_OFFSET,
65	CRTC6_REGISTER_OFFSET
66	};
67
68	static const u32 hpd_offsets[] =
69	{
70	HPD0_REGISTER_OFFSET,
71	HPD1_REGISTER_OFFSET,
72	HPD2_REGISTER_OFFSET,
73	HPD3_REGISTER_OFFSET,
74	HPD4_REGISTER_OFFSET,
75	HPD5_REGISTER_OFFSET
76	};
77
78	static const uint32_t dig_offsets[] = {
79	DIG0_REGISTER_OFFSET,
80	DIG1_REGISTER_OFFSET,
81	DIG2_REGISTER_OFFSET,
82	DIG3_REGISTER_OFFSET,
83	DIG4_REGISTER_OFFSET,
84	DIG5_REGISTER_OFFSET,
85	DIG6_REGISTER_OFFSET,
86	DIG7_REGISTER_OFFSET,
87	DIG8_REGISTER_OFFSET
88	};
89
90	static const struct {
91	uint32_t reg;
92	uint32_t vblank;
93	uint32_t vline;
94	uint32_t hpd;
95
96	} interrupt_status_offsets[] = { {
97	.reg = mmDISP_INTERRUPT_STATUS,
98	.vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
99	.vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
100	.hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
101	}, {
102	.reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
103	.vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
104	.vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
105	.hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
106	}, {
107	.reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
108	.vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
109	.vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
110	.hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
111	}, {
112	.reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
113	.vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
114	.vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
115	.hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
116	}, {
117	.reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
118	.vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
119	.vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
120	.hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
121	}, {
122	.reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
123	.vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
124	.vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
125	.hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
126	} };
127
128	static const u32 cz_golden_settings_a11[] =
129	{
130	mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
131	mmFBC_MISC, 0x1f311fff, 0x14300000,
132	};
133
134	static const u32 cz_mgcg_cgcg_init[] =
135	{
136	mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
137	mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
138	};
139
140	static const u32 stoney_golden_settings_a11[] =
141	{
142	mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
143	mmFBC_MISC, 0x1f311fff, 0x14302000,
144	};
145
146	static const u32 polaris11_golden_settings_a11[] =
147	{
148	mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
149	mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
150	mmFBC_DEBUG1, 0xffffffff, 0x00000008,
151	mmFBC_MISC, 0x9f313fff, 0x14302008,
152	mmHDMI_CONTROL, 0x313f031f, 0x00000011,
153	};
154
155	static const u32 polaris10_golden_settings_a11[] =
156	{
157	mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
158	mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
159	mmFBC_MISC, 0x9f313fff, 0x14302008,
160	mmHDMI_CONTROL, 0x313f031f, 0x00000011,
161	};
162
163	static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev)
164	{
165	switch (adev->asic_type) {
166	case CHIP_CARRIZO:
167	amdgpu_device_program_register_sequence(adev,
168	registers: cz_mgcg_cgcg_init,
169	ARRAY_SIZE(cz_mgcg_cgcg_init));
170	amdgpu_device_program_register_sequence(adev,
171	registers: cz_golden_settings_a11,
172	ARRAY_SIZE(cz_golden_settings_a11));
173	break;
174	case CHIP_STONEY:
175	amdgpu_device_program_register_sequence(adev,
176	registers: stoney_golden_settings_a11,
177	ARRAY_SIZE(stoney_golden_settings_a11));
178	break;
179	case CHIP_POLARIS11:
180	case CHIP_POLARIS12:
181	amdgpu_device_program_register_sequence(adev,
182	registers: polaris11_golden_settings_a11,
183	ARRAY_SIZE(polaris11_golden_settings_a11));
184	break;
185	case CHIP_POLARIS10:
186	case CHIP_VEGAM:
187	amdgpu_device_program_register_sequence(adev,
188	registers: polaris10_golden_settings_a11,
189	ARRAY_SIZE(polaris10_golden_settings_a11));
190	break;
191	default:
192	break;
193	}
194	}
195
196	static u32 dce_v11_0_audio_endpt_rreg(struct amdgpu_device *adev,
197	u32 block_offset, u32 reg)
198	{
199	unsigned long flags;
200	u32 r;
201
202	spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
203	WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
204	r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
205	spin_unlock_irqrestore(lock: &adev->audio_endpt_idx_lock, flags);
206
207	return r;
208	}
209
210	static void dce_v11_0_audio_endpt_wreg(struct amdgpu_device *adev,
211	u32 block_offset, u32 reg, u32 v)
212	{
213	unsigned long flags;
214
215	spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
216	WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
217	WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
218	spin_unlock_irqrestore(lock: &adev->audio_endpt_idx_lock, flags);
219	}
220
221	static u32 dce_v11_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
222	{
223	if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
224	return 0;
225	else
226	return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
227	}
228
229	static void dce_v11_0_pageflip_interrupt_init(struct amdgpu_device *adev)
230	{
231	unsigned i;
232
233	/* Enable pflip interrupts */
234	for (i = 0; i < adev->mode_info.num_crtc; i++)
235	amdgpu_irq_get(adev, src: &adev->pageflip_irq, type: i);
236	}
237
238	static void dce_v11_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
239	{
240	unsigned i;
241
242	/* Disable pflip interrupts */
243	for (i = 0; i < adev->mode_info.num_crtc; i++)
244	amdgpu_irq_put(adev, src: &adev->pageflip_irq, type: i);
245	}
246
247	/**
248	* dce_v11_0_page_flip - pageflip callback.
249	*
250	* @adev: amdgpu_device pointer
251	* @crtc_id: crtc to cleanup pageflip on
252	* @crtc_base: new address of the crtc (GPU MC address)
253	* @async: asynchronous flip
254	*
255	* Triggers the actual pageflip by updating the primary
256	* surface base address.
257	*/
258	static void dce_v11_0_page_flip(struct amdgpu_device *adev,
259	int crtc_id, u64 crtc_base, bool async)
260	{
261	struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
262	struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;
263	u32 tmp;
264
265	/* flip immediate for async, default is vsync */
266	tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
267	tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
268	GRPH_SURFACE_UPDATE_IMMEDIATE_EN, async ? 1 : 0);
269	WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
270	/* update pitch */
271	WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
272	fb->pitches[0] / fb->format->cpp[0]);
273	/* update the scanout addresses */
274	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
275	upper_32_bits(crtc_base));
276	/* writing to the low address triggers the update */
277	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
278	lower_32_bits(crtc_base));
279	/* post the write */
280	RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
281	}
282
283	static int dce_v11_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
284	u32 *vbl, u32 *position)
285	{
286	if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
287	return -EINVAL;
288
289	*vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
290	*position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
291
292	return 0;
293	}
294
295	/**
296	* dce_v11_0_hpd_sense - hpd sense callback.
297	*
298	* @adev: amdgpu_device pointer
299	* @hpd: hpd (hotplug detect) pin
300	*
301	* Checks if a digital monitor is connected (evergreen+).
302	* Returns true if connected, false if not connected.
303	*/
304	static bool dce_v11_0_hpd_sense(struct amdgpu_device *adev,
305	enum amdgpu_hpd_id hpd)
306	{
307	bool connected = false;
308
309	if (hpd >= adev->mode_info.num_hpd)
310	return connected;
311
312	if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) &
313	DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK)
314	connected = true;
315
316	return connected;
317	}
318
319	/**
320	* dce_v11_0_hpd_set_polarity - hpd set polarity callback.
321	*
322	* @adev: amdgpu_device pointer
323	* @hpd: hpd (hotplug detect) pin
324	*
325	* Set the polarity of the hpd pin (evergreen+).
326	*/
327	static void dce_v11_0_hpd_set_polarity(struct amdgpu_device *adev,
328	enum amdgpu_hpd_id hpd)
329	{
330	u32 tmp;
331	bool connected = dce_v11_0_hpd_sense(adev, hpd);
332
333	if (hpd >= adev->mode_info.num_hpd)
334	return;
335
336	tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
337	if (connected)
338	tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
339	else
340	tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
341	WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
342	}
343
344	/**
345	* dce_v11_0_hpd_init - hpd setup callback.
346	*
347	* @adev: amdgpu_device pointer
348	*
349	* Setup the hpd pins used by the card (evergreen+).
350	* Enable the pin, set the polarity, and enable the hpd interrupts.
351	*/
352	static void dce_v11_0_hpd_init(struct amdgpu_device *adev)
353	{
354	struct drm_device *dev = adev_to_drm(adev);
355	struct drm_connector *connector;
356	struct drm_connector_list_iter iter;
357	u32 tmp;
358
359	drm_connector_list_iter_begin(dev, iter: &iter);
360	drm_for_each_connector_iter(connector, &iter) {
361	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
362
363	if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
364	continue;
365
366	if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
367	connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
368	/* don't try to enable hpd on eDP or LVDS avoid breaking the
369	* aux dp channel on imac and help (but not completely fix)
370	* https://bugzilla.redhat.com/show_bug.cgi?id=726143
371	* also avoid interrupt storms during dpms.
372	*/
373	tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
374	tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
375	WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
376	continue;
377	}
378
379	tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
380	tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
381	WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
382
383	tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]);
384	tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
385	DC_HPD_CONNECT_INT_DELAY,
386	AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS);
387	tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
388	DC_HPD_DISCONNECT_INT_DELAY,
389	AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
390	WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
391
392	dce_v11_0_hpd_int_ack(adev, hpd: amdgpu_connector->hpd.hpd);
393	dce_v11_0_hpd_set_polarity(adev, hpd: amdgpu_connector->hpd.hpd);
394	amdgpu_irq_get(adev, src: &adev->hpd_irq, type: amdgpu_connector->hpd.hpd);
395	}
396	drm_connector_list_iter_end(iter: &iter);
397	}
398
399	/**
400	* dce_v11_0_hpd_fini - hpd tear down callback.
401	*
402	* @adev: amdgpu_device pointer
403	*
404	* Tear down the hpd pins used by the card (evergreen+).
405	* Disable the hpd interrupts.
406	*/
407	static void dce_v11_0_hpd_fini(struct amdgpu_device *adev)
408	{
409	struct drm_device *dev = adev_to_drm(adev);
410	struct drm_connector *connector;
411	struct drm_connector_list_iter iter;
412	u32 tmp;
413
414	drm_connector_list_iter_begin(dev, iter: &iter);
415	drm_for_each_connector_iter(connector, &iter) {
416	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
417
418	if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
419	continue;
420
421	tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
422	tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
423	WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
424
425	amdgpu_irq_put(adev, src: &adev->hpd_irq, type: amdgpu_connector->hpd.hpd);
426	}
427	drm_connector_list_iter_end(iter: &iter);
428	}
429
430	static u32 dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
431	{
432	return mmDC_GPIO_HPD_A;
433	}
434
435	static bool dce_v11_0_is_display_hung(struct amdgpu_device *adev)
436	{
437	u32 crtc_hung = 0;
438	u32 crtc_status[6];
439	u32 i, j, tmp;
440
441	for (i = 0; i < adev->mode_info.num_crtc; i++) {
442	tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
443	if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
444	crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
445	crtc_hung |= (1 << i);
446	}
447	}
448
449	for (j = 0; j < 10; j++) {
450	for (i = 0; i < adev->mode_info.num_crtc; i++) {
451	if (crtc_hung & (1 << i)) {
452	tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
453	if (tmp != crtc_status[i])
454	crtc_hung &= ~(1 << i);
455	}
456	}
457	if (crtc_hung == 0)
458	return false;
459	udelay(100);
460	}
461
462	return true;
463	}
464
465	static void dce_v11_0_set_vga_render_state(struct amdgpu_device *adev,
466	bool render)
467	{
468	u32 tmp;
469
470	/* Lockout access through VGA aperture*/
471	tmp = RREG32(mmVGA_HDP_CONTROL);
472	if (render)
473	tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
474	else
475	tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
476	WREG32(mmVGA_HDP_CONTROL, tmp);
477
478	/* disable VGA render */
479	tmp = RREG32(mmVGA_RENDER_CONTROL);
480	if (render)
481	tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
482	else
483	tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
484	WREG32(mmVGA_RENDER_CONTROL, tmp);
485	}
486
487	static int dce_v11_0_get_num_crtc (struct amdgpu_device *adev)
488	{
489	int num_crtc = 0;
490
491	switch (adev->asic_type) {
492	case CHIP_CARRIZO:
493	num_crtc = 3;
494	break;
495	case CHIP_STONEY:
496	num_crtc = 2;
497	break;
498	case CHIP_POLARIS10:
499	case CHIP_VEGAM:
500	num_crtc = 6;
501	break;
502	case CHIP_POLARIS11:
503	case CHIP_POLARIS12:
504	num_crtc = 5;
505	break;
506	default:
507	num_crtc = 0;
508	}
509	return num_crtc;
510	}
511
512	void dce_v11_0_disable_dce(struct amdgpu_device *adev)
513	{
514	/*Disable VGA render and enabled crtc, if has DCE engine*/
515	if (amdgpu_atombios_has_dce_engine_info(adev)) {
516	u32 tmp;
517	int crtc_enabled, i;
518
519	dce_v11_0_set_vga_render_state(adev, render: false);
520
521	/*Disable crtc*/
522	for (i = 0; i < dce_v11_0_get_num_crtc(adev); i++) {
523	crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
524	CRTC_CONTROL, CRTC_MASTER_EN);
525	if (crtc_enabled) {
526	WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
527	tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
528	tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
529	WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
530	WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
531	}
532	}
533	}
534	}
535
536	static void dce_v11_0_program_fmt(struct drm_encoder *encoder)
537	{
538	struct drm_device *dev = encoder->dev;
539	struct amdgpu_device *adev = drm_to_adev(ddev: dev);
540	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
541	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
542	struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
543	int bpc = 0;
544	u32 tmp = 0;
545	enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
546
547	if (connector) {
548	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
549	bpc = amdgpu_connector_get_monitor_bpc(connector);
550	dither = amdgpu_connector->dither;
551	}
552
553	/* LVDS/eDP FMT is set up by atom */
554	if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
555	return;
556
557	/* not needed for analog */
558	if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
559	(amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
560	return;
561
562	if (bpc == 0)
563	return;
564
565	switch (bpc) {
566	case 6:
567	if (dither == AMDGPU_FMT_DITHER_ENABLE) {
568	/* XXX sort out optimal dither settings */
569	tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
570	tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
571	tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
572	tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
573	} else {
574	tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
575	tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
576	}
577	break;
578	case 8:
579	if (dither == AMDGPU_FMT_DITHER_ENABLE) {
580	/* XXX sort out optimal dither settings */
581	tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
582	tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
583	tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
584	tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
585	tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
586	} else {
587	tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
588	tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
589	}
590	break;
591	case 10:
592	if (dither == AMDGPU_FMT_DITHER_ENABLE) {
593	/* XXX sort out optimal dither settings */
594	tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
595	tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
596	tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
597	tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
598	tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
599	} else {
600	tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
601	tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
602	}
603	break;
604	default:
605	/* not needed */
606	break;
607	}
608
609	WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
610	}
611
612
613	/* display watermark setup */
614	/**
615	* dce_v11_0_line_buffer_adjust - Set up the line buffer
616	*
617	* @adev: amdgpu_device pointer
618	* @amdgpu_crtc: the selected display controller
619	* @mode: the current display mode on the selected display
620	* controller
621	*
622	* Setup up the line buffer allocation for
623	* the selected display controller (CIK).
624	* Returns the line buffer size in pixels.
625	*/
626	static u32 dce_v11_0_line_buffer_adjust(struct amdgpu_device *adev,
627	struct amdgpu_crtc *amdgpu_crtc,
628	struct drm_display_mode *mode)
629	{
630	u32 tmp, buffer_alloc, i, mem_cfg;
631	u32 pipe_offset = amdgpu_crtc->crtc_id;
632	/*
633	* Line Buffer Setup
634	* There are 6 line buffers, one for each display controllers.
635	* There are 3 partitions per LB. Select the number of partitions
636	* to enable based on the display width. For display widths larger
637	* than 4096, you need use to use 2 display controllers and combine
638	* them using the stereo blender.
639	*/
640	if (amdgpu_crtc->base.enabled && mode) {
641	if (mode->crtc_hdisplay < 1920) {
642	mem_cfg = 1;
643	buffer_alloc = 2;
644	} else if (mode->crtc_hdisplay < 2560) {
645	mem_cfg = 2;
646	buffer_alloc = 2;
647	} else if (mode->crtc_hdisplay < 4096) {
648	mem_cfg = 0;
649	buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
650	} else {
651	DRM_DEBUG_KMS("Mode too big for LB!\n");
652	mem_cfg = 0;
653	buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
654	}
655	} else {
656	mem_cfg = 1;
657	buffer_alloc = 0;
658	}
659
660	tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
661	tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
662	WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
663
664	tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
665	tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
666	WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
667
668	for (i = 0; i < adev->usec_timeout; i++) {
669	tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
670	if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
671	break;
672	udelay(1);
673	}
674
675	if (amdgpu_crtc->base.enabled && mode) {
676	switch (mem_cfg) {
677	case 0:
678	default:
679	return 4096 * 2;
680	case 1:
681	return 1920 * 2;
682	case 2:
683	return 2560 * 2;
684	}
685	}
686
687	/* controller not enabled, so no lb used */
688	return 0;
689	}
690
691	/**
692	* cik_get_number_of_dram_channels - get the number of dram channels
693	*
694	* @adev: amdgpu_device pointer
695	*
696	* Look up the number of video ram channels (CIK).
697	* Used for display watermark bandwidth calculations
698	* Returns the number of dram channels
699	*/
700	static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
701	{
702	u32 tmp = RREG32(mmMC_SHARED_CHMAP);
703
704	switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
705	case 0:
706	default:
707	return 1;
708	case 1:
709	return 2;
710	case 2:
711	return 4;
712	case 3:
713	return 8;
714	case 4:
715	return 3;
716	case 5:
717	return 6;
718	case 6:
719	return 10;
720	case 7:
721	return 12;
722	case 8:
723	return 16;
724	}
725	}
726
727	struct dce10_wm_params {
728	u32 dram_channels; /* number of dram channels */
729	u32 yclk; /* bandwidth per dram data pin in kHz */
730	u32 sclk; /* engine clock in kHz */
731	u32 disp_clk; /* display clock in kHz */
732	u32 src_width; /* viewport width */
733	u32 active_time; /* active display time in ns */
734	u32 blank_time; /* blank time in ns */
735	bool interlaced; /* mode is interlaced */
736	fixed20_12 vsc; /* vertical scale ratio */
737	u32 num_heads; /* number of active crtcs */
738	u32 bytes_per_pixel; /* bytes per pixel display + overlay */
739	u32 lb_size; /* line buffer allocated to pipe */
740	u32 vtaps; /* vertical scaler taps */
741	};
742
743	/**
744	* dce_v11_0_dram_bandwidth - get the dram bandwidth
745	*
746	* @wm: watermark calculation data
747	*
748	* Calculate the raw dram bandwidth (CIK).
749	* Used for display watermark bandwidth calculations
750	* Returns the dram bandwidth in MBytes/s
751	*/
752	static u32 dce_v11_0_dram_bandwidth(struct dce10_wm_params *wm)
753	{
754	/* Calculate raw DRAM Bandwidth */
755	fixed20_12 dram_efficiency; /* 0.7 */
756	fixed20_12 yclk, dram_channels, bandwidth;
757	fixed20_12 a;
758
759	a.full = dfixed_const(1000);
760	yclk.full = dfixed_const(wm->yclk);
761	yclk.full = dfixed_div(A: yclk, B: a);
762	dram_channels.full = dfixed_const(wm->dram_channels * 4);
763	a.full = dfixed_const(10);
764	dram_efficiency.full = dfixed_const(7);
765	dram_efficiency.full = dfixed_div(A: dram_efficiency, B: a);
766	bandwidth.full = dfixed_mul(dram_channels, yclk);
767	bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
768
769	return dfixed_trunc(bandwidth);
770	}
771
772	/**
773	* dce_v11_0_dram_bandwidth_for_display - get the dram bandwidth for display
774	*
775	* @wm: watermark calculation data
776	*
777	* Calculate the dram bandwidth used for display (CIK).
778	* Used for display watermark bandwidth calculations
779	* Returns the dram bandwidth for display in MBytes/s
780	*/
781	static u32 dce_v11_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
782	{
783	/* Calculate DRAM Bandwidth and the part allocated to display. */
784	fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
785	fixed20_12 yclk, dram_channels, bandwidth;
786	fixed20_12 a;
787
788	a.full = dfixed_const(1000);
789	yclk.full = dfixed_const(wm->yclk);
790	yclk.full = dfixed_div(A: yclk, B: a);
791	dram_channels.full = dfixed_const(wm->dram_channels * 4);
792	a.full = dfixed_const(10);
793	disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
794	disp_dram_allocation.full = dfixed_div(A: disp_dram_allocation, B: a);
795	bandwidth.full = dfixed_mul(dram_channels, yclk);
796	bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
797
798	return dfixed_trunc(bandwidth);
799	}
800
801	/**
802	* dce_v11_0_data_return_bandwidth - get the data return bandwidth
803	*
804	* @wm: watermark calculation data
805	*
806	* Calculate the data return bandwidth used for display (CIK).
807	* Used for display watermark bandwidth calculations
808	* Returns the data return bandwidth in MBytes/s
809	*/
810	static u32 dce_v11_0_data_return_bandwidth(struct dce10_wm_params *wm)
811	{
812	/* Calculate the display Data return Bandwidth */
813	fixed20_12 return_efficiency; /* 0.8 */
814	fixed20_12 sclk, bandwidth;
815	fixed20_12 a;
816
817	a.full = dfixed_const(1000);
818	sclk.full = dfixed_const(wm->sclk);
819	sclk.full = dfixed_div(A: sclk, B: a);
820	a.full = dfixed_const(10);
821	return_efficiency.full = dfixed_const(8);
822	return_efficiency.full = dfixed_div(A: return_efficiency, B: a);
823	a.full = dfixed_const(32);
824	bandwidth.full = dfixed_mul(a, sclk);
825	bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
826
827	return dfixed_trunc(bandwidth);
828	}
829
830	/**
831	* dce_v11_0_dmif_request_bandwidth - get the dmif bandwidth
832	*
833	* @wm: watermark calculation data
834	*
835	* Calculate the dmif bandwidth used for display (CIK).
836	* Used for display watermark bandwidth calculations
837	* Returns the dmif bandwidth in MBytes/s
838	*/
839	static u32 dce_v11_0_dmif_request_bandwidth(struct dce10_wm_params *wm)
840	{
841	/* Calculate the DMIF Request Bandwidth */
842	fixed20_12 disp_clk_request_efficiency; /* 0.8 */
843	fixed20_12 disp_clk, bandwidth;
844	fixed20_12 a, b;
845
846	a.full = dfixed_const(1000);
847	disp_clk.full = dfixed_const(wm->disp_clk);
848	disp_clk.full = dfixed_div(A: disp_clk, B: a);
849	a.full = dfixed_const(32);
850	b.full = dfixed_mul(a, disp_clk);
851
852	a.full = dfixed_const(10);
853	disp_clk_request_efficiency.full = dfixed_const(8);
854	disp_clk_request_efficiency.full = dfixed_div(A: disp_clk_request_efficiency, B: a);
855
856	bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
857
858	return dfixed_trunc(bandwidth);
859	}
860
861	/**
862	* dce_v11_0_available_bandwidth - get the min available bandwidth
863	*
864	* @wm: watermark calculation data
865	*
866	* Calculate the min available bandwidth used for display (CIK).
867	* Used for display watermark bandwidth calculations
868	* Returns the min available bandwidth in MBytes/s
869	*/
870	static u32 dce_v11_0_available_bandwidth(struct dce10_wm_params *wm)
871	{
872	/* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
873	u32 dram_bandwidth = dce_v11_0_dram_bandwidth(wm);
874	u32 data_return_bandwidth = dce_v11_0_data_return_bandwidth(wm);
875	u32 dmif_req_bandwidth = dce_v11_0_dmif_request_bandwidth(wm);
876
877	return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
878	}
879
880	/**
881	* dce_v11_0_average_bandwidth - get the average available bandwidth
882	*
883	* @wm: watermark calculation data
884	*
885	* Calculate the average available bandwidth used for display (CIK).
886	* Used for display watermark bandwidth calculations
887	* Returns the average available bandwidth in MBytes/s
888	*/
889	static u32 dce_v11_0_average_bandwidth(struct dce10_wm_params *wm)
890	{
891	/* Calculate the display mode Average Bandwidth
892	* DisplayMode should contain the source and destination dimensions,
893	* timing, etc.
894	*/
895	fixed20_12 bpp;
896	fixed20_12 line_time;
897	fixed20_12 src_width;
898	fixed20_12 bandwidth;
899	fixed20_12 a;
900
901	a.full = dfixed_const(1000);
902	line_time.full = dfixed_const(wm->active_time + wm->blank_time);
903	line_time.full = dfixed_div(A: line_time, B: a);
904	bpp.full = dfixed_const(wm->bytes_per_pixel);
905	src_width.full = dfixed_const(wm->src_width);
906	bandwidth.full = dfixed_mul(src_width, bpp);
907	bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
908	bandwidth.full = dfixed_div(A: bandwidth, B: line_time);
909
910	return dfixed_trunc(bandwidth);
911	}
912
913	/**
914	* dce_v11_0_latency_watermark - get the latency watermark
915	*
916	* @wm: watermark calculation data
917	*
918	* Calculate the latency watermark (CIK).
919	* Used for display watermark bandwidth calculations
920	* Returns the latency watermark in ns
921	*/
922	static u32 dce_v11_0_latency_watermark(struct dce10_wm_params *wm)
923	{
924	/* First calculate the latency in ns */
925	u32 mc_latency = 2000; /* 2000 ns. */
926	u32 available_bandwidth = dce_v11_0_available_bandwidth(wm);
927	u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
928	u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
929	u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
930	u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
931	(wm->num_heads * cursor_line_pair_return_time);
932	u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
933	u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
934	u32 tmp, dmif_size = 12288;
935	fixed20_12 a, b, c;
936
937	if (wm->num_heads == 0)
938	return 0;
939
940	a.full = dfixed_const(2);
941	b.full = dfixed_const(1);
942	if ((wm->vsc.full > a.full) ||
943	((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
944	(wm->vtaps >= 5) ||
945	((wm->vsc.full >= a.full) && wm->interlaced))
946	max_src_lines_per_dst_line = 4;
947	else
948	max_src_lines_per_dst_line = 2;
949
950	a.full = dfixed_const(available_bandwidth);
951	b.full = dfixed_const(wm->num_heads);
952	a.full = dfixed_div(A: a, B: b);
953	tmp = div_u64(dividend: (u64) dmif_size * (u64) wm->disp_clk, divisor: mc_latency + 512);
954	tmp = min(dfixed_trunc(a), tmp);
955
956	lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
957
958	a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
959	b.full = dfixed_const(1000);
960	c.full = dfixed_const(lb_fill_bw);
961	b.full = dfixed_div(A: c, B: b);
962	a.full = dfixed_div(A: a, B: b);
963	line_fill_time = dfixed_trunc(a);
964
965	if (line_fill_time < wm->active_time)
966	return latency;
967	else
968	return latency + (line_fill_time - wm->active_time);
969
970	}
971
972	/**
973	* dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display - check
974	* average and available dram bandwidth
975	*
976	* @wm: watermark calculation data
977	*
978	* Check if the display average bandwidth fits in the display
979	* dram bandwidth (CIK).
980	* Used for display watermark bandwidth calculations
981	* Returns true if the display fits, false if not.
982	*/
983	static bool dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)
984	{
985	if (dce_v11_0_average_bandwidth(wm) <=
986	(dce_v11_0_dram_bandwidth_for_display(wm) / wm->num_heads))
987	return true;
988	else
989	return false;
990	}
991
992	/**
993	* dce_v11_0_average_bandwidth_vs_available_bandwidth - check
994	* average and available bandwidth
995	*
996	* @wm: watermark calculation data
997	*
998	* Check if the display average bandwidth fits in the display
999	* available bandwidth (CIK).
1000	* Used for display watermark bandwidth calculations
1001	* Returns true if the display fits, false if not.
1002	*/
1003	static bool dce_v11_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)
1004	{
1005	if (dce_v11_0_average_bandwidth(wm) <=
1006	(dce_v11_0_available_bandwidth(wm) / wm->num_heads))
1007	return true;
1008	else
1009	return false;
1010	}
1011
1012	/**
1013	* dce_v11_0_check_latency_hiding - check latency hiding
1014	*
1015	* @wm: watermark calculation data
1016	*
1017	* Check latency hiding (CIK).
1018	* Used for display watermark bandwidth calculations
1019	* Returns true if the display fits, false if not.
1020	*/
1021	static bool dce_v11_0_check_latency_hiding(struct dce10_wm_params *wm)
1022	{
1023	u32 lb_partitions = wm->lb_size / wm->src_width;
1024	u32 line_time = wm->active_time + wm->blank_time;
1025	u32 latency_tolerant_lines;
1026	u32 latency_hiding;
1027	fixed20_12 a;
1028
1029	a.full = dfixed_const(1);
1030	if (wm->vsc.full > a.full)
1031	latency_tolerant_lines = 1;
1032	else {
1033	if (lb_partitions <= (wm->vtaps + 1))
1034	latency_tolerant_lines = 1;
1035	else
1036	latency_tolerant_lines = 2;
1037	}
1038
1039	latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1040
1041	if (dce_v11_0_latency_watermark(wm) <= latency_hiding)
1042	return true;
1043	else
1044	return false;
1045	}
1046
1047	/**
1048	* dce_v11_0_program_watermarks - program display watermarks
1049	*
1050	* @adev: amdgpu_device pointer
1051	* @amdgpu_crtc: the selected display controller
1052	* @lb_size: line buffer size
1053	* @num_heads: number of display controllers in use
1054	*
1055	* Calculate and program the display watermarks for the
1056	* selected display controller (CIK).
1057	*/
1058	static void dce_v11_0_program_watermarks(struct amdgpu_device *adev,
1059	struct amdgpu_crtc *amdgpu_crtc,
1060	u32 lb_size, u32 num_heads)
1061	{
1062	struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1063	struct dce10_wm_params wm_low, wm_high;
1064	u32 active_time;
1065	u32 line_time = 0;
1066	u32 latency_watermark_a = 0, latency_watermark_b = 0;
1067	u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
1068
1069	if (amdgpu_crtc->base.enabled && num_heads && mode) {
1070	active_time = (u32) div_u64(dividend: (u64)mode->crtc_hdisplay * 1000000,
1071	divisor: (u32)mode->clock);
1072	line_time = (u32) div_u64(dividend: (u64)mode->crtc_htotal * 1000000,
1073	divisor: (u32)mode->clock);
1074	line_time = min_t(u32, line_time, 65535);
1075
1076	/* watermark for high clocks */
1077	if (adev->pm.dpm_enabled) {
1078	wm_high.yclk =
1079	amdgpu_dpm_get_mclk(adev, low: false) * 10;
1080	wm_high.sclk =
1081	amdgpu_dpm_get_sclk(adev, low: false) * 10;
1082	} else {
1083	wm_high.yclk = adev->pm.current_mclk * 10;
1084	wm_high.sclk = adev->pm.current_sclk * 10;
1085	}
1086
1087	wm_high.disp_clk = mode->clock;
1088	wm_high.src_width = mode->crtc_hdisplay;
1089	wm_high.active_time = active_time;
1090	wm_high.blank_time = line_time - wm_high.active_time;
1091	wm_high.interlaced = false;
1092	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1093	wm_high.interlaced = true;
1094	wm_high.vsc = amdgpu_crtc->vsc;
1095	wm_high.vtaps = 1;
1096	if (amdgpu_crtc->rmx_type != RMX_OFF)
1097	wm_high.vtaps = 2;
1098	wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1099	wm_high.lb_size = lb_size;
1100	wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1101	wm_high.num_heads = num_heads;
1102
1103	/* set for high clocks */
1104	latency_watermark_a = min_t(u32, dce_v11_0_latency_watermark(&wm_high), 65535);
1105
1106	/* possibly force display priority to high */
1107	/* should really do this at mode validation time... */
1108	if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(wm: &wm_high) ||
1109	!dce_v11_0_average_bandwidth_vs_available_bandwidth(wm: &wm_high) ||
1110	!dce_v11_0_check_latency_hiding(wm: &wm_high) ||
1111	(adev->mode_info.disp_priority == 2)) {
1112	DRM_DEBUG_KMS("force priority to high\n");
1113	}
1114
1115	/* watermark for low clocks */
1116	if (adev->pm.dpm_enabled) {
1117	wm_low.yclk =
1118	amdgpu_dpm_get_mclk(adev, low: true) * 10;
1119	wm_low.sclk =
1120	amdgpu_dpm_get_sclk(adev, low: true) * 10;
1121	} else {
1122	wm_low.yclk = adev->pm.current_mclk * 10;
1123	wm_low.sclk = adev->pm.current_sclk * 10;
1124	}
1125
1126	wm_low.disp_clk = mode->clock;
1127	wm_low.src_width = mode->crtc_hdisplay;
1128	wm_low.active_time = active_time;
1129	wm_low.blank_time = line_time - wm_low.active_time;
1130	wm_low.interlaced = false;
1131	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1132	wm_low.interlaced = true;
1133	wm_low.vsc = amdgpu_crtc->vsc;
1134	wm_low.vtaps = 1;
1135	if (amdgpu_crtc->rmx_type != RMX_OFF)
1136	wm_low.vtaps = 2;
1137	wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1138	wm_low.lb_size = lb_size;
1139	wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1140	wm_low.num_heads = num_heads;
1141
1142	/* set for low clocks */
1143	latency_watermark_b = min_t(u32, dce_v11_0_latency_watermark(&wm_low), 65535);
1144
1145	/* possibly force display priority to high */
1146	/* should really do this at mode validation time... */
1147	if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(wm: &wm_low) ||
1148	!dce_v11_0_average_bandwidth_vs_available_bandwidth(wm: &wm_low) ||
1149	!dce_v11_0_check_latency_hiding(wm: &wm_low) ||
1150	(adev->mode_info.disp_priority == 2)) {
1151	DRM_DEBUG_KMS("force priority to high\n");
1152	}
1153	lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
1154	}
1155
1156	/* select wm A */
1157	wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1158	tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
1159	WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1160	tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1161	tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
1162	tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1163	WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1164	/* select wm B */
1165	tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
1166	WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1167	tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1168	tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
1169	tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1170	WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1171	/* restore original selection */
1172	WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1173
1174	/* save values for DPM */
1175	amdgpu_crtc->line_time = line_time;
1176	amdgpu_crtc->wm_high = latency_watermark_a;
1177	amdgpu_crtc->wm_low = latency_watermark_b;
1178	/* Save number of lines the linebuffer leads before the scanout */
1179	amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1180	}
1181
1182	/**
1183	* dce_v11_0_bandwidth_update - program display watermarks
1184	*
1185	* @adev: amdgpu_device pointer
1186	*
1187	* Calculate and program the display watermarks and line
1188	* buffer allocation (CIK).
1189	*/
1190	static void dce_v11_0_bandwidth_update(struct amdgpu_device *adev)
1191	{
1192	struct drm_display_mode *mode = NULL;
1193	u32 num_heads = 0, lb_size;
1194	int i;
1195
1196	amdgpu_display_update_priority(adev);
1197
1198	for (i = 0; i < adev->mode_info.num_crtc; i++) {
1199	if (adev->mode_info.crtcs[i]->base.enabled)
1200	num_heads++;
1201	}
1202	for (i = 0; i < adev->mode_info.num_crtc; i++) {
1203	mode = &adev->mode_info.crtcs[i]->base.mode;
1204	lb_size = dce_v11_0_line_buffer_adjust(adev, amdgpu_crtc: adev->mode_info.crtcs[i], mode);
1205	dce_v11_0_program_watermarks(adev, amdgpu_crtc: adev->mode_info.crtcs[i],
1206	lb_size, num_heads);
1207	}
1208	}
1209
1210	static void dce_v11_0_audio_get_connected_pins(struct amdgpu_device *adev)
1211	{
1212	int i;
1213	u32 offset, tmp;
1214
1215	for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1216	offset = adev->mode_info.audio.pin[i].offset;
1217	tmp = RREG32_AUDIO_ENDPT(offset,
1218	ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1219	if (((tmp &
1220	AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1221	AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1222	adev->mode_info.audio.pin[i].connected = false;
1223	else
1224	adev->mode_info.audio.pin[i].connected = true;
1225	}
1226	}
1227
1228	static struct amdgpu_audio_pin *dce_v11_0_audio_get_pin(struct amdgpu_device *adev)
1229	{
1230	int i;
1231
1232	dce_v11_0_audio_get_connected_pins(adev);
1233
1234	for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1235	if (adev->mode_info.audio.pin[i].connected)
1236	return &adev->mode_info.audio.pin[i];
1237	}
1238	DRM_ERROR("No connected audio pins found!\n");
1239	return NULL;
1240	}
1241
1242	static void dce_v11_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1243	{
1244	struct amdgpu_device *adev = drm_to_adev(ddev: encoder->dev);
1245	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1246	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1247	u32 tmp;
1248
1249	if (!dig || !dig->afmt || !dig->afmt->pin)
1250	return;
1251
1252	tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
1253	tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
1254	WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);
1255	}
1256
1257	static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder,
1258	struct drm_display_mode *mode)
1259	{
1260	struct drm_device *dev = encoder->dev;
1261	struct amdgpu_device *adev = drm_to_adev(ddev: dev);
1262	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1263	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1264	struct drm_connector *connector;
1265	struct drm_connector_list_iter iter;
1266	struct amdgpu_connector *amdgpu_connector = NULL;
1267	u32 tmp;
1268	int interlace = 0;
1269
1270	if (!dig || !dig->afmt || !dig->afmt->pin)
1271	return;
1272
1273	drm_connector_list_iter_begin(dev, iter: &iter);
1274	drm_for_each_connector_iter(connector, &iter) {
1275	if (connector->encoder == encoder) {
1276	amdgpu_connector = to_amdgpu_connector(connector);
1277	break;
1278	}
1279	}
1280	drm_connector_list_iter_end(iter: &iter);
1281
1282	if (!amdgpu_connector) {
1283	DRM_ERROR("Couldn't find encoder's connector\n");
1284	return;
1285	}
1286
1287	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1288	interlace = 1;
1289	if (connector->latency_present[interlace]) {
1290	tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1291	VIDEO_LIPSYNC, connector->video_latency[interlace]);
1292	tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1293	AUDIO_LIPSYNC, connector->audio_latency[interlace]);
1294	} else {
1295	tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1296	VIDEO_LIPSYNC, 0);
1297	tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1298	AUDIO_LIPSYNC, 0);
1299	}
1300	WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1301	ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1302	}
1303
1304	static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1305	{
1306	struct drm_device *dev = encoder->dev;
1307	struct amdgpu_device *adev = drm_to_adev(ddev: dev);
1308	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1309	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1310	struct drm_connector *connector;
1311	struct drm_connector_list_iter iter;
1312	struct amdgpu_connector *amdgpu_connector = NULL;
1313	u32 tmp;
1314	u8 *sadb = NULL;
1315	int sad_count;
1316
1317	if (!dig || !dig->afmt || !dig->afmt->pin)
1318	return;
1319
1320	drm_connector_list_iter_begin(dev, iter: &iter);
1321	drm_for_each_connector_iter(connector, &iter) {
1322	if (connector->encoder == encoder) {
1323	amdgpu_connector = to_amdgpu_connector(connector);
1324	break;
1325	}
1326	}
1327	drm_connector_list_iter_end(iter: &iter);
1328
1329	if (!amdgpu_connector) {
1330	DRM_ERROR("Couldn't find encoder's connector\n");
1331	return;
1332	}
1333
1334	sad_count = drm_edid_to_speaker_allocation(edid: amdgpu_connector_edid(connector), sadb: &sadb);
1335	if (sad_count < 0) {
1336	DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1337	sad_count = 0;
1338	}
1339
1340	/* program the speaker allocation */
1341	tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1342	ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1343	tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1344	DP_CONNECTION, 0);
1345	/* set HDMI mode */
1346	tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1347	HDMI_CONNECTION, 1);
1348	if (sad_count)
1349	tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1350	SPEAKER_ALLOCATION, sadb[0]);
1351	else
1352	tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1353	SPEAKER_ALLOCATION, 5); /* stereo */
1354	WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1355	ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1356
1357	kfree(objp: sadb);
1358	}
1359
1360	static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder)
1361	{
1362	struct drm_device *dev = encoder->dev;
1363	struct amdgpu_device *adev = drm_to_adev(ddev: dev);
1364	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1365	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1366	struct drm_connector *connector;
1367	struct drm_connector_list_iter iter;
1368	struct amdgpu_connector *amdgpu_connector = NULL;
1369	struct cea_sad *sads;
1370	int i, sad_count;
1371
1372	static const u16 eld_reg_to_type[][2] = {
1373	{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1374	{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1375	{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1376	{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1377	{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1378	{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1379	{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1380	{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1381	{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1382	{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1383	{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1384	{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1385	};
1386
1387	if (!dig || !dig->afmt || !dig->afmt->pin)
1388	return;
1389
1390	drm_connector_list_iter_begin(dev, iter: &iter);
1391	drm_for_each_connector_iter(connector, &iter) {
1392	if (connector->encoder == encoder) {
1393	amdgpu_connector = to_amdgpu_connector(connector);
1394	break;
1395	}
1396	}
1397	drm_connector_list_iter_end(iter: &iter);
1398
1399	if (!amdgpu_connector) {
1400	DRM_ERROR("Couldn't find encoder's connector\n");
1401	return;
1402	}
1403
1404	sad_count = drm_edid_to_sad(edid: amdgpu_connector_edid(connector), sads: &sads);
1405	if (sad_count < 0)
1406	DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1407	if (sad_count <= 0)
1408	return;
1409	BUG_ON(!sads);
1410
1411	for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1412	u32 tmp = 0;
1413	u8 stereo_freqs = 0;
1414	int max_channels = -1;
1415	int j;
1416
1417	for (j = 0; j < sad_count; j++) {
1418	struct cea_sad *sad = &sads[j];
1419
1420	if (sad->format == eld_reg_to_type[i][1]) {
1421	if (sad->channels > max_channels) {
1422	tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1423	MAX_CHANNELS, sad->channels);
1424	tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1425	DESCRIPTOR_BYTE_2, sad->byte2);
1426	tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1427	SUPPORTED_FREQUENCIES, sad->freq);
1428	max_channels = sad->channels;
1429	}
1430
1431	if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1432	stereo_freqs |= sad->freq;
1433	else
1434	break;
1435	}
1436	}
1437
1438	tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1439	SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
1440	WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
1441	}
1442
1443	kfree(objp: sads);
1444	}
1445
1446	static void dce_v11_0_audio_enable(struct amdgpu_device *adev,
1447	struct amdgpu_audio_pin *pin,
1448	bool enable)
1449	{
1450	if (!pin)
1451	return;
1452
1453	WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1454	enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1455	}
1456
1457	static const u32 pin_offsets[] =
1458	{
1459	AUD0_REGISTER_OFFSET,
1460	AUD1_REGISTER_OFFSET,
1461	AUD2_REGISTER_OFFSET,
1462	AUD3_REGISTER_OFFSET,
1463	AUD4_REGISTER_OFFSET,
1464	AUD5_REGISTER_OFFSET,
1465	AUD6_REGISTER_OFFSET,
1466	AUD7_REGISTER_OFFSET,
1467	};
1468
1469	static int dce_v11_0_audio_init(struct amdgpu_device *adev)
1470	{
1471	int i;
1472
1473	if (!amdgpu_audio)
1474	return 0;
1475
1476	adev->mode_info.audio.enabled = true;
1477
1478	switch (adev->asic_type) {
1479	case CHIP_CARRIZO:
1480	case CHIP_STONEY:
1481	adev->mode_info.audio.num_pins = 7;
1482	break;
1483	case CHIP_POLARIS10:
1484	case CHIP_VEGAM:
1485	adev->mode_info.audio.num_pins = 8;
1486	break;
1487	case CHIP_POLARIS11:
1488	case CHIP_POLARIS12:
1489	adev->mode_info.audio.num_pins = 6;
1490	break;
1491	default:
1492	return -EINVAL;
1493	}
1494
1495	for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1496	adev->mode_info.audio.pin[i].channels = -1;
1497	adev->mode_info.audio.pin[i].rate = -1;
1498	adev->mode_info.audio.pin[i].bits_per_sample = -1;
1499	adev->mode_info.audio.pin[i].status_bits = 0;
1500	adev->mode_info.audio.pin[i].category_code = 0;
1501	adev->mode_info.audio.pin[i].connected = false;
1502	adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1503	adev->mode_info.audio.pin[i].id = i;
1504	/* disable audio. it will be set up later */
1505	/* XXX remove once we switch to ip funcs */
1506	dce_v11_0_audio_enable(adev, pin: &adev->mode_info.audio.pin[i], enable: false);
1507	}
1508
1509	return 0;
1510	}
1511
1512	static void dce_v11_0_audio_fini(struct amdgpu_device *adev)
1513	{
1514	int i;
1515
1516	if (!amdgpu_audio)
1517	return;
1518
1519	if (!adev->mode_info.audio.enabled)
1520	return;
1521
1522	for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1523	dce_v11_0_audio_enable(adev, pin: &adev->mode_info.audio.pin[i], enable: false);
1524
1525	adev->mode_info.audio.enabled = false;
1526	}
1527
1528	/*
1529	* update the N and CTS parameters for a given pixel clock rate
1530	*/
1531	static void dce_v11_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1532	{
1533	struct drm_device *dev = encoder->dev;
1534	struct amdgpu_device *adev = drm_to_adev(ddev: dev);
1535	struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1536	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1537	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1538	u32 tmp;
1539
1540	tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
1541	tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1542	WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
1543	tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
1544	tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1545	WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
1546
1547	tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
1548	tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1549	WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
1550	tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
1551	tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1552	WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
1553
1554	tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
1555	tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1556	WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
1557	tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
1558	tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
1559	WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
1560
1561	}
1562
1563	/*
1564	* build a HDMI Video Info Frame
1565	*/
1566	static void dce_v11_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1567	void *buffer, size_t size)
1568	{
1569	struct drm_device *dev = encoder->dev;
1570	struct amdgpu_device *adev = drm_to_adev(ddev: dev);
1571	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1572	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1573	uint8_t *frame = buffer + 3;
1574	uint8_t *header = buffer;
1575
1576	WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
1577	frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1578	WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
1579	frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1580	WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
1581	frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1582	WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
1583	frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1584	}
1585
1586	static void dce_v11_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1587	{
1588	struct drm_device *dev = encoder->dev;
1589	struct amdgpu_device *adev = drm_to_adev(ddev: dev);
1590	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1591	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1592	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1593	u32 dto_phase = 24 * 1000;
1594	u32 dto_modulo = clock;
1595	u32 tmp;
1596
1597	if (!dig || !dig->afmt)
1598	return;
1599
1600	/* XXX two dtos; generally use dto0 for hdmi */
1601	/* Express [24MHz / target pixel clock] as an exact rational
1602	* number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
1603	* is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1604	*/
1605	tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
1606	tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
1607	amdgpu_crtc->crtc_id);
1608	WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
1609	WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1610	WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1611	}
1612
1613	/*
1614	* update the info frames with the data from the current display mode
1615	*/
1616	static void dce_v11_0_afmt_setmode(struct drm_encoder *encoder,
1617	struct drm_display_mode *mode)
1618	{
1619	struct drm_device *dev = encoder->dev;
1620	struct amdgpu_device *adev = drm_to_adev(ddev: dev);
1621	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1622	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1623	struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1624	u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1625	struct hdmi_avi_infoframe frame;
1626	ssize_t err;
1627	u32 tmp;
1628	int bpc = 8;
1629
1630	if (!dig || !dig->afmt)
1631	return;
1632
1633	/* Silent, r600_hdmi_enable will raise WARN for us */
1634	if (!dig->afmt->enabled)
1635	return;
1636
1637	/* hdmi deep color mode general control packets setup, if bpc > 8 */
1638	if (encoder->crtc) {
1639	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1640	bpc = amdgpu_crtc->bpc;
1641	}
1642
1643	/* disable audio prior to setting up hw */
1644	dig->afmt->pin = dce_v11_0_audio_get_pin(adev);
1645	dce_v11_0_audio_enable(adev, pin: dig->afmt->pin, enable: false);
1646
1647	dce_v11_0_audio_set_dto(encoder, clock: mode->clock);
1648
1649	tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1650	tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
1651	WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */
1652
1653	WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);
1654
1655	tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
1656	switch (bpc) {
1657	case 0:
1658	case 6:
1659	case 8:
1660	case 16:
1661	default:
1662	tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
1663	tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
1664	DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1665	connector->name, bpc);
1666	break;
1667	case 10:
1668	tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1669	tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
1670	DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1671	connector->name);
1672	break;
1673	case 12:
1674	tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1675	tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
1676	DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1677	connector->name);
1678	break;
1679	}
1680	WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);
1681
1682	tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1683	tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
1684	tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
1685	tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
1686	WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
1687
1688	tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1689	/* enable audio info frames (frames won't be set until audio is enabled) */
1690	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
1691	/* required for audio info values to be updated */
1692	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
1693	WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1694
1695	tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
1696	/* required for audio info values to be updated */
1697	tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1698	WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1699
1700	tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1701	/* anything other than 0 */
1702	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
1703	WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1704
1705	WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */
1706
1707	tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1708	/* set the default audio delay */
1709	tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
1710	/* should be suffient for all audio modes and small enough for all hblanks */
1711	tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
1712	WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1713
1714	tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1715	/* allow 60958 channel status fields to be updated */
1716	tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1717	WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1718
1719	tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
1720	if (bpc > 8)
1721	/* clear SW CTS value */
1722	tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
1723	else
1724	/* select SW CTS value */
1725	tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
1726	/* allow hw to sent ACR packets when required */
1727	tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
1728	WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
1729
1730	dce_v11_0_afmt_update_ACR(encoder, clock: mode->clock);
1731
1732	tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
1733	tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
1734	WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
1735
1736	tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
1737	tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1738	WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
1739
1740	tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
1741	tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
1742	tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
1743	tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
1744	tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
1745	tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
1746	tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1747	WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
1748
1749	dce_v11_0_audio_write_speaker_allocation(encoder);
1750
1751	WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,
1752	(0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1753
1754	dce_v11_0_afmt_audio_select_pin(encoder);
1755	dce_v11_0_audio_write_sad_regs(encoder);
1756	dce_v11_0_audio_write_latency_fields(encoder, mode);
1757
1758	err = drm_hdmi_avi_infoframe_from_display_mode(frame: &frame, connector, mode);
1759	if (err < 0) {
1760	DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1761	return;
1762	}
1763
1764	err = hdmi_avi_infoframe_pack(frame: &frame, buffer, size: sizeof(buffer));
1765	if (err < 0) {
1766	DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1767	return;
1768	}
1769
1770	dce_v11_0_afmt_update_avi_infoframe(encoder, buffer, size: sizeof(buffer));
1771
1772	tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1773	/* enable AVI info frames */
1774	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
1775	/* required for audio info values to be updated */
1776	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
1777	WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1778
1779	tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1780	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
1781	WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1782
1783	tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1784	/* send audio packets */
1785	tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1786	WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1787
1788	WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);
1789	WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);
1790	WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);
1791	WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);
1792
1793	/* enable audio after to setting up hw */
1794	dce_v11_0_audio_enable(adev, pin: dig->afmt->pin, enable: true);
1795	}
1796
1797	static void dce_v11_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1798	{
1799	struct drm_device *dev = encoder->dev;
1800	struct amdgpu_device *adev = drm_to_adev(ddev: dev);
1801	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1802	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1803
1804	if (!dig || !dig->afmt)
1805	return;
1806
1807	/* Silent, r600_hdmi_enable will raise WARN for us */
1808	if (enable && dig->afmt->enabled)
1809	return;
1810	if (!enable && !dig->afmt->enabled)
1811	return;
1812
1813	if (!enable && dig->afmt->pin) {
1814	dce_v11_0_audio_enable(adev, pin: dig->afmt->pin, enable: false);
1815	dig->afmt->pin = NULL;
1816	}
1817
1818	dig->afmt->enabled = enable;
1819
1820	DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1821	enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1822	}
1823
1824	static int dce_v11_0_afmt_init(struct amdgpu_device *adev)
1825	{
1826	int i;
1827
1828	for (i = 0; i < adev->mode_info.num_dig; i++)
1829	adev->mode_info.afmt[i] = NULL;
1830
1831	/* DCE11 has audio blocks tied to DIG encoders */
1832	for (i = 0; i < adev->mode_info.num_dig; i++) {
1833	adev->mode_info.afmt[i] = kzalloc(size: sizeof(struct amdgpu_afmt), GFP_KERNEL);
1834	if (adev->mode_info.afmt[i]) {
1835	adev->mode_info.afmt[i]->offset = dig_offsets[i];
1836	adev->mode_info.afmt[i]->id = i;
1837	} else {
1838	int j;
1839	for (j = 0; j < i; j++) {
1840	kfree(objp: adev->mode_info.afmt[j]);
1841	adev->mode_info.afmt[j] = NULL;
1842	}
1843	return -ENOMEM;
1844	}
1845	}
1846	return 0;
1847	}
1848
1849	static void dce_v11_0_afmt_fini(struct amdgpu_device *adev)
1850	{
1851	int i;
1852
1853	for (i = 0; i < adev->mode_info.num_dig; i++) {
1854	kfree(objp: adev->mode_info.afmt[i]);
1855	adev->mode_info.afmt[i] = NULL;
1856	}
1857	}
1858
1859	static const u32 vga_control_regs[6] =
1860	{
1861	mmD1VGA_CONTROL,
1862	mmD2VGA_CONTROL,
1863	mmD3VGA_CONTROL,
1864	mmD4VGA_CONTROL,
1865	mmD5VGA_CONTROL,
1866	mmD6VGA_CONTROL,
1867	};
1868
1869	static void dce_v11_0_vga_enable(struct drm_crtc *crtc, bool enable)
1870	{
1871	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1872	struct drm_device *dev = crtc->dev;
1873	struct amdgpu_device *adev = drm_to_adev(ddev: dev);
1874	u32 vga_control;
1875
1876	vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
1877	if (enable)
1878	WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
1879	else
1880	WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
1881	}
1882
1883	static void dce_v11_0_grph_enable(struct drm_crtc *crtc, bool enable)
1884	{
1885	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1886	struct drm_device *dev = crtc->dev;
1887	struct amdgpu_device *adev = drm_to_adev(ddev: dev);
1888
1889	if (enable)
1890	WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
1891	else
1892	WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
1893	}
1894
1895	static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc,
1896	struct drm_framebuffer *fb,
1897	int x, int y, int atomic)
1898	{
1899	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1900	struct drm_device *dev = crtc->dev;
1901	struct amdgpu_device *adev = drm_to_adev(ddev: dev);
1902	struct drm_framebuffer *target_fb;
1903	struct drm_gem_object *obj;
1904	struct amdgpu_bo *abo;
1905	uint64_t fb_location, tiling_flags;
1906	uint32_t fb_format, fb_pitch_pixels;
1907	u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
1908	u32 pipe_config;
1909	u32 tmp, viewport_w, viewport_h;
1910	int r;
1911	bool bypass_lut = false;
1912
1913	/* no fb bound */
1914	if (!atomic && !crtc->primary->fb) {
1915	DRM_DEBUG_KMS("No FB bound\n");
1916	return 0;
1917	}
1918
1919	if (atomic)
1920	target_fb = fb;
1921	else
1922	target_fb = crtc->primary->fb;
1923
1924	/* If atomic, assume fb object is pinned & idle & fenced and
1925	* just update base pointers
1926	*/
1927	obj = target_fb->obj[0];
1928	abo = gem_to_amdgpu_bo(obj);
1929	r = amdgpu_bo_reserve(bo: abo, no_intr: false);
1930	if (unlikely(r != 0))
1931	return r;
1932
1933	if (!atomic) {
1934	r = amdgpu_bo_pin(bo: abo, AMDGPU_GEM_DOMAIN_VRAM);
1935	if (unlikely(r != 0)) {
1936	amdgpu_bo_unreserve(bo: abo);
1937	return -EINVAL;
1938	}
1939	}
1940	fb_location = amdgpu_bo_gpu_offset(bo: abo);
1941
1942	amdgpu_bo_get_tiling_flags(bo: abo, tiling_flags: &tiling_flags);
1943	amdgpu_bo_unreserve(bo: abo);
1944
1945	pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1946
1947	switch (target_fb->format->format) {
1948	case DRM_FORMAT_C8:
1949	fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);
1950	fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1951	break;
1952	case DRM_FORMAT_XRGB4444:
1953	case DRM_FORMAT_ARGB4444:
1954	fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1955	fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);
1956	#ifdef __BIG_ENDIAN
1957	fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1958	ENDIAN_8IN16);
1959	#endif
1960	break;
1961	case DRM_FORMAT_XRGB1555:
1962	case DRM_FORMAT_ARGB1555:
1963	fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1964	fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1965	#ifdef __BIG_ENDIAN
1966	fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1967	ENDIAN_8IN16);
1968	#endif
1969	break;
1970	case DRM_FORMAT_BGRX5551:
1971	case DRM_FORMAT_BGRA5551:
1972	fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1973	fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);
1974	#ifdef __BIG_ENDIAN
1975	fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1976	ENDIAN_8IN16);
1977	#endif
1978	break;
1979	case DRM_FORMAT_RGB565:
1980	fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1981	fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
1982	#ifdef __BIG_ENDIAN
1983	fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1984	ENDIAN_8IN16);
1985	#endif
1986	break;
1987	case DRM_FORMAT_XRGB8888:
1988	case DRM_FORMAT_ARGB8888:
1989	fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1990	fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1991	#ifdef __BIG_ENDIAN
1992	fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1993	ENDIAN_8IN32);
1994	#endif
1995	break;
1996	case DRM_FORMAT_XRGB2101010:
1997	case DRM_FORMAT_ARGB2101010:
1998	fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1999	fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2000	#ifdef __BIG_ENDIAN
2001	fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2002	ENDIAN_8IN32);
2003	#endif
2004	/* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2005	bypass_lut = true;
2006	break;
2007	case DRM_FORMAT_BGRX1010102:
2008	case DRM_FORMAT_BGRA1010102:
2009	fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2010	fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);
2011	#ifdef __BIG_ENDIAN
2012	fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2013	ENDIAN_8IN32);
2014	#endif
2015	/* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2016	bypass_lut = true;
2017	break;
2018	case DRM_FORMAT_XBGR8888:
2019	case DRM_FORMAT_ABGR8888:
2020	fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2021	fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2022	fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_RED_CROSSBAR, 2);
2023	fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_BLUE_CROSSBAR, 2);
2024	#ifdef __BIG_ENDIAN
2025	fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2026	ENDIAN_8IN32);
2027	#endif
2028	break;
2029	default:
2030	DRM_ERROR("Unsupported screen format %p4cc\n",
2031	&target_fb->format->format);
2032	return -EINVAL;
2033	}
2034
2035	if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
2036	unsigned bankw, bankh, mtaspect, tile_split, num_banks;
2037
2038	bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2039	bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2040	mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2041	tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2042	num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2043
2044	fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
2045	fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2046	ARRAY_2D_TILED_THIN1);
2047	fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,
2048	tile_split);
2049	fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
2050	fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
2051	fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,
2052	mtaspect);
2053	fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,
2054	ADDR_SURF_MICRO_TILING_DISPLAY);
2055	} else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
2056	fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2057	ARRAY_1D_TILED_THIN1);
2058	}
2059
2060	fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,
2061	pipe_config);
2062
2063	dce_v11_0_vga_enable(crtc, enable: false);
2064
2065	/* Make sure surface address is updated at vertical blank rather than
2066	* horizontal blank
2067	*/
2068	tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
2069	tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
2070	GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
2071	WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2072
2073	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2074	upper_32_bits(fb_location));
2075	WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2076	upper_32_bits(fb_location));
2077	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2078	(u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2079	WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2080	(u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2081	WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2082	WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2083
2084	/*
2085	* The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2086	* for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2087	* retain the full precision throughout the pipeline.
2088	*/
2089	tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
2090	if (bypass_lut)
2091	tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
2092	else
2093	tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
2094	WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
2095
2096	if (bypass_lut)
2097	DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2098
2099	WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2100	WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2101	WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2102	WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2103	WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2104	WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2105
2106	fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
2107	WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2108
2109	dce_v11_0_grph_enable(crtc, enable: true);
2110
2111	WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2112	target_fb->height);
2113
2114	x &= ~3;
2115	y &= ~1;
2116	WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2117	(x << 16) | y);
2118	viewport_w = crtc->mode.hdisplay;
2119	viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2120	WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2121	(viewport_w << 16) | viewport_h);
2122
2123	/* set pageflip to happen anywhere in vblank interval */
2124	WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
2125
2126	if (!atomic && fb && fb != crtc->primary->fb) {
2127	abo = gem_to_amdgpu_bo(fb->obj[0]);
2128	r = amdgpu_bo_reserve(bo: abo, no_intr: true);
2129	if (unlikely(r != 0))
2130	return r;
2131	amdgpu_bo_unpin(bo: abo);
2132	amdgpu_bo_unreserve(bo: abo);
2133	}
2134
2135	/* Bytes per pixel may have changed */
2136	dce_v11_0_bandwidth_update(adev);
2137
2138	return 0;
2139	}
2140
2141	static void dce_v11_0_set_interleave(struct drm_crtc *crtc,
2142	struct drm_display_mode *mode)
2143	{
2144	struct drm_device *dev = crtc->dev;
2145	struct amdgpu_device *adev = drm_to_adev(ddev: dev);
2146	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2147	u32 tmp;
2148
2149	tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
2150	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2151	tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
2152	else
2153	tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
2154	WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
2155	}
2156
2157	static void dce_v11_0_crtc_load_lut(struct drm_crtc *crtc)
2158	{
2159	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2160	struct drm_device *dev = crtc->dev;
2161	struct amdgpu_device *adev = drm_to_adev(ddev: dev);
2162	u16 *r, *g, *b;
2163	int i;
2164	u32 tmp;
2165
2166	DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2167
2168	tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2169	tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
2170	WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2171
2172	tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
2173	tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
2174	WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2175
2176	tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2177	tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
2178	WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2179
2180	WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2181
2182	WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2183	WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2184	WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2185
2186	WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2187	WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2188	WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2189
2190	WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2191	WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2192
2193	WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2194	r = crtc->gamma_store;
2195	g = r + crtc->gamma_size;
2196	b = g + crtc->gamma_size;
2197	for (i = 0; i < 256; i++) {
2198	WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2199	((*r++ & 0xffc0) << 14) |
2200	((*g++ & 0xffc0) << 4) |
2201	(*b++ >> 6));
2202	}
2203
2204	tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2205	tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
2206	tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
2207	tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, 0);
2208	WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2209
2210	tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
2211	tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
2212	WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2213
2214	tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2215	tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
2216	WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2217
2218	tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2219	tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
2220	WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2221
2222	/* XXX match this to the depth of the crtc fmt block, move to modeset? */
2223	WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);
2224	/* XXX this only needs to be programmed once per crtc at startup,
2225	* not sure where the best place for it is
2226	*/
2227	tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
2228	tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
2229	WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2230	}
2231
2232	static int dce_v11_0_pick_dig_encoder(struct drm_encoder *encoder)
2233	{
2234	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2235	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2236
2237	switch (amdgpu_encoder->encoder_id) {
2238	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2239	if (dig->linkb)
2240	return 1;
2241	else
2242	return 0;
2243	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2244	if (dig->linkb)
2245	return 3;
2246	else
2247	return 2;
2248	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2249	if (dig->linkb)
2250	return 5;
2251	else
2252	return 4;
2253	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2254	return 6;
2255	default:
2256	DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2257	return 0;
2258	}
2259	}
2260
2261	/**
2262	* dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc.
2263	*
2264	* @crtc: drm crtc
2265	*
2266	* Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2267	* a single PPLL can be used for all DP crtcs/encoders. For non-DP
2268	* monitors a dedicated PPLL must be used. If a particular board has
2269	* an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2270	* as there is no need to program the PLL itself. If we are not able to
2271	* allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2272	* avoid messing up an existing monitor.
2273	*
2274	* Asic specific PLL information
2275	*
2276	* DCE 10.x
2277	* Tonga
2278	* - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2279	* CI
2280	* - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2281	*
2282	*/
2283	static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc)
2284	{
2285	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2286	struct drm_device *dev = crtc->dev;
2287	struct amdgpu_device *adev = drm_to_adev(ddev: dev);
2288	u32 pll_in_use;
2289	int pll;
2290
2291	if ((adev->asic_type == CHIP_POLARIS10) ||
2292	(adev->asic_type == CHIP_POLARIS11) ||
2293	(adev->asic_type == CHIP_POLARIS12) ||
2294	(adev->asic_type == CHIP_VEGAM)) {
2295	struct amdgpu_encoder *amdgpu_encoder =
2296	to_amdgpu_encoder(amdgpu_crtc->encoder);
2297	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2298
2299	if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2300	return ATOM_DP_DTO;
2301
2302	switch (amdgpu_encoder->encoder_id) {
2303	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2304	if (dig->linkb)
2305	return ATOM_COMBOPHY_PLL1;
2306	else
2307	return ATOM_COMBOPHY_PLL0;
2308	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2309	if (dig->linkb)
2310	return ATOM_COMBOPHY_PLL3;
2311	else
2312	return ATOM_COMBOPHY_PLL2;
2313	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2314	if (dig->linkb)
2315	return ATOM_COMBOPHY_PLL5;
2316	else
2317	return ATOM_COMBOPHY_PLL4;
2318	default:
2319	DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2320	return ATOM_PPLL_INVALID;
2321	}
2322	}
2323
2324	if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2325	if (adev->clock.dp_extclk)
2326	/* skip PPLL programming if using ext clock */
2327	return ATOM_PPLL_INVALID;
2328	else {
2329	/* use the same PPLL for all DP monitors */
2330	pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2331	if (pll != ATOM_PPLL_INVALID)
2332	return pll;
2333	}
2334	} else {
2335	/* use the same PPLL for all monitors with the same clock */
2336	pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2337	if (pll != ATOM_PPLL_INVALID)
2338	return pll;
2339	}
2340
2341	/* XXX need to determine what plls are available on each DCE11 part */
2342	pll_in_use = amdgpu_pll_get_use_mask(crtc);
2343	if (adev->flags & AMD_IS_APU) {
2344	if (!(pll_in_use & (1 << ATOM_PPLL1)))
2345	return ATOM_PPLL1;
2346	if (!(pll_in_use & (1 << ATOM_PPLL0)))
2347	return ATOM_PPLL0;
2348	DRM_ERROR("unable to allocate a PPLL\n");
2349	return ATOM_PPLL_INVALID;
2350	} else {
2351	if (!(pll_in_use & (1 << ATOM_PPLL2)))
2352	return ATOM_PPLL2;
2353	if (!(pll_in_use & (1 << ATOM_PPLL1)))
2354	return ATOM_PPLL1;
2355	if (!(pll_in_use & (1 << ATOM_PPLL0)))
2356	return ATOM_PPLL0;
2357	DRM_ERROR("unable to allocate a PPLL\n");
2358	return ATOM_PPLL_INVALID;
2359	}
2360	return ATOM_PPLL_INVALID;
2361	}
2362
2363	static void dce_v11_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2364	{
2365	struct amdgpu_device *adev = drm_to_adev(ddev: crtc->dev);
2366	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2367	uint32_t cur_lock;
2368
2369	cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2370	if (lock)
2371	cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);
2372	else
2373	cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);
2374	WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2375	}
2376
2377	static void dce_v11_0_hide_cursor(struct drm_crtc *crtc)
2378	{
2379	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2380	struct amdgpu_device *adev = drm_to_adev(ddev: crtc->dev);
2381	u32 tmp;
2382
2383	tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2384	tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
2385	WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2386	}
2387
2388	static void dce_v11_0_show_cursor(struct drm_crtc *crtc)
2389	{
2390	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2391	struct amdgpu_device *adev = drm_to_adev(ddev: crtc->dev);
2392	u32 tmp;
2393
2394	WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2395	upper_32_bits(amdgpu_crtc->cursor_addr));
2396	WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2397	lower_32_bits(amdgpu_crtc->cursor_addr));
2398
2399	tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2400	tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
2401	tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
2402	WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2403	}
2404
2405	static int dce_v11_0_cursor_move_locked(struct drm_crtc *crtc,
2406	int x, int y)
2407	{
2408	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2409	struct amdgpu_device *adev = drm_to_adev(ddev: crtc->dev);
2410	int xorigin = 0, yorigin = 0;
2411
2412	amdgpu_crtc->cursor_x = x;
2413	amdgpu_crtc->cursor_y = y;
2414
2415	/* avivo cursor are offset into the total surface */
2416	x += crtc->x;
2417	y += crtc->y;
2418	DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2419
2420	if (x < 0) {
2421	xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2422	x = 0;
2423	}
2424	if (y < 0) {
2425	yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2426	y = 0;
2427	}
2428
2429	WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2430	WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2431	WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2432	((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2433
2434	return 0;
2435	}
2436
2437	static int dce_v11_0_crtc_cursor_move(struct drm_crtc *crtc,
2438	int x, int y)
2439	{
2440	int ret;
2441
2442	dce_v11_0_lock_cursor(crtc, lock: true);
2443	ret = dce_v11_0_cursor_move_locked(crtc, x, y);
2444	dce_v11_0_lock_cursor(crtc, lock: false);
2445
2446	return ret;
2447	}
2448
2449	static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc,
2450	struct drm_file *file_priv,
2451	uint32_t handle,
2452	uint32_t width,
2453	uint32_t height,
2454	int32_t hot_x,
2455	int32_t hot_y)
2456	{
2457	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2458	struct drm_gem_object *obj;
2459	struct amdgpu_bo *aobj;
2460	int ret;
2461
2462	if (!handle) {
2463	/* turn off cursor */
2464	dce_v11_0_hide_cursor(crtc);
2465	obj = NULL;
2466	goto unpin;
2467	}
2468
2469	if ((width > amdgpu_crtc->max_cursor_width) ||
2470	(height > amdgpu_crtc->max_cursor_height)) {
2471	DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2472	return -EINVAL;
2473	}
2474
2475	obj = drm_gem_object_lookup(filp: file_priv, handle);
2476	if (!obj) {
2477	DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2478	return -ENOENT;
2479	}
2480
2481	aobj = gem_to_amdgpu_bo(obj);
2482	ret = amdgpu_bo_reserve(bo: aobj, no_intr: false);
2483	if (ret != 0) {
2484	drm_gem_object_put(obj);
2485	return ret;
2486	}
2487
2488	ret = amdgpu_bo_pin(bo: aobj, AMDGPU_GEM_DOMAIN_VRAM);
2489	amdgpu_bo_unreserve(bo: aobj);
2490	if (ret) {
2491	DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2492	drm_gem_object_put(obj);
2493	return ret;
2494	}
2495	amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(bo: aobj);
2496
2497	dce_v11_0_lock_cursor(crtc, lock: true);
2498
2499	if (width != amdgpu_crtc->cursor_width ||
2500	height != amdgpu_crtc->cursor_height ||
2501	hot_x != amdgpu_crtc->cursor_hot_x ||
2502	hot_y != amdgpu_crtc->cursor_hot_y) {
2503	int x, y;
2504
2505	x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2506	y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2507
2508	dce_v11_0_cursor_move_locked(crtc, x, y);
2509
2510	amdgpu_crtc->cursor_width = width;
2511	amdgpu_crtc->cursor_height = height;
2512	amdgpu_crtc->cursor_hot_x = hot_x;
2513	amdgpu_crtc->cursor_hot_y = hot_y;
2514	}
2515
2516	dce_v11_0_show_cursor(crtc);
2517	dce_v11_0_lock_cursor(crtc, lock: false);
2518
2519	unpin:
2520	if (amdgpu_crtc->cursor_bo) {
2521	struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2522	ret = amdgpu_bo_reserve(bo: aobj, no_intr: true);
2523	if (likely(ret == 0)) {
2524	amdgpu_bo_unpin(bo: aobj);
2525	amdgpu_bo_unreserve(bo: aobj);
2526	}
2527	drm_gem_object_put(obj: amdgpu_crtc->cursor_bo);
2528	}
2529
2530	amdgpu_crtc->cursor_bo = obj;
2531	return 0;
2532	}
2533
2534	static void dce_v11_0_cursor_reset(struct drm_crtc *crtc)
2535	{
2536	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2537
2538	if (amdgpu_crtc->cursor_bo) {
2539	dce_v11_0_lock_cursor(crtc, lock: true);
2540
2541	dce_v11_0_cursor_move_locked(crtc, x: amdgpu_crtc->cursor_x,
2542	y: amdgpu_crtc->cursor_y);
2543
2544	dce_v11_0_show_cursor(crtc);
2545
2546	dce_v11_0_lock_cursor(crtc, lock: false);
2547	}
2548	}
2549
2550	static int dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2551	u16 *blue, uint32_t size,
2552	struct drm_modeset_acquire_ctx *ctx)
2553	{
2554	dce_v11_0_crtc_load_lut(crtc);
2555
2556	return 0;
2557	}
2558
2559	static void dce_v11_0_crtc_destroy(struct drm_crtc *crtc)
2560	{
2561	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2562
2563	drm_crtc_cleanup(crtc);
2564	kfree(objp: amdgpu_crtc);
2565	}
2566
2567	static const struct drm_crtc_funcs dce_v11_0_crtc_funcs = {
2568	.cursor_set2 = dce_v11_0_crtc_cursor_set2,
2569	.cursor_move = dce_v11_0_crtc_cursor_move,
2570	.gamma_set = dce_v11_0_crtc_gamma_set,
2571	.set_config = amdgpu_display_crtc_set_config,
2572	.destroy = dce_v11_0_crtc_destroy,
2573	.page_flip_target = amdgpu_display_crtc_page_flip_target,
2574	.get_vblank_counter = amdgpu_get_vblank_counter_kms,
2575	.enable_vblank = amdgpu_enable_vblank_kms,
2576	.disable_vblank = amdgpu_disable_vblank_kms,
2577	.get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
2578	};
2579
2580	static void dce_v11_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2581	{
2582	struct drm_device *dev = crtc->dev;
2583	struct amdgpu_device *adev = drm_to_adev(ddev: dev);
2584	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2585	unsigned type;
2586
2587	switch (mode) {
2588	case DRM_MODE_DPMS_ON:
2589	amdgpu_crtc->enabled = true;
2590	amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2591	dce_v11_0_vga_enable(crtc, enable: true);
2592	amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2593	dce_v11_0_vga_enable(crtc, enable: false);
2594	/* Make sure VBLANK and PFLIP interrupts are still enabled */
2595	type = amdgpu_display_crtc_idx_to_irq_type(adev,
2596	crtc: amdgpu_crtc->crtc_id);
2597	amdgpu_irq_update(adev, src: &adev->crtc_irq, type);
2598	amdgpu_irq_update(adev, src: &adev->pageflip_irq, type);
2599	drm_crtc_vblank_on(crtc);
2600	dce_v11_0_crtc_load_lut(crtc);
2601	break;
2602	case DRM_MODE_DPMS_STANDBY:
2603	case DRM_MODE_DPMS_SUSPEND:
2604	case DRM_MODE_DPMS_OFF:
2605	drm_crtc_vblank_off(crtc);
2606	if (amdgpu_crtc->enabled) {
2607	dce_v11_0_vga_enable(crtc, enable: true);
2608	amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2609	dce_v11_0_vga_enable(crtc, enable: false);
2610	}
2611	amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2612	amdgpu_crtc->enabled = false;
2613	break;
2614	}
2615	/* adjust pm to dpms */
2616	amdgpu_dpm_compute_clocks(adev);
2617	}
2618
2619	static void dce_v11_0_crtc_prepare(struct drm_crtc *crtc)
2620	{
2621	/* disable crtc pair power gating before programming */
2622	amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2623	amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2624	dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2625	}
2626
2627	static void dce_v11_0_crtc_commit(struct drm_crtc *crtc)
2628	{
2629	dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2630	amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2631	}
2632
2633	static void dce_v11_0_crtc_disable(struct drm_crtc *crtc)
2634	{
2635	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2636	struct drm_device *dev = crtc->dev;
2637	struct amdgpu_device *adev = drm_to_adev(ddev: dev);
2638	struct amdgpu_atom_ss ss;
2639	int i;
2640
2641	dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2642	if (crtc->primary->fb) {
2643	int r;
2644	struct amdgpu_bo *abo;
2645
2646	abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]);
2647	r = amdgpu_bo_reserve(bo: abo, no_intr: true);
2648	if (unlikely(r))
2649	DRM_ERROR("failed to reserve abo before unpin\n");
2650	else {
2651	amdgpu_bo_unpin(bo: abo);
2652	amdgpu_bo_unreserve(bo: abo);
2653	}
2654	}
2655	/* disable the GRPH */
2656	dce_v11_0_grph_enable(crtc, enable: false);
2657
2658	amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2659
2660	for (i = 0; i < adev->mode_info.num_crtc; i++) {
2661	if (adev->mode_info.crtcs[i] &&
2662	adev->mode_info.crtcs[i]->enabled &&
2663	i != amdgpu_crtc->crtc_id &&
2664	amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2665	/* one other crtc is using this pll don't turn
2666	* off the pll
2667	*/
2668	goto done;
2669	}
2670	}
2671
2672	switch (amdgpu_crtc->pll_id) {
2673	case ATOM_PPLL0:
2674	case ATOM_PPLL1:
2675	case ATOM_PPLL2:
2676	/* disable the ppll */
2677	amdgpu_atombios_crtc_program_pll(crtc, crtc_id: amdgpu_crtc->crtc_id, pll_id: amdgpu_crtc->pll_id,
2678	encoder_mode: 0, encoder_id: 0, ATOM_DISABLE, ref_div: 0, fb_div: 0, frac_fb_div: 0, post_div: 0, bpc: 0, ss_enabled: false, ss: &ss);
2679	break;
2680	case ATOM_COMBOPHY_PLL0:
2681	case ATOM_COMBOPHY_PLL1:
2682	case ATOM_COMBOPHY_PLL2:
2683	case ATOM_COMBOPHY_PLL3:
2684	case ATOM_COMBOPHY_PLL4:
2685	case ATOM_COMBOPHY_PLL5:
2686	/* disable the ppll */
2687	amdgpu_atombios_crtc_program_pll(crtc, ATOM_CRTC_INVALID, pll_id: amdgpu_crtc->pll_id,
2688	encoder_mode: 0, encoder_id: 0, ATOM_DISABLE, ref_div: 0, fb_div: 0, frac_fb_div: 0, post_div: 0, bpc: 0, ss_enabled: false, ss: &ss);
2689	break;
2690	default:
2691	break;
2692	}
2693	done:
2694	amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2695	amdgpu_crtc->adjusted_clock = 0;
2696	amdgpu_crtc->encoder = NULL;
2697	amdgpu_crtc->connector = NULL;
2698	}
2699
2700	static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc,
2701	struct drm_display_mode *mode,
2702	struct drm_display_mode *adjusted_mode,
2703	int x, int y, struct drm_framebuffer *old_fb)
2704	{
2705	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2706	struct drm_device *dev = crtc->dev;
2707	struct amdgpu_device *adev = drm_to_adev(ddev: dev);
2708
2709	if (!amdgpu_crtc->adjusted_clock)
2710	return -EINVAL;
2711
2712	if ((adev->asic_type == CHIP_POLARIS10) ||
2713	(adev->asic_type == CHIP_POLARIS11) ||
2714	(adev->asic_type == CHIP_POLARIS12) ||
2715	(adev->asic_type == CHIP_VEGAM)) {
2716	struct amdgpu_encoder *amdgpu_encoder =
2717	to_amdgpu_encoder(amdgpu_crtc->encoder);
2718	int encoder_mode =
2719	amdgpu_atombios_encoder_get_encoder_mode(encoder: amdgpu_crtc->encoder);
2720
2721	/* SetPixelClock calculates the plls and ss values now */
2722	amdgpu_atombios_crtc_program_pll(crtc, crtc_id: amdgpu_crtc->crtc_id,
2723	pll_id: amdgpu_crtc->pll_id,
2724	encoder_mode, encoder_id: amdgpu_encoder->encoder_id,
2725	clock: adjusted_mode->clock, ref_div: 0, fb_div: 0, frac_fb_div: 0, post_div: 0,
2726	bpc: amdgpu_crtc->bpc, ss_enabled: amdgpu_crtc->ss_enabled, ss: &amdgpu_crtc->ss);
2727	} else {
2728	amdgpu_atombios_crtc_set_pll(crtc, mode: adjusted_mode);
2729	}
2730	amdgpu_atombios_crtc_set_dtd_timing(crtc, mode: adjusted_mode);
2731	dce_v11_0_crtc_do_set_base(crtc, fb: old_fb, x, y, atomic: 0);
2732	amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2733	amdgpu_atombios_crtc_scaler_setup(crtc);
2734	dce_v11_0_cursor_reset(crtc);
2735	/* update the hw version fpr dpm */
2736	amdgpu_crtc->hw_mode = *adjusted_mode;
2737
2738	return 0;
2739	}
2740
2741	static bool dce_v11_0_crtc_mode_fixup(struct drm_crtc *crtc,
2742	const struct drm_display_mode *mode,
2743	struct drm_display_mode *adjusted_mode)
2744	{
2745	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2746	struct drm_device *dev = crtc->dev;
2747	struct drm_encoder *encoder;
2748
2749	/* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2750	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2751	if (encoder->crtc == crtc) {
2752	amdgpu_crtc->encoder = encoder;
2753	amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2754	break;
2755	}
2756	}
2757	if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2758	amdgpu_crtc->encoder = NULL;
2759	amdgpu_crtc->connector = NULL;
2760	return false;
2761	}
2762	if (!amdgpu_display_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2763	return false;
2764	if (amdgpu_atombios_crtc_prepare_pll(crtc, mode: adjusted_mode))
2765	return false;
2766	/* pick pll */
2767	amdgpu_crtc->pll_id = dce_v11_0_pick_pll(crtc);
2768	/* if we can't get a PPLL for a non-DP encoder, fail */
2769	if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2770	!ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2771	return false;
2772
2773	return true;
2774	}
2775
2776	static int dce_v11_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2777	struct drm_framebuffer *old_fb)
2778	{
2779	return dce_v11_0_crtc_do_set_base(crtc, fb: old_fb, x, y, atomic: 0);
2780	}
2781
2782	static int dce_v11_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2783	struct drm_framebuffer *fb,
2784	int x, int y, enum mode_set_atomic state)
2785	{
2786	return dce_v11_0_crtc_do_set_base(crtc, fb, x, y, atomic: 1);
2787	}
2788
2789	static const struct drm_crtc_helper_funcs dce_v11_0_crtc_helper_funcs = {
2790	.dpms = dce_v11_0_crtc_dpms,
2791	.mode_fixup = dce_v11_0_crtc_mode_fixup,
2792	.mode_set = dce_v11_0_crtc_mode_set,
2793	.mode_set_base = dce_v11_0_crtc_set_base,
2794	.mode_set_base_atomic = dce_v11_0_crtc_set_base_atomic,
2795	.prepare = dce_v11_0_crtc_prepare,
2796	.commit = dce_v11_0_crtc_commit,
2797	.disable = dce_v11_0_crtc_disable,
2798	.get_scanout_position = amdgpu_crtc_get_scanout_position,
2799	};
2800
2801	static int dce_v11_0_crtc_init(struct amdgpu_device *adev, int index)
2802	{
2803	struct amdgpu_crtc *amdgpu_crtc;
2804
2805	amdgpu_crtc = kzalloc(size: sizeof(struct amdgpu_crtc) +
2806	(AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2807	if (amdgpu_crtc == NULL)
2808	return -ENOMEM;
2809
2810	drm_crtc_init(dev: adev_to_drm(adev), crtc: &amdgpu_crtc->base, funcs: &dce_v11_0_crtc_funcs);
2811
2812	drm_mode_crtc_set_gamma_size(crtc: &amdgpu_crtc->base, gamma_size: 256);
2813	amdgpu_crtc->crtc_id = index;
2814	adev->mode_info.crtcs[index] = amdgpu_crtc;
2815
2816	amdgpu_crtc->max_cursor_width = 128;
2817	amdgpu_crtc->max_cursor_height = 128;
2818	adev_to_drm(adev)->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2819	adev_to_drm(adev)->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2820
2821	switch (amdgpu_crtc->crtc_id) {
2822	case 0:
2823	default:
2824	amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
2825	break;
2826	case 1:
2827	amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;
2828	break;
2829	case 2:
2830	amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;
2831	break;
2832	case 3:
2833	amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;
2834	break;
2835	case 4:
2836	amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;
2837	break;
2838	case 5:
2839	amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;
2840	break;
2841	}
2842
2843	amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2844	amdgpu_crtc->adjusted_clock = 0;
2845	amdgpu_crtc->encoder = NULL;
2846	amdgpu_crtc->connector = NULL;
2847	drm_crtc_helper_add(crtc: &amdgpu_crtc->base, funcs: &dce_v11_0_crtc_helper_funcs);
2848
2849	return 0;
2850	}
2851
2852	static int dce_v11_0_early_init(void *handle)
2853	{
2854	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2855
2856	adev->audio_endpt_rreg = &dce_v11_0_audio_endpt_rreg;
2857	adev->audio_endpt_wreg = &dce_v11_0_audio_endpt_wreg;
2858
2859	dce_v11_0_set_display_funcs(adev);
2860
2861	adev->mode_info.num_crtc = dce_v11_0_get_num_crtc(adev);
2862
2863	switch (adev->asic_type) {
2864	case CHIP_CARRIZO:
2865	adev->mode_info.num_hpd = 6;
2866	adev->mode_info.num_dig = 9;
2867	break;
2868	case CHIP_STONEY:
2869	adev->mode_info.num_hpd = 6;
2870	adev->mode_info.num_dig = 9;
2871	break;
2872	case CHIP_POLARIS10:
2873	case CHIP_VEGAM:
2874	adev->mode_info.num_hpd = 6;
2875	adev->mode_info.num_dig = 6;
2876	break;
2877	case CHIP_POLARIS11:
2878	case CHIP_POLARIS12:
2879	adev->mode_info.num_hpd = 5;
2880	adev->mode_info.num_dig = 5;
2881	break;
2882	default:
2883	/* FIXME: not supported yet */
2884	return -EINVAL;
2885	}
2886
2887	dce_v11_0_set_irq_funcs(adev);
2888
2889	return 0;
2890	}
2891
2892	static int dce_v11_0_sw_init(void *handle)
2893	{
2894	int r, i;
2895	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2896
2897	for (i = 0; i < adev->mode_info.num_crtc; i++) {
2898	r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, src_id: i + 1, source: &adev->crtc_irq);
2899	if (r)
2900	return r;
2901	}
2902
2903	for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; i < 20; i += 2) {
2904	r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, src_id: i, source: &adev->pageflip_irq);
2905	if (r)
2906	return r;
2907	}
2908
2909	/* HPD hotplug */
2910	r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, source: &adev->hpd_irq);
2911	if (r)
2912	return r;
2913
2914	adev_to_drm(adev)->mode_config.funcs = &amdgpu_mode_funcs;
2915
2916	adev_to_drm(adev)->mode_config.async_page_flip = true;
2917
2918	adev_to_drm(adev)->mode_config.max_width = 16384;
2919	adev_to_drm(adev)->mode_config.max_height = 16384;
2920
2921	adev_to_drm(adev)->mode_config.preferred_depth = 24;
2922	adev_to_drm(adev)->mode_config.prefer_shadow = 1;
2923
2924	adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true;
2925
2926	r = amdgpu_display_modeset_create_props(adev);
2927	if (r)
2928	return r;
2929
2930	adev_to_drm(adev)->mode_config.max_width = 16384;
2931	adev_to_drm(adev)->mode_config.max_height = 16384;
2932
2933
2934	/* allocate crtcs */
2935	for (i = 0; i < adev->mode_info.num_crtc; i++) {
2936	r = dce_v11_0_crtc_init(adev, index: i);
2937	if (r)
2938	return r;
2939	}
2940
2941	if (amdgpu_atombios_get_connector_info_from_object_table(adev))
2942	amdgpu_display_print_display_setup(dev: adev_to_drm(adev));
2943	else
2944	return -EINVAL;
2945
2946	/* setup afmt */
2947	r = dce_v11_0_afmt_init(adev);
2948	if (r)
2949	return r;
2950
2951	r = dce_v11_0_audio_init(adev);
2952	if (r)
2953	return r;
2954
2955	/* Disable vblank IRQs aggressively for power-saving */
2956	/* XXX: can this be enabled for DC? */
2957	adev_to_drm(adev)->vblank_disable_immediate = true;
2958
2959	r = drm_vblank_init(dev: adev_to_drm(adev), num_crtcs: adev->mode_info.num_crtc);
2960	if (r)
2961	return r;
2962
2963	INIT_DELAYED_WORK(&adev->hotplug_work,
2964	amdgpu_display_hotplug_work_func);
2965
2966	drm_kms_helper_poll_init(dev: adev_to_drm(adev));
2967
2968	adev->mode_info.mode_config_initialized = true;
2969	return 0;
2970	}
2971
2972	static int dce_v11_0_sw_fini(void *handle)
2973	{
2974	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2975
2976	kfree(objp: adev->mode_info.bios_hardcoded_edid);
2977
2978	drm_kms_helper_poll_fini(dev: adev_to_drm(adev));
2979
2980	dce_v11_0_audio_fini(adev);
2981
2982	dce_v11_0_afmt_fini(adev);
2983
2984	drm_mode_config_cleanup(dev: adev_to_drm(adev));
2985	adev->mode_info.mode_config_initialized = false;
2986
2987	return 0;
2988	}
2989
2990	static int dce_v11_0_hw_init(void *handle)
2991	{
2992	int i;
2993	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2994
2995	dce_v11_0_init_golden_registers(adev);
2996
2997	/* disable vga render */
2998	dce_v11_0_set_vga_render_state(adev, render: false);
2999	/* init dig PHYs, disp eng pll */
3000	amdgpu_atombios_crtc_powergate_init(adev);
3001	amdgpu_atombios_encoder_init_dig(adev);
3002	if ((adev->asic_type == CHIP_POLARIS10) ||
3003	(adev->asic_type == CHIP_POLARIS11) ||
3004	(adev->asic_type == CHIP_POLARIS12) ||
3005	(adev->asic_type == CHIP_VEGAM)) {
3006	amdgpu_atombios_crtc_set_dce_clock(adev, freq: adev->clock.default_dispclk,
3007	DCE_CLOCK_TYPE_DISPCLK, ATOM_GCK_DFS);
3008	amdgpu_atombios_crtc_set_dce_clock(adev, freq: 0,
3009	DCE_CLOCK_TYPE_DPREFCLK, ATOM_GCK_DFS);
3010	} else {
3011	amdgpu_atombios_crtc_set_disp_eng_pll(adev, dispclk: adev->clock.default_dispclk);
3012	}
3013
3014	/* initialize hpd */
3015	dce_v11_0_hpd_init(adev);
3016
3017	for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3018	dce_v11_0_audio_enable(adev, pin: &adev->mode_info.audio.pin[i], enable: false);
3019	}
3020
3021	dce_v11_0_pageflip_interrupt_init(adev);
3022
3023	return 0;
3024	}
3025
3026	static int dce_v11_0_hw_fini(void *handle)
3027	{
3028	int i;
3029	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3030
3031	dce_v11_0_hpd_fini(adev);
3032
3033	for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3034	dce_v11_0_audio_enable(adev, pin: &adev->mode_info.audio.pin[i], enable: false);
3035	}
3036
3037	dce_v11_0_pageflip_interrupt_fini(adev);
3038
3039	flush_delayed_work(dwork: &adev->hotplug_work);
3040
3041	return 0;
3042	}
3043
3044	static int dce_v11_0_suspend(void *handle)
3045	{
3046	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3047	int r;
3048
3049	r = amdgpu_display_suspend_helper(adev);
3050	if (r)
3051	return r;
3052
3053	adev->mode_info.bl_level =
3054	amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);
3055
3056	return dce_v11_0_hw_fini(handle);
3057	}
3058
3059	static int dce_v11_0_resume(void *handle)
3060	{
3061	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3062	int ret;
3063
3064	amdgpu_atombios_encoder_set_backlight_level_to_reg(adev,
3065	backlight_level: adev->mode_info.bl_level);
3066
3067	ret = dce_v11_0_hw_init(handle);
3068
3069	/* turn on the BL */
3070	if (adev->mode_info.bl_encoder) {
3071	u8 bl_level = amdgpu_display_backlight_get_level(adev,
3072	adev->mode_info.bl_encoder);
3073	amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
3074	bl_level);
3075	}
3076	if (ret)
3077	return ret;
3078
3079	return amdgpu_display_resume_helper(adev);
3080	}
3081
3082	static bool dce_v11_0_is_idle(void *handle)
3083	{
3084	return true;
3085	}
3086
3087	static int dce_v11_0_wait_for_idle(void *handle)
3088	{
3089	return 0;
3090	}
3091
3092	static int dce_v11_0_soft_reset(void *handle)
3093	{
3094	u32 srbm_soft_reset = 0, tmp;
3095	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3096
3097	if (dce_v11_0_is_display_hung(adev))
3098	srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
3099
3100	if (srbm_soft_reset) {
3101	tmp = RREG32(mmSRBM_SOFT_RESET);
3102	tmp |= srbm_soft_reset;
3103	dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3104	WREG32(mmSRBM_SOFT_RESET, tmp);
3105	tmp = RREG32(mmSRBM_SOFT_RESET);
3106
3107	udelay(50);
3108
3109	tmp &= ~srbm_soft_reset;
3110	WREG32(mmSRBM_SOFT_RESET, tmp);
3111	tmp = RREG32(mmSRBM_SOFT_RESET);
3112
3113	/* Wait a little for things to settle down */
3114	udelay(50);
3115	}
3116	return 0;
3117	}
3118
3119	static void dce_v11_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
3120	int crtc,
3121	enum amdgpu_interrupt_state state)
3122	{
3123	u32 lb_interrupt_mask;
3124
3125	if (crtc >= adev->mode_info.num_crtc) {
3126	DRM_DEBUG("invalid crtc %d\n", crtc);
3127	return;
3128	}
3129
3130	switch (state) {
3131	case AMDGPU_IRQ_STATE_DISABLE:
3132	lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3133	lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3134	VBLANK_INTERRUPT_MASK, 0);
3135	WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3136	break;
3137	case AMDGPU_IRQ_STATE_ENABLE:
3138	lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3139	lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3140	VBLANK_INTERRUPT_MASK, 1);
3141	WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3142	break;
3143	default:
3144	break;
3145	}
3146	}
3147
3148	static void dce_v11_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3149	int crtc,
3150	enum amdgpu_interrupt_state state)
3151	{
3152	u32 lb_interrupt_mask;
3153
3154	if (crtc >= adev->mode_info.num_crtc) {
3155	DRM_DEBUG("invalid crtc %d\n", crtc);
3156	return;
3157	}
3158
3159	switch (state) {
3160	case AMDGPU_IRQ_STATE_DISABLE:
3161	lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3162	lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3163	VLINE_INTERRUPT_MASK, 0);
3164	WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3165	break;
3166	case AMDGPU_IRQ_STATE_ENABLE:
3167	lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3168	lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3169	VLINE_INTERRUPT_MASK, 1);
3170	WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3171	break;
3172	default:
3173	break;
3174	}
3175	}
3176
3177	static int dce_v11_0_set_hpd_irq_state(struct amdgpu_device *adev,
3178	struct amdgpu_irq_src *source,
3179	unsigned hpd,
3180	enum amdgpu_interrupt_state state)
3181	{
3182	u32 tmp;
3183
3184	if (hpd >= adev->mode_info.num_hpd) {
3185	DRM_DEBUG("invalid hdp %d\n", hpd);
3186	return 0;
3187	}
3188
3189	switch (state) {
3190	case AMDGPU_IRQ_STATE_DISABLE:
3191	tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3192	tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
3193	WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3194	break;
3195	case AMDGPU_IRQ_STATE_ENABLE:
3196	tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3197	tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
3198	WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3199	break;
3200	default:
3201	break;
3202	}
3203
3204	return 0;
3205	}
3206
3207	static int dce_v11_0_set_crtc_irq_state(struct amdgpu_device *adev,
3208	struct amdgpu_irq_src *source,
3209	unsigned type,
3210	enum amdgpu_interrupt_state state)
3211	{
3212	switch (type) {
3213	case AMDGPU_CRTC_IRQ_VBLANK1:
3214	dce_v11_0_set_crtc_vblank_interrupt_state(adev, crtc: 0, state);
3215	break;
3216	case AMDGPU_CRTC_IRQ_VBLANK2:
3217	dce_v11_0_set_crtc_vblank_interrupt_state(adev, crtc: 1, state);
3218	break;
3219	case AMDGPU_CRTC_IRQ_VBLANK3:
3220	dce_v11_0_set_crtc_vblank_interrupt_state(adev, crtc: 2, state);
3221	break;
3222	case AMDGPU_CRTC_IRQ_VBLANK4:
3223	dce_v11_0_set_crtc_vblank_interrupt_state(adev, crtc: 3, state);
3224	break;
3225	case AMDGPU_CRTC_IRQ_VBLANK5:
3226	dce_v11_0_set_crtc_vblank_interrupt_state(adev, crtc: 4, state);
3227	break;
3228	case AMDGPU_CRTC_IRQ_VBLANK6:
3229	dce_v11_0_set_crtc_vblank_interrupt_state(adev, crtc: 5, state);
3230	break;
3231	case AMDGPU_CRTC_IRQ_VLINE1:
3232	dce_v11_0_set_crtc_vline_interrupt_state(adev, crtc: 0, state);
3233	break;
3234	case AMDGPU_CRTC_IRQ_VLINE2:
3235	dce_v11_0_set_crtc_vline_interrupt_state(adev, crtc: 1, state);
3236	break;
3237	case AMDGPU_CRTC_IRQ_VLINE3:
3238	dce_v11_0_set_crtc_vline_interrupt_state(adev, crtc: 2, state);
3239	break;
3240	case AMDGPU_CRTC_IRQ_VLINE4:
3241	dce_v11_0_set_crtc_vline_interrupt_state(adev, crtc: 3, state);
3242	break;
3243	case AMDGPU_CRTC_IRQ_VLINE5:
3244	dce_v11_0_set_crtc_vline_interrupt_state(adev, crtc: 4, state);
3245	break;
3246	case AMDGPU_CRTC_IRQ_VLINE6:
3247	dce_v11_0_set_crtc_vline_interrupt_state(adev, crtc: 5, state);
3248	break;
3249	default:
3250	break;
3251	}
3252	return 0;
3253	}
3254
3255	static int dce_v11_0_set_pageflip_irq_state(struct amdgpu_device *adev,
3256	struct amdgpu_irq_src *src,
3257	unsigned type,
3258	enum amdgpu_interrupt_state state)
3259	{
3260	u32 reg;
3261
3262	if (type >= adev->mode_info.num_crtc) {
3263	DRM_ERROR("invalid pageflip crtc %d\n", type);
3264	return -EINVAL;
3265	}
3266
3267	reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3268	if (state == AMDGPU_IRQ_STATE_DISABLE)
3269	WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3270	reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3271	else
3272	WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3273	reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3274
3275	return 0;
3276	}
3277
3278	static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev,
3279	struct amdgpu_irq_src *source,
3280	struct amdgpu_iv_entry *entry)
3281	{
3282	unsigned long flags;
3283	unsigned crtc_id;
3284	struct amdgpu_crtc *amdgpu_crtc;
3285	struct amdgpu_flip_work *works;
3286
3287	crtc_id = (entry->src_id - 8) >> 1;
3288	amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3289
3290	if (crtc_id >= adev->mode_info.num_crtc) {
3291	DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3292	return -EINVAL;
3293	}
3294
3295	if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3296	GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3297	WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3298	GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3299
3300	/* IRQ could occur when in initial stage */
3301	if(amdgpu_crtc == NULL)
3302	return 0;
3303
3304	spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
3305	works = amdgpu_crtc->pflip_works;
3306	if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
3307	DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3308	"AMDGPU_FLIP_SUBMITTED(%d)\n",
3309	amdgpu_crtc->pflip_status,
3310	AMDGPU_FLIP_SUBMITTED);
3311	spin_unlock_irqrestore(lock: &adev_to_drm(adev)->event_lock, flags);
3312	return 0;
3313	}
3314
3315	/* page flip completed. clean up */
3316	amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3317	amdgpu_crtc->pflip_works = NULL;
3318
3319	/* wakeup usersapce */
3320	if(works->event)
3321	drm_crtc_send_vblank_event(crtc: &amdgpu_crtc->base, e: works->event);
3322
3323	spin_unlock_irqrestore(lock: &adev_to_drm(adev)->event_lock, flags);
3324
3325	drm_crtc_vblank_put(crtc: &amdgpu_crtc->base);
3326	schedule_work(work: &works->unpin_work);
3327
3328	return 0;
3329	}
3330
3331	static void dce_v11_0_hpd_int_ack(struct amdgpu_device *adev,
3332	int hpd)
3333	{
3334	u32 tmp;
3335
3336	if (hpd >= adev->mode_info.num_hpd) {
3337	DRM_DEBUG("invalid hdp %d\n", hpd);
3338	return;
3339	}
3340
3341	tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3342	tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
3343	WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3344	}
3345
3346	static void dce_v11_0_crtc_vblank_int_ack(struct amdgpu_device *adev,
3347	int crtc)
3348	{
3349	u32 tmp;
3350
3351	if (crtc < 0 || crtc >= adev->mode_info.num_crtc) {
3352	DRM_DEBUG("invalid crtc %d\n", crtc);
3353	return;
3354	}
3355
3356	tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
3357	tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
3358	WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);
3359	}
3360
3361	static void dce_v11_0_crtc_vline_int_ack(struct amdgpu_device *adev,
3362	int crtc)
3363	{
3364	u32 tmp;
3365
3366	if (crtc < 0 || crtc >= adev->mode_info.num_crtc) {
3367	DRM_DEBUG("invalid crtc %d\n", crtc);
3368	return;
3369	}
3370
3371	tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
3372	tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
3373	WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);
3374	}
3375
3376	static int dce_v11_0_crtc_irq(struct amdgpu_device *adev,
3377	struct amdgpu_irq_src *source,
3378	struct amdgpu_iv_entry *entry)
3379	{
3380	unsigned crtc = entry->src_id - 1;
3381	uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3382	unsigned int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev,
3383	crtc);
3384
3385	switch (entry->src_data[0]) {
3386	case 0: /* vblank */
3387	if (disp_int & interrupt_status_offsets[crtc].vblank)
3388	dce_v11_0_crtc_vblank_int_ack(adev, crtc);
3389	else
3390	DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3391
3392	if (amdgpu_irq_enabled(adev, src: source, type: irq_type)) {
3393	drm_handle_vblank(dev: adev_to_drm(adev), pipe: crtc);
3394	}
3395	DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3396
3397	break;
3398	case 1: /* vline */
3399	if (disp_int & interrupt_status_offsets[crtc].vline)
3400	dce_v11_0_crtc_vline_int_ack(adev, crtc);
3401	else
3402	DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3403
3404	DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3405
3406	break;
3407	default:
3408	DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3409	break;
3410	}
3411
3412	return 0;
3413	}
3414
3415	static int dce_v11_0_hpd_irq(struct amdgpu_device *adev,
3416	struct amdgpu_irq_src *source,
3417	struct amdgpu_iv_entry *entry)
3418	{
3419	uint32_t disp_int, mask;
3420	unsigned hpd;
3421
3422	if (entry->src_data[0] >= adev->mode_info.num_hpd) {
3423	DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3424	return 0;
3425	}
3426
3427	hpd = entry->src_data[0];
3428	disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3429	mask = interrupt_status_offsets[hpd].hpd;
3430
3431	if (disp_int & mask) {
3432	dce_v11_0_hpd_int_ack(adev, hpd);
3433	schedule_delayed_work(dwork: &adev->hotplug_work, delay: 0);
3434	DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3435	}
3436
3437	return 0;
3438	}
3439
3440	static int dce_v11_0_set_clockgating_state(void *handle,
3441	enum amd_clockgating_state state)
3442	{
3443	return 0;
3444	}
3445
3446	static int dce_v11_0_set_powergating_state(void *handle,
3447	enum amd_powergating_state state)
3448	{
3449	return 0;
3450	}
3451
3452	static const struct amd_ip_funcs dce_v11_0_ip_funcs = {
3453	.name = "dce_v11_0",
3454	.early_init = dce_v11_0_early_init,
3455	.late_init = NULL,
3456	.sw_init = dce_v11_0_sw_init,
3457	.sw_fini = dce_v11_0_sw_fini,
3458	.hw_init = dce_v11_0_hw_init,
3459	.hw_fini = dce_v11_0_hw_fini,
3460	.suspend = dce_v11_0_suspend,
3461	.resume = dce_v11_0_resume,
3462	.is_idle = dce_v11_0_is_idle,
3463	.wait_for_idle = dce_v11_0_wait_for_idle,
3464	.soft_reset = dce_v11_0_soft_reset,
3465	.set_clockgating_state = dce_v11_0_set_clockgating_state,
3466	.set_powergating_state = dce_v11_0_set_powergating_state,
3467	};
3468
3469	static void
3470	dce_v11_0_encoder_mode_set(struct drm_encoder *encoder,
3471	struct drm_display_mode *mode,
3472	struct drm_display_mode *adjusted_mode)
3473	{
3474	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3475
3476	amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3477
3478	/* need to call this here rather than in prepare() since we need some crtc info */
3479	amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3480
3481	/* set scaler clears this on some chips */
3482	dce_v11_0_set_interleave(crtc: encoder->crtc, mode);
3483
3484	if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3485	dce_v11_0_afmt_enable(encoder, enable: true);
3486	dce_v11_0_afmt_setmode(encoder, mode: adjusted_mode);
3487	}
3488	}
3489
3490	static void dce_v11_0_encoder_prepare(struct drm_encoder *encoder)
3491	{
3492	struct amdgpu_device *adev = drm_to_adev(ddev: encoder->dev);
3493	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3494	struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3495
3496	if ((amdgpu_encoder->active_device &
3497	(ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3498	(amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3499	ENCODER_OBJECT_ID_NONE)) {
3500	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3501	if (dig) {
3502	dig->dig_encoder = dce_v11_0_pick_dig_encoder(encoder);
3503	if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3504	dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3505	}
3506	}
3507
3508	amdgpu_atombios_scratch_regs_lock(adev, lock: true);
3509
3510	if (connector) {
3511	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3512
3513	/* select the clock/data port if it uses a router */
3514	if (amdgpu_connector->router.cd_valid)
3515	amdgpu_i2c_router_select_cd_port(connector: amdgpu_connector);
3516
3517	/* turn eDP panel on for mode set */
3518	if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3519	amdgpu_atombios_encoder_set_edp_panel_power(connector,
3520	ATOM_TRANSMITTER_ACTION_POWER_ON);
3521	}
3522
3523	/* this is needed for the pll/ss setup to work correctly in some cases */
3524	amdgpu_atombios_encoder_set_crtc_source(encoder);
3525	/* set up the FMT blocks */
3526	dce_v11_0_program_fmt(encoder);
3527	}
3528
3529	static void dce_v11_0_encoder_commit(struct drm_encoder *encoder)
3530	{
3531	struct drm_device *dev = encoder->dev;
3532	struct amdgpu_device *adev = drm_to_adev(ddev: dev);
3533
3534	/* need to call this here as we need the crtc set up */
3535	amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3536	amdgpu_atombios_scratch_regs_lock(adev, lock: false);
3537	}
3538
3539	static void dce_v11_0_encoder_disable(struct drm_encoder *encoder)
3540	{
3541	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3542	struct amdgpu_encoder_atom_dig *dig;
3543
3544	amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3545
3546	if (amdgpu_atombios_encoder_is_digital(encoder)) {
3547	if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3548	dce_v11_0_afmt_enable(encoder, enable: false);
3549	dig = amdgpu_encoder->enc_priv;
3550	dig->dig_encoder = -1;
3551	}
3552	amdgpu_encoder->active_device = 0;
3553	}
3554
3555	/* these are handled by the primary encoders */
3556	static void dce_v11_0_ext_prepare(struct drm_encoder *encoder)
3557	{
3558
3559	}
3560
3561	static void dce_v11_0_ext_commit(struct drm_encoder *encoder)
3562	{
3563
3564	}
3565
3566	static void
3567	dce_v11_0_ext_mode_set(struct drm_encoder *encoder,
3568	struct drm_display_mode *mode,
3569	struct drm_display_mode *adjusted_mode)
3570	{
3571
3572	}
3573
3574	static void dce_v11_0_ext_disable(struct drm_encoder *encoder)
3575	{
3576
3577	}
3578
3579	static void
3580	dce_v11_0_ext_dpms(struct drm_encoder *encoder, int mode)
3581	{
3582
3583	}
3584
3585	static const struct drm_encoder_helper_funcs dce_v11_0_ext_helper_funcs = {
3586	.dpms = dce_v11_0_ext_dpms,
3587	.prepare = dce_v11_0_ext_prepare,
3588	.mode_set = dce_v11_0_ext_mode_set,
3589	.commit = dce_v11_0_ext_commit,
3590	.disable = dce_v11_0_ext_disable,
3591	/* no detect for TMDS/LVDS yet */
3592	};
3593
3594	static const struct drm_encoder_helper_funcs dce_v11_0_dig_helper_funcs = {
3595	.dpms = amdgpu_atombios_encoder_dpms,
3596	.mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3597	.prepare = dce_v11_0_encoder_prepare,
3598	.mode_set = dce_v11_0_encoder_mode_set,
3599	.commit = dce_v11_0_encoder_commit,
3600	.disable = dce_v11_0_encoder_disable,
3601	.detect = amdgpu_atombios_encoder_dig_detect,
3602	};
3603
3604	static const struct drm_encoder_helper_funcs dce_v11_0_dac_helper_funcs = {
3605	.dpms = amdgpu_atombios_encoder_dpms,
3606	.mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3607	.prepare = dce_v11_0_encoder_prepare,
3608	.mode_set = dce_v11_0_encoder_mode_set,
3609	.commit = dce_v11_0_encoder_commit,
3610	.detect = amdgpu_atombios_encoder_dac_detect,
3611	};
3612
3613	static void dce_v11_0_encoder_destroy(struct drm_encoder *encoder)
3614	{
3615	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3616	if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3617	amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3618	kfree(objp: amdgpu_encoder->enc_priv);
3619	drm_encoder_cleanup(encoder);
3620	kfree(objp: amdgpu_encoder);
3621	}
3622
3623	static const struct drm_encoder_funcs dce_v11_0_encoder_funcs = {
3624	.destroy = dce_v11_0_encoder_destroy,
3625	};
3626
3627	static void dce_v11_0_encoder_add(struct amdgpu_device *adev,
3628	uint32_t encoder_enum,
3629	uint32_t supported_device,
3630	u16 caps)
3631	{
3632	struct drm_device *dev = adev_to_drm(adev);
3633	struct drm_encoder *encoder;
3634	struct amdgpu_encoder *amdgpu_encoder;
3635
3636	/* see if we already added it */
3637	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3638	amdgpu_encoder = to_amdgpu_encoder(encoder);
3639	if (amdgpu_encoder->encoder_enum == encoder_enum) {
3640	amdgpu_encoder->devices |= supported_device;
3641	return;
3642	}
3643
3644	}
3645
3646	/* add a new one */
3647	amdgpu_encoder = kzalloc(size: sizeof(struct amdgpu_encoder), GFP_KERNEL);
3648	if (!amdgpu_encoder)
3649	return;
3650
3651	encoder = &amdgpu_encoder->base;
3652	switch (adev->mode_info.num_crtc) {
3653	case 1:
3654	encoder->possible_crtcs = 0x1;
3655	break;
3656	case 2:
3657	default:
3658	encoder->possible_crtcs = 0x3;
3659	break;
3660	case 3:
3661	encoder->possible_crtcs = 0x7;
3662	break;
3663	case 4:
3664	encoder->possible_crtcs = 0xf;
3665	break;
3666	case 5:
3667	encoder->possible_crtcs = 0x1f;
3668	break;
3669	case 6:
3670	encoder->possible_crtcs = 0x3f;
3671	break;
3672	}
3673
3674	amdgpu_encoder->enc_priv = NULL;
3675
3676	amdgpu_encoder->encoder_enum = encoder_enum;
3677	amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3678	amdgpu_encoder->devices = supported_device;
3679	amdgpu_encoder->rmx_type = RMX_OFF;
3680	amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3681	amdgpu_encoder->is_ext_encoder = false;
3682	amdgpu_encoder->caps = caps;
3683
3684	switch (amdgpu_encoder->encoder_id) {
3685	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3686	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3687	drm_encoder_init(dev, encoder, funcs: &dce_v11_0_encoder_funcs,
3688	DRM_MODE_ENCODER_DAC, NULL);
3689	drm_encoder_helper_add(encoder, funcs: &dce_v11_0_dac_helper_funcs);
3690	break;
3691	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3692	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3693	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3694	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3695	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3696	if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3697	amdgpu_encoder->rmx_type = RMX_FULL;
3698	drm_encoder_init(dev, encoder, funcs: &dce_v11_0_encoder_funcs,
3699	DRM_MODE_ENCODER_LVDS, NULL);
3700	amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(encoder: amdgpu_encoder);
3701	} else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3702	drm_encoder_init(dev, encoder, funcs: &dce_v11_0_encoder_funcs,
3703	DRM_MODE_ENCODER_DAC, NULL);
3704	amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3705	} else {
3706	drm_encoder_init(dev, encoder, funcs: &dce_v11_0_encoder_funcs,
3707	DRM_MODE_ENCODER_TMDS, NULL);
3708	amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3709	}
3710	drm_encoder_helper_add(encoder, funcs: &dce_v11_0_dig_helper_funcs);
3711	break;
3712	case ENCODER_OBJECT_ID_SI170B:
3713	case ENCODER_OBJECT_ID_CH7303:
3714	case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3715	case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3716	case ENCODER_OBJECT_ID_TITFP513:
3717	case ENCODER_OBJECT_ID_VT1623:
3718	case ENCODER_OBJECT_ID_HDMI_SI1930:
3719	case ENCODER_OBJECT_ID_TRAVIS:
3720	case ENCODER_OBJECT_ID_NUTMEG:
3721	/* these are handled by the primary encoders */
3722	amdgpu_encoder->is_ext_encoder = true;
3723	if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3724	drm_encoder_init(dev, encoder, funcs: &dce_v11_0_encoder_funcs,
3725	DRM_MODE_ENCODER_LVDS, NULL);
3726	else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3727	drm_encoder_init(dev, encoder, funcs: &dce_v11_0_encoder_funcs,
3728	DRM_MODE_ENCODER_DAC, NULL);
3729	else
3730	drm_encoder_init(dev, encoder, funcs: &dce_v11_0_encoder_funcs,
3731	DRM_MODE_ENCODER_TMDS, NULL);
3732	drm_encoder_helper_add(encoder, funcs: &dce_v11_0_ext_helper_funcs);
3733	break;
3734	}
3735	}
3736
3737	static const struct amdgpu_display_funcs dce_v11_0_display_funcs = {
3738	.bandwidth_update = &dce_v11_0_bandwidth_update,
3739	.vblank_get_counter = &dce_v11_0_vblank_get_counter,
3740	.backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3741	.backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3742	.hpd_sense = &dce_v11_0_hpd_sense,
3743	.hpd_set_polarity = &dce_v11_0_hpd_set_polarity,
3744	.hpd_get_gpio_reg = &dce_v11_0_hpd_get_gpio_reg,
3745	.page_flip = &dce_v11_0_page_flip,
3746	.page_flip_get_scanoutpos = &dce_v11_0_crtc_get_scanoutpos,
3747	.add_encoder = &dce_v11_0_encoder_add,
3748	.add_connector = &amdgpu_connector_add,
3749	};
3750
3751	static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev)
3752	{
3753	adev->mode_info.funcs = &dce_v11_0_display_funcs;
3754	}
3755
3756	static const struct amdgpu_irq_src_funcs dce_v11_0_crtc_irq_funcs = {
3757	.set = dce_v11_0_set_crtc_irq_state,
3758	.process = dce_v11_0_crtc_irq,
3759	};
3760
3761	static const struct amdgpu_irq_src_funcs dce_v11_0_pageflip_irq_funcs = {
3762	.set = dce_v11_0_set_pageflip_irq_state,
3763	.process = dce_v11_0_pageflip_irq,
3764	};
3765
3766	static const struct amdgpu_irq_src_funcs dce_v11_0_hpd_irq_funcs = {
3767	.set = dce_v11_0_set_hpd_irq_state,
3768	.process = dce_v11_0_hpd_irq,
3769	};
3770
3771	static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev)
3772	{
3773	if (adev->mode_info.num_crtc > 0)
3774	adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc;
3775	else
3776	adev->crtc_irq.num_types = 0;
3777	adev->crtc_irq.funcs = &dce_v11_0_crtc_irq_funcs;
3778
3779	adev->pageflip_irq.num_types = adev->mode_info.num_crtc;
3780	adev->pageflip_irq.funcs = &dce_v11_0_pageflip_irq_funcs;
3781
3782	adev->hpd_irq.num_types = adev->mode_info.num_hpd;
3783	adev->hpd_irq.funcs = &dce_v11_0_hpd_irq_funcs;
3784	}
3785
3786	const struct amdgpu_ip_block_version dce_v11_0_ip_block =
3787	{
3788	.type = AMD_IP_BLOCK_TYPE_DCE,
3789	.major = 11,
3790	.minor = 0,
3791	.rev = 0,
3792	.funcs = &dce_v11_0_ip_funcs,
3793	};
3794
3795	const struct amdgpu_ip_block_version dce_v11_2_ip_block =
3796	{
3797	.type = AMD_IP_BLOCK_TYPE_DCE,
3798	.major = 11,
3799	.minor = 2,
3800	.rev = 0,
3801	.funcs = &dce_v11_0_ip_funcs,
3802	};
3803