1 | /* |
2 | * Copyright 2021 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | */ |
23 | #include <linux/firmware.h> |
24 | #include <linux/slab.h> |
25 | #include <linux/module.h> |
26 | #include <linux/pci.h> |
27 | |
28 | #include "amdgpu.h" |
29 | #include "amdgpu_atombios.h" |
30 | #include "amdgpu_ih.h" |
31 | #include "amdgpu_uvd.h" |
32 | #include "amdgpu_vce.h" |
33 | #include "amdgpu_ucode.h" |
34 | #include "amdgpu_psp.h" |
35 | #include "amdgpu_smu.h" |
36 | #include "atom.h" |
37 | #include "amd_pcie.h" |
38 | |
39 | #include "gc/gc_11_0_0_offset.h" |
40 | #include "gc/gc_11_0_0_sh_mask.h" |
41 | #include "mp/mp_13_0_0_offset.h" |
42 | |
43 | #include "soc15.h" |
44 | #include "soc15_common.h" |
45 | #include "soc21.h" |
46 | #include "mxgpu_nv.h" |
47 | |
48 | static const struct amd_ip_funcs soc21_common_ip_funcs; |
49 | |
50 | /* SOC21 */ |
51 | static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn0[] = { |
52 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)}, |
53 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)}, |
54 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, |
55 | }; |
56 | |
57 | static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn1[] = { |
58 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)}, |
59 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)}, |
60 | }; |
61 | |
62 | static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode_vcn0 = { |
63 | .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_encode_array_vcn0), |
64 | .codec_array = vcn_4_0_0_video_codecs_encode_array_vcn0, |
65 | }; |
66 | |
67 | static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode_vcn1 = { |
68 | .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_encode_array_vcn1), |
69 | .codec_array = vcn_4_0_0_video_codecs_encode_array_vcn1, |
70 | }; |
71 | |
72 | static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decode_array_vcn0[] = { |
73 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, |
74 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, |
75 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, |
76 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, |
77 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, |
78 | }; |
79 | |
80 | static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decode_array_vcn1[] = { |
81 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, |
82 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, |
83 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, |
84 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, |
85 | }; |
86 | |
87 | static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode_vcn0 = { |
88 | .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_decode_array_vcn0), |
89 | .codec_array = vcn_4_0_0_video_codecs_decode_array_vcn0, |
90 | }; |
91 | |
92 | static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode_vcn1 = { |
93 | .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_decode_array_vcn1), |
94 | .codec_array = vcn_4_0_0_video_codecs_decode_array_vcn1, |
95 | }; |
96 | |
97 | /* SRIOV SOC21, not const since data is controlled by host */ |
98 | static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_encode_array_vcn0[] = { |
99 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)}, |
100 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)}, |
101 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, |
102 | }; |
103 | |
104 | static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_encode_array_vcn1[] = { |
105 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)}, |
106 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)}, |
107 | }; |
108 | |
109 | static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_encode_vcn0 = { |
110 | .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn0), |
111 | .codec_array = sriov_vcn_4_0_0_video_codecs_encode_array_vcn0, |
112 | }; |
113 | |
114 | static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_encode_vcn1 = { |
115 | .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn1), |
116 | .codec_array = sriov_vcn_4_0_0_video_codecs_encode_array_vcn1, |
117 | }; |
118 | |
119 | static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_decode_array_vcn0[] = { |
120 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, |
121 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, |
122 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, |
123 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, |
124 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, |
125 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, |
126 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, |
127 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, |
128 | }; |
129 | |
130 | static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_decode_array_vcn1[] = { |
131 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, |
132 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, |
133 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, |
134 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, |
135 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, |
136 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, |
137 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, |
138 | }; |
139 | |
140 | static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_decode_vcn0 = { |
141 | .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn0), |
142 | .codec_array = sriov_vcn_4_0_0_video_codecs_decode_array_vcn0, |
143 | }; |
144 | |
145 | static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_decode_vcn1 = { |
146 | .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn1), |
147 | .codec_array = sriov_vcn_4_0_0_video_codecs_decode_array_vcn1, |
148 | }; |
149 | |
150 | static int soc21_query_video_codecs(struct amdgpu_device *adev, bool encode, |
151 | const struct amdgpu_video_codecs **codecs) |
152 | { |
153 | if (adev->vcn.num_vcn_inst == hweight8(adev->vcn.harvest_config)) |
154 | return -EINVAL; |
155 | |
156 | switch (amdgpu_ip_version(adev, ip: UVD_HWIP, inst: 0)) { |
157 | case IP_VERSION(4, 0, 0): |
158 | case IP_VERSION(4, 0, 2): |
159 | case IP_VERSION(4, 0, 4): |
160 | case IP_VERSION(4, 0, 5): |
161 | if (amdgpu_sriov_vf(adev)) { |
162 | if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) || |
163 | !amdgpu_sriov_is_av1_support(adev)) { |
164 | if (encode) |
165 | *codecs = &sriov_vcn_4_0_0_video_codecs_encode_vcn1; |
166 | else |
167 | *codecs = &sriov_vcn_4_0_0_video_codecs_decode_vcn1; |
168 | } else { |
169 | if (encode) |
170 | *codecs = &sriov_vcn_4_0_0_video_codecs_encode_vcn0; |
171 | else |
172 | *codecs = &sriov_vcn_4_0_0_video_codecs_decode_vcn0; |
173 | } |
174 | } else { |
175 | if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0)) { |
176 | if (encode) |
177 | *codecs = &vcn_4_0_0_video_codecs_encode_vcn1; |
178 | else |
179 | *codecs = &vcn_4_0_0_video_codecs_decode_vcn1; |
180 | } else { |
181 | if (encode) |
182 | *codecs = &vcn_4_0_0_video_codecs_encode_vcn0; |
183 | else |
184 | *codecs = &vcn_4_0_0_video_codecs_decode_vcn0; |
185 | } |
186 | } |
187 | return 0; |
188 | case IP_VERSION(4, 0, 6): |
189 | if (encode) |
190 | *codecs = &vcn_4_0_0_video_codecs_encode_vcn0; |
191 | else |
192 | *codecs = &vcn_4_0_0_video_codecs_decode_vcn0; |
193 | return 0; |
194 | default: |
195 | return -EINVAL; |
196 | } |
197 | } |
198 | |
199 | static u32 soc21_didt_rreg(struct amdgpu_device *adev, u32 reg) |
200 | { |
201 | unsigned long flags, address, data; |
202 | u32 r; |
203 | |
204 | address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX); |
205 | data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA); |
206 | |
207 | spin_lock_irqsave(&adev->didt_idx_lock, flags); |
208 | WREG32(address, (reg)); |
209 | r = RREG32(data); |
210 | spin_unlock_irqrestore(lock: &adev->didt_idx_lock, flags); |
211 | return r; |
212 | } |
213 | |
214 | static void soc21_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) |
215 | { |
216 | unsigned long flags, address, data; |
217 | |
218 | address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX); |
219 | data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA); |
220 | |
221 | spin_lock_irqsave(&adev->didt_idx_lock, flags); |
222 | WREG32(address, (reg)); |
223 | WREG32(data, (v)); |
224 | spin_unlock_irqrestore(lock: &adev->didt_idx_lock, flags); |
225 | } |
226 | |
227 | static u32 soc21_get_config_memsize(struct amdgpu_device *adev) |
228 | { |
229 | return adev->nbio.funcs->get_memsize(adev); |
230 | } |
231 | |
232 | static u32 soc21_get_xclk(struct amdgpu_device *adev) |
233 | { |
234 | return adev->clock.spll.reference_freq; |
235 | } |
236 | |
237 | |
238 | void soc21_grbm_select(struct amdgpu_device *adev, |
239 | u32 me, u32 pipe, u32 queue, u32 vmid) |
240 | { |
241 | u32 grbm_gfx_cntl = 0; |
242 | grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); |
243 | grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); |
244 | grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); |
245 | grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); |
246 | |
247 | WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, grbm_gfx_cntl); |
248 | } |
249 | |
250 | static bool soc21_read_disabled_bios(struct amdgpu_device *adev) |
251 | { |
252 | /* todo */ |
253 | return false; |
254 | } |
255 | |
256 | static struct soc15_allowed_register_entry soc21_allowed_read_registers[] = { |
257 | { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS)}, |
258 | { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS2)}, |
259 | { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE0)}, |
260 | { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE1)}, |
261 | { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE2)}, |
262 | { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE3)}, |
263 | { SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_STATUS_REG)}, |
264 | { SOC15_REG_ENTRY(SDMA1, 0, regSDMA1_STATUS_REG)}, |
265 | { SOC15_REG_ENTRY(GC, 0, regCP_STAT)}, |
266 | { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT1)}, |
267 | { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT2)}, |
268 | { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT3)}, |
269 | { SOC15_REG_ENTRY(GC, 0, regCP_CPF_BUSY_STAT)}, |
270 | { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STALLED_STAT1)}, |
271 | { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STATUS)}, |
272 | { SOC15_REG_ENTRY(GC, 0, regCP_CPC_BUSY_STAT)}, |
273 | { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STALLED_STAT1)}, |
274 | { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STATUS)}, |
275 | { SOC15_REG_ENTRY(GC, 0, regGB_ADDR_CONFIG)}, |
276 | }; |
277 | |
278 | static uint32_t soc21_read_indexed_register(struct amdgpu_device *adev, u32 se_num, |
279 | u32 sh_num, u32 reg_offset) |
280 | { |
281 | uint32_t val; |
282 | |
283 | mutex_lock(&adev->grbm_idx_mutex); |
284 | if (se_num != 0xffffffff || sh_num != 0xffffffff) |
285 | amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); |
286 | |
287 | val = RREG32(reg_offset); |
288 | |
289 | if (se_num != 0xffffffff || sh_num != 0xffffffff) |
290 | amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); |
291 | mutex_unlock(lock: &adev->grbm_idx_mutex); |
292 | return val; |
293 | } |
294 | |
295 | static uint32_t soc21_get_register_value(struct amdgpu_device *adev, |
296 | bool indexed, u32 se_num, |
297 | u32 sh_num, u32 reg_offset) |
298 | { |
299 | if (indexed) { |
300 | return soc21_read_indexed_register(adev, se_num, sh_num, reg_offset); |
301 | } else { |
302 | if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG) && adev->gfx.config.gb_addr_config) |
303 | return adev->gfx.config.gb_addr_config; |
304 | return RREG32(reg_offset); |
305 | } |
306 | } |
307 | |
308 | static int soc21_read_register(struct amdgpu_device *adev, u32 se_num, |
309 | u32 sh_num, u32 reg_offset, u32 *value) |
310 | { |
311 | uint32_t i; |
312 | struct soc15_allowed_register_entry *en; |
313 | |
314 | *value = 0; |
315 | for (i = 0; i < ARRAY_SIZE(soc21_allowed_read_registers); i++) { |
316 | en = &soc21_allowed_read_registers[i]; |
317 | if (!adev->reg_offset[en->hwip][en->inst]) |
318 | continue; |
319 | else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] |
320 | + en->reg_offset)) |
321 | continue; |
322 | |
323 | *value = soc21_get_register_value(adev, |
324 | indexed: soc21_allowed_read_registers[i].grbm_indexed, |
325 | se_num, sh_num, reg_offset); |
326 | return 0; |
327 | } |
328 | return -EINVAL; |
329 | } |
330 | |
331 | #if 0 |
332 | static int soc21_asic_mode1_reset(struct amdgpu_device *adev) |
333 | { |
334 | u32 i; |
335 | int ret = 0; |
336 | |
337 | amdgpu_atombios_scratch_regs_engine_hung(adev, true); |
338 | |
339 | /* disable BM */ |
340 | pci_clear_master(adev->pdev); |
341 | |
342 | amdgpu_device_cache_pci_state(adev->pdev); |
343 | |
344 | if (amdgpu_dpm_is_mode1_reset_supported(adev)) { |
345 | dev_info(adev->dev, "GPU smu mode1 reset\n" ); |
346 | ret = amdgpu_dpm_mode1_reset(adev); |
347 | } else { |
348 | dev_info(adev->dev, "GPU psp mode1 reset\n" ); |
349 | ret = psp_gpu_reset(adev); |
350 | } |
351 | |
352 | if (ret) |
353 | dev_err(adev->dev, "GPU mode1 reset failed\n" ); |
354 | amdgpu_device_load_pci_state(adev->pdev); |
355 | |
356 | /* wait for asic to come out of reset */ |
357 | for (i = 0; i < adev->usec_timeout; i++) { |
358 | u32 memsize = adev->nbio.funcs->get_memsize(adev); |
359 | |
360 | if (memsize != 0xffffffff) |
361 | break; |
362 | udelay(1); |
363 | } |
364 | |
365 | amdgpu_atombios_scratch_regs_engine_hung(adev, false); |
366 | |
367 | return ret; |
368 | } |
369 | #endif |
370 | |
371 | static enum amd_reset_method |
372 | soc21_asic_reset_method(struct amdgpu_device *adev) |
373 | { |
374 | if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || |
375 | amdgpu_reset_method == AMD_RESET_METHOD_MODE2 || |
376 | amdgpu_reset_method == AMD_RESET_METHOD_BACO) |
377 | return amdgpu_reset_method; |
378 | |
379 | if (amdgpu_reset_method != -1) |
380 | dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n" , |
381 | amdgpu_reset_method); |
382 | |
383 | switch (amdgpu_ip_version(adev, ip: MP1_HWIP, inst: 0)) { |
384 | case IP_VERSION(13, 0, 0): |
385 | case IP_VERSION(13, 0, 7): |
386 | case IP_VERSION(13, 0, 10): |
387 | return AMD_RESET_METHOD_MODE1; |
388 | case IP_VERSION(13, 0, 4): |
389 | case IP_VERSION(13, 0, 11): |
390 | case IP_VERSION(14, 0, 0): |
391 | case IP_VERSION(14, 0, 1): |
392 | return AMD_RESET_METHOD_MODE2; |
393 | default: |
394 | if (amdgpu_dpm_is_baco_supported(adev)) |
395 | return AMD_RESET_METHOD_BACO; |
396 | else |
397 | return AMD_RESET_METHOD_MODE1; |
398 | } |
399 | } |
400 | |
401 | static int soc21_asic_reset(struct amdgpu_device *adev) |
402 | { |
403 | int ret = 0; |
404 | |
405 | switch (soc21_asic_reset_method(adev)) { |
406 | case AMD_RESET_METHOD_PCI: |
407 | dev_info(adev->dev, "PCI reset\n" ); |
408 | ret = amdgpu_device_pci_reset(adev); |
409 | break; |
410 | case AMD_RESET_METHOD_BACO: |
411 | dev_info(adev->dev, "BACO reset\n" ); |
412 | ret = amdgpu_dpm_baco_reset(adev); |
413 | break; |
414 | case AMD_RESET_METHOD_MODE2: |
415 | dev_info(adev->dev, "MODE2 reset\n" ); |
416 | ret = amdgpu_dpm_mode2_reset(adev); |
417 | break; |
418 | default: |
419 | dev_info(adev->dev, "MODE1 reset\n" ); |
420 | ret = amdgpu_device_mode1_reset(adev); |
421 | break; |
422 | } |
423 | |
424 | return ret; |
425 | } |
426 | |
427 | static int soc21_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) |
428 | { |
429 | /* todo */ |
430 | return 0; |
431 | } |
432 | |
433 | static int soc21_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) |
434 | { |
435 | /* todo */ |
436 | return 0; |
437 | } |
438 | |
439 | static void soc21_program_aspm(struct amdgpu_device *adev) |
440 | { |
441 | if (!amdgpu_device_should_use_aspm(adev)) |
442 | return; |
443 | |
444 | if (adev->nbio.funcs->program_aspm) |
445 | adev->nbio.funcs->program_aspm(adev); |
446 | } |
447 | |
448 | const struct amdgpu_ip_block_version soc21_common_ip_block = { |
449 | .type = AMD_IP_BLOCK_TYPE_COMMON, |
450 | .major = 1, |
451 | .minor = 0, |
452 | .rev = 0, |
453 | .funcs = &soc21_common_ip_funcs, |
454 | }; |
455 | |
456 | static bool soc21_need_full_reset(struct amdgpu_device *adev) |
457 | { |
458 | switch (amdgpu_ip_version(adev, ip: GC_HWIP, inst: 0)) { |
459 | case IP_VERSION(11, 0, 0): |
460 | case IP_VERSION(11, 0, 2): |
461 | case IP_VERSION(11, 0, 3): |
462 | default: |
463 | return true; |
464 | } |
465 | } |
466 | |
467 | static bool soc21_need_reset_on_init(struct amdgpu_device *adev) |
468 | { |
469 | u32 sol_reg; |
470 | |
471 | if (adev->flags & AMD_IS_APU) |
472 | return false; |
473 | |
474 | /* Check sOS sign of life register to confirm sys driver and sOS |
475 | * are already been loaded. |
476 | */ |
477 | sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); |
478 | if (sol_reg) |
479 | return true; |
480 | |
481 | return false; |
482 | } |
483 | |
484 | static void soc21_init_doorbell_index(struct amdgpu_device *adev) |
485 | { |
486 | adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; |
487 | adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; |
488 | adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; |
489 | adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; |
490 | adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; |
491 | adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; |
492 | adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; |
493 | adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; |
494 | adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; |
495 | adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; |
496 | adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; |
497 | adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; |
498 | adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; |
499 | adev->doorbell_index.gfx_userqueue_start = |
500 | AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START; |
501 | adev->doorbell_index.gfx_userqueue_end = |
502 | AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END; |
503 | adev->doorbell_index.mes_ring0 = AMDGPU_NAVI10_DOORBELL_MES_RING0; |
504 | adev->doorbell_index.mes_ring1 = AMDGPU_NAVI10_DOORBELL_MES_RING1; |
505 | adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; |
506 | adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; |
507 | adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; |
508 | adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; |
509 | adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; |
510 | adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; |
511 | adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; |
512 | adev->doorbell_index.vpe_ring = AMDGPU_NAVI10_DOORBELL64_VPE; |
513 | adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; |
514 | adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; |
515 | |
516 | adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; |
517 | adev->doorbell_index.sdma_doorbell_range = 20; |
518 | } |
519 | |
520 | static void soc21_pre_asic_init(struct amdgpu_device *adev) |
521 | { |
522 | } |
523 | |
524 | static int soc21_update_umd_stable_pstate(struct amdgpu_device *adev, |
525 | bool enter) |
526 | { |
527 | if (enter) |
528 | amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id: 0); |
529 | else |
530 | amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id: 0); |
531 | |
532 | if (adev->gfx.funcs->update_perfmon_mgcg) |
533 | adev->gfx.funcs->update_perfmon_mgcg(adev, !enter); |
534 | |
535 | return 0; |
536 | } |
537 | |
538 | static const struct amdgpu_asic_funcs soc21_asic_funcs = { |
539 | .read_disabled_bios = &soc21_read_disabled_bios, |
540 | .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom, |
541 | .read_register = &soc21_read_register, |
542 | .reset = &soc21_asic_reset, |
543 | .reset_method = &soc21_asic_reset_method, |
544 | .get_xclk = &soc21_get_xclk, |
545 | .set_uvd_clocks = &soc21_set_uvd_clocks, |
546 | .set_vce_clocks = &soc21_set_vce_clocks, |
547 | .get_config_memsize = &soc21_get_config_memsize, |
548 | .init_doorbell_index = &soc21_init_doorbell_index, |
549 | .need_full_reset = &soc21_need_full_reset, |
550 | .need_reset_on_init = &soc21_need_reset_on_init, |
551 | .get_pcie_replay_count = &amdgpu_nbio_get_pcie_replay_count, |
552 | .supports_baco = &amdgpu_dpm_is_baco_supported, |
553 | .pre_asic_init = &soc21_pre_asic_init, |
554 | .query_video_codecs = &soc21_query_video_codecs, |
555 | .update_umd_stable_pstate = &soc21_update_umd_stable_pstate, |
556 | }; |
557 | |
558 | static int soc21_common_early_init(void *handle) |
559 | { |
560 | #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) |
561 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
562 | |
563 | adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; |
564 | adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; |
565 | adev->smc_rreg = NULL; |
566 | adev->smc_wreg = NULL; |
567 | adev->pcie_rreg = &amdgpu_device_indirect_rreg; |
568 | adev->pcie_wreg = &amdgpu_device_indirect_wreg; |
569 | adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64; |
570 | adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64; |
571 | adev->pciep_rreg = amdgpu_device_pcie_port_rreg; |
572 | adev->pciep_wreg = amdgpu_device_pcie_port_wreg; |
573 | |
574 | /* TODO: will add them during VCN v2 implementation */ |
575 | adev->uvd_ctx_rreg = NULL; |
576 | adev->uvd_ctx_wreg = NULL; |
577 | |
578 | adev->didt_rreg = &soc21_didt_rreg; |
579 | adev->didt_wreg = &soc21_didt_wreg; |
580 | |
581 | adev->asic_funcs = &soc21_asic_funcs; |
582 | |
583 | adev->rev_id = amdgpu_device_get_rev_id(adev); |
584 | adev->external_rev_id = 0xff; |
585 | switch (amdgpu_ip_version(adev, ip: GC_HWIP, inst: 0)) { |
586 | case IP_VERSION(11, 0, 0): |
587 | adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG | |
588 | AMD_CG_SUPPORT_GFX_CGLS | |
589 | #if 0 |
590 | AMD_CG_SUPPORT_GFX_3D_CGCG | |
591 | AMD_CG_SUPPORT_GFX_3D_CGLS | |
592 | #endif |
593 | AMD_CG_SUPPORT_GFX_MGCG | |
594 | AMD_CG_SUPPORT_REPEATER_FGCG | |
595 | AMD_CG_SUPPORT_GFX_FGCG | |
596 | AMD_CG_SUPPORT_GFX_PERF_CLK | |
597 | AMD_CG_SUPPORT_VCN_MGCG | |
598 | AMD_CG_SUPPORT_JPEG_MGCG | |
599 | AMD_CG_SUPPORT_ATHUB_MGCG | |
600 | AMD_CG_SUPPORT_ATHUB_LS | |
601 | AMD_CG_SUPPORT_MC_MGCG | |
602 | AMD_CG_SUPPORT_MC_LS | |
603 | AMD_CG_SUPPORT_IH_CG | |
604 | AMD_CG_SUPPORT_HDP_SD; |
605 | adev->pg_flags = AMD_PG_SUPPORT_VCN | |
606 | AMD_PG_SUPPORT_VCN_DPG | |
607 | AMD_PG_SUPPORT_JPEG | |
608 | AMD_PG_SUPPORT_ATHUB | |
609 | AMD_PG_SUPPORT_MMHUB; |
610 | adev->external_rev_id = adev->rev_id + 0x1; // TODO: need update |
611 | break; |
612 | case IP_VERSION(11, 0, 2): |
613 | adev->cg_flags = |
614 | AMD_CG_SUPPORT_GFX_CGCG | |
615 | AMD_CG_SUPPORT_GFX_CGLS | |
616 | AMD_CG_SUPPORT_REPEATER_FGCG | |
617 | AMD_CG_SUPPORT_VCN_MGCG | |
618 | AMD_CG_SUPPORT_JPEG_MGCG | |
619 | AMD_CG_SUPPORT_ATHUB_MGCG | |
620 | AMD_CG_SUPPORT_ATHUB_LS | |
621 | AMD_CG_SUPPORT_IH_CG | |
622 | AMD_CG_SUPPORT_HDP_SD; |
623 | adev->pg_flags = |
624 | AMD_PG_SUPPORT_VCN | |
625 | AMD_PG_SUPPORT_VCN_DPG | |
626 | AMD_PG_SUPPORT_JPEG | |
627 | AMD_PG_SUPPORT_ATHUB | |
628 | AMD_PG_SUPPORT_MMHUB; |
629 | adev->external_rev_id = adev->rev_id + 0x10; |
630 | break; |
631 | case IP_VERSION(11, 0, 1): |
632 | adev->cg_flags = |
633 | AMD_CG_SUPPORT_GFX_CGCG | |
634 | AMD_CG_SUPPORT_GFX_CGLS | |
635 | AMD_CG_SUPPORT_GFX_MGCG | |
636 | AMD_CG_SUPPORT_GFX_FGCG | |
637 | AMD_CG_SUPPORT_REPEATER_FGCG | |
638 | AMD_CG_SUPPORT_GFX_PERF_CLK | |
639 | AMD_CG_SUPPORT_MC_MGCG | |
640 | AMD_CG_SUPPORT_MC_LS | |
641 | AMD_CG_SUPPORT_HDP_MGCG | |
642 | AMD_CG_SUPPORT_HDP_LS | |
643 | AMD_CG_SUPPORT_ATHUB_MGCG | |
644 | AMD_CG_SUPPORT_ATHUB_LS | |
645 | AMD_CG_SUPPORT_IH_CG | |
646 | AMD_CG_SUPPORT_BIF_MGCG | |
647 | AMD_CG_SUPPORT_BIF_LS | |
648 | AMD_CG_SUPPORT_VCN_MGCG | |
649 | AMD_CG_SUPPORT_JPEG_MGCG; |
650 | adev->pg_flags = |
651 | AMD_PG_SUPPORT_GFX_PG | |
652 | AMD_PG_SUPPORT_VCN | |
653 | AMD_PG_SUPPORT_VCN_DPG | |
654 | AMD_PG_SUPPORT_JPEG; |
655 | adev->external_rev_id = adev->rev_id + 0x1; |
656 | break; |
657 | case IP_VERSION(11, 0, 3): |
658 | adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG | |
659 | AMD_CG_SUPPORT_JPEG_MGCG | |
660 | AMD_CG_SUPPORT_GFX_CGCG | |
661 | AMD_CG_SUPPORT_GFX_CGLS | |
662 | AMD_CG_SUPPORT_REPEATER_FGCG | |
663 | AMD_CG_SUPPORT_GFX_MGCG | |
664 | AMD_CG_SUPPORT_HDP_SD | |
665 | AMD_CG_SUPPORT_ATHUB_MGCG | |
666 | AMD_CG_SUPPORT_ATHUB_LS; |
667 | adev->pg_flags = AMD_PG_SUPPORT_VCN | |
668 | AMD_PG_SUPPORT_VCN_DPG | |
669 | AMD_PG_SUPPORT_JPEG; |
670 | adev->external_rev_id = adev->rev_id + 0x20; |
671 | break; |
672 | case IP_VERSION(11, 0, 4): |
673 | adev->cg_flags = |
674 | AMD_CG_SUPPORT_GFX_CGCG | |
675 | AMD_CG_SUPPORT_GFX_CGLS | |
676 | AMD_CG_SUPPORT_GFX_MGCG | |
677 | AMD_CG_SUPPORT_GFX_FGCG | |
678 | AMD_CG_SUPPORT_REPEATER_FGCG | |
679 | AMD_CG_SUPPORT_GFX_PERF_CLK | |
680 | AMD_CG_SUPPORT_MC_MGCG | |
681 | AMD_CG_SUPPORT_MC_LS | |
682 | AMD_CG_SUPPORT_HDP_MGCG | |
683 | AMD_CG_SUPPORT_HDP_LS | |
684 | AMD_CG_SUPPORT_ATHUB_MGCG | |
685 | AMD_CG_SUPPORT_ATHUB_LS | |
686 | AMD_CG_SUPPORT_IH_CG | |
687 | AMD_CG_SUPPORT_BIF_MGCG | |
688 | AMD_CG_SUPPORT_BIF_LS | |
689 | AMD_CG_SUPPORT_VCN_MGCG | |
690 | AMD_CG_SUPPORT_JPEG_MGCG; |
691 | adev->pg_flags = AMD_PG_SUPPORT_VCN | |
692 | AMD_PG_SUPPORT_VCN_DPG | |
693 | AMD_PG_SUPPORT_GFX_PG | |
694 | AMD_PG_SUPPORT_JPEG; |
695 | adev->external_rev_id = adev->rev_id + 0x80; |
696 | break; |
697 | case IP_VERSION(11, 5, 0): |
698 | adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG | |
699 | AMD_CG_SUPPORT_JPEG_MGCG | |
700 | AMD_CG_SUPPORT_GFX_CGCG | |
701 | AMD_CG_SUPPORT_GFX_CGLS | |
702 | AMD_CG_SUPPORT_GFX_MGCG | |
703 | AMD_CG_SUPPORT_GFX_FGCG | |
704 | AMD_CG_SUPPORT_REPEATER_FGCG | |
705 | AMD_CG_SUPPORT_GFX_PERF_CLK | |
706 | AMD_CG_SUPPORT_GFX_3D_CGCG | |
707 | AMD_CG_SUPPORT_GFX_3D_CGLS | |
708 | AMD_CG_SUPPORT_MC_MGCG | |
709 | AMD_CG_SUPPORT_MC_LS | |
710 | AMD_CG_SUPPORT_HDP_LS | |
711 | AMD_CG_SUPPORT_HDP_DS | |
712 | AMD_CG_SUPPORT_HDP_SD | |
713 | AMD_CG_SUPPORT_ATHUB_MGCG | |
714 | AMD_CG_SUPPORT_ATHUB_LS | |
715 | AMD_CG_SUPPORT_IH_CG | |
716 | AMD_CG_SUPPORT_BIF_MGCG | |
717 | AMD_CG_SUPPORT_BIF_LS; |
718 | adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG | |
719 | AMD_PG_SUPPORT_JPEG_DPG | |
720 | AMD_PG_SUPPORT_VCN | |
721 | AMD_PG_SUPPORT_JPEG | |
722 | AMD_PG_SUPPORT_GFX_PG; |
723 | if (adev->rev_id == 0) |
724 | adev->external_rev_id = 0x1; |
725 | else |
726 | adev->external_rev_id = adev->rev_id + 0x10; |
727 | break; |
728 | case IP_VERSION(11, 5, 1): |
729 | adev->cg_flags = |
730 | AMD_CG_SUPPORT_GFX_CGCG | |
731 | AMD_CG_SUPPORT_GFX_CGLS | |
732 | AMD_CG_SUPPORT_GFX_MGCG | |
733 | AMD_CG_SUPPORT_GFX_FGCG | |
734 | AMD_CG_SUPPORT_REPEATER_FGCG | |
735 | AMD_CG_SUPPORT_GFX_PERF_CLK | |
736 | AMD_CG_SUPPORT_GFX_3D_CGCG | |
737 | AMD_CG_SUPPORT_GFX_3D_CGLS | |
738 | AMD_CG_SUPPORT_MC_MGCG | |
739 | AMD_CG_SUPPORT_MC_LS | |
740 | AMD_CG_SUPPORT_HDP_LS | |
741 | AMD_CG_SUPPORT_HDP_DS | |
742 | AMD_CG_SUPPORT_HDP_SD | |
743 | AMD_CG_SUPPORT_ATHUB_MGCG | |
744 | AMD_CG_SUPPORT_ATHUB_LS | |
745 | AMD_CG_SUPPORT_IH_CG | |
746 | AMD_CG_SUPPORT_BIF_MGCG | |
747 | AMD_CG_SUPPORT_BIF_LS | |
748 | AMD_CG_SUPPORT_VCN_MGCG | |
749 | AMD_CG_SUPPORT_JPEG_MGCG; |
750 | adev->pg_flags = |
751 | AMD_PG_SUPPORT_GFX_PG | |
752 | AMD_PG_SUPPORT_VCN | |
753 | AMD_PG_SUPPORT_VCN_DPG | |
754 | AMD_PG_SUPPORT_JPEG; |
755 | adev->external_rev_id = adev->rev_id + 0xc1; |
756 | break; |
757 | default: |
758 | /* FIXME: not supported yet */ |
759 | return -EINVAL; |
760 | } |
761 | |
762 | if (amdgpu_sriov_vf(adev)) { |
763 | amdgpu_virt_init_setting(adev); |
764 | xgpu_nv_mailbox_set_irq_funcs(adev); |
765 | } |
766 | |
767 | return 0; |
768 | } |
769 | |
770 | static int soc21_common_late_init(void *handle) |
771 | { |
772 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
773 | |
774 | if (amdgpu_sriov_vf(adev)) { |
775 | xgpu_nv_mailbox_get_irq(adev); |
776 | if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) || |
777 | !amdgpu_sriov_is_av1_support(adev)) { |
778 | amdgpu_virt_update_sriov_video_codec(adev, |
779 | encode: sriov_vcn_4_0_0_video_codecs_encode_array_vcn1, |
780 | ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn1), |
781 | decode: sriov_vcn_4_0_0_video_codecs_decode_array_vcn1, |
782 | ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn1)); |
783 | } else { |
784 | amdgpu_virt_update_sriov_video_codec(adev, |
785 | encode: sriov_vcn_4_0_0_video_codecs_encode_array_vcn0, |
786 | ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn0), |
787 | decode: sriov_vcn_4_0_0_video_codecs_decode_array_vcn0, |
788 | ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn0)); |
789 | } |
790 | } else { |
791 | if (adev->nbio.ras && |
792 | adev->nbio.ras_err_event_athub_irq.funcs) |
793 | /* don't need to fail gpu late init |
794 | * if enabling athub_err_event interrupt failed |
795 | * nbio v4_3 only support fatal error hanlding |
796 | * just enable the interrupt directly */ |
797 | amdgpu_irq_get(adev, src: &adev->nbio.ras_err_event_athub_irq, type: 0); |
798 | } |
799 | |
800 | /* Enable selfring doorbell aperture late because doorbell BAR |
801 | * aperture will change if resize BAR successfully in gmc sw_init. |
802 | */ |
803 | adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true); |
804 | |
805 | return 0; |
806 | } |
807 | |
808 | static int soc21_common_sw_init(void *handle) |
809 | { |
810 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
811 | |
812 | if (amdgpu_sriov_vf(adev)) |
813 | xgpu_nv_mailbox_add_irq_id(adev); |
814 | |
815 | return 0; |
816 | } |
817 | |
818 | static int soc21_common_sw_fini(void *handle) |
819 | { |
820 | return 0; |
821 | } |
822 | |
823 | static int soc21_common_hw_init(void *handle) |
824 | { |
825 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
826 | |
827 | /* enable aspm */ |
828 | soc21_program_aspm(adev); |
829 | /* setup nbio registers */ |
830 | adev->nbio.funcs->init_registers(adev); |
831 | /* remap HDP registers to a hole in mmio space, |
832 | * for the purpose of expose those registers |
833 | * to process space |
834 | */ |
835 | if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev)) |
836 | adev->nbio.funcs->remap_hdp_registers(adev); |
837 | /* enable the doorbell aperture */ |
838 | adev->nbio.funcs->enable_doorbell_aperture(adev, true); |
839 | |
840 | return 0; |
841 | } |
842 | |
843 | static int soc21_common_hw_fini(void *handle) |
844 | { |
845 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
846 | |
847 | /* Disable the doorbell aperture and selfring doorbell aperture |
848 | * separately in hw_fini because soc21_enable_doorbell_aperture |
849 | * has been removed and there is no need to delay disabling |
850 | * selfring doorbell. |
851 | */ |
852 | adev->nbio.funcs->enable_doorbell_aperture(adev, false); |
853 | adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false); |
854 | |
855 | if (amdgpu_sriov_vf(adev)) { |
856 | xgpu_nv_mailbox_put_irq(adev); |
857 | } else { |
858 | if (adev->nbio.ras && |
859 | adev->nbio.ras_err_event_athub_irq.funcs) |
860 | amdgpu_irq_put(adev, src: &adev->nbio.ras_err_event_athub_irq, type: 0); |
861 | } |
862 | |
863 | return 0; |
864 | } |
865 | |
866 | static int soc21_common_suspend(void *handle) |
867 | { |
868 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
869 | |
870 | return soc21_common_hw_fini(handle: adev); |
871 | } |
872 | |
873 | static bool soc21_need_reset_on_resume(struct amdgpu_device *adev) |
874 | { |
875 | u32 sol_reg1, sol_reg2; |
876 | |
877 | /* Will reset for the following suspend abort cases. |
878 | * 1) Only reset dGPU side. |
879 | * 2) S3 suspend got aborted and TOS is active. |
880 | */ |
881 | if (!(adev->flags & AMD_IS_APU) && adev->in_s3 && |
882 | !adev->suspend_complete) { |
883 | sol_reg1 = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); |
884 | msleep(msecs: 100); |
885 | sol_reg2 = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); |
886 | |
887 | return (sol_reg1 != sol_reg2); |
888 | } |
889 | |
890 | return false; |
891 | } |
892 | |
893 | static int soc21_common_resume(void *handle) |
894 | { |
895 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
896 | |
897 | if (soc21_need_reset_on_resume(adev)) { |
898 | dev_info(adev->dev, "S3 suspend aborted, resetting..." ); |
899 | soc21_asic_reset(adev); |
900 | } |
901 | |
902 | return soc21_common_hw_init(handle: adev); |
903 | } |
904 | |
905 | static bool soc21_common_is_idle(void *handle) |
906 | { |
907 | return true; |
908 | } |
909 | |
910 | static int soc21_common_wait_for_idle(void *handle) |
911 | { |
912 | return 0; |
913 | } |
914 | |
915 | static int soc21_common_soft_reset(void *handle) |
916 | { |
917 | return 0; |
918 | } |
919 | |
920 | static int soc21_common_set_clockgating_state(void *handle, |
921 | enum amd_clockgating_state state) |
922 | { |
923 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
924 | |
925 | switch (amdgpu_ip_version(adev, ip: NBIO_HWIP, inst: 0)) { |
926 | case IP_VERSION(4, 3, 0): |
927 | case IP_VERSION(4, 3, 1): |
928 | case IP_VERSION(7, 7, 0): |
929 | case IP_VERSION(7, 7, 1): |
930 | case IP_VERSION(7, 11, 0): |
931 | case IP_VERSION(7, 11, 1): |
932 | adev->nbio.funcs->update_medium_grain_clock_gating(adev, |
933 | state == AMD_CG_STATE_GATE); |
934 | adev->nbio.funcs->update_medium_grain_light_sleep(adev, |
935 | state == AMD_CG_STATE_GATE); |
936 | adev->hdp.funcs->update_clock_gating(adev, |
937 | state == AMD_CG_STATE_GATE); |
938 | break; |
939 | default: |
940 | break; |
941 | } |
942 | return 0; |
943 | } |
944 | |
945 | static int soc21_common_set_powergating_state(void *handle, |
946 | enum amd_powergating_state state) |
947 | { |
948 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
949 | |
950 | switch (amdgpu_ip_version(adev, ip: LSDMA_HWIP, inst: 0)) { |
951 | case IP_VERSION(6, 0, 0): |
952 | case IP_VERSION(6, 0, 2): |
953 | adev->lsdma.funcs->update_memory_power_gating(adev, |
954 | state == AMD_PG_STATE_GATE); |
955 | break; |
956 | default: |
957 | break; |
958 | } |
959 | |
960 | return 0; |
961 | } |
962 | |
963 | static void soc21_common_get_clockgating_state(void *handle, u64 *flags) |
964 | { |
965 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
966 | |
967 | adev->nbio.funcs->get_clockgating_state(adev, flags); |
968 | |
969 | adev->hdp.funcs->get_clock_gating_state(adev, flags); |
970 | } |
971 | |
972 | static const struct amd_ip_funcs soc21_common_ip_funcs = { |
973 | .name = "soc21_common" , |
974 | .early_init = soc21_common_early_init, |
975 | .late_init = soc21_common_late_init, |
976 | .sw_init = soc21_common_sw_init, |
977 | .sw_fini = soc21_common_sw_fini, |
978 | .hw_init = soc21_common_hw_init, |
979 | .hw_fini = soc21_common_hw_fini, |
980 | .suspend = soc21_common_suspend, |
981 | .resume = soc21_common_resume, |
982 | .is_idle = soc21_common_is_idle, |
983 | .wait_for_idle = soc21_common_wait_for_idle, |
984 | .soft_reset = soc21_common_soft_reset, |
985 | .set_clockgating_state = soc21_common_set_clockgating_state, |
986 | .set_powergating_state = soc21_common_set_powergating_state, |
987 | .get_clockgating_state = soc21_common_get_clockgating_state, |
988 | }; |
989 | |