1	// SPDX-License-Identifier: GPL-2.0
2	/* Copyright (c) 2018-2023, Intel Corporation. */
3
4	#include "ice_common.h"
5	#include "ice_sched.h"
6	#include "ice_adminq_cmd.h"
7	#include "ice_flow.h"
8	#include "ice_ptp_hw.h"
9	#include <linux/packing.h>
10
11	#define ICE_PF_RESET_WAIT_COUNT 300
12	#define ICE_MAX_NETLIST_SIZE 10
13
14	static const char * const ice_link_mode_str_low[] = {
15	[0] = "100BASE_TX",
16	[1] = "100M_SGMII",
17	[2] = "1000BASE_T",
18	[3] = "1000BASE_SX",
19	[4] = "1000BASE_LX",
20	[5] = "1000BASE_KX",
21	[6] = "1G_SGMII",
22	[7] = "2500BASE_T",
23	[8] = "2500BASE_X",
24	[9] = "2500BASE_KX",
25	[10] = "5GBASE_T",
26	[11] = "5GBASE_KR",
27	[12] = "10GBASE_T",
28	[13] = "10G_SFI_DA",
29	[14] = "10GBASE_SR",
30	[15] = "10GBASE_LR",
31	[16] = "10GBASE_KR_CR1",
32	[17] = "10G_SFI_AOC_ACC",
33	[18] = "10G_SFI_C2C",
34	[19] = "25GBASE_T",
35	[20] = "25GBASE_CR",
36	[21] = "25GBASE_CR_S",
37	[22] = "25GBASE_CR1",
38	[23] = "25GBASE_SR",
39	[24] = "25GBASE_LR",
40	[25] = "25GBASE_KR",
41	[26] = "25GBASE_KR_S",
42	[27] = "25GBASE_KR1",
43	[28] = "25G_AUI_AOC_ACC",
44	[29] = "25G_AUI_C2C",
45	[30] = "40GBASE_CR4",
46	[31] = "40GBASE_SR4",
47	[32] = "40GBASE_LR4",
48	[33] = "40GBASE_KR4",
49	[34] = "40G_XLAUI_AOC_ACC",
50	[35] = "40G_XLAUI",
51	[36] = "50GBASE_CR2",
52	[37] = "50GBASE_SR2",
53	[38] = "50GBASE_LR2",
54	[39] = "50GBASE_KR2",
55	[40] = "50G_LAUI2_AOC_ACC",
56	[41] = "50G_LAUI2",
57	[42] = "50G_AUI2_AOC_ACC",
58	[43] = "50G_AUI2",
59	[44] = "50GBASE_CP",
60	[45] = "50GBASE_SR",
61	[46] = "50GBASE_FR",
62	[47] = "50GBASE_LR",
63	[48] = "50GBASE_KR_PAM4",
64	[49] = "50G_AUI1_AOC_ACC",
65	[50] = "50G_AUI1",
66	[51] = "100GBASE_CR4",
67	[52] = "100GBASE_SR4",
68	[53] = "100GBASE_LR4",
69	[54] = "100GBASE_KR4",
70	[55] = "100G_CAUI4_AOC_ACC",
71	[56] = "100G_CAUI4",
72	[57] = "100G_AUI4_AOC_ACC",
73	[58] = "100G_AUI4",
74	[59] = "100GBASE_CR_PAM4",
75	[60] = "100GBASE_KR_PAM4",
76	[61] = "100GBASE_CP2",
77	[62] = "100GBASE_SR2",
78	[63] = "100GBASE_DR",
79	};
80
81	static const char * const ice_link_mode_str_high[] = {
82	[0] = "100GBASE_KR2_PAM4",
83	[1] = "100G_CAUI2_AOC_ACC",
84	[2] = "100G_CAUI2",
85	[3] = "100G_AUI2_AOC_ACC",
86	[4] = "100G_AUI2",
87	};
88
89	/**
90	* ice_dump_phy_type - helper function to dump phy_type
91	* @hw: pointer to the HW structure
92	* @low: 64 bit value for phy_type_low
93	* @high: 64 bit value for phy_type_high
94	* @prefix: prefix string to differentiate multiple dumps
95	*/
96	static void
97	ice_dump_phy_type(struct ice_hw *hw, u64 low, u64 high, const char *prefix)
98	{
99	ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_low: 0x%016llx\n", prefix, low);
100
101	for (u32 i = 0; i < BITS_PER_TYPE(typeof(low)); i++) {
102	if (low & BIT_ULL(i))
103	ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n",
104	prefix, i, ice_link_mode_str_low[i]);
105	}
106
107	ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_high: 0x%016llx\n", prefix, high);
108
109	for (u32 i = 0; i < BITS_PER_TYPE(typeof(high)); i++) {
110	if (high & BIT_ULL(i))
111	ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n",
112	prefix, i, ice_link_mode_str_high[i]);
113	}
114	}
115
116	/**
117	* ice_set_mac_type - Sets MAC type
118	* @hw: pointer to the HW structure
119	*
120	* This function sets the MAC type of the adapter based on the
121	* vendor ID and device ID stored in the HW structure.
122	*/
123	static int ice_set_mac_type(struct ice_hw *hw)
124	{
125	if (hw->vendor_id != PCI_VENDOR_ID_INTEL)
126	return -ENODEV;
127
128	switch (hw->device_id) {
129	case ICE_DEV_ID_E810C_BACKPLANE:
130	case ICE_DEV_ID_E810C_QSFP:
131	case ICE_DEV_ID_E810C_SFP:
132	case ICE_DEV_ID_E810_XXV_BACKPLANE:
133	case ICE_DEV_ID_E810_XXV_QSFP:
134	case ICE_DEV_ID_E810_XXV_SFP:
135	hw->mac_type = ICE_MAC_E810;
136	break;
137	case ICE_DEV_ID_E823C_10G_BASE_T:
138	case ICE_DEV_ID_E823C_BACKPLANE:
139	case ICE_DEV_ID_E823C_QSFP:
140	case ICE_DEV_ID_E823C_SFP:
141	case ICE_DEV_ID_E823C_SGMII:
142	case ICE_DEV_ID_E822C_10G_BASE_T:
143	case ICE_DEV_ID_E822C_BACKPLANE:
144	case ICE_DEV_ID_E822C_QSFP:
145	case ICE_DEV_ID_E822C_SFP:
146	case ICE_DEV_ID_E822C_SGMII:
147	case ICE_DEV_ID_E822L_10G_BASE_T:
148	case ICE_DEV_ID_E822L_BACKPLANE:
149	case ICE_DEV_ID_E822L_SFP:
150	case ICE_DEV_ID_E822L_SGMII:
151	case ICE_DEV_ID_E823L_10G_BASE_T:
152	case ICE_DEV_ID_E823L_1GBE:
153	case ICE_DEV_ID_E823L_BACKPLANE:
154	case ICE_DEV_ID_E823L_QSFP:
155	case ICE_DEV_ID_E823L_SFP:
156	hw->mac_type = ICE_MAC_GENERIC;
157	break;
158	case ICE_DEV_ID_E825C_BACKPLANE:
159	case ICE_DEV_ID_E825C_QSFP:
160	case ICE_DEV_ID_E825C_SFP:
161	case ICE_DEV_ID_E825C_SGMII:
162	hw->mac_type = ICE_MAC_GENERIC_3K_E825;
163	break;
164	case ICE_DEV_ID_E830CC_BACKPLANE:
165	case ICE_DEV_ID_E830CC_QSFP56:
166	case ICE_DEV_ID_E830CC_SFP:
167	case ICE_DEV_ID_E830CC_SFP_DD:
168	case ICE_DEV_ID_E830C_BACKPLANE:
169	case ICE_DEV_ID_E830_XXV_BACKPLANE:
170	case ICE_DEV_ID_E830C_QSFP:
171	case ICE_DEV_ID_E830_XXV_QSFP:
172	case ICE_DEV_ID_E830C_SFP:
173	case ICE_DEV_ID_E830_XXV_SFP:
174	hw->mac_type = ICE_MAC_E830;
175	break;
176	default:
177	hw->mac_type = ICE_MAC_UNKNOWN;
178	break;
179	}
180
181	ice_debug(hw, ICE_DBG_INIT, "mac_type: %d\n", hw->mac_type);
182	return 0;
183	}
184
185	/**
186	* ice_is_generic_mac - check if device's mac_type is generic
187	* @hw: pointer to the hardware structure
188	*
189	* Return: true if mac_type is ICE_MAC_GENERIC*, false otherwise.
190	*/
191	bool ice_is_generic_mac(struct ice_hw *hw)
192	{
193	return (hw->mac_type == ICE_MAC_GENERIC ||
194	hw->mac_type == ICE_MAC_GENERIC_3K_E825);
195	}
196
197	/**
198	* ice_is_pf_c827 - check if pf contains c827 phy
199	* @hw: pointer to the hw struct
200	*
201	* Return: true if the device has c827 phy.
202	*/
203	static bool ice_is_pf_c827(struct ice_hw *hw)
204	{
205	struct ice_aqc_get_link_topo cmd = {};
206	u8 node_part_number;
207	u16 node_handle;
208	int status;
209
210	if (hw->mac_type != ICE_MAC_E810)
211	return false;
212
213	if (hw->device_id != ICE_DEV_ID_E810C_QSFP)
214	return true;
215
216	cmd.addr.topo_params.node_type_ctx =
217	FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_TYPE_M, ICE_AQC_LINK_TOPO_NODE_TYPE_PHY) |
218	FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_CTX_M, ICE_AQC_LINK_TOPO_NODE_CTX_PORT);
219	cmd.addr.topo_params.index = 0;
220
221	status = ice_aq_get_netlist_node(hw, cmd: &cmd, node_part_number: &node_part_number,
222	node_handle: &node_handle);
223
224	if (status || node_part_number != ICE_AQC_GET_LINK_TOPO_NODE_NR_C827)
225	return false;
226
227	if (node_handle == E810C_QSFP_C827_0_HANDLE || node_handle == E810C_QSFP_C827_1_HANDLE)
228	return true;
229
230	return false;
231	}
232
233	/**
234	* ice_clear_pf_cfg - Clear PF configuration
235	* @hw: pointer to the hardware structure
236	*
237	* Clears any existing PF configuration (VSIs, VSI lists, switch rules, port
238	* configuration, flow director filters, etc.).
239	*/
240	int ice_clear_pf_cfg(struct ice_hw *hw)
241	{
242	struct ice_aq_desc desc;
243
244	ice_fill_dflt_direct_cmd_desc(desc: &desc, opcode: ice_aqc_opc_clear_pf_cfg);
245
246	return ice_aq_send_cmd(hw, desc: &desc, NULL, buf_size: 0, NULL);
247	}
248
249	/**
250	* ice_aq_manage_mac_read - manage MAC address read command
251	* @hw: pointer to the HW struct
252	* @buf: a virtual buffer to hold the manage MAC read response
253	* @buf_size: Size of the virtual buffer
254	* @cd: pointer to command details structure or NULL
255	*
256	* This function is used to return per PF station MAC address (0x0107).
257	* NOTE: Upon successful completion of this command, MAC address information
258	* is returned in user specified buffer. Please interpret user specified
259	* buffer as "manage_mac_read" response.
260	* Response such as various MAC addresses are stored in HW struct (port.mac)
261	* ice_discover_dev_caps is expected to be called before this function is
262	* called.
263	*/
264	static int
265	ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size,
266	struct ice_sq_cd *cd)
267	{
268	struct ice_aqc_manage_mac_read_resp *resp;
269	struct ice_aqc_manage_mac_read *cmd;
270	struct ice_aq_desc desc;
271	int status;
272	u16 flags;
273	u8 i;
274
275	cmd = &desc.params.mac_read;
276
277	if (buf_size < sizeof(*resp))
278	return -EINVAL;
279
280	ice_fill_dflt_direct_cmd_desc(desc: &desc, opcode: ice_aqc_opc_manage_mac_read);
281
282	status = ice_aq_send_cmd(hw, desc: &desc, buf, buf_size, cd);
283	if (status)
284	return status;
285
286	resp = buf;
287	flags = le16_to_cpu(cmd->flags) & ICE_AQC_MAN_MAC_READ_M;
288
289	if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) {
290	ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n");
291	return -EIO;
292	}
293
294	/* A single port can report up to two (LAN and WoL) addresses */
295	for (i = 0; i < cmd->num_addr; i++)
296	if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) {
297	ether_addr_copy(dst: hw->port_info->mac.lan_addr,
298	src: resp[i].mac_addr);
299	ether_addr_copy(dst: hw->port_info->mac.perm_addr,
300	src: resp[i].mac_addr);
301	break;
302	}
303
304	return 0;
305	}
306
307	/**
308	* ice_aq_get_phy_caps - returns PHY capabilities
309	* @pi: port information structure
310	* @qual_mods: report qualified modules
311	* @report_mode: report mode capabilities
312	* @pcaps: structure for PHY capabilities to be filled
313	* @cd: pointer to command details structure or NULL
314	*
315	* Returns the various PHY capabilities supported on the Port (0x0600)
316	*/
317	int
318	ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,
319	struct ice_aqc_get_phy_caps_data *pcaps,
320	struct ice_sq_cd *cd)
321	{
322	struct ice_aqc_get_phy_caps *cmd;
323	u16 pcaps_size = sizeof(*pcaps);
324	struct ice_aq_desc desc;
325	const char *prefix;
326	struct ice_hw *hw;
327	int status;
328
329	cmd = &desc.params.get_phy;
330
331	if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi)
332	return -EINVAL;
333	hw = pi->hw;
334
335	if (report_mode == ICE_AQC_REPORT_DFLT_CFG &&
336	!ice_fw_supports_report_dflt_cfg(hw))
337	return -EINVAL;
338
339	ice_fill_dflt_direct_cmd_desc(desc: &desc, opcode: ice_aqc_opc_get_phy_caps);
340
341	if (qual_mods)
342	cmd->param0 |= cpu_to_le16(ICE_AQC_GET_PHY_RQM);
343
344	cmd->param0 |= cpu_to_le16(report_mode);
345	status = ice_aq_send_cmd(hw, desc: &desc, buf: pcaps, buf_size: pcaps_size, cd);
346
347	ice_debug(hw, ICE_DBG_LINK, "get phy caps dump\n");
348
349	switch (report_mode) {
350	case ICE_AQC_REPORT_TOPO_CAP_MEDIA:
351	prefix = "phy_caps_media";
352	break;
353	case ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA:
354	prefix = "phy_caps_no_media";
355	break;
356	case ICE_AQC_REPORT_ACTIVE_CFG:
357	prefix = "phy_caps_active";
358	break;
359	case ICE_AQC_REPORT_DFLT_CFG:
360	prefix = "phy_caps_default";
361	break;
362	default:
363	prefix = "phy_caps_invalid";
364	}
365
366	ice_dump_phy_type(hw, le64_to_cpu(pcaps->phy_type_low),
367	le64_to_cpu(pcaps->phy_type_high), prefix);
368
369	ice_debug(hw, ICE_DBG_LINK, "%s: report_mode = 0x%x\n",
370	prefix, report_mode);
371	ice_debug(hw, ICE_DBG_LINK, "%s: caps = 0x%x\n", prefix, pcaps->caps);
372	ice_debug(hw, ICE_DBG_LINK, "%s: low_power_ctrl_an = 0x%x\n", prefix,
373	pcaps->low_power_ctrl_an);
374	ice_debug(hw, ICE_DBG_LINK, "%s: eee_cap = 0x%x\n", prefix,
375	pcaps->eee_cap);
376	ice_debug(hw, ICE_DBG_LINK, "%s: eeer_value = 0x%x\n", prefix,
377	pcaps->eeer_value);
378	ice_debug(hw, ICE_DBG_LINK, "%s: link_fec_options = 0x%x\n", prefix,
379	pcaps->link_fec_options);
380	ice_debug(hw, ICE_DBG_LINK, "%s: module_compliance_enforcement = 0x%x\n",
381	prefix, pcaps->module_compliance_enforcement);
382	ice_debug(hw, ICE_DBG_LINK, "%s: extended_compliance_code = 0x%x\n",
383	prefix, pcaps->extended_compliance_code);
384	ice_debug(hw, ICE_DBG_LINK, "%s: module_type[0] = 0x%x\n", prefix,
385	pcaps->module_type[0]);
386	ice_debug(hw, ICE_DBG_LINK, "%s: module_type[1] = 0x%x\n", prefix,
387	pcaps->module_type[1]);
388	ice_debug(hw, ICE_DBG_LINK, "%s: module_type[2] = 0x%x\n", prefix,
389	pcaps->module_type[2]);
390
391	if (!status && report_mode == ICE_AQC_REPORT_TOPO_CAP_MEDIA) {
392	pi->phy.phy_type_low = le64_to_cpu(pcaps->phy_type_low);
393	pi->phy.phy_type_high = le64_to_cpu(pcaps->phy_type_high);
394	memcpy(pi->phy.link_info.module_type, &pcaps->module_type,
395	sizeof(pi->phy.link_info.module_type));
396	}
397
398	return status;
399	}
400
401	/**
402	* ice_aq_get_link_topo_handle - get link topology node return status
403	* @pi: port information structure
404	* @node_type: requested node type
405	* @cd: pointer to command details structure or NULL
406	*
407	* Get link topology node return status for specified node type (0x06E0)
408	*
409	* Node type cage can be used to determine if cage is present. If AQC
410	* returns error (ENOENT), then no cage present. If no cage present, then
411	* connection type is backplane or BASE-T.
412	*/
413	static int
414	ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type,
415	struct ice_sq_cd *cd)
416	{
417	struct ice_aqc_get_link_topo *cmd;
418	struct ice_aq_desc desc;
419
420	cmd = &desc.params.get_link_topo;
421
422	ice_fill_dflt_direct_cmd_desc(desc: &desc, opcode: ice_aqc_opc_get_link_topo);
423
424	cmd->addr.topo_params.node_type_ctx =
425	(ICE_AQC_LINK_TOPO_NODE_CTX_PORT <<
426	ICE_AQC_LINK_TOPO_NODE_CTX_S);
427
428	/* set node type */
429	cmd->addr.topo_params.node_type_ctx |=
430	(ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type);
431
432	return ice_aq_send_cmd(hw: pi->hw, desc: &desc, NULL, buf_size: 0, cd);
433	}
434
435	/**
436	* ice_aq_get_netlist_node
437	* @hw: pointer to the hw struct
438	* @cmd: get_link_topo AQ structure
439	* @node_part_number: output node part number if node found
440	* @node_handle: output node handle parameter if node found
441	*
442	* Get netlist node handle.
443	*/
444	int
445	ice_aq_get_netlist_node(struct ice_hw *hw, struct ice_aqc_get_link_topo *cmd,
446	u8 *node_part_number, u16 *node_handle)
447	{
448	struct ice_aq_desc desc;
449
450	ice_fill_dflt_direct_cmd_desc(desc: &desc, opcode: ice_aqc_opc_get_link_topo);
451	desc.params.get_link_topo = *cmd;
452
453	if (ice_aq_send_cmd(hw, desc: &desc, NULL, buf_size: 0, NULL))
454	return -EINTR;
455
456	if (node_handle)
457	*node_handle =
458	le16_to_cpu(desc.params.get_link_topo.addr.handle);
459	if (node_part_number)
460	*node_part_number = desc.params.get_link_topo.node_part_num;
461
462	return 0;
463	}
464
465	/**
466	* ice_find_netlist_node
467	* @hw: pointer to the hw struct
468	* @node_type: type of netlist node to look for
469	* @ctx: context of the search
470	* @node_part_number: node part number to look for
471	* @node_handle: output parameter if node found - optional
472	*
473	* Scan the netlist for a node handle of the given node type and part number.
474	*
475	* If node_handle is non-NULL it will be modified on function exit. It is only
476	* valid if the function returns zero, and should be ignored on any non-zero
477	* return value.
478	*
479	* Return:
480	* * 0 if the node is found,
481	* * -ENOENT if no handle was found,
482	* * negative error code on failure to access the AQ.
483	*/
484	static int ice_find_netlist_node(struct ice_hw *hw, u8 node_type, u8 ctx,
485	u8 node_part_number, u16 *node_handle)
486	{
487	u8 idx;
488
489	for (idx = 0; idx < ICE_MAX_NETLIST_SIZE; idx++) {
490	struct ice_aqc_get_link_topo cmd = {};
491	u8 rec_node_part_number;
492	int status;
493
494	cmd.addr.topo_params.node_type_ctx =
495	FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_TYPE_M, node_type) |
496	FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_CTX_M, ctx);
497	cmd.addr.topo_params.index = idx;
498
499	status = ice_aq_get_netlist_node(hw, cmd: &cmd,
500	node_part_number: &rec_node_part_number,
501	node_handle);
502	if (status)
503	return status;
504
505	if (rec_node_part_number == node_part_number)
506	return 0;
507	}
508
509	return -ENOENT;
510	}
511
512	/**
513	* ice_is_media_cage_present
514	* @pi: port information structure
515	*
516	* Returns true if media cage is present, else false. If no cage, then
517	* media type is backplane or BASE-T.
518	*/
519	static bool ice_is_media_cage_present(struct ice_port_info *pi)
520	{
521	/* Node type cage can be used to determine if cage is present. If AQC
522	* returns error (ENOENT), then no cage present. If no cage present then
523	* connection type is backplane or BASE-T.
524	*/
525	return !ice_aq_get_link_topo_handle(pi,
526	ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE,
527	NULL);
528	}
529
530	/**
531	* ice_get_media_type - Gets media type
532	* @pi: port information structure
533	*/
534	static enum ice_media_type ice_get_media_type(struct ice_port_info *pi)
535	{
536	struct ice_link_status *hw_link_info;
537
538	if (!pi)
539	return ICE_MEDIA_UNKNOWN;
540
541	hw_link_info = &pi->phy.link_info;
542	if (hw_link_info->phy_type_low && hw_link_info->phy_type_high)
543	/* If more than one media type is selected, report unknown */
544	return ICE_MEDIA_UNKNOWN;
545
546	if (hw_link_info->phy_type_low) {
547	/* 1G SGMII is a special case where some DA cable PHYs
548	* may show this as an option when it really shouldn't
549	* be since SGMII is meant to be between a MAC and a PHY
550	* in a backplane. Try to detect this case and handle it
551	*/
552	if (hw_link_info->phy_type_low == ICE_PHY_TYPE_LOW_1G_SGMII &&
553	(hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] ==
554	ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE ||
555	hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] ==
556	ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE))
557	return ICE_MEDIA_DA;
558
559	switch (hw_link_info->phy_type_low) {
560	case ICE_PHY_TYPE_LOW_1000BASE_SX:
561	case ICE_PHY_TYPE_LOW_1000BASE_LX:
562	case ICE_PHY_TYPE_LOW_10GBASE_SR:
563	case ICE_PHY_TYPE_LOW_10GBASE_LR:
564	case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
565	case ICE_PHY_TYPE_LOW_25GBASE_SR:
566	case ICE_PHY_TYPE_LOW_25GBASE_LR:
567	case ICE_PHY_TYPE_LOW_40GBASE_SR4:
568	case ICE_PHY_TYPE_LOW_40GBASE_LR4:
569	case ICE_PHY_TYPE_LOW_50GBASE_SR2:
570	case ICE_PHY_TYPE_LOW_50GBASE_LR2:
571	case ICE_PHY_TYPE_LOW_50GBASE_SR:
572	case ICE_PHY_TYPE_LOW_50GBASE_FR:
573	case ICE_PHY_TYPE_LOW_50GBASE_LR:
574	case ICE_PHY_TYPE_LOW_100GBASE_SR4:
575	case ICE_PHY_TYPE_LOW_100GBASE_LR4:
576	case ICE_PHY_TYPE_LOW_100GBASE_SR2:
577	case ICE_PHY_TYPE_LOW_100GBASE_DR:
578	case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC:
579	case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC:
580	case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC:
581	case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC:
582	case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC:
583	case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC:
584	case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC:
585	case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC:
586	return ICE_MEDIA_FIBER;
587	case ICE_PHY_TYPE_LOW_100BASE_TX:
588	case ICE_PHY_TYPE_LOW_1000BASE_T:
589	case ICE_PHY_TYPE_LOW_2500BASE_T:
590	case ICE_PHY_TYPE_LOW_5GBASE_T:
591	case ICE_PHY_TYPE_LOW_10GBASE_T:
592	case ICE_PHY_TYPE_LOW_25GBASE_T:
593	return ICE_MEDIA_BASET;
594	case ICE_PHY_TYPE_LOW_10G_SFI_DA:
595	case ICE_PHY_TYPE_LOW_25GBASE_CR:
596	case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
597	case ICE_PHY_TYPE_LOW_25GBASE_CR1:
598	case ICE_PHY_TYPE_LOW_40GBASE_CR4:
599	case ICE_PHY_TYPE_LOW_50GBASE_CR2:
600	case ICE_PHY_TYPE_LOW_50GBASE_CP:
601	case ICE_PHY_TYPE_LOW_100GBASE_CR4:
602	case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
603	case ICE_PHY_TYPE_LOW_100GBASE_CP2:
604	return ICE_MEDIA_DA;
605	case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
606	case ICE_PHY_TYPE_LOW_40G_XLAUI:
607	case ICE_PHY_TYPE_LOW_50G_LAUI2:
608	case ICE_PHY_TYPE_LOW_50G_AUI2:
609	case ICE_PHY_TYPE_LOW_50G_AUI1:
610	case ICE_PHY_TYPE_LOW_100G_AUI4:
611	case ICE_PHY_TYPE_LOW_100G_CAUI4:
612	if (ice_is_media_cage_present(pi))
613	return ICE_MEDIA_DA;
614	fallthrough;
615	case ICE_PHY_TYPE_LOW_1000BASE_KX:
616	case ICE_PHY_TYPE_LOW_2500BASE_KX:
617	case ICE_PHY_TYPE_LOW_2500BASE_X:
618	case ICE_PHY_TYPE_LOW_5GBASE_KR:
619	case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
620	case ICE_PHY_TYPE_LOW_25GBASE_KR:
621	case ICE_PHY_TYPE_LOW_25GBASE_KR1:
622	case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
623	case ICE_PHY_TYPE_LOW_40GBASE_KR4:
624	case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
625	case ICE_PHY_TYPE_LOW_50GBASE_KR2:
626	case ICE_PHY_TYPE_LOW_100GBASE_KR4:
627	case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
628	return ICE_MEDIA_BACKPLANE;
629	}
630	} else {
631	switch (hw_link_info->phy_type_high) {
632	case ICE_PHY_TYPE_HIGH_100G_AUI2:
633	case ICE_PHY_TYPE_HIGH_100G_CAUI2:
634	if (ice_is_media_cage_present(pi))
635	return ICE_MEDIA_DA;
636	fallthrough;
637	case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
638	return ICE_MEDIA_BACKPLANE;
639	case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC:
640	case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC:
641	return ICE_MEDIA_FIBER;
642	}
643	}
644	return ICE_MEDIA_UNKNOWN;
645	}
646
647	/**
648	* ice_get_link_status_datalen
649	* @hw: pointer to the HW struct
650	*
651	* Returns datalength for the Get Link Status AQ command, which is bigger for
652	* newer adapter families handled by ice driver.
653	*/
654	static u16 ice_get_link_status_datalen(struct ice_hw *hw)
655	{
656	switch (hw->mac_type) {
657	case ICE_MAC_E830:
658	return ICE_AQC_LS_DATA_SIZE_V2;
659	case ICE_MAC_E810:
660	default:
661	return ICE_AQC_LS_DATA_SIZE_V1;
662	}
663	}
664
665	/**
666	* ice_aq_get_link_info
667	* @pi: port information structure
668	* @ena_lse: enable/disable LinkStatusEvent reporting
669	* @link: pointer to link status structure - optional
670	* @cd: pointer to command details structure or NULL
671	*
672	* Get Link Status (0x607). Returns the link status of the adapter.
673	*/
674	int
675	ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
676	struct ice_link_status *link, struct ice_sq_cd *cd)
677	{
678	struct ice_aqc_get_link_status_data link_data = { 0 };
679	struct ice_aqc_get_link_status *resp;
680	struct ice_link_status *li_old, *li;
681	enum ice_media_type *hw_media_type;
682	struct ice_fc_info *hw_fc_info;
683	bool tx_pause, rx_pause;
684	struct ice_aq_desc desc;
685	struct ice_hw *hw;
686	u16 cmd_flags;
687	int status;
688
689	if (!pi)
690	return -EINVAL;
691	hw = pi->hw;
692	li_old = &pi->phy.link_info_old;
693	hw_media_type = &pi->phy.media_type;
694	li = &pi->phy.link_info;
695	hw_fc_info = &pi->fc;
696
697	ice_fill_dflt_direct_cmd_desc(desc: &desc, opcode: ice_aqc_opc_get_link_status);
698	cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS;
699	resp = &desc.params.get_link_status;
700	resp->cmd_flags = cpu_to_le16(cmd_flags);
701	resp->lport_num = pi->lport;
702
703	status = ice_aq_send_cmd(hw, desc: &desc, buf: &link_data,
704	buf_size: ice_get_link_status_datalen(hw), cd);
705	if (status)
706	return status;
707
708	/* save off old link status information */
709	*li_old = *li;
710
711	/* update current link status information */
712	li->link_speed = le16_to_cpu(link_data.link_speed);
713	li->phy_type_low = le64_to_cpu(link_data.phy_type_low);
714	li->phy_type_high = le64_to_cpu(link_data.phy_type_high);
715	*hw_media_type = ice_get_media_type(pi);
716	li->link_info = link_data.link_info;
717	li->link_cfg_err = link_data.link_cfg_err;
718	li->an_info = link_data.an_info;
719	li->ext_info = link_data.ext_info;
720	li->max_frame_size = le16_to_cpu(link_data.max_frame_size);
721	li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK;
722	li->topo_media_conflict = link_data.topo_media_conflict;
723	li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M |
724	ICE_AQ_CFG_PACING_TYPE_M);
725
726	/* update fc info */
727	tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX);
728	rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX);
729	if (tx_pause && rx_pause)
730	hw_fc_info->current_mode = ICE_FC_FULL;
731	else if (tx_pause)
732	hw_fc_info->current_mode = ICE_FC_TX_PAUSE;
733	else if (rx_pause)
734	hw_fc_info->current_mode = ICE_FC_RX_PAUSE;
735	else
736	hw_fc_info->current_mode = ICE_FC_NONE;
737
738	li->lse_ena = !!(resp->cmd_flags & cpu_to_le16(ICE_AQ_LSE_IS_ENABLED));
739
740	ice_debug(hw, ICE_DBG_LINK, "get link info\n");
741	ice_debug(hw, ICE_DBG_LINK, " link_speed = 0x%x\n", li->link_speed);
742	ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n",
743	(unsigned long long)li->phy_type_low);
744	ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n",
745	(unsigned long long)li->phy_type_high);
746	ice_debug(hw, ICE_DBG_LINK, " media_type = 0x%x\n", *hw_media_type);
747	ice_debug(hw, ICE_DBG_LINK, " link_info = 0x%x\n", li->link_info);
748	ice_debug(hw, ICE_DBG_LINK, " link_cfg_err = 0x%x\n", li->link_cfg_err);
749	ice_debug(hw, ICE_DBG_LINK, " an_info = 0x%x\n", li->an_info);
750	ice_debug(hw, ICE_DBG_LINK, " ext_info = 0x%x\n", li->ext_info);
751	ice_debug(hw, ICE_DBG_LINK, " fec_info = 0x%x\n", li->fec_info);
752	ice_debug(hw, ICE_DBG_LINK, " lse_ena = 0x%x\n", li->lse_ena);
753	ice_debug(hw, ICE_DBG_LINK, " max_frame = 0x%x\n",
754	li->max_frame_size);
755	ice_debug(hw, ICE_DBG_LINK, " pacing = 0x%x\n", li->pacing);
756
757	/* save link status information */
758	if (link)
759	*link = *li;
760
761	/* flag cleared so calling functions don't call AQ again */
762	pi->phy.get_link_info = false;
763
764	return 0;
765	}
766
767	/**
768	* ice_fill_tx_timer_and_fc_thresh
769	* @hw: pointer to the HW struct
770	* @cmd: pointer to MAC cfg structure
771	*
772	* Add Tx timer and FC refresh threshold info to Set MAC Config AQ command
773	* descriptor
774	*/
775	static void
776	ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw,
777	struct ice_aqc_set_mac_cfg *cmd)
778	{
779	u32 val, fc_thres_m;
780
781	/* We read back the transmit timer and FC threshold value of
782	* LFC. Thus, we will use index =
783	* PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX.
784	*
785	* Also, because we are operating on transmit timer and FC
786	* threshold of LFC, we don't turn on any bit in tx_tmr_priority
787	*/
788	#define E800_IDX_OF_LFC E800_PRTMAC_HSEC_CTL_TX_PS_QNT_MAX
789	#define E800_REFRESH_TMR E800_PRTMAC_HSEC_CTL_TX_PS_RFSH_TMR
790
791	if (hw->mac_type == ICE_MAC_E830) {
792	/* Retrieve the transmit timer */
793	val = rd32(hw, E830_PRTMAC_CL01_PS_QNT);
794	cmd->tx_tmr_value =
795	le16_encode_bits(v: val, E830_PRTMAC_CL01_PS_QNT_CL0_M);
796
797	/* Retrieve the fc threshold */
798	val = rd32(hw, E830_PRTMAC_CL01_QNT_THR);
799	fc_thres_m = E830_PRTMAC_CL01_QNT_THR_CL0_M;
800	} else {
801	/* Retrieve the transmit timer */
802	val = rd32(hw,
803	E800_PRTMAC_HSEC_CTL_TX_PS_QNT(E800_IDX_OF_LFC));
804	cmd->tx_tmr_value =
805	le16_encode_bits(v: val,
806	E800_PRTMAC_HSEC_CTL_TX_PS_QNT_M);
807
808	/* Retrieve the fc threshold */
809	val = rd32(hw,
810	E800_REFRESH_TMR(E800_IDX_OF_LFC));
811	fc_thres_m = E800_PRTMAC_HSEC_CTL_TX_PS_RFSH_TMR_M;
812	}
813	cmd->fc_refresh_threshold = le16_encode_bits(v: val, field: fc_thres_m);
814	}
815
816	/**
817	* ice_aq_set_mac_cfg
818	* @hw: pointer to the HW struct
819	* @max_frame_size: Maximum Frame Size to be supported
820	* @cd: pointer to command details structure or NULL
821	*
822	* Set MAC configuration (0x0603)
823	*/
824	int
825	ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd)
826	{
827	struct ice_aqc_set_mac_cfg *cmd;
828	struct ice_aq_desc desc;
829
830	cmd = &desc.params.set_mac_cfg;
831
832	if (max_frame_size == 0)
833	return -EINVAL;
834
835	ice_fill_dflt_direct_cmd_desc(desc: &desc, opcode: ice_aqc_opc_set_mac_cfg);
836
837	cmd->max_frame_size = cpu_to_le16(max_frame_size);
838
839	ice_fill_tx_timer_and_fc_thresh(hw, cmd);
840
841	return ice_aq_send_cmd(hw, desc: &desc, NULL, buf_size: 0, cd);
842	}
843
844	/**
845	* ice_init_fltr_mgmt_struct - initializes filter management list and locks
846	* @hw: pointer to the HW struct
847	*/
848	static int ice_init_fltr_mgmt_struct(struct ice_hw *hw)
849	{
850	struct ice_switch_info *sw;
851	int status;
852
853	hw->switch_info = devm_kzalloc(dev: ice_hw_to_dev(hw),
854	size: sizeof(*hw->switch_info), GFP_KERNEL);
855	sw = hw->switch_info;
856
857	if (!sw)
858	return -ENOMEM;
859
860	INIT_LIST_HEAD(list: &sw->vsi_list_map_head);
861	sw->prof_res_bm_init = 0;
862
863	/* Initialize recipe count with default recipes read from NVM */
864	sw->recp_cnt = ICE_SW_LKUP_LAST;
865
866	status = ice_init_def_sw_recp(hw);
867	if (status) {
868	devm_kfree(dev: ice_hw_to_dev(hw), p: hw->switch_info);
869	return status;
870	}
871	return 0;
872	}
873
874	/**
875	* ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks
876	* @hw: pointer to the HW struct
877	*/
878	static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw)
879	{
880	struct ice_switch_info *sw = hw->switch_info;
881	struct ice_vsi_list_map_info *v_pos_map;
882	struct ice_vsi_list_map_info *v_tmp_map;
883	struct ice_sw_recipe *recps;
884	u8 i;
885
886	list_for_each_entry_safe(v_pos_map, v_tmp_map, &sw->vsi_list_map_head,
887	list_entry) {
888	list_del(entry: &v_pos_map->list_entry);
889	devm_kfree(dev: ice_hw_to_dev(hw), p: v_pos_map);
890	}
891	recps = sw->recp_list;
892	for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) {
893	recps[i].root_rid = i;
894
895	if (recps[i].adv_rule) {
896	struct ice_adv_fltr_mgmt_list_entry *tmp_entry;
897	struct ice_adv_fltr_mgmt_list_entry *lst_itr;
898
899	mutex_destroy(lock: &recps[i].filt_rule_lock);
900	list_for_each_entry_safe(lst_itr, tmp_entry,
901	&recps[i].filt_rules,
902	list_entry) {
903	list_del(entry: &lst_itr->list_entry);
904	devm_kfree(dev: ice_hw_to_dev(hw), p: lst_itr->lkups);
905	devm_kfree(dev: ice_hw_to_dev(hw), p: lst_itr);
906	}
907	} else {
908	struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry;
909
910	mutex_destroy(lock: &recps[i].filt_rule_lock);
911	list_for_each_entry_safe(lst_itr, tmp_entry,
912	&recps[i].filt_rules,
913	list_entry) {
914	list_del(entry: &lst_itr->list_entry);
915	devm_kfree(dev: ice_hw_to_dev(hw), p: lst_itr);
916	}
917	}
918	}
919	ice_rm_all_sw_replay_rule_info(hw);
920	devm_kfree(dev: ice_hw_to_dev(hw), p: sw->recp_list);
921	devm_kfree(dev: ice_hw_to_dev(hw), p: sw);
922	}
923
924	/**
925	* ice_get_itr_intrl_gran
926	* @hw: pointer to the HW struct
927	*
928	* Determines the ITR/INTRL granularities based on the maximum aggregate
929	* bandwidth according to the device's configuration during power-on.
930	*/
931	static void ice_get_itr_intrl_gran(struct ice_hw *hw)
932	{
933	u8 max_agg_bw = FIELD_GET(GL_PWR_MODE_CTL_CAR_MAX_BW_M,
934	rd32(hw, GL_PWR_MODE_CTL));
935
936	switch (max_agg_bw) {
937	case ICE_MAX_AGG_BW_200G:
938	case ICE_MAX_AGG_BW_100G:
939	case ICE_MAX_AGG_BW_50G:
940	hw->itr_gran = ICE_ITR_GRAN_ABOVE_25;
941	hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25;
942	break;
943	case ICE_MAX_AGG_BW_25G:
944	hw->itr_gran = ICE_ITR_GRAN_MAX_25;
945	hw->intrl_gran = ICE_INTRL_GRAN_MAX_25;
946	break;
947	}
948	}
949
950	/**
951	* ice_wait_for_fw - wait for full FW readiness
952	* @hw: pointer to the hardware structure
953	* @timeout: milliseconds that can elapse before timing out
954	*
955	* Return: 0 on success, -ETIMEDOUT on timeout.
956	*/
957	static int ice_wait_for_fw(struct ice_hw *hw, u32 timeout)
958	{
959	int fw_loading;
960	u32 elapsed = 0;
961
962	while (elapsed <= timeout) {
963	fw_loading = rd32(hw, GL_MNG_FWSM) & GL_MNG_FWSM_FW_LOADING_M;
964
965	/* firmware was not yet loaded, we have to wait more */
966	if (fw_loading) {
967	elapsed += 100;
968	msleep(msecs: 100);
969	continue;
970	}
971	return 0;
972	}
973
974	return -ETIMEDOUT;
975	}
976
977	/**
978	* ice_init_hw - main hardware initialization routine
979	* @hw: pointer to the hardware structure
980	*/
981	int ice_init_hw(struct ice_hw *hw)
982	{
983	struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL;
984	void *mac_buf __free(kfree) = NULL;
985	u16 mac_buf_len;
986	int status;
987
988	/* Set MAC type based on DeviceID */
989	status = ice_set_mac_type(hw);
990	if (status)
991	return status;
992
993	hw->pf_id = FIELD_GET(PF_FUNC_RID_FUNC_NUM_M, rd32(hw, PF_FUNC_RID));
994
995	status = ice_reset(hw, req: ICE_RESET_PFR);
996	if (status)
997	return status;
998
999	ice_get_itr_intrl_gran(hw);
1000
1001	status = ice_create_all_ctrlq(hw);
1002	if (status)
1003	goto err_unroll_cqinit;
1004
1005	status = ice_fwlog_init(hw);
1006	if (status)
1007	ice_debug(hw, ICE_DBG_FW_LOG, "Error initializing FW logging: %d\n",
1008	status);
1009
1010	status = ice_clear_pf_cfg(hw);
1011	if (status)
1012	goto err_unroll_cqinit;
1013
1014	/* Set bit to enable Flow Director filters */
1015	wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M);
1016	INIT_LIST_HEAD(list: &hw->fdir_list_head);
1017
1018	ice_clear_pxe_mode(hw);
1019
1020	status = ice_init_nvm(hw);
1021	if (status)
1022	goto err_unroll_cqinit;
1023
1024	status = ice_get_caps(hw);
1025	if (status)
1026	goto err_unroll_cqinit;
1027
1028	if (!hw->port_info)
1029	hw->port_info = devm_kzalloc(dev: ice_hw_to_dev(hw),
1030	size: sizeof(*hw->port_info),
1031	GFP_KERNEL);
1032	if (!hw->port_info) {
1033	status = -ENOMEM;
1034	goto err_unroll_cqinit;
1035	}
1036
1037	hw->port_info->local_fwd_mode = ICE_LOCAL_FWD_MODE_ENABLED;
1038	/* set the back pointer to HW */
1039	hw->port_info->hw = hw;
1040
1041	/* Initialize port_info struct with switch configuration data */
1042	status = ice_get_initial_sw_cfg(hw);
1043	if (status)
1044	goto err_unroll_alloc;
1045
1046	hw->evb_veb = true;
1047
1048	/* init xarray for identifying scheduling nodes uniquely */
1049	xa_init_flags(xa: &hw->port_info->sched_node_ids, XA_FLAGS_ALLOC);
1050
1051	/* Query the allocated resources for Tx scheduler */
1052	status = ice_sched_query_res_alloc(hw);
1053	if (status) {
1054	ice_debug(hw, ICE_DBG_SCHED, "Failed to get scheduler allocated resources\n");
1055	goto err_unroll_alloc;
1056	}
1057	ice_sched_get_psm_clk_freq(hw);
1058
1059	/* Initialize port_info struct with scheduler data */
1060	status = ice_sched_init_port(pi: hw->port_info);
1061	if (status)
1062	goto err_unroll_sched;
1063
1064	pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL);
1065	if (!pcaps) {
1066	status = -ENOMEM;
1067	goto err_unroll_sched;
1068	}
1069
1070	/* Initialize port_info struct with PHY capabilities */
1071	status = ice_aq_get_phy_caps(pi: hw->port_info, qual_mods: false,
1072	ICE_AQC_REPORT_TOPO_CAP_MEDIA, pcaps,
1073	NULL);
1074	if (status)
1075	dev_warn(ice_hw_to_dev(hw), "Get PHY capabilities failed status = %d, continuing anyway\n",
1076	status);
1077
1078	/* Initialize port_info struct with link information */
1079	status = ice_aq_get_link_info(pi: hw->port_info, ena_lse: false, NULL, NULL);
1080	if (status)
1081	goto err_unroll_sched;
1082
1083	/* need a valid SW entry point to build a Tx tree */
1084	if (!hw->sw_entry_point_layer) {
1085	ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n");
1086	status = -EIO;
1087	goto err_unroll_sched;
1088	}
1089	INIT_LIST_HEAD(list: &hw->agg_list);
1090	/* Initialize max burst size */
1091	if (!hw->max_burst_size)
1092	ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE);
1093
1094	status = ice_init_fltr_mgmt_struct(hw);
1095	if (status)
1096	goto err_unroll_sched;
1097
1098	/* Get MAC information */
1099	/* A single port can report up to two (LAN and WoL) addresses */
1100	mac_buf = kcalloc(2, sizeof(struct ice_aqc_manage_mac_read_resp),
1101	GFP_KERNEL);
1102	if (!mac_buf) {
1103	status = -ENOMEM;
1104	goto err_unroll_fltr_mgmt_struct;
1105	}
1106
1107	mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp);
1108	status = ice_aq_manage_mac_read(hw, buf: mac_buf, buf_size: mac_buf_len, NULL);
1109
1110	if (status)
1111	goto err_unroll_fltr_mgmt_struct;
1112	/* enable jumbo frame support at MAC level */
1113	status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL);
1114	if (status)
1115	goto err_unroll_fltr_mgmt_struct;
1116	/* Obtain counter base index which would be used by flow director */
1117	status = ice_alloc_fd_res_cntr(hw, cntr_id: &hw->fd_ctr_base);
1118	if (status)
1119	goto err_unroll_fltr_mgmt_struct;
1120	status = ice_init_hw_tbls(hw);
1121	if (status)
1122	goto err_unroll_fltr_mgmt_struct;
1123	mutex_init(&hw->tnl_lock);
1124	ice_init_chk_recipe_reuse_support(hw);
1125
1126	/* Some cards require longer initialization times
1127	* due to necessity of loading FW from an external source.
1128	* This can take even half a minute.
1129	*/
1130	if (ice_is_pf_c827(hw)) {
1131	status = ice_wait_for_fw(hw, timeout: 30000);
1132	if (status) {
1133	dev_err(ice_hw_to_dev(hw), "ice_wait_for_fw timed out");
1134	goto err_unroll_fltr_mgmt_struct;
1135	}
1136	}
1137
1138	hw->lane_num = ice_get_phy_lane_number(hw);
1139
1140	return 0;
1141	err_unroll_fltr_mgmt_struct:
1142	ice_cleanup_fltr_mgmt_struct(hw);
1143	err_unroll_sched:
1144	ice_sched_cleanup_all(hw);
1145	err_unroll_alloc:
1146	devm_kfree(dev: ice_hw_to_dev(hw), p: hw->port_info);
1147	err_unroll_cqinit:
1148	ice_destroy_all_ctrlq(hw);
1149	return status;
1150	}
1151
1152	/**
1153	* ice_deinit_hw - unroll initialization operations done by ice_init_hw
1154	* @hw: pointer to the hardware structure
1155	*
1156	* This should be called only during nominal operation, not as a result of
1157	* ice_init_hw() failing since ice_init_hw() will take care of unrolling
1158	* applicable initializations if it fails for any reason.
1159	*/
1160	void ice_deinit_hw(struct ice_hw *hw)
1161	{
1162	ice_free_fd_res_cntr(hw, cntr_id: hw->fd_ctr_base);
1163	ice_cleanup_fltr_mgmt_struct(hw);
1164
1165	ice_sched_cleanup_all(hw);
1166	ice_sched_clear_agg(hw);
1167	ice_free_seg(hw);
1168	ice_free_hw_tbls(hw);
1169	mutex_destroy(lock: &hw->tnl_lock);
1170
1171	ice_fwlog_deinit(hw);
1172	ice_destroy_all_ctrlq(hw);
1173
1174	/* Clear VSI contexts if not already cleared */
1175	ice_clear_all_vsi_ctx(hw);
1176	}
1177
1178	/**
1179	* ice_check_reset - Check to see if a global reset is complete
1180	* @hw: pointer to the hardware structure
1181	*/
1182	int ice_check_reset(struct ice_hw *hw)
1183	{
1184	u32 cnt, reg = 0, grst_timeout, uld_mask;
1185
1186	/* Poll for Device Active state in case a recent CORER, GLOBR,
1187	* or EMPR has occurred. The grst delay value is in 100ms units.
1188	* Add 1sec for outstanding AQ commands that can take a long time.
1189	*/
1190	grst_timeout = FIELD_GET(GLGEN_RSTCTL_GRSTDEL_M,
1191	rd32(hw, GLGEN_RSTCTL)) + 10;
1192
1193	for (cnt = 0; cnt < grst_timeout; cnt++) {
1194	mdelay(100);
1195	reg = rd32(hw, GLGEN_RSTAT);
1196	if (!(reg & GLGEN_RSTAT_DEVSTATE_M))
1197	break;
1198	}
1199
1200	if (cnt == grst_timeout) {
1201	ice_debug(hw, ICE_DBG_INIT, "Global reset polling failed to complete.\n");
1202	return -EIO;
1203	}
1204
1205	#define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M |\
1206	GLNVM_ULD_PCIER_DONE_1_M |\
1207	GLNVM_ULD_CORER_DONE_M |\
1208	GLNVM_ULD_GLOBR_DONE_M |\
1209	GLNVM_ULD_POR_DONE_M |\
1210	GLNVM_ULD_POR_DONE_1_M |\
1211	GLNVM_ULD_PCIER_DONE_2_M)
1212
1213	uld_mask = ICE_RESET_DONE_MASK | (hw->func_caps.common_cap.rdma ?
1214	GLNVM_ULD_PE_DONE_M : 0);
1215
1216	/* Device is Active; check Global Reset processes are done */
1217	for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {
1218	reg = rd32(hw, GLNVM_ULD) & uld_mask;
1219	if (reg == uld_mask) {
1220	ice_debug(hw, ICE_DBG_INIT, "Global reset processes done. %d\n", cnt);
1221	break;
1222	}
1223	mdelay(10);
1224	}
1225
1226	if (cnt == ICE_PF_RESET_WAIT_COUNT) {
1227	ice_debug(hw, ICE_DBG_INIT, "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n",
1228	reg);
1229	return -EIO;
1230	}
1231
1232	return 0;
1233	}
1234
1235	/**
1236	* ice_pf_reset - Reset the PF
1237	* @hw: pointer to the hardware structure
1238	*
1239	* If a global reset has been triggered, this function checks
1240	* for its completion and then issues the PF reset
1241	*/
1242	static int ice_pf_reset(struct ice_hw *hw)
1243	{
1244	u32 cnt, reg;
1245
1246	/* If at function entry a global reset was already in progress, i.e.
1247	* state is not 'device active' or any of the reset done bits are not
1248	* set in GLNVM_ULD, there is no need for a PF Reset; poll until the
1249	* global reset is done.
1250	*/
1251	if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) ||
1252	(rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) {
1253	/* poll on global reset currently in progress until done */
1254	if (ice_check_reset(hw))
1255	return -EIO;
1256
1257	return 0;
1258	}
1259
1260	/* Reset the PF */
1261	reg = rd32(hw, PFGEN_CTRL);
1262
1263	wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M));
1264
1265	/* Wait for the PFR to complete. The wait time is the global config lock
1266	* timeout plus the PFR timeout which will account for a possible reset
1267	* that is occurring during a download package operation.
1268	*/
1269	for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT +
1270	ICE_PF_RESET_WAIT_COUNT; cnt++) {
1271	reg = rd32(hw, PFGEN_CTRL);
1272	if (!(reg & PFGEN_CTRL_PFSWR_M))
1273	break;
1274
1275	mdelay(1);
1276	}
1277
1278	if (cnt == ICE_PF_RESET_WAIT_COUNT) {
1279	ice_debug(hw, ICE_DBG_INIT, "PF reset polling failed to complete.\n");
1280	return -EIO;
1281	}
1282
1283	return 0;
1284	}
1285
1286	/**
1287	* ice_reset - Perform different types of reset
1288	* @hw: pointer to the hardware structure
1289	* @req: reset request
1290	*
1291	* This function triggers a reset as specified by the req parameter.
1292	*
1293	* Note:
1294	* If anything other than a PF reset is triggered, PXE mode is restored.
1295	* This has to be cleared using ice_clear_pxe_mode again, once the AQ
1296	* interface has been restored in the rebuild flow.
1297	*/
1298	int ice_reset(struct ice_hw *hw, enum ice_reset_req req)
1299	{
1300	u32 val = 0;
1301
1302	switch (req) {
1303	case ICE_RESET_PFR:
1304	return ice_pf_reset(hw);
1305	case ICE_RESET_CORER:
1306	ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n");
1307	val = GLGEN_RTRIG_CORER_M;
1308	break;
1309	case ICE_RESET_GLOBR:
1310	ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n");
1311	val = GLGEN_RTRIG_GLOBR_M;
1312	break;
1313	default:
1314	return -EINVAL;
1315	}
1316
1317	val |= rd32(hw, GLGEN_RTRIG);
1318	wr32(hw, GLGEN_RTRIG, val);
1319	ice_flush(hw);
1320
1321	/* wait for the FW to be ready */
1322	return ice_check_reset(hw);
1323	}
1324
1325	/**
1326	* ice_copy_rxq_ctx_to_hw - Copy packed Rx queue context to HW registers
1327	* @hw: pointer to the hardware structure
1328	* @rxq_ctx: pointer to the packed Rx queue context
1329	* @rxq_index: the index of the Rx queue
1330	*/
1331	static void ice_copy_rxq_ctx_to_hw(struct ice_hw *hw,
1332	const ice_rxq_ctx_buf_t *rxq_ctx,
1333	u32 rxq_index)
1334	{
1335	/* Copy each dword separately to HW */
1336	for (int i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) {
1337	u32 ctx = ((const u32 *)rxq_ctx)[i];
1338
1339	wr32(hw, QRX_CONTEXT(i, rxq_index), ctx);
1340
1341	ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, ctx);
1342	}
1343	}
1344
1345	#define ICE_CTX_STORE(struct_name, struct_field, width, lsb) \
1346	PACKED_FIELD((lsb) + (width) - 1, (lsb), struct struct_name, struct_field)
1347
1348	/* LAN Rx Queue Context */
1349	static const struct packed_field_u8 ice_rlan_ctx_fields[] = {
1350	/* Field Width LSB */
1351	ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0),
1352	ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13),
1353	ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32),
1354	ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89),
1355	ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102),
1356	ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109),
1357	ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114),
1358	ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116),
1359	ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117),
1360	ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119),
1361	ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120),
1362	ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124),
1363	ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127),
1364	ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174),
1365	ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193),
1366	ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194),
1367	ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195),
1368	ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196),
1369	ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198),
1370	ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201),
1371	};
1372
1373	/**
1374	* ice_pack_rxq_ctx - Pack Rx queue context into a HW buffer
1375	* @ctx: the Rx queue context to pack
1376	* @buf: the HW buffer to pack into
1377	*
1378	* Pack the Rx queue context from the CPU-friendly unpacked buffer into its
1379	* bit-packed HW layout.
1380	*/
1381	static void ice_pack_rxq_ctx(const struct ice_rlan_ctx *ctx,
1382	ice_rxq_ctx_buf_t *buf)
1383	{
1384	pack_fields(buf, sizeof(*buf), ctx, ice_rlan_ctx_fields,
1385	QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST);
1386	}
1387
1388	/**
1389	* ice_write_rxq_ctx - Write Rx Queue context to hardware
1390	* @hw: pointer to the hardware structure
1391	* @rlan_ctx: pointer to the unpacked Rx queue context
1392	* @rxq_index: the index of the Rx queue
1393	*
1394	* Pack the sparse Rx Queue context into dense hardware format and write it
1395	* into the HW register space.
1396	*
1397	* Return: 0 on success, or -EINVAL if the Rx queue index is invalid.
1398	*/
1399	int ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
1400	u32 rxq_index)
1401	{
1402	ice_rxq_ctx_buf_t buf = {};
1403
1404	if (rxq_index > QRX_CTRL_MAX_INDEX)
1405	return -EINVAL;
1406
1407	ice_pack_rxq_ctx(ctx: rlan_ctx, buf: &buf);
1408	ice_copy_rxq_ctx_to_hw(hw, rxq_ctx: &buf, rxq_index);
1409
1410	return 0;
1411	}
1412
1413	/* LAN Tx Queue Context */
1414	static const struct packed_field_u8 ice_tlan_ctx_fields[] = {
1415	/* Field Width LSB */
1416	ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0),
1417	ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57),
1418	ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60),
1419	ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65),
1420	ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68),
1421	ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78),
1422	ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80),
1423	ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90),
1424	ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91),
1425	ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92),
1426	ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93),
1427	ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101),
1428	ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102),
1429	ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103),
1430	ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104),
1431	ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105),
1432	ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114),
1433	ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128),
1434	ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129),
1435	ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135),
1436	ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148),
1437	ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152),
1438	ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153),
1439	ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164),
1440	ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165),
1441	ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166),
1442	ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168),
1443	};
1444
1445	/**
1446	* ice_pack_txq_ctx - Pack Tx queue context into a HW buffer
1447	* @ctx: the Tx queue context to pack
1448	* @buf: the HW buffer to pack into
1449	*
1450	* Pack the Tx queue context from the CPU-friendly unpacked buffer into its
1451	* bit-packed HW layout.
1452	*/
1453	void ice_pack_txq_ctx(const struct ice_tlan_ctx *ctx, ice_txq_ctx_buf_t *buf)
1454	{
1455	pack_fields(buf, sizeof(*buf), ctx, ice_tlan_ctx_fields,
1456	QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST);
1457	}
1458
1459	/* Sideband Queue command wrappers */
1460
1461	/**
1462	* ice_sbq_send_cmd - send Sideband Queue command to Sideband Queue
1463	* @hw: pointer to the HW struct
1464	* @desc: descriptor describing the command
1465	* @buf: buffer to use for indirect commands (NULL for direct commands)
1466	* @buf_size: size of buffer for indirect commands (0 for direct commands)
1467	* @cd: pointer to command details structure
1468	*/
1469	static int
1470	ice_sbq_send_cmd(struct ice_hw *hw, struct ice_sbq_cmd_desc *desc,
1471	void *buf, u16 buf_size, struct ice_sq_cd *cd)
1472	{
1473	return ice_sq_send_cmd(hw, cq: ice_get_sbq(hw),
1474	desc: (struct ice_aq_desc *)desc, buf, buf_size, cd);
1475	}
1476
1477	/**
1478	* ice_sbq_rw_reg - Fill Sideband Queue command
1479	* @hw: pointer to the HW struct
1480	* @in: message info to be filled in descriptor
1481	* @flags: control queue descriptor flags
1482	*/
1483	int ice_sbq_rw_reg(struct ice_hw *hw, struct ice_sbq_msg_input *in, u16 flags)
1484	{
1485	struct ice_sbq_cmd_desc desc = {0};
1486	struct ice_sbq_msg_req msg = {0};
1487	u16 msg_len;
1488	int status;
1489
1490	msg_len = sizeof(msg);
1491
1492	msg.dest_dev = in->dest_dev;
1493	msg.opcode = in->opcode;
1494	msg.flags = ICE_SBQ_MSG_FLAGS;
1495	msg.sbe_fbe = ICE_SBQ_MSG_SBE_FBE;
1496	msg.msg_addr_low = cpu_to_le16(in->msg_addr_low);
1497	msg.msg_addr_high = cpu_to_le32(in->msg_addr_high);
1498
1499	if (in->opcode)
1500	msg.data = cpu_to_le32(in->data);
1501	else
1502	/* data read comes back in completion, so shorten the struct by
1503	* sizeof(msg.data)
1504	*/
1505	msg_len -= sizeof(msg.data);
1506
1507	desc.flags = cpu_to_le16(flags);
1508	desc.opcode = cpu_to_le16(ice_sbq_opc_neigh_dev_req);
1509	desc.param0.cmd_len = cpu_to_le16(msg_len);
1510	status = ice_sbq_send_cmd(hw, desc: &desc, buf: &msg, buf_size: msg_len, NULL);
1511	if (!status && !in->opcode)
1512	in->data = le32_to_cpu
1513	(((struct ice_sbq_msg_cmpl *)&msg)->data);
1514	return status;
1515	}
1516
1517	/* FW Admin Queue command wrappers */
1518
1519	/* Software lock/mutex that is meant to be held while the Global Config Lock
1520	* in firmware is acquired by the software to prevent most (but not all) types
1521	* of AQ commands from being sent to FW
1522	*/
1523	DEFINE_MUTEX(ice_global_cfg_lock_sw);
1524
1525	/**
1526	* ice_should_retry_sq_send_cmd
1527	* @opcode: AQ opcode
1528	*
1529	* Decide if we should retry the send command routine for the ATQ, depending
1530	* on the opcode.
1531	*/
1532	static bool ice_should_retry_sq_send_cmd(u16 opcode)
1533	{
1534	switch (opcode) {
1535	case ice_aqc_opc_get_link_topo:
1536	case ice_aqc_opc_lldp_stop:
1537	case ice_aqc_opc_lldp_start:
1538	case ice_aqc_opc_lldp_filter_ctrl:
1539	return true;
1540	}
1541
1542	return false;
1543	}
1544
1545	/**
1546	* ice_sq_send_cmd_retry - send command to Control Queue (ATQ)
1547	* @hw: pointer to the HW struct
1548	* @cq: pointer to the specific Control queue
1549	* @desc: prefilled descriptor describing the command
1550	* @buf: buffer to use for indirect commands (or NULL for direct commands)
1551	* @buf_size: size of buffer for indirect commands (or 0 for direct commands)
1552	* @cd: pointer to command details structure
1553	*
1554	* Retry sending the FW Admin Queue command, multiple times, to the FW Admin
1555	* Queue if the EBUSY AQ error is returned.
1556	*/
1557	static int
1558	ice_sq_send_cmd_retry(struct ice_hw *hw, struct ice_ctl_q_info *cq,
1559	struct ice_aq_desc *desc, void *buf, u16 buf_size,
1560	struct ice_sq_cd *cd)
1561	{
1562	struct ice_aq_desc desc_cpy;
1563	bool is_cmd_for_retry;
1564	u8 idx = 0;
1565	u16 opcode;
1566	int status;
1567
1568	opcode = le16_to_cpu(desc->opcode);
1569	is_cmd_for_retry = ice_should_retry_sq_send_cmd(opcode);
1570	memset(&desc_cpy, 0, sizeof(desc_cpy));
1571
1572	if (is_cmd_for_retry) {
1573	/* All retryable cmds are direct, without buf. */
1574	WARN_ON(buf);
1575
1576	memcpy(&desc_cpy, desc, sizeof(desc_cpy));
1577	}
1578
1579	do {
1580	status = ice_sq_send_cmd(hw, cq, desc, buf, buf_size, cd);
1581
1582	if (!is_cmd_for_retry || !status ||
1583	hw->adminq.sq_last_status != ICE_AQ_RC_EBUSY)
1584	break;
1585
1586	memcpy(desc, &desc_cpy, sizeof(desc_cpy));
1587
1588	msleep(ICE_SQ_SEND_DELAY_TIME_MS);
1589
1590	} while (++idx < ICE_SQ_SEND_MAX_EXECUTE);
1591
1592	return status;
1593	}
1594
1595	/**
1596	* ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue
1597	* @hw: pointer to the HW struct
1598	* @desc: descriptor describing the command
1599	* @buf: buffer to use for indirect commands (NULL for direct commands)
1600	* @buf_size: size of buffer for indirect commands (0 for direct commands)
1601	* @cd: pointer to command details structure
1602	*
1603	* Helper function to send FW Admin Queue commands to the FW Admin Queue.
1604	*/
1605	int
1606	ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf,
1607	u16 buf_size, struct ice_sq_cd *cd)
1608	{
1609	struct ice_aqc_req_res *cmd = &desc->params.res_owner;
1610	bool lock_acquired = false;
1611	int status;
1612
1613	/* When a package download is in process (i.e. when the firmware's
1614	* Global Configuration Lock resource is held), only the Download
1615	* Package, Get Version, Get Package Info List, Upload Section,
1616	* Update Package, Set Port Parameters, Get/Set VLAN Mode Parameters,
1617	* Add Recipe, Set Recipes to Profile Association, Get Recipe, and Get
1618	* Recipes to Profile Association, and Release Resource (with resource
1619	* ID set to Global Config Lock) AdminQ commands are allowed; all others
1620	* must block until the package download completes and the Global Config
1621	* Lock is released. See also ice_acquire_global_cfg_lock().
1622	*/
1623	switch (le16_to_cpu(desc->opcode)) {
1624	case ice_aqc_opc_download_pkg:
1625	case ice_aqc_opc_get_pkg_info_list:
1626	case ice_aqc_opc_get_ver:
1627	case ice_aqc_opc_upload_section:
1628	case ice_aqc_opc_update_pkg:
1629	case ice_aqc_opc_set_port_params:
1630	case ice_aqc_opc_get_vlan_mode_parameters:
1631	case ice_aqc_opc_set_vlan_mode_parameters:
1632	case ice_aqc_opc_set_tx_topo:
1633	case ice_aqc_opc_get_tx_topo:
1634	case ice_aqc_opc_add_recipe:
1635	case ice_aqc_opc_recipe_to_profile:
1636	case ice_aqc_opc_get_recipe:
1637	case ice_aqc_opc_get_recipe_to_profile:
1638	break;
1639	case ice_aqc_opc_release_res:
1640	if (le16_to_cpu(cmd->res_id) == ICE_AQC_RES_ID_GLBL_LOCK)
1641	break;
1642	fallthrough;
1643	default:
1644	mutex_lock(&ice_global_cfg_lock_sw);
1645	lock_acquired = true;
1646	break;
1647	}
1648
1649	status = ice_sq_send_cmd_retry(hw, cq: &hw->adminq, desc, buf, buf_size, cd);
1650	if (lock_acquired)
1651	mutex_unlock(lock: &ice_global_cfg_lock_sw);
1652
1653	return status;
1654	}
1655
1656	/**
1657	* ice_aq_get_fw_ver
1658	* @hw: pointer to the HW struct
1659	* @cd: pointer to command details structure or NULL
1660	*
1661	* Get the firmware version (0x0001) from the admin queue commands
1662	*/
1663	int ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd)
1664	{
1665	struct ice_aqc_get_ver *resp;
1666	struct ice_aq_desc desc;
1667	int status;
1668
1669	resp = &desc.params.get_ver;
1670
1671	ice_fill_dflt_direct_cmd_desc(desc: &desc, opcode: ice_aqc_opc_get_ver);
1672
1673	status = ice_aq_send_cmd(hw, desc: &desc, NULL, buf_size: 0, cd);
1674
1675	if (!status) {
1676	hw->fw_branch = resp->fw_branch;
1677	hw->fw_maj_ver = resp->fw_major;
1678	hw->fw_min_ver = resp->fw_minor;
1679	hw->fw_patch = resp->fw_patch;
1680	hw->fw_build = le32_to_cpu(resp->fw_build);
1681	hw->api_branch = resp->api_branch;
1682	hw->api_maj_ver = resp->api_major;
1683	hw->api_min_ver = resp->api_minor;
1684	hw->api_patch = resp->api_patch;
1685	}
1686
1687	return status;
1688	}
1689
1690	/**
1691	* ice_aq_send_driver_ver
1692	* @hw: pointer to the HW struct
1693	* @dv: driver's major, minor version
1694	* @cd: pointer to command details structure or NULL
1695	*
1696	* Send the driver version (0x0002) to the firmware
1697	*/
1698	int
1699	ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv,
1700	struct ice_sq_cd *cd)
1701	{
1702	struct ice_aqc_driver_ver *cmd;
1703	struct ice_aq_desc desc;
1704	u16 len;
1705
1706	cmd = &desc.params.driver_ver;
1707
1708	if (!dv)
1709	return -EINVAL;
1710
1711	ice_fill_dflt_direct_cmd_desc(desc: &desc, opcode: ice_aqc_opc_driver_ver);
1712
1713	desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
1714	cmd->major_ver = dv->major_ver;
1715	cmd->minor_ver = dv->minor_ver;
1716	cmd->build_ver = dv->build_ver;
1717	cmd->subbuild_ver = dv->subbuild_ver;
1718
1719	len = 0;
1720	while (len < sizeof(dv->driver_string) &&
1721	isascii(dv->driver_string[len]) && dv->driver_string[len])
1722	len++;
1723
1724	return ice_aq_send_cmd(hw, desc: &desc, buf: dv->driver_string, buf_size: len, cd);
1725	}
1726
1727	/**
1728	* ice_aq_q_shutdown
1729	* @hw: pointer to the HW struct
1730	* @unloading: is the driver unloading itself
1731	*
1732	* Tell the Firmware that we're shutting down the AdminQ and whether
1733	* or not the driver is unloading as well (0x0003).
1734	*/
1735	int ice_aq_q_shutdown(struct ice_hw *hw, bool unloading)
1736	{
1737	struct ice_aqc_q_shutdown *cmd;
1738	struct ice_aq_desc desc;
1739
1740	cmd = &desc.params.q_shutdown;
1741
1742	ice_fill_dflt_direct_cmd_desc(desc: &desc, opcode: ice_aqc_opc_q_shutdown);
1743
1744	if (unloading)
1745	cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING;
1746
1747	return ice_aq_send_cmd(hw, desc: &desc, NULL, buf_size: 0, NULL);
1748	}
1749
1750	/**
1751	* ice_aq_req_res
1752	* @hw: pointer to the HW struct
1753	* @res: resource ID
1754	* @access: access type
1755	* @sdp_number: resource number
1756	* @timeout: the maximum time in ms that the driver may hold the resource
1757	* @cd: pointer to command details structure or NULL
1758	*
1759	* Requests common resource using the admin queue commands (0x0008).
1760	* When attempting to acquire the Global Config Lock, the driver can
1761	* learn of three states:
1762	* 1) 0 - acquired lock, and can perform download package
1763	* 2) -EIO - did not get lock, driver should fail to load
1764	* 3) -EALREADY - did not get lock, but another driver has
1765	* successfully downloaded the package; the driver does
1766	* not have to download the package and can continue
1767	* loading
1768	*
1769	* Note that if the caller is in an acquire lock, perform action, release lock
1770	* phase of operation, it is possible that the FW may detect a timeout and issue
1771	* a CORER. In this case, the driver will receive a CORER interrupt and will
1772	* have to determine its cause. The calling thread that is handling this flow
1773	* will likely get an error propagated back to it indicating the Download
1774	* Package, Update Package or the Release Resource AQ commands timed out.
1775	*/
1776	static int
1777	ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1778	enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout,
1779	struct ice_sq_cd *cd)
1780	{
1781	struct ice_aqc_req_res *cmd_resp;
1782	struct ice_aq_desc desc;
1783	int status;
1784
1785	cmd_resp = &desc.params.res_owner;
1786
1787	ice_fill_dflt_direct_cmd_desc(desc: &desc, opcode: ice_aqc_opc_req_res);
1788
1789	cmd_resp->res_id = cpu_to_le16(res);
1790	cmd_resp->access_type = cpu_to_le16(access);
1791	cmd_resp->res_number = cpu_to_le32(sdp_number);
1792	cmd_resp->timeout = cpu_to_le32(*timeout);
1793	*timeout = 0;
1794
1795	status = ice_aq_send_cmd(hw, desc: &desc, NULL, buf_size: 0, cd);
1796
1797	/* The completion specifies the maximum time in ms that the driver
1798	* may hold the resource in the Timeout field.
1799	*/
1800
1801	/* Global config lock response utilizes an additional status field.
1802	*
1803	* If the Global config lock resource is held by some other driver, the
1804	* command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field
1805	* and the timeout field indicates the maximum time the current owner
1806	* of the resource has to free it.
1807	*/
1808	if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) {
1809	if (le16_to_cpu(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) {
1810	*timeout = le32_to_cpu(cmd_resp->timeout);
1811	return 0;
1812	} else if (le16_to_cpu(cmd_resp->status) ==
1813	ICE_AQ_RES_GLBL_IN_PROG) {
1814	*timeout = le32_to_cpu(cmd_resp->timeout);
1815	return -EIO;
1816	} else if (le16_to_cpu(cmd_resp->status) ==
1817	ICE_AQ_RES_GLBL_DONE) {
1818	return -EALREADY;
1819	}
1820
1821	/* invalid FW response, force a timeout immediately */
1822	*timeout = 0;
1823	return -EIO;
1824	}
1825
1826	/* If the resource is held by some other driver, the command completes
1827	* with a busy return value and the timeout field indicates the maximum
1828	* time the current owner of the resource has to free it.
1829	*/
1830	if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY)
1831	*timeout = le32_to_cpu(cmd_resp->timeout);
1832
1833	return status;
1834	}
1835
1836	/**
1837	* ice_aq_release_res
1838	* @hw: pointer to the HW struct
1839	* @res: resource ID
1840	* @sdp_number: resource number
1841	* @cd: pointer to command details structure or NULL
1842	*
1843	* release common resource using the admin queue commands (0x0009)
1844	*/
1845	static int
1846	ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number,
1847	struct ice_sq_cd *cd)
1848	{
1849	struct ice_aqc_req_res *cmd;
1850	struct ice_aq_desc desc;
1851
1852	cmd = &desc.params.res_owner;
1853
1854	ice_fill_dflt_direct_cmd_desc(desc: &desc, opcode: ice_aqc_opc_release_res);
1855
1856	cmd->res_id = cpu_to_le16(res);
1857	cmd->res_number = cpu_to_le32(sdp_number);
1858
1859	return ice_aq_send_cmd(hw, desc: &desc, NULL, buf_size: 0, cd);
1860	}
1861
1862	/**
1863	* ice_acquire_res
1864	* @hw: pointer to the HW structure
1865	* @res: resource ID
1866	* @access: access type (read or write)
1867	* @timeout: timeout in milliseconds
1868	*
1869	* This function will attempt to acquire the ownership of a resource.
1870	*/
1871	int
1872	ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1873	enum ice_aq_res_access_type access, u32 timeout)
1874	{
1875	#define ICE_RES_POLLING_DELAY_MS 10
1876	u32 delay = ICE_RES_POLLING_DELAY_MS;
1877	u32 time_left = timeout;
1878	int status;
1879
1880	status = ice_aq_req_res(hw, res, access, sdp_number: 0, timeout: &time_left, NULL);
1881
1882	/* A return code of -EALREADY means that another driver has
1883	* previously acquired the resource and performed any necessary updates;
1884	* in this case the caller does not obtain the resource and has no
1885	* further work to do.
1886	*/
1887	if (status == -EALREADY)
1888	goto ice_acquire_res_exit;
1889
1890	if (status)
1891	ice_debug(hw, ICE_DBG_RES, "resource %d acquire type %d failed.\n", res, access);
1892
1893	/* If necessary, poll until the current lock owner timeouts */
1894	timeout = time_left;
1895	while (status && timeout && time_left) {
1896	mdelay(delay);
1897	timeout = (timeout > delay) ? timeout - delay : 0;
1898	status = ice_aq_req_res(hw, res, access, sdp_number: 0, timeout: &time_left, NULL);
1899
1900	if (status == -EALREADY)
1901	/* lock free, but no work to do */
1902	break;
1903
1904	if (!status)
1905	/* lock acquired */
1906	break;
1907	}
1908	if (status && status != -EALREADY)
1909	ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n");
1910
1911	ice_acquire_res_exit:
1912	if (status == -EALREADY) {
1913	if (access == ICE_RES_WRITE)
1914	ice_debug(hw, ICE_DBG_RES, "resource indicates no work to do.\n");
1915	else
1916	ice_debug(hw, ICE_DBG_RES, "Warning: -EALREADY not expected\n");
1917	}
1918	return status;
1919	}
1920
1921	/**
1922	* ice_release_res
1923	* @hw: pointer to the HW structure
1924	* @res: resource ID
1925	*
1926	* This function will release a resource using the proper Admin Command.
1927	*/
1928	void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res)
1929	{
1930	unsigned long timeout;
1931	int status;
1932
1933	/* there are some rare cases when trying to release the resource
1934	* results in an admin queue timeout, so handle them correctly
1935	*/
1936	timeout = jiffies + 10 * ICE_CTL_Q_SQ_CMD_TIMEOUT;
1937	do {
1938	status = ice_aq_release_res(hw, res, sdp_number: 0, NULL);
1939	if (status != -EIO)
1940	break;
1941	usleep_range(min: 1000, max: 2000);
1942	} while (time_before(jiffies, timeout));
1943	}
1944
1945	/**
1946	* ice_aq_alloc_free_res - command to allocate/free resources
1947	* @hw: pointer to the HW struct
1948	* @buf: Indirect buffer to hold data parameters and response
1949	* @buf_size: size of buffer for indirect commands
1950	* @opc: pass in the command opcode
1951	*
1952	* Helper function to allocate/free resources using the admin queue commands
1953	*/
1954	int ice_aq_alloc_free_res(struct ice_hw *hw,
1955	struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size,
1956	enum ice_adminq_opc opc)
1957	{
1958	struct ice_aqc_alloc_free_res_cmd *cmd;
1959	struct ice_aq_desc desc;
1960
1961	cmd = &desc.params.sw_res_ctrl;
1962
1963	if (!buf || buf_size < flex_array_size(buf, elem, 1))
1964	return -EINVAL;
1965
1966	ice_fill_dflt_direct_cmd_desc(desc: &desc, opcode: opc);
1967
1968	desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
1969
1970	cmd->num_entries = cpu_to_le16(1);
1971
1972	return ice_aq_send_cmd(hw, desc: &desc, buf, buf_size, NULL);
1973	}
1974
1975	/**
1976	* ice_alloc_hw_res - allocate resource
1977	* @hw: pointer to the HW struct
1978	* @type: type of resource
1979	* @num: number of resources to allocate
1980	* @btm: allocate from bottom
1981	* @res: pointer to array that will receive the resources
1982	*/
1983	int
1984	ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res)
1985	{
1986	struct ice_aqc_alloc_free_res_elem *buf;
1987	u16 buf_len;
1988	int status;
1989
1990	buf_len = struct_size(buf, elem, num);
1991	buf = kzalloc(buf_len, GFP_KERNEL);
1992	if (!buf)
1993	return -ENOMEM;
1994
1995	/* Prepare buffer to allocate resource. */
1996	buf->num_elems = cpu_to_le16(num);
1997	buf->res_type = cpu_to_le16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED |
1998	ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX);
1999	if (btm)
2000	buf->res_type |= cpu_to_le16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM);
2001
2002	status = ice_aq_alloc_free_res(hw, buf, buf_size: buf_len, opc: ice_aqc_opc_alloc_res);
2003	if (status)
2004	goto ice_alloc_res_exit;
2005
2006	memcpy(res, buf->elem, sizeof(*buf->elem) * num);
2007
2008	ice_alloc_res_exit:
2009	kfree(objp: buf);
2010	return status;
2011	}
2012
2013	/**
2014	* ice_free_hw_res - free allocated HW resource
2015	* @hw: pointer to the HW struct
2016	* @type: type of resource to free
2017	* @num: number of resources
2018	* @res: pointer to array that contains the resources to free
2019	*/
2020	int ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res)
2021	{
2022	struct ice_aqc_alloc_free_res_elem *buf;
2023	u16 buf_len;
2024	int status;
2025
2026	buf_len = struct_size(buf, elem, num);
2027	buf = kzalloc(buf_len, GFP_KERNEL);
2028	if (!buf)
2029	return -ENOMEM;
2030
2031	/* Prepare buffer to free resource. */
2032	buf->num_elems = cpu_to_le16(num);
2033	buf->res_type = cpu_to_le16(type);
2034	memcpy(buf->elem, res, sizeof(*buf->elem) * num);
2035
2036	status = ice_aq_alloc_free_res(hw, buf, buf_size: buf_len, opc: ice_aqc_opc_free_res);
2037	if (status)
2038	ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n");
2039
2040	kfree(objp: buf);
2041	return status;
2042	}
2043
2044	/**
2045	* ice_get_num_per_func - determine number of resources per PF
2046	* @hw: pointer to the HW structure
2047	* @max: value to be evenly split between each PF
2048	*
2049	* Determine the number of valid functions by going through the bitmap returned
2050	* from parsing capabilities and use this to calculate the number of resources
2051	* per PF based on the max value passed in.
2052	*/
2053	static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max)
2054	{
2055	u8 funcs;
2056
2057	#define ICE_CAPS_VALID_FUNCS_M 0xFF
2058	funcs = hweight8(hw->dev_caps.common_cap.valid_functions &
2059	ICE_CAPS_VALID_FUNCS_M);
2060
2061	if (!funcs)
2062	return 0;
2063
2064	return max / funcs;
2065	}
2066
2067	/**
2068	* ice_parse_common_caps - parse common device/function capabilities
2069	* @hw: pointer to the HW struct
2070	* @caps: pointer to common capabilities structure
2071	* @elem: the capability element to parse
2072	* @prefix: message prefix for tracing capabilities
2073	*
2074	* Given a capability element, extract relevant details into the common
2075	* capability structure.
2076	*
2077	* Returns: true if the capability matches one of the common capability ids,
2078	* false otherwise.
2079	*/
2080	static bool
2081	ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps,
2082	struct ice_aqc_list_caps_elem *elem, const char *prefix)
2083	{
2084	u32 logical_id = le32_to_cpu(elem->logical_id);
2085	u32 phys_id = le32_to_cpu(elem->phys_id);
2086	u32 number = le32_to_cpu(elem->number);
2087	u16 cap = le16_to_cpu(elem->cap);
2088	bool found = true;
2089
2090	switch (cap) {
2091	case ICE_AQC_CAPS_VALID_FUNCTIONS:
2092	caps->valid_functions = number;
2093	ice_debug(hw, ICE_DBG_INIT, "%s: valid_functions (bitmap) = %d\n", prefix,
2094	caps->valid_functions);
2095	break;
2096	case ICE_AQC_CAPS_SRIOV:
2097	caps->sr_iov_1_1 = (number == 1);
2098	ice_debug(hw, ICE_DBG_INIT, "%s: sr_iov_1_1 = %d\n", prefix,
2099	caps->sr_iov_1_1);
2100	break;
2101	case ICE_AQC_CAPS_DCB:
2102	caps->dcb = (number == 1);
2103	caps->active_tc_bitmap = logical_id;
2104	caps->maxtc = phys_id;
2105	ice_debug(hw, ICE_DBG_INIT, "%s: dcb = %d\n", prefix, caps->dcb);
2106	ice_debug(hw, ICE_DBG_INIT, "%s: active_tc_bitmap = %d\n", prefix,
2107	caps->active_tc_bitmap);
2108	ice_debug(hw, ICE_DBG_INIT, "%s: maxtc = %d\n", prefix, caps->maxtc);
2109	break;
2110	case ICE_AQC_CAPS_RSS:
2111	caps->rss_table_size = number;
2112	caps->rss_table_entry_width = logical_id;
2113	ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_size = %d\n", prefix,
2114	caps->rss_table_size);
2115	ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_entry_width = %d\n", prefix,
2116	caps->rss_table_entry_width);
2117	break;
2118	case ICE_AQC_CAPS_RXQS:
2119	caps->num_rxq = number;
2120	caps->rxq_first_id = phys_id;
2121	ice_debug(hw, ICE_DBG_INIT, "%s: num_rxq = %d\n", prefix,
2122	caps->num_rxq);
2123	ice_debug(hw, ICE_DBG_INIT, "%s: rxq_first_id = %d\n", prefix,
2124	caps->rxq_first_id);
2125	break;
2126	case ICE_AQC_CAPS_TXQS:
2127	caps->num_txq = number;
2128	caps->txq_first_id = phys_id;
2129	ice_debug(hw, ICE_DBG_INIT, "%s: num_txq = %d\n", prefix,
2130	caps->num_txq);
2131	ice_debug(hw, ICE_DBG_INIT, "%s: txq_first_id = %d\n", prefix,
2132	caps->txq_first_id);
2133	break;
2134	case ICE_AQC_CAPS_MSIX:
2135	caps->num_msix_vectors = number;
2136	caps->msix_vector_first_id = phys_id;
2137	ice_debug(hw, ICE_DBG_INIT, "%s: num_msix_vectors = %d\n", prefix,
2138	caps->num_msix_vectors);
2139	ice_debug(hw, ICE_DBG_INIT, "%s: msix_vector_first_id = %d\n", prefix,
2140	caps->msix_vector_first_id);
2141	break;
2142	case ICE_AQC_CAPS_PENDING_NVM_VER:
2143	caps->nvm_update_pending_nvm = true;
2144	ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_nvm\n", prefix);
2145	break;
2146	case ICE_AQC_CAPS_PENDING_OROM_VER:
2147	caps->nvm_update_pending_orom = true;
2148	ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_orom\n", prefix);
2149	break;
2150	case ICE_AQC_CAPS_PENDING_NET_VER:
2151	caps->nvm_update_pending_netlist = true;
2152	ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_netlist\n", prefix);
2153	break;
2154	case ICE_AQC_CAPS_NVM_MGMT:
2155	caps->nvm_unified_update =
2156	(number & ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT) ?
2157	true : false;
2158	ice_debug(hw, ICE_DBG_INIT, "%s: nvm_unified_update = %d\n", prefix,
2159	caps->nvm_unified_update);
2160	break;
2161	case ICE_AQC_CAPS_RDMA:
2162	if (IS_ENABLED(CONFIG_INFINIBAND_IRDMA))
2163	caps->rdma = (number == 1);
2164	ice_debug(hw, ICE_DBG_INIT, "%s: rdma = %d\n", prefix, caps->rdma);
2165	break;
2166	case ICE_AQC_CAPS_MAX_MTU:
2167	caps->max_mtu = number;
2168	ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n",
2169	prefix, caps->max_mtu);
2170	break;
2171	case ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE:
2172	caps->pcie_reset_avoidance = (number > 0);
2173	ice_debug(hw, ICE_DBG_INIT,
2174	"%s: pcie_reset_avoidance = %d\n", prefix,
2175	caps->pcie_reset_avoidance);
2176	break;
2177	case ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT:
2178	caps->reset_restrict_support = (number == 1);
2179	ice_debug(hw, ICE_DBG_INIT,
2180	"%s: reset_restrict_support = %d\n", prefix,
2181	caps->reset_restrict_support);
2182	break;
2183	case ICE_AQC_CAPS_FW_LAG_SUPPORT:
2184	caps->roce_lag = !!(number & ICE_AQC_BIT_ROCEV2_LAG);
2185	ice_debug(hw, ICE_DBG_INIT, "%s: roce_lag = %u\n",
2186	prefix, caps->roce_lag);
2187	caps->sriov_lag = !!(number & ICE_AQC_BIT_SRIOV_LAG);
2188	ice_debug(hw, ICE_DBG_INIT, "%s: sriov_lag = %u\n",
2189	prefix, caps->sriov_lag);
2190	break;
2191	case ICE_AQC_CAPS_TX_SCHED_TOPO_COMP_MODE:
2192	caps->tx_sched_topo_comp_mode_en = (number == 1);
2193	break;
2194	default:
2195	/* Not one of the recognized common capabilities */
2196	found = false;
2197	}
2198
2199	return found;
2200	}
2201
2202	/**
2203	* ice_recalc_port_limited_caps - Recalculate port limited capabilities
2204	* @hw: pointer to the HW structure
2205	* @caps: pointer to capabilities structure to fix
2206	*
2207	* Re-calculate the capabilities that are dependent on the number of physical
2208	* ports; i.e. some features are not supported or function differently on
2209	* devices with more than 4 ports.
2210	*/
2211	static void
2212	ice_recalc_port_limited_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps)
2213	{
2214	/* This assumes device capabilities are always scanned before function
2215	* capabilities during the initialization flow.
2216	*/
2217	if (hw->dev_caps.num_funcs > 4) {
2218	/* Max 4 TCs per port */
2219	caps->maxtc = 4;
2220	ice_debug(hw, ICE_DBG_INIT, "reducing maxtc to %d (based on #ports)\n",
2221	caps->maxtc);
2222	if (caps->rdma) {
2223	ice_debug(hw, ICE_DBG_INIT, "forcing RDMA off\n");
2224	caps->rdma = 0;
2225	}
2226
2227	/* print message only when processing device capabilities
2228	* during initialization.
2229	*/
2230	if (caps == &hw->dev_caps.common_cap)
2231	dev_info(ice_hw_to_dev(hw), "RDMA functionality is not available with the current device configuration.\n");
2232	}
2233	}
2234
2235	/**
2236	* ice_parse_vf_func_caps - Parse ICE_AQC_CAPS_VF function caps
2237	* @hw: pointer to the HW struct
2238	* @func_p: pointer to function capabilities structure
2239	* @cap: pointer to the capability element to parse
2240	*
2241	* Extract function capabilities for ICE_AQC_CAPS_VF.
2242	*/
2243	static void
2244	ice_parse_vf_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
2245	struct ice_aqc_list_caps_elem *cap)
2246	{
2247	u32 logical_id = le32_to_cpu(cap->logical_id);
2248	u32 number = le32_to_cpu(cap->number);
2249
2250	func_p->num_allocd_vfs = number;
2251	func_p->vf_base_id = logical_id;
2252	ice_debug(hw, ICE_DBG_INIT, "func caps: num_allocd_vfs = %d\n",
2253	func_p->num_allocd_vfs);
2254	ice_debug(hw, ICE_DBG_INIT, "func caps: vf_base_id = %d\n",
2255	func_p->vf_base_id);
2256	}
2257
2258	/**
2259	* ice_parse_vsi_func_caps - Parse ICE_AQC_CAPS_VSI function caps
2260	* @hw: pointer to the HW struct
2261	* @func_p: pointer to function capabilities structure
2262	* @cap: pointer to the capability element to parse
2263	*
2264	* Extract function capabilities for ICE_AQC_CAPS_VSI.
2265	*/
2266	static void
2267	ice_parse_vsi_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
2268	struct ice_aqc_list_caps_elem *cap)
2269	{
2270	func_p->guar_num_vsi = ice_get_num_per_func(hw, ICE_MAX_VSI);
2271	ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi (fw) = %d\n",
2272	le32_to_cpu(cap->number));
2273	ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi = %d\n",
2274	func_p->guar_num_vsi);
2275	}
2276
2277	/**
2278	* ice_parse_1588_func_caps - Parse ICE_AQC_CAPS_1588 function caps
2279	* @hw: pointer to the HW struct
2280	* @func_p: pointer to function capabilities structure
2281	* @cap: pointer to the capability element to parse
2282	*
2283	* Extract function capabilities for ICE_AQC_CAPS_1588.
2284	*/
2285	static void
2286	ice_parse_1588_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
2287	struct ice_aqc_list_caps_elem *cap)
2288	{
2289	struct ice_ts_func_info *info = &func_p->ts_func_info;
2290	u32 number = le32_to_cpu(cap->number);
2291
2292	info->ena = ((number & ICE_TS_FUNC_ENA_M) != 0);
2293	func_p->common_cap.ieee_1588 = info->ena;
2294
2295	info->src_tmr_owned = ((number & ICE_TS_SRC_TMR_OWND_M) != 0);
2296	info->tmr_ena = ((number & ICE_TS_TMR_ENA_M) != 0);
2297	info->tmr_index_owned = ((number & ICE_TS_TMR_IDX_OWND_M) != 0);
2298	info->tmr_index_assoc = ((number & ICE_TS_TMR_IDX_ASSOC_M) != 0);
2299
2300	if (hw->mac_type != ICE_MAC_GENERIC_3K_E825) {
2301	info->clk_freq = FIELD_GET(ICE_TS_CLK_FREQ_M, number);
2302	info->clk_src = ((number & ICE_TS_CLK_SRC_M) != 0);
2303	} else {
2304	info->clk_freq = ICE_TIME_REF_FREQ_156_250;
2305	info->clk_src = ICE_CLK_SRC_TCXO;
2306	}
2307
2308	if (info->clk_freq < NUM_ICE_TIME_REF_FREQ) {
2309	info->time_ref = (enum ice_time_ref_freq)info->clk_freq;
2310	} else {
2311	/* Unknown clock frequency, so assume a (probably incorrect)
2312	* default to avoid out-of-bounds look ups of frequency
2313	* related information.
2314	*/
2315	ice_debug(hw, ICE_DBG_INIT, "1588 func caps: unknown clock frequency %u\n",
2316	info->clk_freq);
2317	info->time_ref = ICE_TIME_REF_FREQ_25_000;
2318	}
2319
2320	ice_debug(hw, ICE_DBG_INIT, "func caps: ieee_1588 = %u\n",
2321	func_p->common_cap.ieee_1588);
2322	ice_debug(hw, ICE_DBG_INIT, "func caps: src_tmr_owned = %u\n",
2323	info->src_tmr_owned);
2324	ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_ena = %u\n",
2325	info->tmr_ena);
2326	ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_owned = %u\n",
2327	info->tmr_index_owned);
2328	ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_assoc = %u\n",
2329	info->tmr_index_assoc);
2330	ice_debug(hw, ICE_DBG_INIT, "func caps: clk_freq = %u\n",
2331	info->clk_freq);
2332	ice_debug(hw, ICE_DBG_INIT, "func caps: clk_src = %u\n",
2333	info->clk_src);
2334	}
2335
2336	/**
2337	* ice_parse_fdir_func_caps - Parse ICE_AQC_CAPS_FD function caps
2338	* @hw: pointer to the HW struct
2339	* @func_p: pointer to function capabilities structure
2340	*
2341	* Extract function capabilities for ICE_AQC_CAPS_FD.
2342	*/
2343	static void
2344	ice_parse_fdir_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p)
2345	{
2346	u32 reg_val, gsize, bsize;
2347
2348	reg_val = rd32(hw, GLQF_FD_SIZE);
2349	switch (hw->mac_type) {
2350	case ICE_MAC_E830:
2351	gsize = FIELD_GET(E830_GLQF_FD_SIZE_FD_GSIZE_M, reg_val);
2352	bsize = FIELD_GET(E830_GLQF_FD_SIZE_FD_BSIZE_M, reg_val);
2353	break;
2354	case ICE_MAC_E810:
2355	default:
2356	gsize = FIELD_GET(E800_GLQF_FD_SIZE_FD_GSIZE_M, reg_val);
2357	bsize = FIELD_GET(E800_GLQF_FD_SIZE_FD_BSIZE_M, reg_val);
2358	}
2359	func_p->fd_fltr_guar = ice_get_num_per_func(hw, max: gsize);
2360	func_p->fd_fltr_best_effort = bsize;
2361
2362	ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_guar = %d\n",
2363	func_p->fd_fltr_guar);
2364	ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_best_effort = %d\n",
2365	func_p->fd_fltr_best_effort);
2366	}
2367
2368	/**
2369	* ice_parse_func_caps - Parse function capabilities
2370	* @hw: pointer to the HW struct
2371	* @func_p: pointer to function capabilities structure
2372	* @buf: buffer containing the function capability records
2373	* @cap_count: the number of capabilities
2374	*
2375	* Helper function to parse function (0x000A) capabilities list. For
2376	* capabilities shared between device and function, this relies on
2377	* ice_parse_common_caps.
2378	*
2379	* Loop through the list of provided capabilities and extract the relevant
2380	* data into the function capabilities structured.
2381	*/
2382	static void
2383	ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
2384	void *buf, u32 cap_count)
2385	{
2386	struct ice_aqc_list_caps_elem *cap_resp;
2387	u32 i;
2388
2389	cap_resp = buf;
2390
2391	memset(func_p, 0, sizeof(*func_p));
2392
2393	for (i = 0; i < cap_count; i++) {
2394	u16 cap = le16_to_cpu(cap_resp[i].cap);
2395	bool found;
2396
2397	found = ice_parse_common_caps(hw, caps: &func_p->common_cap,
2398	elem: &cap_resp[i], prefix: "func caps");
2399
2400	switch (cap) {
2401	case ICE_AQC_CAPS_VF:
2402	ice_parse_vf_func_caps(hw, func_p, cap: &cap_resp[i]);
2403	break;
2404	case ICE_AQC_CAPS_VSI:
2405	ice_parse_vsi_func_caps(hw, func_p, cap: &cap_resp[i]);
2406	break;
2407	case ICE_AQC_CAPS_1588:
2408	ice_parse_1588_func_caps(hw, func_p, cap: &cap_resp[i]);
2409	break;
2410	case ICE_AQC_CAPS_FD:
2411	ice_parse_fdir_func_caps(hw, func_p);
2412	break;
2413	default:
2414	/* Don't list common capabilities as unknown */
2415	if (!found)
2416	ice_debug(hw, ICE_DBG_INIT, "func caps: unknown capability[%d]: 0x%x\n",
2417	i, cap);
2418	break;
2419	}
2420	}
2421
2422	ice_recalc_port_limited_caps(hw, caps: &func_p->common_cap);
2423	}
2424
2425	/**
2426	* ice_func_id_to_logical_id - map from function id to logical pf id
2427	* @active_function_bitmap: active function bitmap
2428	* @pf_id: function number of device
2429	*
2430	* Return: logical PF ID.
2431	*/
2432	static int ice_func_id_to_logical_id(u32 active_function_bitmap, u8 pf_id)
2433	{
2434	u8 logical_id = 0;
2435	u8 i;
2436
2437	for (i = 0; i < pf_id; i++)
2438	if (active_function_bitmap & BIT(i))
2439	logical_id++;
2440
2441	return logical_id;
2442	}
2443
2444	/**
2445	* ice_parse_valid_functions_cap - Parse ICE_AQC_CAPS_VALID_FUNCTIONS caps
2446	* @hw: pointer to the HW struct
2447	* @dev_p: pointer to device capabilities structure
2448	* @cap: capability element to parse
2449	*
2450	* Parse ICE_AQC_CAPS_VALID_FUNCTIONS for device capabilities.
2451	*/
2452	static void
2453	ice_parse_valid_functions_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2454	struct ice_aqc_list_caps_elem *cap)
2455	{
2456	u32 number = le32_to_cpu(cap->number);
2457
2458	dev_p->num_funcs = hweight32(number);
2459	ice_debug(hw, ICE_DBG_INIT, "dev caps: num_funcs = %d\n",
2460	dev_p->num_funcs);
2461
2462	hw->logical_pf_id = ice_func_id_to_logical_id(active_function_bitmap: number, pf_id: hw->pf_id);
2463	}
2464
2465	/**
2466	* ice_parse_vf_dev_caps - Parse ICE_AQC_CAPS_VF device caps
2467	* @hw: pointer to the HW struct
2468	* @dev_p: pointer to device capabilities structure
2469	* @cap: capability element to parse
2470	*
2471	* Parse ICE_AQC_CAPS_VF for device capabilities.
2472	*/
2473	static void
2474	ice_parse_vf_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2475	struct ice_aqc_list_caps_elem *cap)
2476	{
2477	u32 number = le32_to_cpu(cap->number);
2478
2479	dev_p->num_vfs_exposed = number;
2480	ice_debug(hw, ICE_DBG_INIT, "dev_caps: num_vfs_exposed = %d\n",
2481	dev_p->num_vfs_exposed);
2482	}
2483
2484	/**
2485	* ice_parse_vsi_dev_caps - Parse ICE_AQC_CAPS_VSI device caps
2486	* @hw: pointer to the HW struct
2487	* @dev_p: pointer to device capabilities structure
2488	* @cap: capability element to parse
2489	*
2490	* Parse ICE_AQC_CAPS_VSI for device capabilities.
2491	*/
2492	static void
2493	ice_parse_vsi_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2494	struct ice_aqc_list_caps_elem *cap)
2495	{
2496	u32 number = le32_to_cpu(cap->number);
2497
2498	dev_p->num_vsi_allocd_to_host = number;
2499	ice_debug(hw, ICE_DBG_INIT, "dev caps: num_vsi_allocd_to_host = %d\n",
2500	dev_p->num_vsi_allocd_to_host);
2501	}
2502
2503	/**
2504	* ice_parse_1588_dev_caps - Parse ICE_AQC_CAPS_1588 device caps
2505	* @hw: pointer to the HW struct
2506	* @dev_p: pointer to device capabilities structure
2507	* @cap: capability element to parse
2508	*
2509	* Parse ICE_AQC_CAPS_1588 for device capabilities.
2510	*/
2511	static void
2512	ice_parse_1588_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2513	struct ice_aqc_list_caps_elem *cap)
2514	{
2515	struct ice_ts_dev_info *info = &dev_p->ts_dev_info;
2516	u32 logical_id = le32_to_cpu(cap->logical_id);
2517	u32 phys_id = le32_to_cpu(cap->phys_id);
2518	u32 number = le32_to_cpu(cap->number);
2519
2520	info->ena = ((number & ICE_TS_DEV_ENA_M) != 0);
2521	dev_p->common_cap.ieee_1588 = info->ena;
2522
2523	info->tmr0_owner = number & ICE_TS_TMR0_OWNR_M;
2524	info->tmr0_owned = ((number & ICE_TS_TMR0_OWND_M) != 0);
2525	info->tmr0_ena = ((number & ICE_TS_TMR0_ENA_M) != 0);
2526
2527	info->tmr1_owner = FIELD_GET(ICE_TS_TMR1_OWNR_M, number);
2528	info->tmr1_owned = ((number & ICE_TS_TMR1_OWND_M) != 0);
2529	info->tmr1_ena = ((number & ICE_TS_TMR1_ENA_M) != 0);
2530
2531	info->ts_ll_read = ((number & ICE_TS_LL_TX_TS_READ_M) != 0);
2532	info->ts_ll_int_read = ((number & ICE_TS_LL_TX_TS_INT_READ_M) != 0);
2533	info->ll_phy_tmr_update = ((number & ICE_TS_LL_PHY_TMR_UPDATE_M) != 0);
2534
2535	info->ena_ports = logical_id;
2536	info->tmr_own_map = phys_id;
2537
2538	ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 = %u\n",
2539	dev_p->common_cap.ieee_1588);
2540	ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owner = %u\n",
2541	info->tmr0_owner);
2542	ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owned = %u\n",
2543	info->tmr0_owned);
2544	ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_ena = %u\n",
2545	info->tmr0_ena);
2546	ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owner = %u\n",
2547	info->tmr1_owner);
2548	ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owned = %u\n",
2549	info->tmr1_owned);
2550	ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_ena = %u\n",
2551	info->tmr1_ena);
2552	ice_debug(hw, ICE_DBG_INIT, "dev caps: ts_ll_read = %u\n",
2553	info->ts_ll_read);
2554	ice_debug(hw, ICE_DBG_INIT, "dev caps: ts_ll_int_read = %u\n",
2555	info->ts_ll_int_read);
2556	ice_debug(hw, ICE_DBG_INIT, "dev caps: ll_phy_tmr_update = %u\n",
2557	info->ll_phy_tmr_update);
2558	ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 ena_ports = %u\n",
2559	info->ena_ports);
2560	ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr_own_map = %u\n",
2561	info->tmr_own_map);
2562	}
2563
2564	/**
2565	* ice_parse_fdir_dev_caps - Parse ICE_AQC_CAPS_FD device caps
2566	* @hw: pointer to the HW struct
2567	* @dev_p: pointer to device capabilities structure
2568	* @cap: capability element to parse
2569	*
2570	* Parse ICE_AQC_CAPS_FD for device capabilities.
2571	*/
2572	static void
2573	ice_parse_fdir_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2574	struct ice_aqc_list_caps_elem *cap)
2575	{
2576	u32 number = le32_to_cpu(cap->number);
2577
2578	dev_p->num_flow_director_fltr = number;
2579	ice_debug(hw, ICE_DBG_INIT, "dev caps: num_flow_director_fltr = %d\n",
2580	dev_p->num_flow_director_fltr);
2581	}
2582
2583	/**
2584	* ice_parse_sensor_reading_cap - Parse ICE_AQC_CAPS_SENSOR_READING cap
2585	* @hw: pointer to the HW struct
2586	* @dev_p: pointer to device capabilities structure
2587	* @cap: capability element to parse
2588	*
2589	* Parse ICE_AQC_CAPS_SENSOR_READING for device capability for reading
2590	* enabled sensors.
2591	*/
2592	static void
2593	ice_parse_sensor_reading_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2594	struct ice_aqc_list_caps_elem *cap)
2595	{
2596	dev_p->supported_sensors = le32_to_cpu(cap->number);
2597
2598	ice_debug(hw, ICE_DBG_INIT,
2599	"dev caps: supported sensors (bitmap) = 0x%x\n",
2600	dev_p->supported_sensors);
2601	}
2602
2603	/**
2604	* ice_parse_nac_topo_dev_caps - Parse ICE_AQC_CAPS_NAC_TOPOLOGY cap
2605	* @hw: pointer to the HW struct
2606	* @dev_p: pointer to device capabilities structure
2607	* @cap: capability element to parse
2608	*
2609	* Parse ICE_AQC_CAPS_NAC_TOPOLOGY for device capabilities.
2610	*/
2611	static void ice_parse_nac_topo_dev_caps(struct ice_hw *hw,
2612	struct ice_hw_dev_caps *dev_p,
2613	struct ice_aqc_list_caps_elem *cap)
2614	{
2615	dev_p->nac_topo.mode = le32_to_cpu(cap->number);
2616	dev_p->nac_topo.id = le32_to_cpu(cap->phys_id) & ICE_NAC_TOPO_ID_M;
2617
2618	dev_info(ice_hw_to_dev(hw),
2619	"PF is configured in %s mode with IP instance ID %d\n",
2620	(dev_p->nac_topo.mode & ICE_NAC_TOPO_PRIMARY_M) ?
2621	"primary" : "secondary", dev_p->nac_topo.id);
2622
2623	ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology is_primary = %d\n",
2624	!!(dev_p->nac_topo.mode & ICE_NAC_TOPO_PRIMARY_M));
2625	ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology is_dual = %d\n",
2626	!!(dev_p->nac_topo.mode & ICE_NAC_TOPO_DUAL_M));
2627	ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology id = %d\n",
2628	dev_p->nac_topo.id);
2629	}
2630
2631	/**
2632	* ice_parse_dev_caps - Parse device capabilities
2633	* @hw: pointer to the HW struct
2634	* @dev_p: pointer to device capabilities structure
2635	* @buf: buffer containing the device capability records
2636	* @cap_count: the number of capabilities
2637	*
2638	* Helper device to parse device (0x000B) capabilities list. For
2639	* capabilities shared between device and function, this relies on
2640	* ice_parse_common_caps.
2641	*
2642	* Loop through the list of provided capabilities and extract the relevant
2643	* data into the device capabilities structured.
2644	*/
2645	static void
2646	ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2647	void *buf, u32 cap_count)
2648	{
2649	struct ice_aqc_list_caps_elem *cap_resp;
2650	u32 i;
2651
2652	cap_resp = buf;
2653
2654	memset(dev_p, 0, sizeof(*dev_p));
2655
2656	for (i = 0; i < cap_count; i++) {
2657	u16 cap = le16_to_cpu(cap_resp[i].cap);
2658	bool found;
2659
2660	found = ice_parse_common_caps(hw, caps: &dev_p->common_cap,
2661	elem: &cap_resp[i], prefix: "dev caps");
2662
2663	switch (cap) {
2664	case ICE_AQC_CAPS_VALID_FUNCTIONS:
2665	ice_parse_valid_functions_cap(hw, dev_p, cap: &cap_resp[i]);
2666	break;
2667	case ICE_AQC_CAPS_VF:
2668	ice_parse_vf_dev_caps(hw, dev_p, cap: &cap_resp[i]);
2669	break;
2670	case ICE_AQC_CAPS_VSI:
2671	ice_parse_vsi_dev_caps(hw, dev_p, cap: &cap_resp[i]);
2672	break;
2673	case ICE_AQC_CAPS_1588:
2674	ice_parse_1588_dev_caps(hw, dev_p, cap: &cap_resp[i]);
2675	break;
2676	case ICE_AQC_CAPS_FD:
2677	ice_parse_fdir_dev_caps(hw, dev_p, cap: &cap_resp[i]);
2678	break;
2679	case ICE_AQC_CAPS_SENSOR_READING:
2680	ice_parse_sensor_reading_cap(hw, dev_p, cap: &cap_resp[i]);
2681	break;
2682	case ICE_AQC_CAPS_NAC_TOPOLOGY:
2683	ice_parse_nac_topo_dev_caps(hw, dev_p, cap: &cap_resp[i]);
2684	break;
2685	default:
2686	/* Don't list common capabilities as unknown */
2687	if (!found)
2688	ice_debug(hw, ICE_DBG_INIT, "dev caps: unknown capability[%d]: 0x%x\n",
2689	i, cap);
2690	break;
2691	}
2692	}
2693
2694	ice_recalc_port_limited_caps(hw, caps: &dev_p->common_cap);
2695	}
2696
2697	/**
2698	* ice_is_phy_rclk_in_netlist
2699	* @hw: pointer to the hw struct
2700	*
2701	* Check if the PHY Recovered Clock device is present in the netlist
2702	*/
2703	bool ice_is_phy_rclk_in_netlist(struct ice_hw *hw)
2704	{
2705	if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_PHY,
2706	ICE_AQC_LINK_TOPO_NODE_CTX_PORT,
2707	ICE_AQC_GET_LINK_TOPO_NODE_NR_C827, NULL) &&
2708	ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_PHY,
2709	ICE_AQC_LINK_TOPO_NODE_CTX_PORT,
2710	ICE_AQC_GET_LINK_TOPO_NODE_NR_E822_PHY, NULL))
2711	return false;
2712
2713	return true;
2714	}
2715
2716	/**
2717	* ice_is_clock_mux_in_netlist
2718	* @hw: pointer to the hw struct
2719	*
2720	* Check if the Clock Multiplexer device is present in the netlist
2721	*/
2722	bool ice_is_clock_mux_in_netlist(struct ice_hw *hw)
2723	{
2724	if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_MUX,
2725	ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL,
2726	ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_CLK_MUX,
2727	NULL))
2728	return false;
2729
2730	return true;
2731	}
2732
2733	/**
2734	* ice_is_cgu_in_netlist - check for CGU presence
2735	* @hw: pointer to the hw struct
2736	*
2737	* Check if the Clock Generation Unit (CGU) device is present in the netlist.
2738	* Save the CGU part number in the hw structure for later use.
2739	* Return:
2740	* * true - cgu is present
2741	* * false - cgu is not present
2742	*/
2743	bool ice_is_cgu_in_netlist(struct ice_hw *hw)
2744	{
2745	if (!ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_CTRL,
2746	ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL,
2747	ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032,
2748	NULL)) {
2749	hw->cgu_part_number = ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032;
2750	return true;
2751	} else if (!ice_find_netlist_node(hw,
2752	ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_CTRL,
2753	ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL,
2754	ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384,
2755	NULL)) {
2756	hw->cgu_part_number = ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384;
2757	return true;
2758	}
2759
2760	return false;
2761	}
2762
2763	/**
2764	* ice_is_gps_in_netlist
2765	* @hw: pointer to the hw struct
2766	*
2767	* Check if the GPS generic device is present in the netlist
2768	*/
2769	bool ice_is_gps_in_netlist(struct ice_hw *hw)
2770	{
2771	if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_GPS,
2772	ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL,
2773	ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_GPS, NULL))
2774	return false;
2775
2776	return true;
2777	}
2778
2779	/**
2780	* ice_aq_list_caps - query function/device capabilities
2781	* @hw: pointer to the HW struct
2782	* @buf: a buffer to hold the capabilities
2783	* @buf_size: size of the buffer
2784	* @cap_count: if not NULL, set to the number of capabilities reported
2785	* @opc: capabilities type to discover, device or function
2786	* @cd: pointer to command details structure or NULL
2787	*
2788	* Get the function (0x000A) or device (0x000B) capabilities description from
2789	* firmware and store it in the buffer.
2790	*
2791	* If the cap_count pointer is not NULL, then it is set to the number of
2792	* capabilities firmware will report. Note that if the buffer size is too
2793	* small, it is possible the command will return ICE_AQ_ERR_ENOMEM. The
2794	* cap_count will still be updated in this case. It is recommended that the
2795	* buffer size be set to ICE_AQ_MAX_BUF_LEN (the largest possible buffer that
2796	* firmware could return) to avoid this.
2797	*/
2798	int
2799	ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count,
2800	enum ice_adminq_opc opc, struct ice_sq_cd *cd)
2801	{
2802	struct ice_aqc_list_caps *cmd;
2803	struct ice_aq_desc desc;
2804	int status;
2805
2806	cmd = &desc.params.get_cap;
2807
2808	if (opc != ice_aqc_opc_list_func_caps &&
2809	opc != ice_aqc_opc_list_dev_caps)
2810	return -EINVAL;
2811
2812	ice_fill_dflt_direct_cmd_desc(desc: &desc, opcode: opc);
2813	status = ice_aq_send_cmd(hw, desc: &desc, buf, buf_size, cd);
2814
2815	if (cap_count)
2816	*cap_count = le32_to_cpu(cmd->count);
2817
2818	return status;
2819	}
2820
2821	/**
2822	* ice_discover_dev_caps - Read and extract device capabilities
2823	* @hw: pointer to the hardware structure
2824	* @dev_caps: pointer to device capabilities structure
2825	*
2826	* Read the device capabilities and extract them into the dev_caps structure
2827	* for later use.
2828	*/
2829	int
2830	ice_discover_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_caps)
2831	{
2832	u32 cap_count = 0;
2833	void *cbuf;
2834	int status;
2835
2836	cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL);
2837	if (!cbuf)
2838	return -ENOMEM;
2839
2840	/* Although the driver doesn't know the number of capabilities the
2841	* device will return, we can simply send a 4KB buffer, the maximum
2842	* possible size that firmware can return.
2843	*/
2844	cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem);
2845
2846	status = ice_aq_list_caps(hw, buf: cbuf, ICE_AQ_MAX_BUF_LEN, cap_count: &cap_count,
2847	opc: ice_aqc_opc_list_dev_caps, NULL);
2848	if (!status)
2849	ice_parse_dev_caps(hw, dev_p: dev_caps, buf: cbuf, cap_count);
2850	kfree(objp: cbuf);
2851
2852	return status;
2853	}
2854
2855	/**
2856	* ice_discover_func_caps - Read and extract function capabilities
2857	* @hw: pointer to the hardware structure
2858	* @func_caps: pointer to function capabilities structure
2859	*
2860	* Read the function capabilities and extract them into the func_caps structure
2861	* for later use.
2862	*/
2863	static int
2864	ice_discover_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_caps)
2865	{
2866	u32 cap_count = 0;
2867	void *cbuf;
2868	int status;
2869
2870	cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL);
2871	if (!cbuf)
2872	return -ENOMEM;
2873
2874	/* Although the driver doesn't know the number of capabilities the
2875	* device will return, we can simply send a 4KB buffer, the maximum
2876	* possible size that firmware can return.
2877	*/
2878	cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem);
2879
2880	status = ice_aq_list_caps(hw, buf: cbuf, ICE_AQ_MAX_BUF_LEN, cap_count: &cap_count,
2881	opc: ice_aqc_opc_list_func_caps, NULL);
2882	if (!status)
2883	ice_parse_func_caps(hw, func_p: func_caps, buf: cbuf, cap_count);
2884	kfree(objp: cbuf);
2885
2886	return status;
2887	}
2888
2889	/**
2890	* ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode
2891	* @hw: pointer to the hardware structure
2892	*/
2893	void ice_set_safe_mode_caps(struct ice_hw *hw)
2894	{
2895	struct ice_hw_func_caps *func_caps = &hw->func_caps;
2896	struct ice_hw_dev_caps *dev_caps = &hw->dev_caps;
2897	struct ice_hw_common_caps cached_caps;
2898	u32 num_funcs;
2899
2900	/* cache some func_caps values that should be restored after memset */
2901	cached_caps = func_caps->common_cap;
2902
2903	/* unset func capabilities */
2904	memset(func_caps, 0, sizeof(*func_caps));
2905
2906	#define ICE_RESTORE_FUNC_CAP(name) \
2907	func_caps->common_cap.name = cached_caps.name
2908
2909	/* restore cached values */
2910	ICE_RESTORE_FUNC_CAP(valid_functions);
2911	ICE_RESTORE_FUNC_CAP(txq_first_id);
2912	ICE_RESTORE_FUNC_CAP(rxq_first_id);
2913	ICE_RESTORE_FUNC_CAP(msix_vector_first_id);
2914	ICE_RESTORE_FUNC_CAP(max_mtu);
2915	ICE_RESTORE_FUNC_CAP(nvm_unified_update);
2916	ICE_RESTORE_FUNC_CAP(nvm_update_pending_nvm);
2917	ICE_RESTORE_FUNC_CAP(nvm_update_pending_orom);
2918	ICE_RESTORE_FUNC_CAP(nvm_update_pending_netlist);
2919
2920	/* one Tx and one Rx queue in safe mode */
2921	func_caps->common_cap.num_rxq = 1;
2922	func_caps->common_cap.num_txq = 1;
2923
2924	/* two MSIX vectors, one for traffic and one for misc causes */
2925	func_caps->common_cap.num_msix_vectors = 2;
2926	func_caps->guar_num_vsi = 1;
2927
2928	/* cache some dev_caps values that should be restored after memset */
2929	cached_caps = dev_caps->common_cap;
2930	num_funcs = dev_caps->num_funcs;
2931
2932	/* unset dev capabilities */
2933	memset(dev_caps, 0, sizeof(*dev_caps));
2934
2935	#define ICE_RESTORE_DEV_CAP(name) \
2936	dev_caps->common_cap.name = cached_caps.name
2937
2938	/* restore cached values */
2939	ICE_RESTORE_DEV_CAP(valid_functions);
2940	ICE_RESTORE_DEV_CAP(txq_first_id);
2941	ICE_RESTORE_DEV_CAP(rxq_first_id);
2942	ICE_RESTORE_DEV_CAP(msix_vector_first_id);
2943	ICE_RESTORE_DEV_CAP(max_mtu);
2944	ICE_RESTORE_DEV_CAP(nvm_unified_update);
2945	ICE_RESTORE_DEV_CAP(nvm_update_pending_nvm);
2946	ICE_RESTORE_DEV_CAP(nvm_update_pending_orom);
2947	ICE_RESTORE_DEV_CAP(nvm_update_pending_netlist);
2948	dev_caps->num_funcs = num_funcs;
2949
2950	/* one Tx and one Rx queue per function in safe mode */
2951	dev_caps->common_cap.num_rxq = num_funcs;
2952	dev_caps->common_cap.num_txq = num_funcs;
2953
2954	/* two MSIX vectors per function */
2955	dev_caps->common_cap.num_msix_vectors = 2 * num_funcs;
2956	}
2957
2958	/**
2959	* ice_get_caps - get info about the HW
2960	* @hw: pointer to the hardware structure
2961	*/
2962	int ice_get_caps(struct ice_hw *hw)
2963	{
2964	int status;
2965
2966	status = ice_discover_dev_caps(hw, dev_caps: &hw->dev_caps);
2967	if (status)
2968	return status;
2969
2970	return ice_discover_func_caps(hw, func_caps: &hw->func_caps);
2971	}
2972
2973	/**
2974	* ice_aq_manage_mac_write - manage MAC address write command
2975	* @hw: pointer to the HW struct
2976	* @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address
2977	* @flags: flags to control write behavior
2978	* @cd: pointer to command details structure or NULL
2979	*
2980	* This function is used to write MAC address to the NVM (0x0108).
2981	*/
2982	int
2983	ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags,
2984	struct ice_sq_cd *cd)
2985	{
2986	struct ice_aqc_manage_mac_write *cmd;
2987	struct ice_aq_desc desc;
2988
2989	cmd = &desc.params.mac_write;
2990	ice_fill_dflt_direct_cmd_desc(desc: &desc, opcode: ice_aqc_opc_manage_mac_write);
2991
2992	cmd->flags = flags;
2993	ether_addr_copy(dst: cmd->mac_addr, src: mac_addr);
2994
2995	return ice_aq_send_cmd(hw, desc: &desc, NULL, buf_size: 0, cd);
2996	}
2997
2998	/**
2999	* ice_aq_clear_pxe_mode
3000	* @hw: pointer to the HW struct
3001	*
3002	* Tell the firmware that the driver is taking over from PXE (0x0110).
3003	*/
3004	static int ice_aq_clear_pxe_mode(struct ice_hw *hw)
3005	{
3006	struct ice_aq_desc desc;
3007
3008	ice_fill_dflt_direct_cmd_desc(desc: &desc, opcode: ice_aqc_opc_clear_pxe_mode);
3009	desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT;
3010
3011	return ice_aq_send_cmd(hw, desc: &desc, NULL, buf_size: 0, NULL);
3012	}
3013
3014	/**
3015	* ice_clear_pxe_mode - clear pxe operations mode
3016	* @hw: pointer to the HW struct
3017	*
3018	* Make sure all PXE mode settings are cleared, including things
3019	* like descriptor fetch/write-back mode.
3020	*/
3021	void ice_clear_pxe_mode(struct ice_hw *hw)
3022	{
3023	if (ice_check_sq_alive(hw, cq: &hw->adminq))
3024	ice_aq_clear_pxe_mode(hw);
3025	}
3026
3027	/**
3028	* ice_aq_set_port_params - set physical port parameters.
3029	* @pi: pointer to the port info struct
3030	* @double_vlan: if set double VLAN is enabled
3031	* @cd: pointer to command details structure or NULL
3032	*
3033	* Set Physical port parameters (0x0203)
3034	*/
3035	int
3036	ice_aq_set_port_params(struct ice_port_info *pi, bool double_vlan,
3037	struct ice_sq_cd *cd)
3038
3039	{
3040	struct ice_aqc_set_port_params *cmd;
3041	struct ice_hw *hw = pi->hw;
3042	struct ice_aq_desc desc;
3043	u16 cmd_flags = 0;
3044
3045	cmd = &desc.params.set_port_params;
3046
3047	ice_fill_dflt_direct_cmd_desc(desc: &desc, opcode: ice_aqc_opc_set_port_params);
3048	if (double_vlan)
3049	cmd_flags |= ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA;
3050	cmd->cmd_flags = cpu_to_le16(cmd_flags);
3051
3052	cmd->local_fwd_mode = pi->local_fwd_mode |
3053	ICE_AQC_SET_P_PARAMS_LOCAL_FWD_MODE_VALID;
3054
3055	return ice_aq_send_cmd(hw, desc: &desc, NULL, buf_size: 0, cd);
3056	}
3057
3058	/**
3059	* ice_is_100m_speed_supported
3060	* @hw: pointer to the HW struct
3061	*
3062	* returns true if 100M speeds are supported by the device,
3063	* false otherwise.
3064	*/
3065	bool ice_is_100m_speed_supported(struct ice_hw *hw)
3066	{
3067	switch (hw->device_id) {
3068	case ICE_DEV_ID_E822C_SGMII:
3069	case ICE_DEV_ID_E822L_SGMII:
3070	case ICE_DEV_ID_E823L_1GBE:
3071	case ICE_DEV_ID_E823C_SGMII:
3072	return true;
3073	default:
3074	return false;
3075	}
3076	}
3077
3078	/**
3079	* ice_get_link_speed_based_on_phy_type - returns link speed
3080	* @phy_type_low: lower part of phy_type
3081	* @phy_type_high: higher part of phy_type
3082	*
3083	* This helper function will convert an entry in PHY type structure
3084	* [phy_type_low, phy_type_high] to its corresponding link speed.
3085	* Note: In the structure of [phy_type_low, phy_type_high], there should
3086	* be one bit set, as this function will convert one PHY type to its
3087	* speed.
3088	*
3089	* Return:
3090	* * PHY speed for recognized PHY type
3091	* * If no bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned
3092	* * If more than one bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned
3093	*/
3094	u16 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high)
3095	{
3096	u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
3097	u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
3098
3099	switch (phy_type_low) {
3100	case ICE_PHY_TYPE_LOW_100BASE_TX:
3101	case ICE_PHY_TYPE_LOW_100M_SGMII:
3102	speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB;
3103	break;
3104	case ICE_PHY_TYPE_LOW_1000BASE_T:
3105	case ICE_PHY_TYPE_LOW_1000BASE_SX:
3106	case ICE_PHY_TYPE_LOW_1000BASE_LX:
3107	case ICE_PHY_TYPE_LOW_1000BASE_KX:
3108	case ICE_PHY_TYPE_LOW_1G_SGMII:
3109	speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB;
3110	break;
3111	case ICE_PHY_TYPE_LOW_2500BASE_T:
3112	case ICE_PHY_TYPE_LOW_2500BASE_X:
3113	case ICE_PHY_TYPE_LOW_2500BASE_KX:
3114	speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB;
3115	break;
3116	case ICE_PHY_TYPE_LOW_5GBASE_T:
3117	case ICE_PHY_TYPE_LOW_5GBASE_KR:
3118	speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB;
3119	break;
3120	case ICE_PHY_TYPE_LOW_10GBASE_T:
3121	case ICE_PHY_TYPE_LOW_10G_SFI_DA:
3122	case ICE_PHY_TYPE_LOW_10GBASE_SR:
3123	case ICE_PHY_TYPE_LOW_10GBASE_LR:
3124	case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
3125	case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC:
3126	case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
3127	speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB;
3128	break;
3129	case ICE_PHY_TYPE_LOW_25GBASE_T:
3130	case ICE_PHY_TYPE_LOW_25GBASE_CR:
3131	case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
3132	case ICE_PHY_TYPE_LOW_25GBASE_CR1:
3133	case ICE_PHY_TYPE_LOW_25GBASE_SR:
3134	case ICE_PHY_TYPE_LOW_25GBASE_LR:
3135	case ICE_PHY_TYPE_LOW_25GBASE_KR:
3136	case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
3137	case ICE_PHY_TYPE_LOW_25GBASE_KR1:
3138	case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC:
3139	case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
3140	speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB;
3141	break;
3142	case ICE_PHY_TYPE_LOW_40GBASE_CR4:
3143	case ICE_PHY_TYPE_LOW_40GBASE_SR4:
3144	case ICE_PHY_TYPE_LOW_40GBASE_LR4:
3145	case ICE_PHY_TYPE_LOW_40GBASE_KR4:
3146	case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC:
3147	case ICE_PHY_TYPE_LOW_40G_XLAUI:
3148	speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB;
3149	break;
3150	case ICE_PHY_TYPE_LOW_50GBASE_CR2:
3151	case ICE_PHY_TYPE_LOW_50GBASE_SR2:
3152	case ICE_PHY_TYPE_LOW_50GBASE_LR2:
3153	case ICE_PHY_TYPE_LOW_50GBASE_KR2:
3154	case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC:
3155	case ICE_PHY_TYPE_LOW_50G_LAUI2:
3156	case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC:
3157	case ICE_PHY_TYPE_LOW_50G_AUI2:
3158	case ICE_PHY_TYPE_LOW_50GBASE_CP:
3159	case ICE_PHY_TYPE_LOW_50GBASE_SR:
3160	case ICE_PHY_TYPE_LOW_50GBASE_FR:
3161	case ICE_PHY_TYPE_LOW_50GBASE_LR:
3162	case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
3163	case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC:
3164	case ICE_PHY_TYPE_LOW_50G_AUI1:
3165	speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB;
3166	break;
3167	case ICE_PHY_TYPE_LOW_100GBASE_CR4:
3168	case ICE_PHY_TYPE_LOW_100GBASE_SR4:
3169	case ICE_PHY_TYPE_LOW_100GBASE_LR4:
3170	case ICE_PHY_TYPE_LOW_100GBASE_KR4:
3171	case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC:
3172	case ICE_PHY_TYPE_LOW_100G_CAUI4:
3173	case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC:
3174	case ICE_PHY_TYPE_LOW_100G_AUI4:
3175	case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
3176	case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
3177	case ICE_PHY_TYPE_LOW_100GBASE_CP2:
3178	case ICE_PHY_TYPE_LOW_100GBASE_SR2:
3179	case ICE_PHY_TYPE_LOW_100GBASE_DR:
3180	speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB;
3181	break;
3182	default:
3183	speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
3184	break;
3185	}
3186
3187	switch (phy_type_high) {
3188	case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
3189	case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC:
3190	case ICE_PHY_TYPE_HIGH_100G_CAUI2:
3191	case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC:
3192	case ICE_PHY_TYPE_HIGH_100G_AUI2:
3193	speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB;
3194	break;
3195	case ICE_PHY_TYPE_HIGH_200G_CR4_PAM4:
3196	case ICE_PHY_TYPE_HIGH_200G_SR4:
3197	case ICE_PHY_TYPE_HIGH_200G_FR4:
3198	case ICE_PHY_TYPE_HIGH_200G_LR4:
3199	case ICE_PHY_TYPE_HIGH_200G_DR4:
3200	case ICE_PHY_TYPE_HIGH_200G_KR4_PAM4:
3201	case ICE_PHY_TYPE_HIGH_200G_AUI4_AOC_ACC:
3202	case ICE_PHY_TYPE_HIGH_200G_AUI4:
3203	speed_phy_type_high = ICE_AQ_LINK_SPEED_200GB;
3204	break;
3205	default:
3206	speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
3207	break;
3208	}
3209
3210	if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN &&
3211	speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
3212	return ICE_AQ_LINK_SPEED_UNKNOWN;
3213	else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
3214	speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN)
3215	return ICE_AQ_LINK_SPEED_UNKNOWN;
3216	else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
3217	speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
3218	return speed_phy_type_low;
3219	else
3220	return speed_phy_type_high;
3221	}
3222
3223	/**
3224	* ice_update_phy_type
3225	* @phy_type_low: pointer to the lower part of phy_type
3226	* @phy_type_high: pointer to the higher part of phy_type
3227	* @link_speeds_bitmap: targeted link speeds bitmap
3228	*
3229	* Note: For the link_speeds_bitmap structure, you can check it at
3230	* [ice_aqc_get_link_status->link_speed]. Caller can pass in
3231	* link_speeds_bitmap include multiple speeds.
3232	*
3233	* Each entry in this [phy_type_low, phy_type_high] structure will
3234	* present a certain link speed. This helper function will turn on bits
3235	* in [phy_type_low, phy_type_high] structure based on the value of
3236	* link_speeds_bitmap input parameter.
3237	*/
3238	void
3239	ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high,
3240	u16 link_speeds_bitmap)
3241	{
3242	u64 pt_high;
3243	u64 pt_low;
3244	int index;
3245	u16 speed;
3246
3247	/* We first check with low part of phy_type */
3248	for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) {
3249	pt_low = BIT_ULL(index);
3250	speed = ice_get_link_speed_based_on_phy_type(phy_type_low: pt_low, phy_type_high: 0);
3251
3252	if (link_speeds_bitmap & speed)
3253	*phy_type_low |= BIT_ULL(index);
3254	}
3255
3256	/* We then check with high part of phy_type */
3257	for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) {
3258	pt_high = BIT_ULL(index);
3259	speed = ice_get_link_speed_based_on_phy_type(phy_type_low: 0, phy_type_high: pt_high);
3260
3261	if (link_speeds_bitmap & speed)
3262	*phy_type_high |= BIT_ULL(index);
3263	}
3264	}
3265
3266	/**
3267	* ice_aq_set_phy_cfg
3268	* @hw: pointer to the HW struct
3269	* @pi: port info structure of the interested logical port
3270	* @cfg: structure with PHY configuration data to be set
3271	* @cd: pointer to command details structure or NULL
3272	*
3273	* Set the various PHY configuration parameters supported on the Port.
3274	* One or more of the Set PHY config parameters may be ignored in an MFP
3275	* mode as the PF may not have the privilege to set some of the PHY Config
3276	* parameters. This status will be indicated by the command response (0x0601).
3277	*/
3278	int
3279	ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi,
3280	struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd)
3281	{
3282	struct ice_aq_desc desc;
3283	int status;
3284
3285	if (!cfg)
3286	return -EINVAL;
3287
3288	/* Ensure that only valid bits of cfg->caps can be turned on. */
3289	if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) {
3290	ice_debug(hw, ICE_DBG_PHY, "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n",
3291	cfg->caps);
3292
3293	cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK;
3294	}
3295
3296	ice_fill_dflt_direct_cmd_desc(desc: &desc, opcode: ice_aqc_opc_set_phy_cfg);
3297	desc.params.set_phy.lport_num = pi->lport;
3298	desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
3299
3300	ice_debug(hw, ICE_DBG_LINK, "set phy cfg\n");
3301	ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n",
3302	(unsigned long long)le64_to_cpu(cfg->phy_type_low));
3303	ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n",
3304	(unsigned long long)le64_to_cpu(cfg->phy_type_high));
3305	ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", cfg->caps);
3306	ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n",
3307	cfg->low_power_ctrl_an);
3308	ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", cfg->eee_cap);
3309	ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", cfg->eeer_value);
3310	ice_debug(hw, ICE_DBG_LINK, " link_fec_opt = 0x%x\n",
3311	cfg->link_fec_opt);
3312
3313	status = ice_aq_send_cmd(hw, desc: &desc, buf: cfg, buf_size: sizeof(*cfg), cd);
3314	if (hw->adminq.sq_last_status == ICE_AQ_RC_EMODE)
3315	status = 0;
3316
3317	if (!status)
3318	pi->phy.curr_user_phy_cfg = *cfg;
3319
3320	return status;
3321	}
3322
3323	/**
3324	* ice_update_link_info - update status of the HW network link
3325	* @pi: port info structure of the interested logical port
3326	*/
3327	int ice_update_link_info(struct ice_port_info *pi)
3328	{
3329	struct ice_link_status *li;
3330	int status;
3331
3332	if (!pi)
3333	return -EINVAL;
3334
3335	li = &pi->phy.link_info;
3336
3337	status = ice_aq_get_link_info(pi, ena_lse: true, NULL, NULL);
3338	if (status)
3339	return status;
3340
3341	if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) {
3342	struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL;
3343
3344	pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL);
3345	if (!pcaps)
3346	return -ENOMEM;
3347
3348	status = ice_aq_get_phy_caps(pi, qual_mods: false, ICE_AQC_REPORT_TOPO_CAP_MEDIA,
3349	pcaps, NULL);
3350	}
3351
3352	return status;
3353	}
3354
3355	/**
3356	* ice_aq_get_phy_equalization - function to read serdes equaliser
3357	* value from firmware using admin queue command.
3358	* @hw: pointer to the HW struct
3359	* @data_in: represents the serdes equalization parameter requested
3360	* @op_code: represents the serdes number and flag to represent tx or rx
3361	* @serdes_num: represents the serdes number
3362	* @output: pointer to the caller-supplied buffer to return serdes equaliser
3363	*
3364	* Return: non-zero status on error and 0 on success.
3365	*/
3366	int ice_aq_get_phy_equalization(struct ice_hw *hw, u16 data_in, u16 op_code,
3367	u8 serdes_num, int *output)
3368	{
3369	struct ice_aqc_dnl_call_command *cmd;
3370	struct ice_aqc_dnl_call buf = {};
3371	struct ice_aq_desc desc;
3372	int err;
3373
3374	buf.sto.txrx_equa_reqs.data_in = cpu_to_le16(data_in);
3375	buf.sto.txrx_equa_reqs.op_code_serdes_sel =
3376	cpu_to_le16(op_code | (serdes_num & 0xF));
3377	cmd = &desc.params.dnl_call;
3378	ice_fill_dflt_direct_cmd_desc(desc: &desc, opcode: ice_aqc_opc_dnl_call);
3379	desc.flags |= cpu_to_le16(ICE_AQ_FLAG_BUF |
3380	ICE_AQ_FLAG_RD |
3381	ICE_AQ_FLAG_SI);
3382	desc.datalen = cpu_to_le16(sizeof(struct ice_aqc_dnl_call));
3383	cmd->activity_id = cpu_to_le16(ICE_AQC_ACT_ID_DNL);
3384
3385	err = ice_aq_send_cmd(hw, desc: &desc, buf: &buf, buf_size: sizeof(struct ice_aqc_dnl_call),
3386	NULL);
3387	*output = err ? 0 : buf.sto.txrx_equa_resp.val;
3388
3389	return err;
3390	}
3391
3392	#define FEC_REG_PORT(port) { \
3393	FEC_CORR_LOW_REG_PORT##port, \
3394	FEC_CORR_HIGH_REG_PORT##port, \
3395	FEC_UNCORR_LOW_REG_PORT##port, \
3396	FEC_UNCORR_HIGH_REG_PORT##port, \
3397	}
3398
3399	static const u32 fec_reg[][ICE_FEC_MAX] = {
3400	FEC_REG_PORT(0),
3401	FEC_REG_PORT(1),
3402	FEC_REG_PORT(2),
3403	FEC_REG_PORT(3)
3404	};
3405
3406	/**
3407	* ice_aq_get_fec_stats - reads fec stats from phy
3408	* @hw: pointer to the HW struct
3409	* @pcs_quad: represents pcsquad of user input serdes
3410	* @pcs_port: represents the pcs port number part of above pcs quad
3411	* @fec_type: represents FEC stats type
3412	* @output: pointer to the caller-supplied buffer to return requested fec stats
3413	*
3414	* Return: non-zero status on error and 0 on success.
3415	*/
3416	int ice_aq_get_fec_stats(struct ice_hw *hw, u16 pcs_quad, u16 pcs_port,
3417	enum ice_fec_stats_types fec_type, u32 *output)
3418	{
3419	u16 flag = (ICE_AQ_FLAG_RD | ICE_AQ_FLAG_BUF | ICE_AQ_FLAG_SI);
3420	struct ice_sbq_msg_input msg = {};
3421	u32 receiver_id, reg_offset;
3422	int err;
3423
3424	if (pcs_port > 3)
3425	return -EINVAL;
3426
3427	reg_offset = fec_reg[pcs_port][fec_type];
3428
3429	if (pcs_quad == 0)
3430	receiver_id = FEC_RECEIVER_ID_PCS0;
3431	else if (pcs_quad == 1)
3432	receiver_id = FEC_RECEIVER_ID_PCS1;
3433	else
3434	return -EINVAL;
3435
3436	msg.msg_addr_low = lower_16_bits(reg_offset);
3437	msg.msg_addr_high = receiver_id;
3438	msg.opcode = ice_sbq_msg_rd;
3439	msg.dest_dev = ice_sbq_dev_phy_0;
3440
3441	err = ice_sbq_rw_reg(hw, in: &msg, flags: flag);
3442	if (err)
3443	return err;
3444
3445	*output = msg.data;
3446	return 0;
3447	}
3448
3449	/**
3450	* ice_cache_phy_user_req
3451	* @pi: port information structure
3452	* @cache_data: PHY logging data
3453	* @cache_mode: PHY logging mode
3454	*
3455	* Log the user request on (FC, FEC, SPEED) for later use.
3456	*/
3457	static void
3458	ice_cache_phy_user_req(struct ice_port_info *pi,
3459	struct ice_phy_cache_mode_data cache_data,
3460	enum ice_phy_cache_mode cache_mode)
3461	{
3462	if (!pi)
3463	return;
3464
3465	switch (cache_mode) {
3466	case ICE_FC_MODE:
3467	pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req;
3468	break;
3469	case ICE_SPEED_MODE:
3470	pi->phy.curr_user_speed_req =
3471	cache_data.data.curr_user_speed_req;
3472	break;
3473	case ICE_FEC_MODE:
3474	pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req;
3475	break;
3476	default:
3477	break;
3478	}
3479	}
3480
3481	/**
3482	* ice_caps_to_fc_mode
3483	* @caps: PHY capabilities
3484	*
3485	* Convert PHY FC capabilities to ice FC mode
3486	*/
3487	enum ice_fc_mode ice_caps_to_fc_mode(u8 caps)
3488	{
3489	if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE &&
3490	caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)
3491	return ICE_FC_FULL;
3492
3493	if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE)
3494	return ICE_FC_TX_PAUSE;
3495
3496	if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)
3497	return ICE_FC_RX_PAUSE;
3498
3499	return ICE_FC_NONE;
3500	}
3501
3502	/**
3503	* ice_caps_to_fec_mode
3504	* @caps: PHY capabilities
3505	* @fec_options: Link FEC options
3506	*
3507	* Convert PHY FEC capabilities to ice FEC mode
3508	*/
3509	enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options)
3510	{
3511	if (caps & ICE_AQC_PHY_EN_AUTO_FEC)
3512	return ICE_FEC_AUTO;
3513
3514	if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
3515	ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
3516	ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN |
3517	ICE_AQC_PHY_FEC_25G_KR_REQ))
3518	return ICE_FEC_BASER;
3519
3520	if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ |
3521	ICE_AQC_PHY_FEC_25G_RS_544_REQ |
3522	ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN))
3523	return ICE_FEC_RS;
3524
3525	return ICE_FEC_NONE;
3526	}
3527
3528	/**
3529	* ice_cfg_phy_fc - Configure PHY FC data based on FC mode
3530	* @pi: port information structure
3531	* @cfg: PHY configuration data to set FC mode
3532	* @req_mode: FC mode to configure
3533	*/
3534	int
3535	ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,
3536	enum ice_fc_mode req_mode)
3537	{
3538	struct ice_phy_cache_mode_data cache_data;
3539	u8 pause_mask = 0x0;
3540
3541	if (!pi || !cfg)
3542	return -EINVAL;
3543
3544	switch (req_mode) {
3545	case ICE_FC_FULL:
3546	pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
3547	pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
3548	break;
3549	case ICE_FC_RX_PAUSE:
3550	pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
3551	break;
3552	case ICE_FC_TX_PAUSE:
3553	pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
3554	break;
3555	default:
3556	break;
3557	}
3558
3559	/* clear the old pause settings */
3560	cfg->caps &= ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE |
3561	ICE_AQC_PHY_EN_RX_LINK_PAUSE);
3562
3563	/* set the new capabilities */
3564	cfg->caps |= pause_mask;
3565
3566	/* Cache user FC request */
3567	cache_data.data.curr_user_fc_req = req_mode;
3568	ice_cache_phy_user_req(pi, cache_data, cache_mode: ICE_FC_MODE);
3569
3570	return 0;
3571	}
3572
3573	/**
3574	* ice_set_fc
3575	* @pi: port information structure
3576	* @aq_failures: pointer to status code, specific to ice_set_fc routine
3577	* @ena_auto_link_update: enable automatic link update
3578	*
3579	* Set the requested flow control mode.
3580	*/
3581	int
3582	ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update)
3583	{
3584	struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL;
3585	struct ice_aqc_set_phy_cfg_data cfg = { 0 };
3586	struct ice_hw *hw;
3587	int status;
3588
3589	if (!pi || !aq_failures)
3590	return -EINVAL;
3591
3592	*aq_failures = 0;
3593	hw = pi->hw;
3594
3595	pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL);
3596	if (!pcaps)
3597	return -ENOMEM;
3598
3599	/* Get the current PHY config */
3600	status = ice_aq_get_phy_caps(pi, qual_mods: false, ICE_AQC_REPORT_ACTIVE_CFG,
3601	pcaps, NULL);
3602	if (status) {
3603	*aq_failures = ICE_SET_FC_AQ_FAIL_GET;
3604	goto out;
3605	}
3606
3607	ice_copy_phy_caps_to_cfg(pi, caps: pcaps, cfg: &cfg);
3608
3609	/* Configure the set PHY data */
3610	status = ice_cfg_phy_fc(pi, cfg: &cfg, req_mode: pi->fc.req_mode);
3611	if (status)
3612	goto out;
3613
3614	/* If the capabilities have changed, then set the new config */
3615	if (cfg.caps != pcaps->caps) {
3616	int retry_count, retry_max = 10;
3617
3618	/* Auto restart link so settings take effect */
3619	if (ena_auto_link_update)
3620	cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
3621
3622	status = ice_aq_set_phy_cfg(hw, pi, cfg: &cfg, NULL);
3623	if (status) {
3624	*aq_failures = ICE_SET_FC_AQ_FAIL_SET;
3625	goto out;
3626	}
3627
3628	/* Update the link info
3629	* It sometimes takes a really long time for link to
3630	* come back from the atomic reset. Thus, we wait a
3631	* little bit.
3632	*/
3633	for (retry_count = 0; retry_count < retry_max; retry_count++) {
3634	status = ice_update_link_info(pi);
3635
3636	if (!status)
3637	break;
3638
3639	mdelay(100);
3640	}
3641
3642	if (status)
3643	*aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE;
3644	}
3645
3646	out:
3647	return status;
3648	}
3649
3650	/**
3651	* ice_phy_caps_equals_cfg
3652	* @phy_caps: PHY capabilities
3653	* @phy_cfg: PHY configuration
3654	*
3655	* Helper function to determine if PHY capabilities matches PHY
3656	* configuration
3657	*/
3658	bool
3659	ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps,
3660	struct ice_aqc_set_phy_cfg_data *phy_cfg)
3661	{
3662	u8 caps_mask, cfg_mask;
3663
3664	if (!phy_caps || !phy_cfg)
3665	return false;
3666
3667	/* These bits are not common between capabilities and configuration.
3668	* Do not use them to determine equality.
3669	*/
3670	caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE |
3671	ICE_AQC_GET_PHY_EN_MOD_QUAL);
3672	cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
3673
3674	if (phy_caps->phy_type_low != phy_cfg->phy_type_low ||
3675	phy_caps->phy_type_high != phy_cfg->phy_type_high ||
3676	((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) ||
3677	phy_caps->low_power_ctrl_an != phy_cfg->low_power_ctrl_an ||
3678	phy_caps->eee_cap != phy_cfg->eee_cap ||
3679	phy_caps->eeer_value != phy_cfg->eeer_value ||
3680	phy_caps->link_fec_options != phy_cfg->link_fec_opt)
3681	return false;
3682
3683	return true;
3684	}
3685
3686	/**
3687	* ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data
3688	* @pi: port information structure
3689	* @caps: PHY ability structure to copy date from
3690	* @cfg: PHY configuration structure to copy data to
3691	*
3692	* Helper function to copy AQC PHY get ability data to PHY set configuration
3693	* data structure
3694	*/
3695	void
3696	ice_copy_phy_caps_to_cfg(struct ice_port_info *pi,
3697	struct ice_aqc_get_phy_caps_data *caps,
3698	struct ice_aqc_set_phy_cfg_data *cfg)
3699	{
3700	if (!pi || !caps || !cfg)
3701	return;
3702
3703	memset(cfg, 0, sizeof(*cfg));
3704	cfg->phy_type_low = caps->phy_type_low;
3705	cfg->phy_type_high = caps->phy_type_high;
3706	cfg->caps = caps->caps;
3707	cfg->low_power_ctrl_an = caps->low_power_ctrl_an;
3708	cfg->eee_cap = caps->eee_cap;
3709	cfg->eeer_value = caps->eeer_value;
3710	cfg->link_fec_opt = caps->link_fec_options;
3711	cfg->module_compliance_enforcement =
3712	caps->module_compliance_enforcement;
3713	}
3714
3715	/**
3716	* ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode
3717	* @pi: port information structure
3718	* @cfg: PHY configuration data to set FEC mode
3719	* @fec: FEC mode to configure
3720	*/
3721	int
3722	ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,
3723	enum ice_fec_mode fec)
3724	{
3725	struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL;
3726	struct ice_hw *hw;
3727	int status;
3728
3729	if (!pi || !cfg)
3730	return -EINVAL;
3731
3732	hw = pi->hw;
3733
3734	pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL);
3735	if (!pcaps)
3736	return -ENOMEM;
3737
3738	status = ice_aq_get_phy_caps(pi, qual_mods: false,
3739	report_mode: (ice_fw_supports_report_dflt_cfg(hw) ?
3740	ICE_AQC_REPORT_DFLT_CFG :
3741	ICE_AQC_REPORT_TOPO_CAP_MEDIA), pcaps, NULL);
3742	if (status)
3743	goto out;
3744
3745	cfg->caps |= pcaps->caps & ICE_AQC_PHY_EN_AUTO_FEC;
3746	cfg->link_fec_opt = pcaps->link_fec_options;
3747
3748	switch (fec) {
3749	case ICE_FEC_BASER:
3750	/* Clear RS bits, and AND BASE-R ability
3751	* bits and OR request bits.
3752	*/
3753	cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
3754	ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN;
3755	cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
3756	ICE_AQC_PHY_FEC_25G_KR_REQ;
3757	break;
3758	case ICE_FEC_RS:
3759	/* Clear BASE-R bits, and AND RS ability
3760	* bits and OR request bits.
3761	*/
3762	cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN;
3763	cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ |
3764	ICE_AQC_PHY_FEC_25G_RS_544_REQ;
3765	break;
3766	case ICE_FEC_NONE:
3767	/* Clear all FEC option bits. */
3768	cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK;
3769	break;
3770	case ICE_FEC_AUTO:
3771	/* AND auto FEC bit, and all caps bits. */
3772	cfg->caps &= ICE_AQC_PHY_CAPS_MASK;
3773	cfg->link_fec_opt |= pcaps->link_fec_options;
3774	break;
3775	default:
3776	status = -EINVAL;
3777	break;
3778	}
3779
3780	if (fec == ICE_FEC_AUTO && ice_fw_supports_link_override(hw) &&
3781	!ice_fw_supports_report_dflt_cfg(hw)) {
3782	struct ice_link_default_override_tlv tlv = { 0 };
3783
3784	status = ice_get_link_default_override(ldo: &tlv, pi);
3785	if (status)
3786	goto out;
3787
3788	if (!(tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) &&
3789	(tlv.options & ICE_LINK_OVERRIDE_EN))
3790	cfg->link_fec_opt = tlv.fec_options;
3791	}
3792
3793	out:
3794	return status;
3795	}
3796
3797	/**
3798	* ice_get_link_status - get status of the HW network link
3799	* @pi: port information structure
3800	* @link_up: pointer to bool (true/false = linkup/linkdown)
3801	*
3802	* Variable link_up is true if link is up, false if link is down.
3803	* The variable link_up is invalid if status is non zero. As a
3804	* result of this call, link status reporting becomes enabled
3805	*/
3806	int ice_get_link_status(struct ice_port_info *pi, bool *link_up)
3807	{
3808	struct ice_phy_info *phy_info;
3809	int status = 0;
3810
3811	if (!pi || !link_up)
3812	return -EINVAL;
3813
3814	phy_info = &pi->phy;
3815
3816	if (phy_info->get_link_info) {
3817	status = ice_update_link_info(pi);
3818
3819	if (status)
3820	ice_debug(pi->hw, ICE_DBG_LINK, "get link status error, status = %d\n",
3821	status);
3822	}
3823
3824	*link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP;
3825
3826	return status;
3827	}
3828
3829	/**
3830	* ice_aq_set_link_restart_an
3831	* @pi: pointer to the port information structure
3832	* @ena_link: if true: enable link, if false: disable link
3833	* @cd: pointer to command details structure or NULL
3834	*
3835	* Sets up the link and restarts the Auto-Negotiation over the link.
3836	*/
3837	int
3838	ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
3839	struct ice_sq_cd *cd)
3840	{
3841	struct ice_aqc_restart_an *cmd;
3842	struct ice_aq_desc desc;
3843
3844	cmd = &desc.params.restart_an;
3845
3846	ice_fill_dflt_direct_cmd_desc(desc: &desc, opcode: ice_aqc_opc_restart_an);
3847
3848	cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART;
3849	cmd->lport_num = pi->lport;
3850	if (ena_link)
3851	cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE;
3852	else
3853	cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE;
3854
3855	return ice_aq_send_cmd(hw: pi->hw, desc: &desc, NULL, buf_size: 0, cd);
3856	}
3857
3858	/**
3859	* ice_aq_set_event_mask
3860	* @hw: pointer to the HW struct
3861	* @port_num: port number of the physical function
3862	* @mask: event mask to be set
3863	* @cd: pointer to command details structure or NULL
3864	*
3865	* Set event mask (0x0613)
3866	*/
3867	int
3868	ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask,
3869	struct ice_sq_cd *cd)
3870	{
3871	struct ice_aqc_set_event_mask *cmd;
3872	struct ice_aq_desc desc;
3873
3874	cmd = &desc.params.set_event_mask;
3875
3876	ice_fill_dflt_direct_cmd_desc(desc: &desc, opcode: ice_aqc_opc_set_event_mask);
3877
3878	cmd->lport_num = port_num;
3879
3880	cmd->event_mask = cpu_to_le16(mask);
3881	return ice_aq_send_cmd(hw, desc: &desc, NULL, buf_size: 0, cd);
3882	}
3883
3884	/**
3885	* ice_aq_set_mac_loopback
3886	* @hw: pointer to the HW struct
3887	* @ena_lpbk: Enable or Disable loopback
3888	* @cd: pointer to command details structure or NULL
3889	*
3890	* Enable/disable loopback on a given port
3891	*/
3892	int
3893	ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd)
3894	{
3895	struct ice_aqc_set_mac_lb *cmd;
3896	struct ice_aq_desc desc;
3897
3898	cmd = &desc.params.set_mac_lb;
3899
3900	ice_fill_dflt_direct_cmd_desc(desc: &desc, opcode: ice_aqc_opc_set_mac_lb);
3901	if (ena_lpbk)
3902	cmd->lb_mode = ICE_AQ_MAC_LB_EN;
3903
3904	return ice_aq_send_cmd(hw, desc: &desc, NULL, buf_size: 0, cd);
3905	}
3906
3907	/**
3908	* ice_aq_set_port_id_led
3909	* @pi: pointer to the port information
3910	* @is_orig_mode: is this LED set to original mode (by the net-list)
3911	* @cd: pointer to command details structure or NULL
3912	*
3913	* Set LED value for the given port (0x06e9)
3914	*/
3915	int
3916	ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,
3917	struct ice_sq_cd *cd)
3918	{
3919	struct ice_aqc_set_port_id_led *cmd;
3920	struct ice_hw *hw = pi->hw;
3921	struct ice_aq_desc desc;
3922
3923	cmd = &desc.params.set_port_id_led;
3924
3925	ice_fill_dflt_direct_cmd_desc(desc: &desc, opcode: ice_aqc_opc_set_port_id_led);
3926
3927	if (is_orig_mode)
3928	cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG;
3929	else
3930	cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK;
3931
3932	return ice_aq_send_cmd(hw, desc: &desc, NULL, buf_size: 0, cd);
3933	}
3934
3935	/**
3936	* ice_aq_get_port_options
3937	* @hw: pointer to the HW struct
3938	* @options: buffer for the resultant port options
3939	* @option_count: input - size of the buffer in port options structures,
3940	* output - number of returned port options
3941	* @lport: logical port to call the command with (optional)
3942	* @lport_valid: when false, FW uses port owned by the PF instead of lport,
3943	* when PF owns more than 1 port it must be true
3944	* @active_option_idx: index of active port option in returned buffer
3945	* @active_option_valid: active option in returned buffer is valid
3946	* @pending_option_idx: index of pending port option in returned buffer
3947	* @pending_option_valid: pending option in returned buffer is valid
3948	*
3949	* Calls Get Port Options AQC (0x06ea) and verifies result.
3950	*/
3951	int
3952	ice_aq_get_port_options(struct ice_hw *hw,
3953	struct ice_aqc_get_port_options_elem *options,
3954	u8 *option_count, u8 lport, bool lport_valid,
3955	u8 *active_option_idx, bool *active_option_valid,
3956	u8 *pending_option_idx, bool *pending_option_valid)
3957	{
3958	struct ice_aqc_get_port_options *cmd;
3959	struct ice_aq_desc desc;
3960	int status;
3961	u8 i;
3962
3963	/* options buffer shall be able to hold max returned options */
3964	if (*option_count < ICE_AQC_PORT_OPT_COUNT_M)
3965	return -EINVAL;
3966
3967	cmd = &desc.params.get_port_options;
3968	ice_fill_dflt_direct_cmd_desc(desc: &desc, opcode: ice_aqc_opc_get_port_options);
3969
3970	if (lport_valid)
3971	cmd->lport_num = lport;
3972	cmd->lport_num_valid = lport_valid;
3973
3974	status = ice_aq_send_cmd(hw, desc: &desc, buf: options,
3975	buf_size: *option_count * sizeof(*options), NULL);
3976	if (status)
3977	return status;
3978
3979	/* verify direct FW response & set output parameters */
3980	*option_count = FIELD_GET(ICE_AQC_PORT_OPT_COUNT_M,
3981	cmd->port_options_count);
3982	ice_debug(hw, ICE_DBG_PHY, "options: %x\n", *option_count);
3983	*active_option_valid = FIELD_GET(ICE_AQC_PORT_OPT_VALID,
3984	cmd->port_options);
3985	if (*active_option_valid) {
3986	*active_option_idx = FIELD_GET(ICE_AQC_PORT_OPT_ACTIVE_M,
3987	cmd->port_options);
3988	if (*active_option_idx > (*option_count - 1))
3989	return -EIO;
3990	ice_debug(hw, ICE_DBG_PHY, "active idx: %x\n",
3991	*active_option_idx);
3992	}
3993
3994	*pending_option_valid = FIELD_GET(ICE_AQC_PENDING_PORT_OPT_VALID,
3995	cmd->pending_port_option_status);
3996	if (*pending_option_valid) {
3997	*pending_option_idx = FIELD_GET(ICE_AQC_PENDING_PORT_OPT_IDX_M,
3998	cmd->pending_port_option_status);
3999	if (*pending_option_idx > (*option_count - 1))
4000	return -EIO;
4001	ice_debug(hw, ICE_DBG_PHY, "pending idx: %x\n",
4002	*pending_option_idx);
4003	}
4004
4005	/* mask output options fields */
4006	for (i = 0; i < *option_count; i++) {
4007	options[i].pmd = FIELD_GET(ICE_AQC_PORT_OPT_PMD_COUNT_M,
4008	options[i].pmd);
4009	options[i].max_lane_speed = FIELD_GET(ICE_AQC_PORT_OPT_MAX_LANE_M,
4010	options[i].max_lane_speed);
4011	ice_debug(hw, ICE_DBG_PHY, "pmds: %x max speed: %x\n",
4012	options[i].pmd, options[i].max_lane_speed);
4013	}
4014
4015	return 0;
4016	}
4017
4018	/**
4019	* ice_aq_set_port_option
4020	* @hw: pointer to the HW struct
4021	* @lport: logical port to call the command with
4022	* @lport_valid: when false, FW uses port owned by the PF instead of lport,
4023	* when PF owns more than 1 port it must be true
4024	* @new_option: new port option to be written
4025	*
4026	* Calls Set Port Options AQC (0x06eb).
4027	*/
4028	int
4029	ice_aq_set_port_option(struct ice_hw *hw, u8 lport, u8 lport_valid,
4030	u8 new_option)
4031	{
4032	struct ice_aqc_set_port_option *cmd;
4033	struct ice_aq_desc desc;
4034
4035	if (new_option > ICE_AQC_PORT_OPT_COUNT_M)
4036	return -EINVAL;
4037
4038	cmd = &desc.params.set_port_option;
4039	ice_fill_dflt_direct_cmd_desc(desc: &desc, opcode: ice_aqc_opc_set_port_option);
4040
4041	if (lport_valid)
4042	cmd->lport_num = lport;
4043
4044	cmd->lport_num_valid = lport_valid;
4045	cmd->selected_port_option = new_option;
4046
4047	return ice_aq_send_cmd(hw, desc: &desc, NULL, buf_size: 0, NULL);
4048	}
4049
4050	/**
4051	* ice_get_phy_lane_number - Get PHY lane number for current adapter
4052	* @hw: pointer to the hw struct
4053	*
4054	* Return: PHY lane number on success, negative error code otherwise.
4055	*/
4056	int ice_get_phy_lane_number(struct ice_hw *hw)
4057	{
4058	struct ice_aqc_get_port_options_elem *options;
4059	unsigned int lport = 0;
4060	unsigned int lane;
4061	int err;
4062
4063	options = kcalloc(ICE_AQC_PORT_OPT_MAX, sizeof(*options), GFP_KERNEL);
4064	if (!options)
4065	return -ENOMEM;
4066
4067	for (lane = 0; lane < ICE_MAX_PORT_PER_PCI_DEV; lane++) {
4068	u8 options_count = ICE_AQC_PORT_OPT_MAX;
4069	u8 speed, active_idx, pending_idx;
4070	bool active_valid, pending_valid;
4071
4072	err = ice_aq_get_port_options(hw, options, option_count: &options_count, lport: lane,
4073	lport_valid: true, active_option_idx: &active_idx, active_option_valid: &active_valid,
4074	pending_option_idx: &pending_idx, pending_option_valid: &pending_valid);
4075	if (err)
4076	goto err;
4077
4078	if (!active_valid)
4079	continue;
4080
4081	speed = options[active_idx].max_lane_speed;
4082	/* If we don't get speed for this lane, it's unoccupied */
4083	if (speed > ICE_AQC_PORT_OPT_MAX_LANE_200G)
4084	continue;
4085
4086	if (hw->pf_id == lport) {
4087	if (hw->mac_type == ICE_MAC_GENERIC_3K_E825 &&
4088	ice_is_dual(hw) && !ice_is_primary(hw))
4089	lane += ICE_PORTS_PER_QUAD;
4090	kfree(objp: options);
4091	return lane;
4092	}
4093	lport++;
4094	}
4095
4096	/* PHY lane not found */
4097	err = -ENXIO;
4098	err:
4099	kfree(objp: options);
4100	return err;
4101	}
4102
4103	/**
4104	* ice_aq_sff_eeprom
4105	* @hw: pointer to the HW struct
4106	* @lport: bits [7:0] = logical port, bit [8] = logical port valid
4107	* @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default)
4108	* @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding.
4109	* @page: QSFP page
4110	* @set_page: set or ignore the page
4111	* @data: pointer to data buffer to be read/written to the I2C device.
4112	* @length: 1-16 for read, 1 for write.
4113	* @write: 0 read, 1 for write.
4114	* @cd: pointer to command details structure or NULL
4115	*
4116	* Read/Write SFF EEPROM (0x06EE)
4117	*/
4118	int
4119	ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr,
4120	u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length,
4121	bool write, struct ice_sq_cd *cd)
4122	{
4123	struct ice_aqc_sff_eeprom *cmd;
4124	struct ice_aq_desc desc;
4125	u16 i2c_bus_addr;
4126	int status;
4127
4128	if (!data || (mem_addr & 0xff00))
4129	return -EINVAL;
4130
4131	ice_fill_dflt_direct_cmd_desc(desc: &desc, opcode: ice_aqc_opc_sff_eeprom);
4132	cmd = &desc.params.read_write_sff_param;
4133	desc.flags = cpu_to_le16(ICE_AQ_FLAG_RD);
4134	cmd->lport_num = (u8)(lport & 0xff);
4135	cmd->lport_num_valid = (u8)((lport >> 8) & 0x01);
4136	i2c_bus_addr = FIELD_PREP(ICE_AQC_SFF_I2CBUS_7BIT_M, bus_addr >> 1) |
4137	FIELD_PREP(ICE_AQC_SFF_SET_EEPROM_PAGE_M, set_page);
4138	if (write)
4139	i2c_bus_addr |= ICE_AQC_SFF_IS_WRITE;
4140	cmd->i2c_bus_addr = cpu_to_le16(i2c_bus_addr);
4141	cmd->i2c_mem_addr = cpu_to_le16(mem_addr & 0xff);
4142	cmd->eeprom_page = le16_encode_bits(v: page, ICE_AQC_SFF_EEPROM_PAGE_M);
4143
4144	status = ice_aq_send_cmd(hw, desc: &desc, buf: data, buf_size: length, cd);
4145	return status;
4146	}
4147
4148	static enum ice_lut_size ice_lut_type_to_size(enum ice_lut_type type)
4149	{
4150	switch (type) {
4151	case ICE_LUT_VSI:
4152	return ICE_LUT_VSI_SIZE;
4153	case ICE_LUT_GLOBAL:
4154	return ICE_LUT_GLOBAL_SIZE;
4155	case ICE_LUT_PF:
4156	return ICE_LUT_PF_SIZE;
4157	}
4158	WARN_ONCE(1, "incorrect type passed");
4159	return ICE_LUT_VSI_SIZE;
4160	}
4161
4162	static enum ice_aqc_lut_flags ice_lut_size_to_flag(enum ice_lut_size size)
4163	{
4164	switch (size) {
4165	case ICE_LUT_VSI_SIZE:
4166	return ICE_AQC_LUT_SIZE_SMALL;
4167	case ICE_LUT_GLOBAL_SIZE:
4168	return ICE_AQC_LUT_SIZE_512;
4169	case ICE_LUT_PF_SIZE:
4170	return ICE_AQC_LUT_SIZE_2K;
4171	}
4172	WARN_ONCE(1, "incorrect size passed");
4173	return 0;
4174	}
4175
4176	/**
4177	* __ice_aq_get_set_rss_lut
4178	* @hw: pointer to the hardware structure
4179	* @params: RSS LUT parameters
4180	* @set: set true to set the table, false to get the table
4181	*
4182	* Internal function to get (0x0B05) or set (0x0B03) RSS look up table
4183	*/
4184	static int
4185	__ice_aq_get_set_rss_lut(struct ice_hw *hw,
4186	struct ice_aq_get_set_rss_lut_params *params, bool set)
4187	{
4188	u16 opcode, vsi_id, vsi_handle = params->vsi_handle, glob_lut_idx = 0;
4189	enum ice_lut_type lut_type = params->lut_type;
4190	struct ice_aqc_get_set_rss_lut *desc_params;
4191	enum ice_aqc_lut_flags flags;
4192	enum ice_lut_size lut_size;
4193	struct ice_aq_desc desc;
4194	u8 *lut = params->lut;
4195
4196
4197	if (!lut || !ice_is_vsi_valid(hw, vsi_handle))
4198	return -EINVAL;
4199
4200	lut_size = ice_lut_type_to_size(type: lut_type);
4201	if (lut_size > params->lut_size)
4202	return -EINVAL;
4203	else if (set && lut_size != params->lut_size)
4204	return -EINVAL;
4205
4206	opcode = set ? ice_aqc_opc_set_rss_lut : ice_aqc_opc_get_rss_lut;
4207	ice_fill_dflt_direct_cmd_desc(desc: &desc, opcode);
4208	if (set)
4209	desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
4210
4211	desc_params = &desc.params.get_set_rss_lut;
4212	vsi_id = ice_get_hw_vsi_num(hw, vsi_handle);
4213	desc_params->vsi_id = cpu_to_le16(vsi_id | ICE_AQC_RSS_VSI_VALID);
4214
4215	if (lut_type == ICE_LUT_GLOBAL)
4216	glob_lut_idx = FIELD_PREP(ICE_AQC_LUT_GLOBAL_IDX,
4217	params->global_lut_id);
4218
4219	flags = lut_type | glob_lut_idx | ice_lut_size_to_flag(size: lut_size);
4220	desc_params->flags = cpu_to_le16(flags);
4221
4222	return ice_aq_send_cmd(hw, desc: &desc, buf: lut, buf_size: lut_size, NULL);
4223	}
4224
4225	/**
4226	* ice_aq_get_rss_lut
4227	* @hw: pointer to the hardware structure
4228	* @get_params: RSS LUT parameters used to specify which RSS LUT to get
4229	*
4230	* get the RSS lookup table, PF or VSI type
4231	*/
4232	int
4233	ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params)
4234	{
4235	return __ice_aq_get_set_rss_lut(hw, params: get_params, set: false);
4236	}
4237
4238	/**
4239	* ice_aq_set_rss_lut
4240	* @hw: pointer to the hardware structure
4241	* @set_params: RSS LUT parameters used to specify how to set the RSS LUT
4242	*
4243	* set the RSS lookup table, PF or VSI type
4244	*/
4245	int
4246	ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params)
4247	{
4248	return __ice_aq_get_set_rss_lut(hw, params: set_params, set: true);
4249	}
4250
4251	/**
4252	* __ice_aq_get_set_rss_key
4253	* @hw: pointer to the HW struct
4254	* @vsi_id: VSI FW index
4255	* @key: pointer to key info struct
4256	* @set: set true to set the key, false to get the key
4257	*
4258	* get (0x0B04) or set (0x0B02) the RSS key per VSI
4259	*/
4260	static int
4261	__ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id,
4262	struct ice_aqc_get_set_rss_keys *key, bool set)
4263	{
4264	struct ice_aqc_get_set_rss_key *desc_params;
4265	u16 key_size = sizeof(*key);
4266	struct ice_aq_desc desc;
4267
4268	if (set) {
4269	ice_fill_dflt_direct_cmd_desc(desc: &desc, opcode: ice_aqc_opc_set_rss_key);
4270	desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
4271	} else {
4272	ice_fill_dflt_direct_cmd_desc(desc: &desc, opcode: ice_aqc_opc_get_rss_key);
4273	}
4274
4275	desc_params = &desc.params.get_set_rss_key;
4276	desc_params->vsi_id = cpu_to_le16(vsi_id | ICE_AQC_RSS_VSI_VALID);
4277
4278	return ice_aq_send_cmd(hw, desc: &desc, buf: key, buf_size: key_size, NULL);
4279	}
4280
4281	/**
4282	* ice_aq_get_rss_key
4283	* @hw: pointer to the HW struct
4284	* @vsi_handle: software VSI handle
4285	* @key: pointer to key info struct
4286	*
4287	* get the RSS key per VSI
4288	*/
4289	int
4290	ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle,
4291	struct ice_aqc_get_set_rss_keys *key)
4292	{
4293	if (!ice_is_vsi_valid(hw, vsi_handle) || !key)
4294	return -EINVAL;
4295
4296	return __ice_aq_get_set_rss_key(hw, vsi_id: ice_get_hw_vsi_num(hw, vsi_handle),
4297	key, set: false);
4298	}
4299
4300	/**
4301	* ice_aq_set_rss_key
4302	* @hw: pointer to the HW struct
4303	* @vsi_handle: software VSI handle
4304	* @keys: pointer to key info struct
4305	*
4306	* set the RSS key per VSI
4307	*/
4308	int
4309	ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle,
4310	struct ice_aqc_get_set_rss_keys *keys)
4311	{
4312	if (!ice_is_vsi_valid(hw, vsi_handle) || !keys)
4313	return -EINVAL;
4314
4315	return __ice_aq_get_set_rss_key(hw, vsi_id: ice_get_hw_vsi_num(hw, vsi_handle),
4316	key: keys, set: true);
4317	}
4318
4319	/**
4320	* ice_aq_add_lan_txq
4321	* @hw: pointer to the hardware structure
4322	* @num_qgrps: Number of added queue groups
4323	* @qg_list: list of queue groups to be added
4324	* @buf_size: size of buffer for indirect command
4325	* @cd: pointer to command details structure or NULL
4326	*
4327	* Add Tx LAN queue (0x0C30)
4328	*
4329	* NOTE:
4330	* Prior to calling add Tx LAN queue:
4331	* Initialize the following as part of the Tx queue context:
4332	* Completion queue ID if the queue uses Completion queue, Quanta profile,
4333	* Cache profile and Packet shaper profile.
4334	*
4335	* After add Tx LAN queue AQ command is completed:
4336	* Interrupts should be associated with specific queues,
4337	* Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue
4338	* flow.
4339	*/
4340	static int
4341	ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps,
4342	struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size,
4343	struct ice_sq_cd *cd)
4344	{
4345	struct ice_aqc_add_tx_qgrp *list;
4346	struct ice_aqc_add_txqs *cmd;
4347	struct ice_aq_desc desc;
4348	u16 i, sum_size = 0;
4349
4350	cmd = &desc.params.add_txqs;
4351
4352	ice_fill_dflt_direct_cmd_desc(desc: &desc, opcode: ice_aqc_opc_add_txqs);
4353
4354	if (!qg_list)
4355	return -EINVAL;
4356
4357	if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
4358	return -EINVAL;
4359
4360	for (i = 0, list = qg_list; i < num_qgrps; i++) {
4361	sum_size += struct_size(list, txqs, list->num_txqs);
4362	list = (struct ice_aqc_add_tx_qgrp *)(list->txqs +
4363	list->num_txqs);
4364	}
4365
4366	if (buf_size != sum_size)
4367	return -EINVAL;
4368
4369	desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
4370
4371	cmd->num_qgrps = num_qgrps;
4372
4373	return ice_aq_send_cmd(hw, desc: &desc, buf: qg_list, buf_size, cd);
4374	}
4375
4376	/**
4377	* ice_aq_dis_lan_txq
4378	* @hw: pointer to the hardware structure
4379	* @num_qgrps: number of groups in the list
4380	* @qg_list: the list of groups to disable
4381	* @buf_size: the total size of the qg_list buffer in bytes
4382	* @rst_src: if called due to reset, specifies the reset source
4383	* @vmvf_num: the relative VM or VF number that is undergoing the reset
4384	* @cd: pointer to command details structure or NULL
4385	*
4386	* Disable LAN Tx queue (0x0C31)
4387	*/
4388	static int
4389	ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps,
4390	struct ice_aqc_dis_txq_item *qg_list, u16 buf_size,
4391	enum ice_disq_rst_src rst_src, u16 vmvf_num,
4392	struct ice_sq_cd *cd)
4393	{
4394	struct ice_aqc_dis_txq_item *item;
4395	struct ice_aqc_dis_txqs *cmd;
4396	struct ice_aq_desc desc;
4397	u16 vmvf_and_timeout;
4398	u16 i, sz = 0;
4399	int status;
4400
4401	cmd = &desc.params.dis_txqs;
4402	ice_fill_dflt_direct_cmd_desc(desc: &desc, opcode: ice_aqc_opc_dis_txqs);
4403
4404	/* qg_list can be NULL only in VM/VF reset flow */
4405	if (!qg_list && !rst_src)
4406	return -EINVAL;
4407
4408	if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
4409	return -EINVAL;
4410
4411	cmd->num_entries = num_qgrps;
4412
4413	vmvf_and_timeout = FIELD_PREP(ICE_AQC_Q_DIS_TIMEOUT_M, 5);
4414
4415	switch (rst_src) {
4416	case ICE_VM_RESET:
4417	cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET;
4418	vmvf_and_timeout |= vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M;
4419	break;
4420	case ICE_VF_RESET:
4421	cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VF_RESET;
4422	/* In this case, FW expects vmvf_num to be absolute VF ID */
4423	vmvf_and_timeout |= (vmvf_num + hw->func_caps.vf_base_id) &
4424	ICE_AQC_Q_DIS_VMVF_NUM_M;
4425	break;
4426	case ICE_NO_RESET:
4427	default:
4428	break;
4429	}
4430
4431	cmd->vmvf_and_timeout = cpu_to_le16(vmvf_and_timeout);
4432
4433	/* flush pipe on time out */
4434	cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE;
4435	/* If no queue group info, we are in a reset flow. Issue the AQ */
4436	if (!qg_list)
4437	goto do_aq;
4438
4439	/* set RD bit to indicate that command buffer is provided by the driver
4440	* and it needs to be read by the firmware
4441	*/
4442	desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
4443
4444	for (i = 0, item = qg_list; i < num_qgrps; i++) {
4445	u16 item_size = struct_size(item, q_id, item->num_qs);
4446
4447	/* If the num of queues is even, add 2 bytes of padding */
4448	if ((item->num_qs % 2) == 0)
4449	item_size += 2;
4450
4451	sz += item_size;
4452
4453	item = (struct ice_aqc_dis_txq_item *)((u8 *)item + item_size);
4454	}
4455
4456	if (buf_size != sz)
4457	return -EINVAL;
4458
4459	do_aq:
4460	status = ice_aq_send_cmd(hw, desc: &desc, buf: qg_list, buf_size, cd);
4461	if (status) {
4462	if (!qg_list)
4463	ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n",
4464	vmvf_num, hw->adminq.sq_last_status);
4465	else
4466	ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n",
4467	le16_to_cpu(qg_list[0].q_id[0]),
4468	hw->adminq.sq_last_status);
4469	}
4470	return status;
4471	}
4472
4473	/**
4474	* ice_aq_cfg_lan_txq
4475	* @hw: pointer to the hardware structure
4476	* @buf: buffer for command
4477	* @buf_size: size of buffer in bytes
4478	* @num_qs: number of queues being configured
4479	* @oldport: origination lport
4480	* @newport: destination lport
4481	* @cd: pointer to command details structure or NULL
4482	*
4483	* Move/Configure LAN Tx queue (0x0C32)
4484	*
4485	* There is a better AQ command to use for moving nodes, so only coding
4486	* this one for configuring the node.
4487	*/
4488	int
4489	ice_aq_cfg_lan_txq(struct ice_hw *hw, struct ice_aqc_cfg_txqs_buf *buf,
4490	u16 buf_size, u16 num_qs, u8 oldport, u8 newport,
4491	struct ice_sq_cd *cd)
4492	{
4493	struct ice_aqc_cfg_txqs *cmd;
4494	struct ice_aq_desc desc;
4495	int status;
4496
4497	cmd = &desc.params.cfg_txqs;
4498	ice_fill_dflt_direct_cmd_desc(desc: &desc, opcode: ice_aqc_opc_cfg_txqs);
4499	desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
4500
4501	if (!buf)
4502	return -EINVAL;
4503
4504	cmd->cmd_type = ICE_AQC_Q_CFG_TC_CHNG;
4505	cmd->num_qs = num_qs;
4506	cmd->port_num_chng = (oldport & ICE_AQC_Q_CFG_SRC_PRT_M);
4507	cmd->port_num_chng |= FIELD_PREP(ICE_AQC_Q_CFG_DST_PRT_M, newport);
4508	cmd->time_out = FIELD_PREP(ICE_AQC_Q_CFG_TIMEOUT_M, 5);
4509	cmd->blocked_cgds = 0;
4510
4511	status = ice_aq_send_cmd(hw, desc: &desc, buf, buf_size, cd);
4512	if (status)
4513	ice_debug(hw, ICE_DBG_SCHED, "Failed to reconfigure nodes %d\n",
4514	hw->adminq.sq_last_status);
4515	return status;
4516	}
4517
4518	/**
4519	* ice_aq_add_rdma_qsets
4520	* @hw: pointer to the hardware structure
4521	* @num_qset_grps: Number of RDMA Qset groups
4522	* @qset_list: list of Qset groups to be added
4523	* @buf_size: size of buffer for indirect command
4524	* @cd: pointer to command details structure or NULL
4525	*
4526	* Add Tx RDMA Qsets (0x0C33)
4527	*/
4528	static int
4529	ice_aq_add_rdma_qsets(struct ice_hw *hw, u8 num_qset_grps,
4530	struct ice_aqc_add_rdma_qset_data *qset_list,
4531	u16 buf_size, struct ice_sq_cd *cd)
4532	{
4533	struct ice_aqc_add_rdma_qset_data *list;
4534	struct ice_aqc_add_rdma_qset *cmd;
4535	struct ice_aq_desc desc;
4536	u16 i, sum_size = 0;
4537
4538	cmd = &desc.params.add_rdma_qset;
4539
4540	ice_fill_dflt_direct_cmd_desc(desc: &desc, opcode: ice_aqc_opc_add_rdma_qset);
4541
4542	if (num_qset_grps > ICE_LAN_TXQ_MAX_QGRPS)
4543	return -EINVAL;
4544
4545	for (i = 0, list = qset_list; i < num_qset_grps; i++) {
4546	u16 num_qsets = le16_to_cpu(list->num_qsets);
4547
4548	sum_size += struct_size(list, rdma_qsets, num_qsets);
4549	list = (struct ice_aqc_add_rdma_qset_data *)(list->rdma_qsets +
4550	num_qsets);
4551	}
4552
4553	if (buf_size != sum_size)
4554	return -EINVAL;
4555
4556	desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
4557
4558	cmd->num_qset_grps = num_qset_grps;
4559
4560	return ice_aq_send_cmd(hw, desc: &desc, buf: qset_list, buf_size, cd);
4561	}
4562
4563	/* End of FW Admin Queue command wrappers */
4564
4565	/**
4566	* ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC
4567	* @hw: pointer to the HW struct
4568	* @vsi_handle: software VSI handle
4569	* @tc: TC number
4570	* @q_handle: software queue handle
4571	*/
4572	struct ice_q_ctx *
4573	ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle)
4574	{
4575	struct ice_vsi_ctx *vsi;
4576	struct ice_q_ctx *q_ctx;
4577
4578	vsi = ice_get_vsi_ctx(hw, vsi_handle);
4579	if (!vsi)
4580	return NULL;
4581	if (q_handle >= vsi->num_lan_q_entries[tc])
4582	return NULL;
4583	if (!vsi->lan_q_ctx[tc])
4584	return NULL;
4585	q_ctx = vsi->lan_q_ctx[tc];
4586	return &q_ctx[q_handle];
4587	}
4588
4589	/**
4590	* ice_ena_vsi_txq
4591	* @pi: port information structure
4592	* @vsi_handle: software VSI handle
4593	* @tc: TC number
4594	* @q_handle: software queue handle
4595	* @num_qgrps: Number of added queue groups
4596	* @buf: list of queue groups to be added
4597	* @buf_size: size of buffer for indirect command
4598	* @cd: pointer to command details structure or NULL
4599	*
4600	* This function adds one LAN queue
4601	*/
4602	int
4603	ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle,
4604	u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size,
4605	struct ice_sq_cd *cd)
4606	{
4607	struct ice_aqc_txsched_elem_data node = { 0 };
4608	struct ice_sched_node *parent;
4609	struct ice_q_ctx *q_ctx;
4610	struct ice_hw *hw;
4611	int status;
4612
4613	if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
4614	return -EIO;
4615
4616	if (num_qgrps > 1 || buf->num_txqs > 1)
4617	return -ENOSPC;
4618
4619	hw = pi->hw;
4620
4621	if (!ice_is_vsi_valid(hw, vsi_handle))
4622	return -EINVAL;
4623
4624	mutex_lock(&pi->sched_lock);
4625
4626	q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle);
4627	if (!q_ctx) {
4628	ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n",
4629	q_handle);
4630	status = -EINVAL;
4631	goto ena_txq_exit;
4632	}
4633
4634	/* find a parent node */
4635	parent = ice_sched_get_free_qparent(pi, vsi_handle, tc,
4636	ICE_SCHED_NODE_OWNER_LAN);
4637	if (!parent) {
4638	status = -EINVAL;
4639	goto ena_txq_exit;
4640	}
4641
4642	buf->parent_teid = parent->info.node_teid;
4643	node.parent_teid = parent->info.node_teid;
4644	/* Mark that the values in the "generic" section as valid. The default
4645	* value in the "generic" section is zero. This means that :
4646	* - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0.
4647	* - 0 priority among siblings, indicated by Bit 1-3.
4648	* - WFQ, indicated by Bit 4.
4649	* - 0 Adjustment value is used in PSM credit update flow, indicated by
4650	* Bit 5-6.
4651	* - Bit 7 is reserved.
4652	* Without setting the generic section as valid in valid_sections, the
4653	* Admin queue command will fail with error code ICE_AQ_RC_EINVAL.
4654	*/
4655	buf->txqs[0].info.valid_sections =
4656	ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR |
4657	ICE_AQC_ELEM_VALID_EIR;
4658	buf->txqs[0].info.generic = 0;
4659	buf->txqs[0].info.cir_bw.bw_profile_idx =
4660	cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID);
4661	buf->txqs[0].info.cir_bw.bw_alloc =
4662	cpu_to_le16(ICE_SCHED_DFLT_BW_WT);
4663	buf->txqs[0].info.eir_bw.bw_profile_idx =
4664	cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID);
4665	buf->txqs[0].info.eir_bw.bw_alloc =
4666	cpu_to_le16(ICE_SCHED_DFLT_BW_WT);
4667
4668	/* add the LAN queue */
4669	status = ice_aq_add_lan_txq(hw, num_qgrps, qg_list: buf, buf_size, cd);
4670	if (status) {
4671	ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n",
4672	le16_to_cpu(buf->txqs[0].txq_id),
4673	hw->adminq.sq_last_status);
4674	goto ena_txq_exit;
4675	}
4676
4677	node.node_teid = buf->txqs[0].q_teid;
4678	node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF;
4679	q_ctx->q_handle = q_handle;
4680	q_ctx->q_teid = le32_to_cpu(node.node_teid);
4681
4682	/* add a leaf node into scheduler tree queue layer */
4683	status = ice_sched_add_node(pi, layer: hw->num_tx_sched_layers - 1, info: &node, NULL);
4684	if (!status)
4685	status = ice_sched_replay_q_bw(pi, q_ctx);
4686
4687	ena_txq_exit:
4688	mutex_unlock(lock: &pi->sched_lock);
4689	return status;
4690	}
4691
4692	/**
4693	* ice_dis_vsi_txq
4694	* @pi: port information structure
4695	* @vsi_handle: software VSI handle
4696	* @tc: TC number
4697	* @num_queues: number of queues
4698	* @q_handles: pointer to software queue handle array
4699	* @q_ids: pointer to the q_id array
4700	* @q_teids: pointer to queue node teids
4701	* @rst_src: if called due to reset, specifies the reset source
4702	* @vmvf_num: the relative VM or VF number that is undergoing the reset
4703	* @cd: pointer to command details structure or NULL
4704	*
4705	* This function removes queues and their corresponding nodes in SW DB
4706	*/
4707	int
4708	ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues,
4709	u16 *q_handles, u16 *q_ids, u32 *q_teids,
4710	enum ice_disq_rst_src rst_src, u16 vmvf_num,
4711	struct ice_sq_cd *cd)
4712	{
4713	DEFINE_RAW_FLEX(struct ice_aqc_dis_txq_item, qg_list, q_id, 1);
4714	u16 i, buf_size = __struct_size(qg_list);
4715	struct ice_q_ctx *q_ctx;
4716	int status = -ENOENT;
4717	struct ice_hw *hw;
4718
4719	if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
4720	return -EIO;
4721
4722	hw = pi->hw;
4723
4724	if (!num_queues) {
4725	/* if queue is disabled already yet the disable queue command
4726	* has to be sent to complete the VF reset, then call
4727	* ice_aq_dis_lan_txq without any queue information
4728	*/
4729	if (rst_src)
4730	return ice_aq_dis_lan_txq(hw, num_qgrps: 0, NULL, buf_size: 0, rst_src,
4731	vmvf_num, NULL);
4732	return -EIO;
4733	}
4734
4735	mutex_lock(&pi->sched_lock);
4736
4737	for (i = 0; i < num_queues; i++) {
4738	struct ice_sched_node *node;
4739
4740	node = ice_sched_find_node_by_teid(start_node: pi->root, teid: q_teids[i]);
4741	if (!node)
4742	continue;
4743	q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle: q_handles[i]);
4744	if (!q_ctx) {
4745	ice_debug(hw, ICE_DBG_SCHED, "invalid queue handle%d\n",
4746	q_handles[i]);
4747	continue;
4748	}
4749	if (q_ctx->q_handle != q_handles[i]) {
4750	ice_debug(hw, ICE_DBG_SCHED, "Err:handles %d %d\n",
4751	q_ctx->q_handle, q_handles[i]);
4752	continue;
4753	}
4754	qg_list->parent_teid = node->info.parent_teid;
4755	qg_list->num_qs = 1;
4756	qg_list->q_id[0] = cpu_to_le16(q_ids[i]);
4757	status = ice_aq_dis_lan_txq(hw, num_qgrps: 1, qg_list, buf_size, rst_src,
4758	vmvf_num, cd);
4759
4760	if (status)
4761	break;
4762	ice_free_sched_node(pi, node);
4763	q_ctx->q_handle = ICE_INVAL_Q_HANDLE;
4764	q_ctx->q_teid = ICE_INVAL_TEID;
4765	}
4766	mutex_unlock(lock: &pi->sched_lock);
4767	return status;
4768	}
4769
4770	/**
4771	* ice_cfg_vsi_qs - configure the new/existing VSI queues
4772	* @pi: port information structure
4773	* @vsi_handle: software VSI handle
4774	* @tc_bitmap: TC bitmap
4775	* @maxqs: max queues array per TC
4776	* @owner: LAN or RDMA
4777	*
4778	* This function adds/updates the VSI queues per TC.
4779	*/
4780	static int
4781	ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,
4782	u16 *maxqs, u8 owner)
4783	{
4784	int status = 0;
4785	u8 i;
4786
4787	if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
4788	return -EIO;
4789
4790	if (!ice_is_vsi_valid(hw: pi->hw, vsi_handle))
4791	return -EINVAL;
4792
4793	mutex_lock(&pi->sched_lock);
4794
4795	ice_for_each_traffic_class(i) {
4796	/* configuration is possible only if TC node is present */
4797	if (!ice_sched_get_tc_node(pi, tc: i))
4798	continue;
4799
4800	status = ice_sched_cfg_vsi(pi, vsi_handle, tc: i, maxqs: maxqs[i], owner,
4801	enable: ice_is_tc_ena(bitmap: tc_bitmap, tc: i));
4802	if (status)
4803	break;
4804	}
4805
4806	mutex_unlock(lock: &pi->sched_lock);
4807	return status;
4808	}
4809
4810	/**
4811	* ice_cfg_vsi_lan - configure VSI LAN queues
4812	* @pi: port information structure
4813	* @vsi_handle: software VSI handle
4814	* @tc_bitmap: TC bitmap
4815	* @max_lanqs: max LAN queues array per TC
4816	*
4817	* This function adds/updates the VSI LAN queues per TC.
4818	*/
4819	int
4820	ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,
4821	u16 *max_lanqs)
4822	{
4823	return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, maxqs: max_lanqs,
4824	ICE_SCHED_NODE_OWNER_LAN);
4825	}
4826
4827	/**
4828	* ice_cfg_vsi_rdma - configure the VSI RDMA queues
4829	* @pi: port information structure
4830	* @vsi_handle: software VSI handle
4831	* @tc_bitmap: TC bitmap
4832	* @max_rdmaqs: max RDMA queues array per TC
4833	*
4834	* This function adds/updates the VSI RDMA queues per TC.
4835	*/
4836	int
4837	ice_cfg_vsi_rdma(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap,
4838	u16 *max_rdmaqs)
4839	{
4840	return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, maxqs: max_rdmaqs,
4841	ICE_SCHED_NODE_OWNER_RDMA);
4842	}
4843
4844	/**
4845	* ice_ena_vsi_rdma_qset
4846	* @pi: port information structure
4847	* @vsi_handle: software VSI handle
4848	* @tc: TC number
4849	* @rdma_qset: pointer to RDMA Qset
4850	* @num_qsets: number of RDMA Qsets
4851	* @qset_teid: pointer to Qset node TEIDs
4852	*
4853	* This function adds RDMA Qset
4854	*/
4855	int
4856	ice_ena_vsi_rdma_qset(struct ice_port_info *pi, u16 vsi_handle, u8 tc,
4857	u16 *rdma_qset, u16 num_qsets, u32 *qset_teid)
4858	{
4859	struct ice_aqc_txsched_elem_data node = { 0 };
4860	struct ice_aqc_add_rdma_qset_data *buf;
4861	struct ice_sched_node *parent;
4862	struct ice_hw *hw;
4863	u16 i, buf_size;
4864	int ret;
4865
4866	if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
4867	return -EIO;
4868	hw = pi->hw;
4869
4870	if (!ice_is_vsi_valid(hw, vsi_handle))
4871	return -EINVAL;
4872
4873	buf_size = struct_size(buf, rdma_qsets, num_qsets);
4874	buf = kzalloc(buf_size, GFP_KERNEL);
4875	if (!buf)
4876	return -ENOMEM;
4877	mutex_lock(&pi->sched_lock);
4878
4879	parent = ice_sched_get_free_qparent(pi, vsi_handle, tc,
4880	ICE_SCHED_NODE_OWNER_RDMA);
4881	if (!parent) {
4882	ret = -EINVAL;
4883	goto rdma_error_exit;
4884	}
4885	buf->parent_teid = parent->info.node_teid;
4886	node.parent_teid = parent->info.node_teid;
4887
4888	buf->num_qsets = cpu_to_le16(num_qsets);
4889	for (i = 0; i < num_qsets; i++) {
4890	buf->rdma_qsets[i].tx_qset_id = cpu_to_le16(rdma_qset[i]);
4891	buf->rdma_qsets[i].info.valid_sections =
4892	ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR |
4893	ICE_AQC_ELEM_VALID_EIR;
4894	buf->rdma_qsets[i].info.generic = 0;
4895	buf->rdma_qsets[i].info.cir_bw.bw_profile_idx =
4896	cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID);
4897	buf->rdma_qsets[i].info.cir_bw.bw_alloc =
4898	cpu_to_le16(ICE_SCHED_DFLT_BW_WT);
4899	buf->rdma_qsets[i].info.eir_bw.bw_profile_idx =
4900	cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID);
4901	buf->rdma_qsets[i].info.eir_bw.bw_alloc =
4902	cpu_to_le16(ICE_SCHED_DFLT_BW_WT);
4903	}
4904	ret = ice_aq_add_rdma_qsets(hw, num_qset_grps: 1, qset_list: buf, buf_size, NULL);
4905	if (ret) {
4906	ice_debug(hw, ICE_DBG_RDMA, "add RDMA qset failed\n");
4907	goto rdma_error_exit;
4908	}
4909	node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF;
4910	for (i = 0; i < num_qsets; i++) {
4911	node.node_teid = buf->rdma_qsets[i].qset_teid;
4912	ret = ice_sched_add_node(pi, layer: hw->num_tx_sched_layers - 1,
4913	info: &node, NULL);
4914	if (ret)
4915	break;
4916	qset_teid[i] = le32_to_cpu(node.node_teid);
4917	}
4918	rdma_error_exit:
4919	mutex_unlock(lock: &pi->sched_lock);
4920	kfree(objp: buf);
4921	return ret;
4922	}
4923
4924	/**
4925	* ice_dis_vsi_rdma_qset - free RDMA resources
4926	* @pi: port_info struct
4927	* @count: number of RDMA Qsets to free
4928	* @qset_teid: TEID of Qset node
4929	* @q_id: list of queue IDs being disabled
4930	*/
4931	int
4932	ice_dis_vsi_rdma_qset(struct ice_port_info *pi, u16 count, u32 *qset_teid,
4933	u16 *q_id)
4934	{
4935	DEFINE_RAW_FLEX(struct ice_aqc_dis_txq_item, qg_list, q_id, 1);
4936	u16 qg_size = __struct_size(qg_list);
4937	struct ice_hw *hw;
4938	int status = 0;
4939	int i;
4940
4941	if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
4942	return -EIO;
4943
4944	hw = pi->hw;
4945
4946	mutex_lock(&pi->sched_lock);
4947
4948	for (i = 0; i < count; i++) {
4949	struct ice_sched_node *node;
4950
4951	node = ice_sched_find_node_by_teid(start_node: pi->root, teid: qset_teid[i]);
4952	if (!node)
4953	continue;
4954
4955	qg_list->parent_teid = node->info.parent_teid;
4956	qg_list->num_qs = 1;
4957	qg_list->q_id[0] =
4958	cpu_to_le16(q_id[i] |
4959	ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET);
4960
4961	status = ice_aq_dis_lan_txq(hw, num_qgrps: 1, qg_list, buf_size: qg_size,
4962	rst_src: ICE_NO_RESET, vmvf_num: 0, NULL);
4963	if (status)
4964	break;
4965
4966	ice_free_sched_node(pi, node);
4967	}
4968
4969	mutex_unlock(lock: &pi->sched_lock);
4970	return status;
4971	}
4972
4973	/**
4974	* ice_aq_get_cgu_abilities - get cgu abilities
4975	* @hw: pointer to the HW struct
4976	* @abilities: CGU abilities
4977	*
4978	* Get CGU abilities (0x0C61)
4979	* Return: 0 on success or negative value on failure.
4980	*/
4981	int
4982	ice_aq_get_cgu_abilities(struct ice_hw *hw,
4983	struct ice_aqc_get_cgu_abilities *abilities)
4984	{
4985	struct ice_aq_desc desc;
4986
4987	ice_fill_dflt_direct_cmd_desc(desc: &desc, opcode: ice_aqc_opc_get_cgu_abilities);
4988	return ice_aq_send_cmd(hw, desc: &desc, buf: abilities, buf_size: sizeof(*abilities), NULL);
4989	}
4990
4991	/**
4992	* ice_aq_set_input_pin_cfg - set input pin config
4993	* @hw: pointer to the HW struct
4994	* @input_idx: Input index
4995	* @flags1: Input flags
4996	* @flags2: Input flags
4997	* @freq: Frequency in Hz
4998	* @phase_delay: Delay in ps
4999	*
5000	* Set CGU input config (0x0C62)
5001	* Return: 0 on success or negative value on failure.
5002	*/
5003	int
5004	ice_aq_set_input_pin_cfg(struct ice_hw *hw, u8 input_idx, u8 flags1, u8 flags2,
5005	u32 freq, s32 phase_delay)
5006	{
5007	struct ice_aqc_set_cgu_input_config *cmd;
5008	struct ice_aq_desc desc;
5009
5010	ice_fill_dflt_direct_cmd_desc(desc: &desc, opcode: ice_aqc_opc_set_cgu_input_config);
5011	cmd = &desc.params.set_cgu_input_config;
5012	cmd->input_idx = input_idx;
5013	cmd->flags1 = flags1;
5014	cmd->flags2 = flags2;
5015	cmd->freq = cpu_to_le32(freq);
5016	cmd->phase_delay = cpu_to_le32(phase_delay);
5017
5018	return ice_aq_send_cmd(hw, desc: &desc, NULL, buf_size: 0, NULL);
5019	}
5020
5021	/**
5022	* ice_aq_get_input_pin_cfg - get input pin config
5023	* @hw: pointer to the HW struct
5024	* @input_idx: Input index
5025	* @status: Pin status
5026	* @type: Pin type
5027	* @flags1: Input flags
5028	* @flags2: Input flags
5029	* @freq: Frequency in Hz
5030	* @phase_delay: Delay in ps
5031	*
5032	* Get CGU input config (0x0C63)
5033	* Return: 0 on success or negative value on failure.
5034	*/
5035	int
5036	ice_aq_get_input_pin_cfg(struct ice_hw *hw, u8 input_idx, u8 *status, u8 *type,
5037	u8 *flags1, u8 *flags2, u32 *freq, s32 *phase_delay)
5038	{
5039	struct ice_aqc_get_cgu_input_config *cmd;
5040	struct ice_aq_desc desc;
5041	int ret;
5042
5043	ice_fill_dflt_direct_cmd_desc(desc: &desc, opcode: ice_aqc_opc_get_cgu_input_config);
5044	cmd = &desc.params.get_cgu_input_config;
5045	cmd->input_idx = input_idx;
5046
5047	ret = ice_aq_send_cmd(hw, desc: &desc, NULL, buf_size: 0, NULL);
5048	if (!ret) {
5049	if (status)
5050	*status = cmd->status;
5051	if (type)
5052	*type = cmd->type;
5053	if (flags1)
5054	*flags1 = cmd->flags1;
5055	if (flags2)
5056	*flags2 = cmd->flags2;
5057	if (freq)
5058	*freq = le32_to_cpu(cmd->freq);
5059	if (phase_delay)
5060	*phase_delay = le32_to_cpu(cmd->phase_delay);
5061	}
5062
5063	return ret;
5064	}
5065
5066	/**
5067	* ice_aq_set_output_pin_cfg - set output pin config
5068	* @hw: pointer to the HW struct
5069	* @output_idx: Output index
5070	* @flags: Output flags
5071	* @src_sel: Index of DPLL block
5072	* @freq: Output frequency
5073	* @phase_delay: Output phase compensation
5074	*
5075	* Set CGU output config (0x0C64)
5076	* Return: 0 on success or negative value on failure.
5077	*/
5078	int
5079	ice_aq_set_output_pin_cfg(struct ice_hw *hw, u8 output_idx, u8 flags,
5080	u8 src_sel, u32 freq, s32 phase_delay)
5081	{
5082	struct ice_aqc_set_cgu_output_config *cmd;
5083	struct ice_aq_desc desc;
5084
5085	ice_fill_dflt_direct_cmd_desc(desc: &desc, opcode: ice_aqc_opc_set_cgu_output_config);
5086	cmd = &desc.params.set_cgu_output_config;
5087	cmd->output_idx = output_idx;
5088	cmd->flags = flags;
5089	cmd->src_sel = src_sel;
5090	cmd->freq = cpu_to_le32(freq);
5091	cmd->phase_delay = cpu_to_le32(phase_delay);
5092
5093	return ice_aq_send_cmd(hw, desc: &desc, NULL, buf_size: 0, NULL);
5094	}
5095
5096	/**
5097	* ice_aq_get_output_pin_cfg - get output pin config
5098	* @hw: pointer to the HW struct
5099	* @output_idx: Output index
5100	* @flags: Output flags
5101	* @src_sel: Internal DPLL source
5102	* @freq: Output frequency
5103	* @src_freq: Source frequency
5104	*
5105	* Get CGU output config (0x0C65)
5106	* Return: 0 on success or negative value on failure.
5107	*/
5108	int
5109	ice_aq_get_output_pin_cfg(struct ice_hw *hw, u8 output_idx, u8 *flags,
5110	u8 *src_sel, u32 *freq, u32 *src_freq)
5111	{
5112	struct ice_aqc_get_cgu_output_config *cmd;
5113	struct ice_aq_desc desc;
5114	int ret;
5115
5116	ice_fill_dflt_direct_cmd_desc(desc: &desc, opcode: ice_aqc_opc_get_cgu_output_config);
5117	cmd = &desc.params.get_cgu_output_config;
5118	cmd->output_idx = output_idx;
5119
5120	ret = ice_aq_send_cmd(hw, desc: &desc, NULL, buf_size: 0, NULL);
5121	if (!ret) {
5122	if (flags)
5123	*flags = cmd->flags;
5124	if (src_sel)
5125	*src_sel = cmd->src_sel;
5126	if (freq)
5127	*freq = le32_to_cpu(cmd->freq);
5128	if (src_freq)
5129	*src_freq = le32_to_cpu(cmd->src_freq);
5130	}
5131
5132	return ret;
5133	}
5134
5135	/**
5136	* ice_aq_get_cgu_dpll_status - get dpll status
5137	* @hw: pointer to the HW struct
5138	* @dpll_num: DPLL index
5139	* @ref_state: Reference clock state
5140	* @config: current DPLL config
5141	* @dpll_state: current DPLL state
5142	* @phase_offset: Phase offset in ns
5143	* @eec_mode: EEC_mode
5144	*
5145	* Get CGU DPLL status (0x0C66)
5146	* Return: 0 on success or negative value on failure.
5147	*/
5148	int
5149	ice_aq_get_cgu_dpll_status(struct ice_hw *hw, u8 dpll_num, u8 *ref_state,
5150	u8 *dpll_state, u8 *config, s64 *phase_offset,
5151	u8 *eec_mode)
5152	{
5153	struct ice_aqc_get_cgu_dpll_status *cmd;
5154	struct ice_aq_desc desc;
5155	int status;
5156
5157	ice_fill_dflt_direct_cmd_desc(desc: &desc, opcode: ice_aqc_opc_get_cgu_dpll_status);
5158	cmd = &desc.params.get_cgu_dpll_status;
5159	cmd->dpll_num = dpll_num;
5160
5161	status = ice_aq_send_cmd(hw, desc: &desc, NULL, buf_size: 0, NULL);
5162	if (!status) {
5163	*ref_state = cmd->ref_state;
5164	*dpll_state = cmd->dpll_state;
5165	*config = cmd->config;
5166	*phase_offset = le32_to_cpu(cmd->phase_offset_h);
5167	*phase_offset <<= 32;
5168	*phase_offset += le32_to_cpu(cmd->phase_offset_l);
5169	*phase_offset = sign_extend64(value: *phase_offset, index: 47);
5170	*eec_mode = cmd->eec_mode;
5171	}
5172
5173	return status;
5174	}
5175
5176	/**
5177	* ice_aq_set_cgu_dpll_config - set dpll config
5178	* @hw: pointer to the HW struct
5179	* @dpll_num: DPLL index
5180	* @ref_state: Reference clock state
5181	* @config: DPLL config
5182	* @eec_mode: EEC mode
5183	*
5184	* Set CGU DPLL config (0x0C67)
5185	* Return: 0 on success or negative value on failure.
5186	*/
5187	int
5188	ice_aq_set_cgu_dpll_config(struct ice_hw *hw, u8 dpll_num, u8 ref_state,
5189	u8 config, u8 eec_mode)
5190	{
5191	struct ice_aqc_set_cgu_dpll_config *cmd;
5192	struct ice_aq_desc desc;
5193
5194	ice_fill_dflt_direct_cmd_desc(desc: &desc, opcode: ice_aqc_opc_set_cgu_dpll_config);
5195	cmd = &desc.params.set_cgu_dpll_config;
5196	cmd->dpll_num = dpll_num;
5197	cmd->ref_state = ref_state;
5198	cmd->config = config;
5199	cmd->eec_mode = eec_mode;
5200
5201	return ice_aq_send_cmd(hw, desc: &desc, NULL, buf_size: 0, NULL);
5202	}
5203
5204	/**
5205	* ice_aq_set_cgu_ref_prio - set input reference priority
5206	* @hw: pointer to the HW struct
5207	* @dpll_num: DPLL index
5208	* @ref_idx: Reference pin index
5209	* @ref_priority: Reference input priority
5210	*
5211	* Set CGU reference priority (0x0C68)
5212	* Return: 0 on success or negative value on failure.
5213	*/
5214	int
5215	ice_aq_set_cgu_ref_prio(struct ice_hw *hw, u8 dpll_num, u8 ref_idx,
5216	u8 ref_priority)
5217	{
5218	struct ice_aqc_set_cgu_ref_prio *cmd;
5219	struct ice_aq_desc desc;
5220
5221	ice_fill_dflt_direct_cmd_desc(desc: &desc, opcode: ice_aqc_opc_set_cgu_ref_prio);
5222	cmd = &desc.params.set_cgu_ref_prio;
5223	cmd->dpll_num = dpll_num;
5224	cmd->ref_idx = ref_idx;
5225	cmd->ref_priority = ref_priority;
5226
5227	return ice_aq_send_cmd(hw, desc: &desc, NULL, buf_size: 0, NULL);
5228	}
5229
5230	/**
5231	* ice_aq_get_cgu_ref_prio - get input reference priority
5232	* @hw: pointer to the HW struct
5233	* @dpll_num: DPLL index
5234	* @ref_idx: Reference pin index
5235	* @ref_prio: Reference input priority
5236	*
5237	* Get CGU reference priority (0x0C69)
5238	* Return: 0 on success or negative value on failure.
5239	*/
5240	int
5241	ice_aq_get_cgu_ref_prio(struct ice_hw *hw, u8 dpll_num, u8 ref_idx,
5242	u8 *ref_prio)
5243	{
5244	struct ice_aqc_get_cgu_ref_prio *cmd;
5245	struct ice_aq_desc desc;
5246	int status;
5247
5248	ice_fill_dflt_direct_cmd_desc(desc: &desc, opcode: ice_aqc_opc_get_cgu_ref_prio);
5249	cmd = &desc.params.get_cgu_ref_prio;
5250	cmd->dpll_num = dpll_num;
5251	cmd->ref_idx = ref_idx;
5252
5253	status = ice_aq_send_cmd(hw, desc: &desc, NULL, buf_size: 0, NULL);
5254	if (!status)
5255	*ref_prio = cmd->ref_priority;
5256
5257	return status;
5258	}
5259
5260	/**
5261	* ice_aq_get_cgu_info - get cgu info
5262	* @hw: pointer to the HW struct
5263	* @cgu_id: CGU ID
5264	* @cgu_cfg_ver: CGU config version
5265	* @cgu_fw_ver: CGU firmware version
5266	*
5267	* Get CGU info (0x0C6A)
5268	* Return: 0 on success or negative value on failure.
5269	*/
5270	int
5271	ice_aq_get_cgu_info(struct ice_hw *hw, u32 *cgu_id, u32 *cgu_cfg_ver,
5272	u32 *cgu_fw_ver)
5273	{
5274	struct ice_aqc_get_cgu_info *cmd;
5275	struct ice_aq_desc desc;
5276	int status;
5277
5278	ice_fill_dflt_direct_cmd_desc(desc: &desc, opcode: ice_aqc_opc_get_cgu_info);
5279	cmd = &desc.params.get_cgu_info;
5280
5281	status = ice_aq_send_cmd(hw, desc: &desc, NULL, buf_size: 0, NULL);
5282	if (!status) {
5283	*cgu_id = le32_to_cpu(cmd->cgu_id);
5284	*cgu_cfg_ver = le32_to_cpu(cmd->cgu_cfg_ver);
5285	*cgu_fw_ver = le32_to_cpu(cmd->cgu_fw_ver);
5286	}
5287
5288	return status;
5289	}
5290
5291	/**
5292	* ice_aq_set_phy_rec_clk_out - set RCLK phy out
5293	* @hw: pointer to the HW struct
5294	* @phy_output: PHY reference clock output pin
5295	* @enable: GPIO state to be applied
5296	* @freq: PHY output frequency
5297	*
5298	* Set phy recovered clock as reference (0x0630)
5299	* Return: 0 on success or negative value on failure.
5300	*/
5301	int
5302	ice_aq_set_phy_rec_clk_out(struct ice_hw *hw, u8 phy_output, bool enable,
5303	u32 *freq)
5304	{
5305	struct ice_aqc_set_phy_rec_clk_out *cmd;
5306	struct ice_aq_desc desc;
5307	int status;
5308
5309	ice_fill_dflt_direct_cmd_desc(desc: &desc, opcode: ice_aqc_opc_set_phy_rec_clk_out);
5310	cmd = &desc.params.set_phy_rec_clk_out;
5311	cmd->phy_output = phy_output;
5312	cmd->port_num = ICE_AQC_SET_PHY_REC_CLK_OUT_CURR_PORT;
5313	cmd->flags = enable & ICE_AQC_SET_PHY_REC_CLK_OUT_OUT_EN;
5314	cmd->freq = cpu_to_le32(*freq);
5315
5316	status = ice_aq_send_cmd(hw, desc: &desc, NULL, buf_size: 0, NULL);
5317	if (!status)
5318	*freq = le32_to_cpu(cmd->freq);
5319
5320	return status;
5321	}
5322
5323	/**
5324	* ice_aq_get_phy_rec_clk_out - get phy recovered signal info
5325	* @hw: pointer to the HW struct
5326	* @phy_output: PHY reference clock output pin
5327	* @port_num: Port number
5328	* @flags: PHY flags
5329	* @node_handle: PHY output frequency
5330	*
5331	* Get PHY recovered clock output info (0x0631)
5332	* Return: 0 on success or negative value on failure.
5333	*/
5334	int
5335	ice_aq_get_phy_rec_clk_out(struct ice_hw *hw, u8 *phy_output, u8 *port_num,
5336	u8 *flags, u16 *node_handle)
5337	{
5338	struct ice_aqc_get_phy_rec_clk_out *cmd;
5339	struct ice_aq_desc desc;
5340	int status;
5341
5342	ice_fill_dflt_direct_cmd_desc(desc: &desc, opcode: ice_aqc_opc_get_phy_rec_clk_out);
5343	cmd = &desc.params.get_phy_rec_clk_out;
5344	cmd->phy_output = *phy_output;
5345
5346	status = ice_aq_send_cmd(hw, desc: &desc, NULL, buf_size: 0, NULL);
5347	if (!status) {
5348	*phy_output = cmd->phy_output;
5349	if (port_num)
5350	*port_num = cmd->port_num;
5351	if (flags)
5352	*flags = cmd->flags;
5353	if (node_handle)
5354	*node_handle = le16_to_cpu(cmd->node_handle);
5355	}
5356
5357	return status;
5358	}
5359
5360	/**
5361	* ice_aq_get_sensor_reading
5362	* @hw: pointer to the HW struct
5363	* @data: pointer to data to be read from the sensor
5364	*
5365	* Get sensor reading (0x0632)
5366	*/
5367	int ice_aq_get_sensor_reading(struct ice_hw *hw,
5368	struct ice_aqc_get_sensor_reading_resp *data)
5369	{
5370	struct ice_aqc_get_sensor_reading *cmd;
5371	struct ice_aq_desc desc;
5372	int status;
5373
5374	ice_fill_dflt_direct_cmd_desc(desc: &desc, opcode: ice_aqc_opc_get_sensor_reading);
5375	cmd = &desc.params.get_sensor_reading;
5376	#define ICE_INTERNAL_TEMP_SENSOR_FORMAT 0
5377	#define ICE_INTERNAL_TEMP_SENSOR 0
5378	cmd->sensor = ICE_INTERNAL_TEMP_SENSOR;
5379	cmd->format = ICE_INTERNAL_TEMP_SENSOR_FORMAT;
5380
5381	status = ice_aq_send_cmd(hw, desc: &desc, NULL, buf_size: 0, NULL);
5382	if (!status)
5383	memcpy(data, &desc.params.get_sensor_reading_resp,
5384	sizeof(*data));
5385
5386	return status;
5387	}
5388
5389	/**
5390	* ice_replay_pre_init - replay pre initialization
5391	* @hw: pointer to the HW struct
5392	*
5393	* Initializes required config data for VSI, FD, ACL, and RSS before replay.
5394	*/
5395	static int ice_replay_pre_init(struct ice_hw *hw)
5396	{
5397	struct ice_switch_info *sw = hw->switch_info;
5398	u8 i;
5399
5400	/* Delete old entries from replay filter list head if there is any */
5401	ice_rm_all_sw_replay_rule_info(hw);
5402	/* In start of replay, move entries into replay_rules list, it
5403	* will allow adding rules entries back to filt_rules list,
5404	* which is operational list.
5405	*/
5406	for (i = 0; i < ICE_MAX_NUM_RECIPES; i++)
5407	list_replace_init(old: &sw->recp_list[i].filt_rules,
5408	new: &sw->recp_list[i].filt_replay_rules);
5409	ice_sched_replay_agg_vsi_preinit(hw);
5410
5411	return 0;
5412	}
5413
5414	/**
5415	* ice_replay_vsi - replay VSI configuration
5416	* @hw: pointer to the HW struct
5417	* @vsi_handle: driver VSI handle
5418	*
5419	* Restore all VSI configuration after reset. It is required to call this
5420	* function with main VSI first.
5421	*/
5422	int ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle)
5423	{
5424	int status;
5425
5426	if (!ice_is_vsi_valid(hw, vsi_handle))
5427	return -EINVAL;
5428
5429	/* Replay pre-initialization if there is any */
5430	if (vsi_handle == ICE_MAIN_VSI_HANDLE) {
5431	status = ice_replay_pre_init(hw);
5432	if (status)
5433	return status;
5434	}
5435	/* Replay per VSI all RSS configurations */
5436	status = ice_replay_rss_cfg(hw, vsi_handle);
5437	if (status)
5438	return status;
5439	/* Replay per VSI all filters */
5440	status = ice_replay_vsi_all_fltr(hw, vsi_handle);
5441	if (!status)
5442	status = ice_replay_vsi_agg(hw, vsi_handle);
5443	return status;
5444	}
5445
5446	/**
5447	* ice_replay_post - post replay configuration cleanup
5448	* @hw: pointer to the HW struct
5449	*
5450	* Post replay cleanup.
5451	*/
5452	void ice_replay_post(struct ice_hw *hw)
5453	{
5454	/* Delete old entries from replay filter list head */
5455	ice_rm_all_sw_replay_rule_info(hw);
5456	ice_sched_replay_agg(hw);
5457	}
5458
5459	/**
5460	* ice_stat_update40 - read 40 bit stat from the chip and update stat values
5461	* @hw: ptr to the hardware info
5462	* @reg: offset of 64 bit HW register to read from
5463	* @prev_stat_loaded: bool to specify if previous stats are loaded
5464	* @prev_stat: ptr to previous loaded stat value
5465	* @cur_stat: ptr to current stat value
5466	*/
5467	void
5468	ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
5469	u64 *prev_stat, u64 *cur_stat)
5470	{
5471	u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1);
5472
5473	/* device stats are not reset at PFR, they likely will not be zeroed
5474	* when the driver starts. Thus, save the value from the first read
5475	* without adding to the statistic value so that we report stats which
5476	* count up from zero.
5477	*/
5478	if (!prev_stat_loaded) {
5479	*prev_stat = new_data;
5480	return;
5481	}
5482
5483	/* Calculate the difference between the new and old values, and then
5484	* add it to the software stat value.
5485	*/
5486	if (new_data >= *prev_stat)
5487	*cur_stat += new_data - *prev_stat;
5488	else
5489	/* to manage the potential roll-over */
5490	*cur_stat += (new_data + BIT_ULL(40)) - *prev_stat;
5491
5492	/* Update the previously stored value to prepare for next read */
5493	*prev_stat = new_data;
5494	}
5495
5496	/**
5497	* ice_stat_update32 - read 32 bit stat from the chip and update stat values
5498	* @hw: ptr to the hardware info
5499	* @reg: offset of HW register to read from
5500	* @prev_stat_loaded: bool to specify if previous stats are loaded
5501	* @prev_stat: ptr to previous loaded stat value
5502	* @cur_stat: ptr to current stat value
5503	*/
5504	void
5505	ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
5506	u64 *prev_stat, u64 *cur_stat)
5507	{
5508	u32 new_data;
5509
5510	new_data = rd32(hw, reg);
5511
5512	/* device stats are not reset at PFR, they likely will not be zeroed
5513	* when the driver starts. Thus, save the value from the first read
5514	* without adding to the statistic value so that we report stats which
5515	* count up from zero.
5516	*/
5517	if (!prev_stat_loaded) {
5518	*prev_stat = new_data;
5519	return;
5520	}
5521
5522	/* Calculate the difference between the new and old values, and then
5523	* add it to the software stat value.
5524	*/
5525	if (new_data >= *prev_stat)
5526	*cur_stat += new_data - *prev_stat;
5527	else
5528	/* to manage the potential roll-over */
5529	*cur_stat += (new_data + BIT_ULL(32)) - *prev_stat;
5530
5531	/* Update the previously stored value to prepare for next read */
5532	*prev_stat = new_data;
5533	}
5534
5535	/**
5536	* ice_sched_query_elem - query element information from HW
5537	* @hw: pointer to the HW struct
5538	* @node_teid: node TEID to be queried
5539	* @buf: buffer to element information
5540	*
5541	* This function queries HW element information
5542	*/
5543	int
5544	ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
5545	struct ice_aqc_txsched_elem_data *buf)
5546	{
5547	u16 buf_size, num_elem_ret = 0;
5548	int status;
5549
5550	buf_size = sizeof(*buf);
5551	memset(buf, 0, buf_size);
5552	buf->node_teid = cpu_to_le32(node_teid);
5553	status = ice_aq_query_sched_elems(hw, elems_req: 1, buf, buf_size, elems_ret: &num_elem_ret,
5554	NULL);
5555	if (status || num_elem_ret != 1)
5556	ice_debug(hw, ICE_DBG_SCHED, "query element failed\n");
5557	return status;
5558	}
5559
5560	/**
5561	* ice_aq_read_i2c
5562	* @hw: pointer to the hw struct
5563	* @topo_addr: topology address for a device to communicate with
5564	* @bus_addr: 7-bit I2C bus address
5565	* @addr: I2C memory address (I2C offset) with up to 16 bits
5566	* @params: I2C parameters: bit [7] - Repeated start,
5567	* bits [6:5] data offset size,
5568	* bit [4] - I2C address type,
5569	* bits [3:0] - data size to read (0-16 bytes)
5570	* @data: pointer to data (0 to 16 bytes) to be read from the I2C device
5571	* @cd: pointer to command details structure or NULL
5572	*
5573	* Read I2C (0x06E2)
5574	*/
5575	int
5576	ice_aq_read_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr,
5577	u16 bus_addr, __le16 addr, u8 params, u8 *data,
5578	struct ice_sq_cd *cd)
5579	{
5580	struct ice_aq_desc desc = { 0 };
5581	struct ice_aqc_i2c *cmd;
5582	u8 data_size;
5583	int status;
5584
5585	ice_fill_dflt_direct_cmd_desc(desc: &desc, opcode: ice_aqc_opc_read_i2c);
5586	cmd = &desc.params.read_write_i2c;
5587
5588	if (!data)
5589	return -EINVAL;
5590
5591	data_size = FIELD_GET(ICE_AQC_I2C_DATA_SIZE_M, params);
5592
5593	cmd->i2c_bus_addr = cpu_to_le16(bus_addr);
5594	cmd->topo_addr = topo_addr;
5595	cmd->i2c_params = params;
5596	cmd->i2c_addr = addr;
5597
5598	status = ice_aq_send_cmd(hw, desc: &desc, NULL, buf_size: 0, cd);
5599	if (!status) {
5600	struct ice_aqc_read_i2c_resp *resp;
5601	u8 i;
5602
5603	resp = &desc.params.read_i2c_resp;
5604	for (i = 0; i < data_size; i++) {
5605	*data = resp->i2c_data[i];
5606	data++;
5607	}
5608	}
5609
5610	return status;
5611	}
5612
5613	/**
5614	* ice_aq_write_i2c
5615	* @hw: pointer to the hw struct
5616	* @topo_addr: topology address for a device to communicate with
5617	* @bus_addr: 7-bit I2C bus address
5618	* @addr: I2C memory address (I2C offset) with up to 16 bits
5619	* @params: I2C parameters: bit [4] - I2C address type, bits [3:0] - data size to write (0-7 bytes)
5620	* @data: pointer to data (0 to 4 bytes) to be written to the I2C device
5621	* @cd: pointer to command details structure or NULL
5622	*
5623	* Write I2C (0x06E3)
5624	*
5625	* * Return:
5626	* * 0 - Successful write to the i2c device
5627	* * -EINVAL - Data size greater than 4 bytes
5628	* * -EIO - FW error
5629	*/
5630	int
5631	ice_aq_write_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr,
5632	u16 bus_addr, __le16 addr, u8 params, const u8 *data,
5633	struct ice_sq_cd *cd)
5634	{
5635	struct ice_aq_desc desc = { 0 };
5636	struct ice_aqc_i2c *cmd;
5637	u8 data_size;
5638
5639	ice_fill_dflt_direct_cmd_desc(desc: &desc, opcode: ice_aqc_opc_write_i2c);
5640	cmd = &desc.params.read_write_i2c;
5641
5642	data_size = FIELD_GET(ICE_AQC_I2C_DATA_SIZE_M, params);
5643
5644	/* data_size limited to 4 */
5645	if (data_size > 4)
5646	return -EINVAL;
5647
5648	cmd->i2c_bus_addr = cpu_to_le16(bus_addr);
5649	cmd->topo_addr = topo_addr;
5650	cmd->i2c_params = params;
5651	cmd->i2c_addr = addr;
5652
5653	memcpy(cmd->i2c_data, data, data_size);
5654
5655	return ice_aq_send_cmd(hw, desc: &desc, NULL, buf_size: 0, cd);
5656	}
5657
5658	/**
5659	* ice_get_pca9575_handle - find and return the PCA9575 controller
5660	* @hw: pointer to the hw struct
5661	* @pca9575_handle: GPIO controller's handle
5662	*
5663	* Find and return the GPIO controller's handle in the netlist.
5664	* When found - the value will be cached in the hw structure and following calls
5665	* will return cached value.
5666	*
5667	* Return: 0 on success, -ENXIO when there's no PCA9575 present.
5668	*/
5669	int ice_get_pca9575_handle(struct ice_hw *hw, u16 *pca9575_handle)
5670	{
5671	struct ice_aqc_get_link_topo *cmd;
5672	struct ice_aq_desc desc;
5673	int err;
5674	u8 idx;
5675
5676	/* If handle was read previously return cached value */
5677	if (hw->io_expander_handle) {
5678	*pca9575_handle = hw->io_expander_handle;
5679	return 0;
5680	}
5681
5682	#define SW_PCA9575_SFP_TOPO_IDX 2
5683	#define SW_PCA9575_QSFP_TOPO_IDX 1
5684
5685	/* Check if the SW IO expander controlling SMA exists in the netlist. */
5686	if (hw->device_id == ICE_DEV_ID_E810C_SFP)
5687	idx = SW_PCA9575_SFP_TOPO_IDX;
5688	else if (hw->device_id == ICE_DEV_ID_E810C_QSFP)
5689	idx = SW_PCA9575_QSFP_TOPO_IDX;
5690	else
5691	return -ENXIO;
5692
5693	/* If handle was not detected read it from the netlist */
5694	ice_fill_dflt_direct_cmd_desc(desc: &desc, opcode: ice_aqc_opc_get_link_topo);
5695	cmd = &desc.params.get_link_topo;
5696	cmd->addr.topo_params.node_type_ctx =
5697	ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL;
5698	cmd->addr.topo_params.index = idx;
5699
5700	err = ice_aq_send_cmd(hw, desc: &desc, NULL, buf_size: 0, NULL);
5701	if (err)
5702	return -ENXIO;
5703
5704	/* Verify if we found the right IO expander type */
5705	if (desc.params.get_link_topo.node_part_num !=
5706	ICE_AQC_GET_LINK_TOPO_NODE_NR_PCA9575)
5707	return -ENXIO;
5708
5709	/* If present save the handle and return it */
5710	hw->io_expander_handle =
5711	le16_to_cpu(desc.params.get_link_topo.addr.handle);
5712	*pca9575_handle = hw->io_expander_handle;
5713
5714	return 0;
5715	}
5716
5717	/**
5718	* ice_read_pca9575_reg - read the register from the PCA9575 controller
5719	* @hw: pointer to the hw struct
5720	* @offset: GPIO controller register offset
5721	* @data: pointer to data to be read from the GPIO controller
5722	*
5723	* Return: 0 on success, negative error code otherwise.
5724	*/
5725	int ice_read_pca9575_reg(struct ice_hw *hw, u8 offset, u8 *data)
5726	{
5727	struct ice_aqc_link_topo_addr link_topo;
5728	__le16 addr;
5729	u16 handle;
5730	int err;
5731
5732	memset(&link_topo, 0, sizeof(link_topo));
5733
5734	err = ice_get_pca9575_handle(hw, pca9575_handle: &handle);
5735	if (err)
5736	return err;
5737
5738	link_topo.handle = cpu_to_le16(handle);
5739	link_topo.topo_params.node_type_ctx =
5740	FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_CTX_M,
5741	ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED);
5742
5743	addr = cpu_to_le16((u16)offset);
5744
5745	return ice_aq_read_i2c(hw, topo_addr: link_topo, bus_addr: 0, addr, params: 1, data, NULL);
5746	}
5747
5748	/**
5749	* ice_aq_set_gpio
5750	* @hw: pointer to the hw struct
5751	* @gpio_ctrl_handle: GPIO controller node handle
5752	* @pin_idx: IO Number of the GPIO that needs to be set
5753	* @value: SW provide IO value to set in the LSB
5754	* @cd: pointer to command details structure or NULL
5755	*
5756	* Sends 0x06EC AQ command to set the GPIO pin state that's part of the topology
5757	*/
5758	int
5759	ice_aq_set_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, bool value,
5760	struct ice_sq_cd *cd)
5761	{
5762	struct ice_aqc_gpio *cmd;
5763	struct ice_aq_desc desc;
5764
5765	ice_fill_dflt_direct_cmd_desc(desc: &desc, opcode: ice_aqc_opc_set_gpio);
5766	cmd = &desc.params.read_write_gpio;
5767	cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle);
5768	cmd->gpio_num = pin_idx;
5769	cmd->gpio_val = value ? 1 : 0;
5770
5771	return ice_aq_send_cmd(hw, desc: &desc, NULL, buf_size: 0, cd);
5772	}
5773
5774	/**
5775	* ice_aq_get_gpio
5776	* @hw: pointer to the hw struct
5777	* @gpio_ctrl_handle: GPIO controller node handle
5778	* @pin_idx: IO Number of the GPIO that needs to be set
5779	* @value: IO value read
5780	* @cd: pointer to command details structure or NULL
5781	*
5782	* Sends 0x06ED AQ command to get the value of a GPIO signal which is part of
5783	* the topology
5784	*/
5785	int
5786	ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx,
5787	bool *value, struct ice_sq_cd *cd)
5788	{
5789	struct ice_aqc_gpio *cmd;
5790	struct ice_aq_desc desc;
5791	int status;
5792
5793	ice_fill_dflt_direct_cmd_desc(desc: &desc, opcode: ice_aqc_opc_get_gpio);
5794	cmd = &desc.params.read_write_gpio;
5795	cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle);
5796	cmd->gpio_num = pin_idx;
5797
5798	status = ice_aq_send_cmd(hw, desc: &desc, NULL, buf_size: 0, cd);
5799	if (status)
5800	return status;
5801
5802	*value = !!cmd->gpio_val;
5803	return 0;
5804	}
5805
5806	/**
5807	* ice_is_fw_api_min_ver
5808	* @hw: pointer to the hardware structure
5809	* @maj: major version
5810	* @min: minor version
5811	* @patch: patch version
5812	*
5813	* Checks if the firmware API is minimum version
5814	*/
5815	static bool ice_is_fw_api_min_ver(struct ice_hw *hw, u8 maj, u8 min, u8 patch)
5816	{
5817	if (hw->api_maj_ver == maj) {
5818	if (hw->api_min_ver > min)
5819	return true;
5820	if (hw->api_min_ver == min && hw->api_patch >= patch)
5821	return true;
5822	} else if (hw->api_maj_ver > maj) {
5823	return true;
5824	}
5825
5826	return false;
5827	}
5828
5829	/**
5830	* ice_fw_supports_link_override
5831	* @hw: pointer to the hardware structure
5832	*
5833	* Checks if the firmware supports link override
5834	*/
5835	bool ice_fw_supports_link_override(struct ice_hw *hw)
5836	{
5837	return ice_is_fw_api_min_ver(hw, ICE_FW_API_LINK_OVERRIDE_MAJ,
5838	ICE_FW_API_LINK_OVERRIDE_MIN,
5839	ICE_FW_API_LINK_OVERRIDE_PATCH);
5840	}
5841
5842	/**
5843	* ice_get_link_default_override
5844	* @ldo: pointer to the link default override struct
5845	* @pi: pointer to the port info struct
5846	*
5847	* Gets the link default override for a port
5848	*/
5849	int
5850	ice_get_link_default_override(struct ice_link_default_override_tlv *ldo,
5851	struct ice_port_info *pi)
5852	{
5853	u16 i, tlv, tlv_len, tlv_start, buf, offset;
5854	struct ice_hw *hw = pi->hw;
5855	int status;
5856
5857	status = ice_get_pfa_module_tlv(hw, module_tlv: &tlv, module_tlv_len: &tlv_len,
5858	ICE_SR_LINK_DEFAULT_OVERRIDE_PTR);
5859	if (status) {
5860	ice_debug(hw, ICE_DBG_INIT, "Failed to read link override TLV.\n");
5861	return status;
5862	}
5863
5864	/* Each port has its own config; calculate for our port */
5865	tlv_start = tlv + pi->lport * ICE_SR_PFA_LINK_OVERRIDE_WORDS +
5866	ICE_SR_PFA_LINK_OVERRIDE_OFFSET;
5867
5868	/* link options first */
5869	status = ice_read_sr_word(hw, offset: tlv_start, data: &buf);
5870	if (status) {
5871	ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n");
5872	return status;
5873	}
5874	ldo->options = FIELD_GET(ICE_LINK_OVERRIDE_OPT_M, buf);
5875	ldo->phy_config = (buf & ICE_LINK_OVERRIDE_PHY_CFG_M) >>
5876	ICE_LINK_OVERRIDE_PHY_CFG_S;
5877
5878	/* link PHY config */
5879	offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET;
5880	status = ice_read_sr_word(hw, offset, data: &buf);
5881	if (status) {
5882	ice_debug(hw, ICE_DBG_INIT, "Failed to read override phy config.\n");
5883	return status;
5884	}
5885	ldo->fec_options = buf & ICE_LINK_OVERRIDE_FEC_OPT_M;
5886
5887	/* PHY types low */
5888	offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET;
5889	for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) {
5890	status = ice_read_sr_word(hw, offset: (offset + i), data: &buf);
5891	if (status) {
5892	ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n");
5893	return status;
5894	}
5895	/* shift 16 bits at a time to fill 64 bits */
5896	ldo->phy_type_low |= ((u64)buf << (i * 16));
5897	}
5898
5899	/* PHY types high */
5900	offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET +
5901	ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS;
5902	for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) {
5903	status = ice_read_sr_word(hw, offset: (offset + i), data: &buf);
5904	if (status) {
5905	ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n");
5906	return status;
5907	}
5908	/* shift 16 bits at a time to fill 64 bits */
5909	ldo->phy_type_high |= ((u64)buf << (i * 16));
5910	}
5911
5912	return status;
5913	}
5914
5915	/**
5916	* ice_is_phy_caps_an_enabled - check if PHY capabilities autoneg is enabled
5917	* @caps: get PHY capability data
5918	*/
5919	bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps)
5920	{
5921	if (caps->caps & ICE_AQC_PHY_AN_MODE ||
5922	caps->low_power_ctrl_an & (ICE_AQC_PHY_AN_EN_CLAUSE28 |
5923	ICE_AQC_PHY_AN_EN_CLAUSE73 |
5924	ICE_AQC_PHY_AN_EN_CLAUSE37))
5925	return true;
5926
5927	return false;
5928	}
5929
5930	/**
5931	* ice_is_fw_health_report_supported - checks if firmware supports health events
5932	* @hw: pointer to the hardware structure
5933	*
5934	* Return: true if firmware supports health status reports,
5935	* false otherwise
5936	*/
5937	bool ice_is_fw_health_report_supported(struct ice_hw *hw)
5938	{
5939	return ice_is_fw_api_min_ver(hw, ICE_FW_API_HEALTH_REPORT_MAJ,
5940	ICE_FW_API_HEALTH_REPORT_MIN,
5941	ICE_FW_API_HEALTH_REPORT_PATCH);
5942	}
5943
5944	/**
5945	* ice_aq_set_health_status_cfg - Configure FW health events
5946	* @hw: pointer to the HW struct
5947	* @event_source: type of diagnostic events to enable
5948	*
5949	* Configure the health status event types that the firmware will send to this
5950	* PF. The supported event types are: PF-specific, all PFs, and global.
5951	*
5952	* Return: 0 on success, negative error code otherwise.
5953	*/
5954	int ice_aq_set_health_status_cfg(struct ice_hw *hw, u8 event_source)
5955	{
5956	struct ice_aqc_set_health_status_cfg *cmd;
5957	struct ice_aq_desc desc;
5958
5959	cmd = &desc.params.set_health_status_cfg;
5960
5961	ice_fill_dflt_direct_cmd_desc(desc: &desc, opcode: ice_aqc_opc_set_health_status_cfg);
5962
5963	cmd->event_source = event_source;
5964
5965	return ice_aq_send_cmd(hw, desc: &desc, NULL, buf_size: 0, NULL);
5966	}
5967
5968	/**
5969	* ice_aq_set_lldp_mib - Set the LLDP MIB
5970	* @hw: pointer to the HW struct
5971	* @mib_type: Local, Remote or both Local and Remote MIBs
5972	* @buf: pointer to the caller-supplied buffer to store the MIB block
5973	* @buf_size: size of the buffer (in bytes)
5974	* @cd: pointer to command details structure or NULL
5975	*
5976	* Set the LLDP MIB. (0x0A08)
5977	*/
5978	int
5979	ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size,
5980	struct ice_sq_cd *cd)
5981	{
5982	struct ice_aqc_lldp_set_local_mib *cmd;
5983	struct ice_aq_desc desc;
5984
5985	cmd = &desc.params.lldp_set_mib;
5986
5987	if (buf_size == 0 || !buf)
5988	return -EINVAL;
5989
5990	ice_fill_dflt_direct_cmd_desc(desc: &desc, opcode: ice_aqc_opc_lldp_set_local_mib);
5991
5992	desc.flags |= cpu_to_le16((u16)ICE_AQ_FLAG_RD);
5993	desc.datalen = cpu_to_le16(buf_size);
5994
5995	cmd->type = mib_type;
5996	cmd->length = cpu_to_le16(buf_size);
5997
5998	return ice_aq_send_cmd(hw, desc: &desc, buf, buf_size, cd);
5999	}
6000
6001	/**
6002	* ice_fw_supports_lldp_fltr_ctrl - check NVM version supports lldp_fltr_ctrl
6003	* @hw: pointer to HW struct
6004	*/
6005	bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw)
6006	{
6007	if (hw->mac_type != ICE_MAC_E810)
6008	return false;
6009
6010	return ice_is_fw_api_min_ver(hw, ICE_FW_API_LLDP_FLTR_MAJ,
6011	ICE_FW_API_LLDP_FLTR_MIN,
6012	ICE_FW_API_LLDP_FLTR_PATCH);
6013	}
6014
6015	/**
6016	* ice_lldp_fltr_add_remove - add or remove a LLDP Rx switch filter
6017	* @hw: pointer to HW struct
6018	* @vsi: VSI to add the filter to
6019	* @add: boolean for if adding or removing a filter
6020	*
6021	* Return: 0 on success, -EOPNOTSUPP if the operation cannot be performed
6022	* with this HW or VSI, otherwise an error corresponding to
6023	* the AQ transaction result.
6024	*/
6025	int ice_lldp_fltr_add_remove(struct ice_hw *hw, struct ice_vsi *vsi, bool add)
6026	{
6027	struct ice_aqc_lldp_filter_ctrl *cmd;
6028	struct ice_aq_desc desc;
6029
6030	if (vsi->type != ICE_VSI_PF || !ice_fw_supports_lldp_fltr_ctrl(hw))
6031	return -EOPNOTSUPP;
6032
6033	cmd = &desc.params.lldp_filter_ctrl;
6034
6035	ice_fill_dflt_direct_cmd_desc(desc: &desc, opcode: ice_aqc_opc_lldp_filter_ctrl);
6036
6037	if (add)
6038	cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_ADD;
6039	else
6040	cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_DELETE;
6041
6042	cmd->vsi_num = cpu_to_le16(vsi->vsi_num);
6043
6044	return ice_aq_send_cmd(hw, desc: &desc, NULL, buf_size: 0, NULL);
6045	}
6046
6047	/**
6048	* ice_lldp_execute_pending_mib - execute LLDP pending MIB request
6049	* @hw: pointer to HW struct
6050	*/
6051	int ice_lldp_execute_pending_mib(struct ice_hw *hw)
6052	{
6053	struct ice_aq_desc desc;
6054
6055	ice_fill_dflt_direct_cmd_desc(desc: &desc, opcode: ice_aqc_opc_lldp_execute_pending_mib);
6056
6057	return ice_aq_send_cmd(hw, desc: &desc, NULL, buf_size: 0, NULL);
6058	}
6059
6060	/**
6061	* ice_fw_supports_report_dflt_cfg
6062	* @hw: pointer to the hardware structure
6063	*
6064	* Checks if the firmware supports report default configuration
6065	*/
6066	bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw)
6067	{
6068	return ice_is_fw_api_min_ver(hw, ICE_FW_API_REPORT_DFLT_CFG_MAJ,
6069	ICE_FW_API_REPORT_DFLT_CFG_MIN,
6070	ICE_FW_API_REPORT_DFLT_CFG_PATCH);
6071	}
6072
6073	/* each of the indexes into the following array match the speed of a return
6074	* value from the list of AQ returned speeds like the range:
6075	* ICE_AQ_LINK_SPEED_10MB .. ICE_AQ_LINK_SPEED_100GB excluding
6076	* ICE_AQ_LINK_SPEED_UNKNOWN which is BIT(15) and maps to BIT(14) in this
6077	* array. The array is defined as 15 elements long because the link_speed
6078	* returned by the firmware is a 16 bit * value, but is indexed
6079	* by [fls(speed) - 1]
6080	*/
6081	static const u32 ice_aq_to_link_speed[] = {
6082	SPEED_10, /* BIT(0) */
6083	SPEED_100,
6084	SPEED_1000,
6085	SPEED_2500,
6086	SPEED_5000,
6087	SPEED_10000,
6088	SPEED_20000,
6089	SPEED_25000,
6090	SPEED_40000,
6091	SPEED_50000,
6092	SPEED_100000, /* BIT(10) */
6093	SPEED_200000,
6094	};
6095
6096	/**
6097	* ice_get_link_speed - get integer speed from table
6098	* @index: array index from fls(aq speed) - 1
6099	*
6100	* Returns: u32 value containing integer speed
6101	*/
6102	u32 ice_get_link_speed(u16 index)
6103	{
6104	if (index >= ARRAY_SIZE(ice_aq_to_link_speed))
6105	return 0;
6106
6107	return ice_aq_to_link_speed[index];
6108	}
6109