1	/*
2	* Performance events x86 architecture code
3	*
4	* Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5	* Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6	* Copyright (C) 2009 Jaswinder Singh Rajput
7	* Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8	* Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra
9	* Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10	* Copyright (C) 2009 Google, Inc., Stephane Eranian
11	*
12	* For licencing details see kernel-base/COPYING
13	*/
14
15	#include <linux/perf_event.h>
16	#include <linux/capability.h>
17	#include <linux/notifier.h>
18	#include <linux/hardirq.h>
19	#include <linux/kprobes.h>
20	#include <linux/export.h>
21	#include <linux/init.h>
22	#include <linux/kdebug.h>
23	#include <linux/sched/mm.h>
24	#include <linux/sched/clock.h>
25	#include <linux/uaccess.h>
26	#include <linux/slab.h>
27	#include <linux/cpu.h>
28	#include <linux/bitops.h>
29	#include <linux/device.h>
30	#include <linux/nospec.h>
31	#include <linux/static_call.h>
32
33	#include <asm/apic.h>
34	#include <asm/stacktrace.h>
35	#include <asm/nmi.h>
36	#include <asm/smp.h>
37	#include <asm/alternative.h>
38	#include <asm/mmu_context.h>
39	#include <asm/tlbflush.h>
40	#include <asm/timer.h>
41	#include <asm/desc.h>
42	#include <asm/ldt.h>
43	#include <asm/unwind.h>
44
45	#include "perf_event.h"
46
47	struct x86_pmu x86_pmu __read_mostly;
48	static struct pmu pmu;
49
50	DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
51	.enabled = 1,
52	.pmu = &pmu,
53	};
54
55	DEFINE_STATIC_KEY_FALSE(rdpmc_never_available_key);
56	DEFINE_STATIC_KEY_FALSE(rdpmc_always_available_key);
57	DEFINE_STATIC_KEY_FALSE(perf_is_hybrid);
58
59	/*
60	* This here uses DEFINE_STATIC_CALL_NULL() to get a static_call defined
61	* from just a typename, as opposed to an actual function.
62	*/
63	DEFINE_STATIC_CALL_NULL(x86_pmu_handle_irq, *x86_pmu.handle_irq);
64	DEFINE_STATIC_CALL_NULL(x86_pmu_disable_all, *x86_pmu.disable_all);
65	DEFINE_STATIC_CALL_NULL(x86_pmu_enable_all, *x86_pmu.enable_all);
66	DEFINE_STATIC_CALL_NULL(x86_pmu_enable, *x86_pmu.enable);
67	DEFINE_STATIC_CALL_NULL(x86_pmu_disable, *x86_pmu.disable);
68
69	DEFINE_STATIC_CALL_NULL(x86_pmu_assign, *x86_pmu.assign);
70
71	DEFINE_STATIC_CALL_NULL(x86_pmu_add, *x86_pmu.add);
72	DEFINE_STATIC_CALL_NULL(x86_pmu_del, *x86_pmu.del);
73	DEFINE_STATIC_CALL_NULL(x86_pmu_read, *x86_pmu.read);
74
75	DEFINE_STATIC_CALL_NULL(x86_pmu_set_period, *x86_pmu.set_period);
76	DEFINE_STATIC_CALL_NULL(x86_pmu_update, *x86_pmu.update);
77	DEFINE_STATIC_CALL_NULL(x86_pmu_limit_period, *x86_pmu.limit_period);
78
79	DEFINE_STATIC_CALL_NULL(x86_pmu_schedule_events, *x86_pmu.schedule_events);
80	DEFINE_STATIC_CALL_NULL(x86_pmu_get_event_constraints, *x86_pmu.get_event_constraints);
81	DEFINE_STATIC_CALL_NULL(x86_pmu_put_event_constraints, *x86_pmu.put_event_constraints);
82
83	DEFINE_STATIC_CALL_NULL(x86_pmu_start_scheduling, *x86_pmu.start_scheduling);
84	DEFINE_STATIC_CALL_NULL(x86_pmu_commit_scheduling, *x86_pmu.commit_scheduling);
85	DEFINE_STATIC_CALL_NULL(x86_pmu_stop_scheduling, *x86_pmu.stop_scheduling);
86
87	DEFINE_STATIC_CALL_NULL(x86_pmu_sched_task, *x86_pmu.sched_task);
88	DEFINE_STATIC_CALL_NULL(x86_pmu_swap_task_ctx, *x86_pmu.swap_task_ctx);
89
90	DEFINE_STATIC_CALL_NULL(x86_pmu_drain_pebs, *x86_pmu.drain_pebs);
91	DEFINE_STATIC_CALL_NULL(x86_pmu_pebs_aliases, *x86_pmu.pebs_aliases);
92
93	DEFINE_STATIC_CALL_NULL(x86_pmu_filter, *x86_pmu.filter);
94
95	/*
96	* This one is magic, it will get called even when PMU init fails (because
97	* there is no PMU), in which case it should simply return NULL.
98	*/
99	DEFINE_STATIC_CALL_RET0(x86_pmu_guest_get_msrs, *x86_pmu.guest_get_msrs);
100
101	u64 __read_mostly hw_cache_event_ids
102	[PERF_COUNT_HW_CACHE_MAX]
103	[PERF_COUNT_HW_CACHE_OP_MAX]
104	[PERF_COUNT_HW_CACHE_RESULT_MAX];
105	u64 __read_mostly hw_cache_extra_regs
106	[PERF_COUNT_HW_CACHE_MAX]
107	[PERF_COUNT_HW_CACHE_OP_MAX]
108	[PERF_COUNT_HW_CACHE_RESULT_MAX];
109
110	/*
111	* Propagate event elapsed time into the generic event.
112	* Can only be executed on the CPU where the event is active.
113	* Returns the delta events processed.
114	*/
115	u64 x86_perf_event_update(struct perf_event *event)
116	{
117	struct hw_perf_event *hwc = &event->hw;
118	int shift = 64 - x86_pmu.cntval_bits;
119	u64 prev_raw_count, new_raw_count;
120	u64 delta;
121
122	if (unlikely(!hwc->event_base))
123	return 0;
124
125	/*
126	* Careful: an NMI might modify the previous event value.
127	*
128	* Our tactic to handle this is to first atomically read and
129	* exchange a new raw count - then add that new-prev delta
130	* count to the generic event atomically:
131	*/
132	prev_raw_count = local64_read(&hwc->prev_count);
133	do {
134	rdpmcl(hwc->event_base_rdpmc, new_raw_count);
135	} while (!local64_try_cmpxchg(l: &hwc->prev_count,
136	old: &prev_raw_count, new: new_raw_count));
137
138	/*
139	* Now we have the new raw value and have updated the prev
140	* timestamp already. We can now calculate the elapsed delta
141	* (event-)time and add that to the generic event.
142	*
143	* Careful, not all hw sign-extends above the physical width
144	* of the count.
145	*/
146	delta = (new_raw_count << shift) - (prev_raw_count << shift);
147	delta >>= shift;
148
149	local64_add(delta, &event->count);
150	local64_sub(delta, &hwc->period_left);
151
152	return new_raw_count;
153	}
154
155	/*
156	* Find and validate any extra registers to set up.
157	*/
158	static int x86_pmu_extra_regs(u64 config, struct perf_event *event)
159	{
160	struct extra_reg *extra_regs = hybrid(event->pmu, extra_regs);
161	struct hw_perf_event_extra *reg;
162	struct extra_reg *er;
163
164	reg = &event->hw.extra_reg;
165
166	if (!extra_regs)
167	return 0;
168
169	for (er = extra_regs; er->msr; er++) {
170	if (er->event != (config & er->config_mask))
171	continue;
172	if (event->attr.config1 & ~er->valid_mask)
173	return -EINVAL;
174	/* Check if the extra msrs can be safely accessed*/
175	if (!er->extra_msr_access)
176	return -ENXIO;
177
178	reg->idx = er->idx;
179	reg->config = event->attr.config1;
180	reg->reg = er->msr;
181	break;
182	}
183	return 0;
184	}
185
186	static atomic_t active_events;
187	static atomic_t pmc_refcount;
188	static DEFINE_MUTEX(pmc_reserve_mutex);
189
190	#ifdef CONFIG_X86_LOCAL_APIC
191
192	static inline int get_possible_num_counters(void)
193	{
194	int i, num_counters = x86_pmu.num_counters;
195
196	if (!is_hybrid())
197	return num_counters;
198
199	for (i = 0; i < x86_pmu.num_hybrid_pmus; i++)
200	num_counters = max_t(int, num_counters, x86_pmu.hybrid_pmu[i].num_counters);
201
202	return num_counters;
203	}
204
205	static bool reserve_pmc_hardware(void)
206	{
207	int i, num_counters = get_possible_num_counters();
208
209	for (i = 0; i < num_counters; i++) {
210	if (!reserve_perfctr_nmi(x86_pmu_event_addr(index: i)))
211	goto perfctr_fail;
212	}
213
214	for (i = 0; i < num_counters; i++) {
215	if (!reserve_evntsel_nmi(x86_pmu_config_addr(index: i)))
216	goto eventsel_fail;
217	}
218
219	return true;
220
221	eventsel_fail:
222	for (i--; i >= 0; i--)
223	release_evntsel_nmi(x86_pmu_config_addr(index: i));
224
225	i = num_counters;
226
227	perfctr_fail:
228	for (i--; i >= 0; i--)
229	release_perfctr_nmi(x86_pmu_event_addr(index: i));
230
231	return false;
232	}
233
234	static void release_pmc_hardware(void)
235	{
236	int i, num_counters = get_possible_num_counters();
237
238	for (i = 0; i < num_counters; i++) {
239	release_perfctr_nmi(x86_pmu_event_addr(index: i));
240	release_evntsel_nmi(x86_pmu_config_addr(index: i));
241	}
242	}
243
244	#else
245
246	static bool reserve_pmc_hardware(void) { return true; }
247	static void release_pmc_hardware(void) {}
248
249	#endif
250
251	bool check_hw_exists(struct pmu *pmu, int num_counters, int num_counters_fixed)
252	{
253	u64 val, val_fail = -1, val_new= ~0;
254	int i, reg, reg_fail = -1, ret = 0;
255	int bios_fail = 0;
256	int reg_safe = -1;
257
258	/*
259	* Check to see if the BIOS enabled any of the counters, if so
260	* complain and bail.
261	*/
262	for (i = 0; i < num_counters; i++) {
263	reg = x86_pmu_config_addr(index: i);
264	ret = rdmsrl_safe(msr: reg, p: &val);
265	if (ret)
266	goto msr_fail;
267	if (val & ARCH_PERFMON_EVENTSEL_ENABLE) {
268	bios_fail = 1;
269	val_fail = val;
270	reg_fail = reg;
271	} else {
272	reg_safe = i;
273	}
274	}
275
276	if (num_counters_fixed) {
277	reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
278	ret = rdmsrl_safe(msr: reg, p: &val);
279	if (ret)
280	goto msr_fail;
281	for (i = 0; i < num_counters_fixed; i++) {
282	if (fixed_counter_disabled(i, pmu))
283	continue;
284	if (val & (0x03ULL << i*4)) {
285	bios_fail = 1;
286	val_fail = val;
287	reg_fail = reg;
288	}
289	}
290	}
291
292	/*
293	* If all the counters are enabled, the below test will always
294	* fail. The tools will also become useless in this scenario.
295	* Just fail and disable the hardware counters.
296	*/
297
298	if (reg_safe == -1) {
299	reg = reg_safe;
300	goto msr_fail;
301	}
302
303	/*
304	* Read the current value, change it and read it back to see if it
305	* matches, this is needed to detect certain hardware emulators
306	* (qemu/kvm) that don't trap on the MSR access and always return 0s.
307	*/
308	reg = x86_pmu_event_addr(index: reg_safe);
309	if (rdmsrl_safe(msr: reg, p: &val))
310	goto msr_fail;
311	val ^= 0xffffUL;
312	ret = wrmsrl_safe(msr: reg, val);
313	ret |= rdmsrl_safe(msr: reg, p: &val_new);
314	if (ret || val != val_new)
315	goto msr_fail;
316
317	/*
318	* We still allow the PMU driver to operate:
319	*/
320	if (bios_fail) {
321	pr_cont("Broken BIOS detected, complain to your hardware vendor.\n");
322	pr_err(FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n",
323	reg_fail, val_fail);
324	}
325
326	return true;
327
328	msr_fail:
329	if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
330	pr_cont("PMU not available due to virtualization, using software events only.\n");
331	} else {
332	pr_cont("Broken PMU hardware detected, using software events only.\n");
333	pr_err("Failed to access perfctr msr (MSR %x is %Lx)\n",
334	reg, val_new);
335	}
336
337	return false;
338	}
339
340	static void hw_perf_event_destroy(struct perf_event *event)
341	{
342	x86_release_hardware();
343	atomic_dec(v: &active_events);
344	}
345
346	void hw_perf_lbr_event_destroy(struct perf_event *event)
347	{
348	hw_perf_event_destroy(event);
349
350	/* undo the lbr/bts event accounting */
351	x86_del_exclusive(what: x86_lbr_exclusive_lbr);
352	}
353
354	static inline int x86_pmu_initialized(void)
355	{
356	return x86_pmu.handle_irq != NULL;
357	}
358
359	static inline int
360	set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event)
361	{
362	struct perf_event_attr *attr = &event->attr;
363	unsigned int cache_type, cache_op, cache_result;
364	u64 config, val;
365
366	config = attr->config;
367
368	cache_type = (config >> 0) & 0xff;
369	if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
370	return -EINVAL;
371	cache_type = array_index_nospec(cache_type, PERF_COUNT_HW_CACHE_MAX);
372
373	cache_op = (config >> 8) & 0xff;
374	if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
375	return -EINVAL;
376	cache_op = array_index_nospec(cache_op, PERF_COUNT_HW_CACHE_OP_MAX);
377
378	cache_result = (config >> 16) & 0xff;
379	if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
380	return -EINVAL;
381	cache_result = array_index_nospec(cache_result, PERF_COUNT_HW_CACHE_RESULT_MAX);
382
383	val = hybrid_var(event->pmu, hw_cache_event_ids)[cache_type][cache_op][cache_result];
384	if (val == 0)
385	return -ENOENT;
386
387	if (val == -1)
388	return -EINVAL;
389
390	hwc->config |= val;
391	attr->config1 = hybrid_var(event->pmu, hw_cache_extra_regs)[cache_type][cache_op][cache_result];
392	return x86_pmu_extra_regs(config: val, event);
393	}
394
395	int x86_reserve_hardware(void)
396	{
397	int err = 0;
398
399	if (!atomic_inc_not_zero(v: &pmc_refcount)) {
400	mutex_lock(&pmc_reserve_mutex);
401	if (atomic_read(v: &pmc_refcount) == 0) {
402	if (!reserve_pmc_hardware()) {
403	err = -EBUSY;
404	} else {
405	reserve_ds_buffers();
406	reserve_lbr_buffers();
407	}
408	}
409	if (!err)
410	atomic_inc(v: &pmc_refcount);
411	mutex_unlock(lock: &pmc_reserve_mutex);
412	}
413
414	return err;
415	}
416
417	void x86_release_hardware(void)
418	{
419	if (atomic_dec_and_mutex_lock(cnt: &pmc_refcount, lock: &pmc_reserve_mutex)) {
420	release_pmc_hardware();
421	release_ds_buffers();
422	release_lbr_buffers();
423	mutex_unlock(lock: &pmc_reserve_mutex);
424	}
425	}
426
427	/*
428	* Check if we can create event of a certain type (that no conflicting events
429	* are present).
430	*/
431	int x86_add_exclusive(unsigned int what)
432	{
433	int i;
434
435	/*
436	* When lbr_pt_coexist we allow PT to coexist with either LBR or BTS.
437	* LBR and BTS are still mutually exclusive.
438	*/
439	if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt)
440	goto out;
441
442	if (!atomic_inc_not_zero(v: &x86_pmu.lbr_exclusive[what])) {
443	mutex_lock(&pmc_reserve_mutex);
444	for (i = 0; i < ARRAY_SIZE(x86_pmu.lbr_exclusive); i++) {
445	if (i != what && atomic_read(v: &x86_pmu.lbr_exclusive[i]))
446	goto fail_unlock;
447	}
448	atomic_inc(v: &x86_pmu.lbr_exclusive[what]);
449	mutex_unlock(lock: &pmc_reserve_mutex);
450	}
451
452	out:
453	atomic_inc(v: &active_events);
454	return 0;
455
456	fail_unlock:
457	mutex_unlock(lock: &pmc_reserve_mutex);
458	return -EBUSY;
459	}
460
461	void x86_del_exclusive(unsigned int what)
462	{
463	atomic_dec(v: &active_events);
464
465	/*
466	* See the comment in x86_add_exclusive().
467	*/
468	if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt)
469	return;
470
471	atomic_dec(v: &x86_pmu.lbr_exclusive[what]);
472	}
473
474	int x86_setup_perfctr(struct perf_event *event)
475	{
476	struct perf_event_attr *attr = &event->attr;
477	struct hw_perf_event *hwc = &event->hw;
478	u64 config;
479
480	if (!is_sampling_event(event)) {
481	hwc->sample_period = x86_pmu.max_period;
482	hwc->last_period = hwc->sample_period;
483	local64_set(&hwc->period_left, hwc->sample_period);
484	}
485
486	if (attr->type == event->pmu->type)
487	return x86_pmu_extra_regs(config: event->attr.config, event);
488
489	if (attr->type == PERF_TYPE_HW_CACHE)
490	return set_ext_hw_attr(hwc, event);
491
492	if (attr->config >= x86_pmu.max_events)
493	return -EINVAL;
494
495	attr->config = array_index_nospec((unsigned long)attr->config, x86_pmu.max_events);
496
497	/*
498	* The generic map:
499	*/
500	config = x86_pmu.event_map(attr->config);
501
502	if (config == 0)
503	return -ENOENT;
504
505	if (config == -1LL)
506	return -EINVAL;
507
508	hwc->config |= config;
509
510	return 0;
511	}
512
513	/*
514	* check that branch_sample_type is compatible with
515	* settings needed for precise_ip > 1 which implies
516	* using the LBR to capture ALL taken branches at the
517	* priv levels of the measurement
518	*/
519	static inline int precise_br_compat(struct perf_event *event)
520	{
521	u64 m = event->attr.branch_sample_type;
522	u64 b = 0;
523
524	/* must capture all branches */
525	if (!(m & PERF_SAMPLE_BRANCH_ANY))
526	return 0;
527
528	m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER;
529
530	if (!event->attr.exclude_user)
531	b |= PERF_SAMPLE_BRANCH_USER;
532
533	if (!event->attr.exclude_kernel)
534	b |= PERF_SAMPLE_BRANCH_KERNEL;
535
536	/*
537	* ignore PERF_SAMPLE_BRANCH_HV, not supported on x86
538	*/
539
540	return m == b;
541	}
542
543	int x86_pmu_max_precise(void)
544	{
545	int precise = 0;
546
547	/* Support for constant skid */
548	if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) {
549	precise++;
550
551	/* Support for IP fixup */
552	if (x86_pmu.lbr_nr || x86_pmu.intel_cap.pebs_format >= 2)
553	precise++;
554
555	if (x86_pmu.pebs_prec_dist)
556	precise++;
557	}
558	return precise;
559	}
560
561	int x86_pmu_hw_config(struct perf_event *event)
562	{
563	if (event->attr.precise_ip) {
564	int precise = x86_pmu_max_precise();
565
566	if (event->attr.precise_ip > precise)
567	return -EOPNOTSUPP;
568
569	/* There's no sense in having PEBS for non sampling events: */
570	if (!is_sampling_event(event))
571	return -EINVAL;
572	}
573	/*
574	* check that PEBS LBR correction does not conflict with
575	* whatever the user is asking with attr->branch_sample_type
576	*/
577	if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format < 2) {
578	u64 *br_type = &event->attr.branch_sample_type;
579
580	if (has_branch_stack(event)) {
581	if (!precise_br_compat(event))
582	return -EOPNOTSUPP;
583
584	/* branch_sample_type is compatible */
585
586	} else {
587	/*
588	* user did not specify branch_sample_type
589	*
590	* For PEBS fixups, we capture all
591	* the branches at the priv level of the
592	* event.
593	*/
594	*br_type = PERF_SAMPLE_BRANCH_ANY;
595
596	if (!event->attr.exclude_user)
597	*br_type |= PERF_SAMPLE_BRANCH_USER;
598
599	if (!event->attr.exclude_kernel)
600	*br_type |= PERF_SAMPLE_BRANCH_KERNEL;
601	}
602	}
603
604	if (branch_sample_call_stack(event))
605	event->attach_state |= PERF_ATTACH_TASK_DATA;
606
607	/*
608	* Generate PMC IRQs:
609	* (keep 'enabled' bit clear for now)
610	*/
611	event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
612
613	/*
614	* Count user and OS events unless requested not to
615	*/
616	if (!event->attr.exclude_user)
617	event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
618	if (!event->attr.exclude_kernel)
619	event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
620
621	if (event->attr.type == event->pmu->type)
622	event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
623
624	if (event->attr.sample_period && x86_pmu.limit_period) {
625	s64 left = event->attr.sample_period;
626	x86_pmu.limit_period(event, &left);
627	if (left > event->attr.sample_period)
628	return -EINVAL;
629	}
630
631	/* sample_regs_user never support XMM registers */
632	if (unlikely(event->attr.sample_regs_user & PERF_REG_EXTENDED_MASK))
633	return -EINVAL;
634	/*
635	* Besides the general purpose registers, XMM registers may
636	* be collected in PEBS on some platforms, e.g. Icelake
637	*/
638	if (unlikely(event->attr.sample_regs_intr & PERF_REG_EXTENDED_MASK)) {
639	if (!(event->pmu->capabilities & PERF_PMU_CAP_EXTENDED_REGS))
640	return -EINVAL;
641
642	if (!event->attr.precise_ip)
643	return -EINVAL;
644	}
645
646	return x86_setup_perfctr(event);
647	}
648
649	/*
650	* Setup the hardware configuration for a given attr_type
651	*/
652	static int __x86_pmu_event_init(struct perf_event *event)
653	{
654	int err;
655
656	if (!x86_pmu_initialized())
657	return -ENODEV;
658
659	err = x86_reserve_hardware();
660	if (err)
661	return err;
662
663	atomic_inc(v: &active_events);
664	event->destroy = hw_perf_event_destroy;
665
666	event->hw.idx = -1;
667	event->hw.last_cpu = -1;
668	event->hw.last_tag = ~0ULL;
669
670	/* mark unused */
671	event->hw.extra_reg.idx = EXTRA_REG_NONE;
672	event->hw.branch_reg.idx = EXTRA_REG_NONE;
673
674	return x86_pmu.hw_config(event);
675	}
676
677	void x86_pmu_disable_all(void)
678	{
679	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
680	int idx;
681
682	for (idx = 0; idx < x86_pmu.num_counters; idx++) {
683	struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
684	u64 val;
685
686	if (!test_bit(idx, cpuc->active_mask))
687	continue;
688	rdmsrl(x86_pmu_config_addr(idx), val);
689	if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
690	continue;
691	val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
692	wrmsrl(msr: x86_pmu_config_addr(index: idx), val);
693	if (is_counter_pair(hwc))
694	wrmsrl(msr: x86_pmu_config_addr(index: idx + 1), val: 0);
695	}
696	}
697
698	struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr, void *data)
699	{
700	return static_call(x86_pmu_guest_get_msrs)(nr, data);
701	}
702	EXPORT_SYMBOL_GPL(perf_guest_get_msrs);
703
704	/*
705	* There may be PMI landing after enabled=0. The PMI hitting could be before or
706	* after disable_all.
707	*
708	* If PMI hits before disable_all, the PMU will be disabled in the NMI handler.
709	* It will not be re-enabled in the NMI handler again, because enabled=0. After
710	* handling the NMI, disable_all will be called, which will not change the
711	* state either. If PMI hits after disable_all, the PMU is already disabled
712	* before entering NMI handler. The NMI handler will not change the state
713	* either.
714	*
715	* So either situation is harmless.
716	*/
717	static void x86_pmu_disable(struct pmu *pmu)
718	{
719	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
720
721	if (!x86_pmu_initialized())
722	return;
723
724	if (!cpuc->enabled)
725	return;
726
727	cpuc->n_added = 0;
728	cpuc->enabled = 0;
729	barrier();
730
731	static_call(x86_pmu_disable_all)();
732	}
733
734	void x86_pmu_enable_all(int added)
735	{
736	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
737	int idx;
738
739	for (idx = 0; idx < x86_pmu.num_counters; idx++) {
740	struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
741
742	if (!test_bit(idx, cpuc->active_mask))
743	continue;
744
745	__x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
746	}
747	}
748
749	static inline int is_x86_event(struct perf_event *event)
750	{
751	int i;
752
753	if (!is_hybrid())
754	return event->pmu == &pmu;
755
756	for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) {
757	if (event->pmu == &x86_pmu.hybrid_pmu[i].pmu)
758	return true;
759	}
760
761	return false;
762	}
763
764	struct pmu *x86_get_pmu(unsigned int cpu)
765	{
766	struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
767
768	/*
769	* All CPUs of the hybrid type have been offline.
770	* The x86_get_pmu() should not be invoked.
771	*/
772	if (WARN_ON_ONCE(!cpuc->pmu))
773	return &pmu;
774
775	return cpuc->pmu;
776	}
777	/*
778	* Event scheduler state:
779	*
780	* Assign events iterating over all events and counters, beginning
781	* with events with least weights first. Keep the current iterator
782	* state in struct sched_state.
783	*/
784	struct sched_state {
785	int weight;
786	int event; /* event index */
787	int counter; /* counter index */
788	int unassigned; /* number of events to be assigned left */
789	int nr_gp; /* number of GP counters used */
790	u64 used;
791	};
792
793	/* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */
794	#define SCHED_STATES_MAX 2
795
796	struct perf_sched {
797	int max_weight;
798	int max_events;
799	int max_gp;
800	int saved_states;
801	struct event_constraint **constraints;
802	struct sched_state state;
803	struct sched_state saved[SCHED_STATES_MAX];
804	};
805
806	/*
807	* Initialize iterator that runs through all events and counters.
808	*/
809	static void perf_sched_init(struct perf_sched *sched, struct event_constraint **constraints,
810	int num, int wmin, int wmax, int gpmax)
811	{
812	int idx;
813
814	memset(sched, 0, sizeof(*sched));
815	sched->max_events = num;
816	sched->max_weight = wmax;
817	sched->max_gp = gpmax;
818	sched->constraints = constraints;
819
820	for (idx = 0; idx < num; idx++) {
821	if (constraints[idx]->weight == wmin)
822	break;
823	}
824
825	sched->state.event = idx; /* start with min weight */
826	sched->state.weight = wmin;
827	sched->state.unassigned = num;
828	}
829
830	static void perf_sched_save_state(struct perf_sched *sched)
831	{
832	if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX))
833	return;
834
835	sched->saved[sched->saved_states] = sched->state;
836	sched->saved_states++;
837	}
838
839	static bool perf_sched_restore_state(struct perf_sched *sched)
840	{
841	if (!sched->saved_states)
842	return false;
843
844	sched->saved_states--;
845	sched->state = sched->saved[sched->saved_states];
846
847	/* this assignment didn't work out */
848	/* XXX broken vs EVENT_PAIR */
849	sched->state.used &= ~BIT_ULL(sched->state.counter);
850
851	/* try the next one */
852	sched->state.counter++;
853
854	return true;
855	}
856
857	/*
858	* Select a counter for the current event to schedule. Return true on
859	* success.
860	*/
861	static bool __perf_sched_find_counter(struct perf_sched *sched)
862	{
863	struct event_constraint *c;
864	int idx;
865
866	if (!sched->state.unassigned)
867	return false;
868
869	if (sched->state.event >= sched->max_events)
870	return false;
871
872	c = sched->constraints[sched->state.event];
873	/* Prefer fixed purpose counters */
874	if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) {
875	idx = INTEL_PMC_IDX_FIXED;
876	for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) {
877	u64 mask = BIT_ULL(idx);
878
879	if (sched->state.used & mask)
880	continue;
881
882	sched->state.used |= mask;
883	goto done;
884	}
885	}
886
887	/* Grab the first unused counter starting with idx */
888	idx = sched->state.counter;
889	for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) {
890	u64 mask = BIT_ULL(idx);
891
892	if (c->flags & PERF_X86_EVENT_PAIR)
893	mask |= mask << 1;
894
895	if (sched->state.used & mask)
896	continue;
897
898	if (sched->state.nr_gp++ >= sched->max_gp)
899	return false;
900
901	sched->state.used |= mask;
902	goto done;
903	}
904
905	return false;
906
907	done:
908	sched->state.counter = idx;
909
910	if (c->overlap)
911	perf_sched_save_state(sched);
912
913	return true;
914	}
915
916	static bool perf_sched_find_counter(struct perf_sched *sched)
917	{
918	while (!__perf_sched_find_counter(sched)) {
919	if (!perf_sched_restore_state(sched))
920	return false;
921	}
922
923	return true;
924	}
925
926	/*
927	* Go through all unassigned events and find the next one to schedule.
928	* Take events with the least weight first. Return true on success.
929	*/
930	static bool perf_sched_next_event(struct perf_sched *sched)
931	{
932	struct event_constraint *c;
933
934	if (!sched->state.unassigned || !--sched->state.unassigned)
935	return false;
936
937	do {
938	/* next event */
939	sched->state.event++;
940	if (sched->state.event >= sched->max_events) {
941	/* next weight */
942	sched->state.event = 0;
943	sched->state.weight++;
944	if (sched->state.weight > sched->max_weight)
945	return false;
946	}
947	c = sched->constraints[sched->state.event];
948	} while (c->weight != sched->state.weight);
949
950	sched->state.counter = 0; /* start with first counter */
951
952	return true;
953	}
954
955	/*
956	* Assign a counter for each event.
957	*/
958	int perf_assign_events(struct event_constraint **constraints, int n,
959	int wmin, int wmax, int gpmax, int *assign)
960	{
961	struct perf_sched sched;
962
963	perf_sched_init(sched: &sched, constraints, num: n, wmin, wmax, gpmax);
964
965	do {
966	if (!perf_sched_find_counter(sched: &sched))
967	break; /* failed */
968	if (assign)
969	assign[sched.state.event] = sched.state.counter;
970	} while (perf_sched_next_event(sched: &sched));
971
972	return sched.state.unassigned;
973	}
974	EXPORT_SYMBOL_GPL(perf_assign_events);
975
976	int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
977	{
978	int num_counters = hybrid(cpuc->pmu, num_counters);
979	struct event_constraint *c;
980	struct perf_event *e;
981	int n0, i, wmin, wmax, unsched = 0;
982	struct hw_perf_event *hwc;
983	u64 used_mask = 0;
984
985	/*
986	* Compute the number of events already present; see x86_pmu_add(),
987	* validate_group() and x86_pmu_commit_txn(). For the former two
988	* cpuc->n_events hasn't been updated yet, while for the latter
989	* cpuc->n_txn contains the number of events added in the current
990	* transaction.
991	*/
992	n0 = cpuc->n_events;
993	if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
994	n0 -= cpuc->n_txn;
995
996	static_call_cond(x86_pmu_start_scheduling)(cpuc);
997
998	for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) {
999	c = cpuc->event_constraint[i];
1000
1001	/*
1002	* Previously scheduled events should have a cached constraint,
1003	* while new events should not have one.
1004	*/
1005	WARN_ON_ONCE((c && i >= n0) || (!c && i < n0));
1006
1007	/*
1008	* Request constraints for new events; or for those events that
1009	* have a dynamic constraint -- for those the constraint can
1010	* change due to external factors (sibling state, allow_tfa).
1011	*/
1012	if (!c || (c->flags & PERF_X86_EVENT_DYNAMIC)) {
1013	c = static_call(x86_pmu_get_event_constraints)(cpuc, i, cpuc->event_list[i]);
1014	cpuc->event_constraint[i] = c;
1015	}
1016
1017	wmin = min(wmin, c->weight);
1018	wmax = max(wmax, c->weight);
1019	}
1020
1021	/*
1022	* fastpath, try to reuse previous register
1023	*/
1024	for (i = 0; i < n; i++) {
1025	u64 mask;
1026
1027	hwc = &cpuc->event_list[i]->hw;
1028	c = cpuc->event_constraint[i];
1029
1030	/* never assigned */
1031	if (hwc->idx == -1)
1032	break;
1033
1034	/* constraint still honored */
1035	if (!test_bit(hwc->idx, c->idxmsk))
1036	break;
1037
1038	mask = BIT_ULL(hwc->idx);
1039	if (is_counter_pair(hwc))
1040	mask |= mask << 1;
1041
1042	/* not already used */
1043	if (used_mask & mask)
1044	break;
1045
1046	used_mask |= mask;
1047
1048	if (assign)
1049	assign[i] = hwc->idx;
1050	}
1051
1052	/* slow path */
1053	if (i != n) {
1054	int gpmax = num_counters;
1055
1056	/*
1057	* Do not allow scheduling of more than half the available
1058	* generic counters.
1059	*
1060	* This helps avoid counter starvation of sibling thread by
1061	* ensuring at most half the counters cannot be in exclusive
1062	* mode. There is no designated counters for the limits. Any
1063	* N/2 counters can be used. This helps with events with
1064	* specific counter constraints.
1065	*/
1066	if (is_ht_workaround_enabled() && !cpuc->is_fake &&
1067	READ_ONCE(cpuc->excl_cntrs->exclusive_present))
1068	gpmax /= 2;
1069
1070	/*
1071	* Reduce the amount of available counters to allow fitting
1072	* the extra Merge events needed by large increment events.
1073	*/
1074	if (x86_pmu.flags & PMU_FL_PAIR) {
1075	gpmax = num_counters - cpuc->n_pair;
1076	WARN_ON(gpmax <= 0);
1077	}
1078
1079	unsched = perf_assign_events(cpuc->event_constraint, n, wmin,
1080	wmax, gpmax, assign);
1081	}
1082
1083	/*
1084	* In case of success (unsched = 0), mark events as committed,
1085	* so we do not put_constraint() in case new events are added
1086	* and fail to be scheduled
1087	*
1088	* We invoke the lower level commit callback to lock the resource
1089	*
1090	* We do not need to do all of this in case we are called to
1091	* validate an event group (assign == NULL)
1092	*/
1093	if (!unsched && assign) {
1094	for (i = 0; i < n; i++)
1095	static_call_cond(x86_pmu_commit_scheduling)(cpuc, i, assign[i]);
1096	} else {
1097	for (i = n0; i < n; i++) {
1098	e = cpuc->event_list[i];
1099
1100	/*
1101	* release events that failed scheduling
1102	*/
1103	static_call_cond(x86_pmu_put_event_constraints)(cpuc, e);
1104
1105	cpuc->event_constraint[i] = NULL;
1106	}
1107	}
1108
1109	static_call_cond(x86_pmu_stop_scheduling)(cpuc);
1110
1111	return unsched ? -EINVAL : 0;
1112	}
1113
1114	static int add_nr_metric_event(struct cpu_hw_events *cpuc,
1115	struct perf_event *event)
1116	{
1117	if (is_metric_event(event)) {
1118	if (cpuc->n_metric == INTEL_TD_METRIC_NUM)
1119	return -EINVAL;
1120	cpuc->n_metric++;
1121	cpuc->n_txn_metric++;
1122	}
1123
1124	return 0;
1125	}
1126
1127	static void del_nr_metric_event(struct cpu_hw_events *cpuc,
1128	struct perf_event *event)
1129	{
1130	if (is_metric_event(event))
1131	cpuc->n_metric--;
1132	}
1133
1134	static int collect_event(struct cpu_hw_events *cpuc, struct perf_event *event,
1135	int max_count, int n)
1136	{
1137	union perf_capabilities intel_cap = hybrid(cpuc->pmu, intel_cap);
1138
1139	if (intel_cap.perf_metrics && add_nr_metric_event(cpuc, event))
1140	return -EINVAL;
1141
1142	if (n >= max_count + cpuc->n_metric)
1143	return -EINVAL;
1144
1145	cpuc->event_list[n] = event;
1146	if (is_counter_pair(hwc: &event->hw)) {
1147	cpuc->n_pair++;
1148	cpuc->n_txn_pair++;
1149	}
1150
1151	return 0;
1152	}
1153
1154	/*
1155	* dogrp: true if must collect siblings events (group)
1156	* returns total number of events and error code
1157	*/
1158	static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
1159	{
1160	int num_counters = hybrid(cpuc->pmu, num_counters);
1161	int num_counters_fixed = hybrid(cpuc->pmu, num_counters_fixed);
1162	struct perf_event *event;
1163	int n, max_count;
1164
1165	max_count = num_counters + num_counters_fixed;
1166
1167	/* current number of events already accepted */
1168	n = cpuc->n_events;
1169	if (!cpuc->n_events)
1170	cpuc->pebs_output = 0;
1171
1172	if (!cpuc->is_fake && leader->attr.precise_ip) {
1173	/*
1174	* For PEBS->PT, if !aux_event, the group leader (PT) went
1175	* away, the group was broken down and this singleton event
1176	* can't schedule any more.
1177	*/
1178	if (is_pebs_pt(event: leader) && !leader->aux_event)
1179	return -EINVAL;
1180
1181	/*
1182	* pebs_output: 0: no PEBS so far, 1: PT, 2: DS
1183	*/
1184	if (cpuc->pebs_output &&
1185	cpuc->pebs_output != is_pebs_pt(event: leader) + 1)
1186	return -EINVAL;
1187
1188	cpuc->pebs_output = is_pebs_pt(event: leader) + 1;
1189	}
1190
1191	if (is_x86_event(event: leader)) {
1192	if (collect_event(cpuc, event: leader, max_count, n))
1193	return -EINVAL;
1194	n++;
1195	}
1196
1197	if (!dogrp)
1198	return n;
1199
1200	for_each_sibling_event(event, leader) {
1201	if (!is_x86_event(event) || event->state <= PERF_EVENT_STATE_OFF)
1202	continue;
1203
1204	if (collect_event(cpuc, event, max_count, n))
1205	return -EINVAL;
1206
1207	n++;
1208	}
1209	return n;
1210	}
1211
1212	static inline void x86_assign_hw_event(struct perf_event *event,
1213	struct cpu_hw_events *cpuc, int i)
1214	{
1215	struct hw_perf_event *hwc = &event->hw;
1216	int idx;
1217
1218	idx = hwc->idx = cpuc->assign[i];
1219	hwc->last_cpu = smp_processor_id();
1220	hwc->last_tag = ++cpuc->tags[i];
1221
1222	static_call_cond(x86_pmu_assign)(event, idx);
1223
1224	switch (hwc->idx) {
1225	case INTEL_PMC_IDX_FIXED_BTS:
1226	case INTEL_PMC_IDX_FIXED_VLBR:
1227	hwc->config_base = 0;
1228	hwc->event_base = 0;
1229	break;
1230
1231	case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END:
1232	/* All the metric events are mapped onto the fixed counter 3. */
1233	idx = INTEL_PMC_IDX_FIXED_SLOTS;
1234	fallthrough;
1235	case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS-1:
1236	hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
1237	hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 +
1238	(idx - INTEL_PMC_IDX_FIXED);
1239	hwc->event_base_rdpmc = (idx - INTEL_PMC_IDX_FIXED) |
1240	INTEL_PMC_FIXED_RDPMC_BASE;
1241	break;
1242
1243	default:
1244	hwc->config_base = x86_pmu_config_addr(index: hwc->idx);
1245	hwc->event_base = x86_pmu_event_addr(index: hwc->idx);
1246	hwc->event_base_rdpmc = x86_pmu_rdpmc_index(index: hwc->idx);
1247	break;
1248	}
1249	}
1250
1251	/**
1252	* x86_perf_rdpmc_index - Return PMC counter used for event
1253	* @event: the perf_event to which the PMC counter was assigned
1254	*
1255	* The counter assigned to this performance event may change if interrupts
1256	* are enabled. This counter should thus never be used while interrupts are
1257	* enabled. Before this function is used to obtain the assigned counter the
1258	* event should be checked for validity using, for example,
1259	* perf_event_read_local(), within the same interrupt disabled section in
1260	* which this counter is planned to be used.
1261	*
1262	* Return: The index of the performance monitoring counter assigned to
1263	* @perf_event.
1264	*/
1265	int x86_perf_rdpmc_index(struct perf_event *event)
1266	{
1267	lockdep_assert_irqs_disabled();
1268
1269	return event->hw.event_base_rdpmc;
1270	}
1271
1272	static inline int match_prev_assignment(struct hw_perf_event *hwc,
1273	struct cpu_hw_events *cpuc,
1274	int i)
1275	{
1276	return hwc->idx == cpuc->assign[i] &&
1277	hwc->last_cpu == smp_processor_id() &&
1278	hwc->last_tag == cpuc->tags[i];
1279	}
1280
1281	static void x86_pmu_start(struct perf_event *event, int flags);
1282
1283	static void x86_pmu_enable(struct pmu *pmu)
1284	{
1285	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1286	struct perf_event *event;
1287	struct hw_perf_event *hwc;
1288	int i, added = cpuc->n_added;
1289
1290	if (!x86_pmu_initialized())
1291	return;
1292
1293	if (cpuc->enabled)
1294	return;
1295
1296	if (cpuc->n_added) {
1297	int n_running = cpuc->n_events - cpuc->n_added;
1298	/*
1299	* apply assignment obtained either from
1300	* hw_perf_group_sched_in() or x86_pmu_enable()
1301	*
1302	* step1: save events moving to new counters
1303	*/
1304	for (i = 0; i < n_running; i++) {
1305	event = cpuc->event_list[i];
1306	hwc = &event->hw;
1307
1308	/*
1309	* we can avoid reprogramming counter if:
1310	* - assigned same counter as last time
1311	* - running on same CPU as last time
1312	* - no other event has used the counter since
1313	*/
1314	if (hwc->idx == -1 ||
1315	match_prev_assignment(hwc, cpuc, i))
1316	continue;
1317
1318	/*
1319	* Ensure we don't accidentally enable a stopped
1320	* counter simply because we rescheduled.
1321	*/
1322	if (hwc->state & PERF_HES_STOPPED)
1323	hwc->state |= PERF_HES_ARCH;
1324
1325	x86_pmu_stop(event, PERF_EF_UPDATE);
1326	}
1327
1328	/*
1329	* step2: reprogram moved events into new counters
1330	*/
1331	for (i = 0; i < cpuc->n_events; i++) {
1332	event = cpuc->event_list[i];
1333	hwc = &event->hw;
1334
1335	if (!match_prev_assignment(hwc, cpuc, i))
1336	x86_assign_hw_event(event, cpuc, i);
1337	else if (i < n_running)
1338	continue;
1339
1340	if (hwc->state & PERF_HES_ARCH)
1341	continue;
1342
1343	/*
1344	* if cpuc->enabled = 0, then no wrmsr as
1345	* per x86_pmu_enable_event()
1346	*/
1347	x86_pmu_start(event, PERF_EF_RELOAD);
1348	}
1349	cpuc->n_added = 0;
1350	perf_events_lapic_init();
1351	}
1352
1353	cpuc->enabled = 1;
1354	barrier();
1355
1356	static_call(x86_pmu_enable_all)(added);
1357	}
1358
1359	DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
1360
1361	/*
1362	* Set the next IRQ period, based on the hwc->period_left value.
1363	* To be called with the event disabled in hw:
1364	*/
1365	int x86_perf_event_set_period(struct perf_event *event)
1366	{
1367	struct hw_perf_event *hwc = &event->hw;
1368	s64 left = local64_read(&hwc->period_left);
1369	s64 period = hwc->sample_period;
1370	int ret = 0, idx = hwc->idx;
1371
1372	if (unlikely(!hwc->event_base))
1373	return 0;
1374
1375	/*
1376	* If we are way outside a reasonable range then just skip forward:
1377	*/
1378	if (unlikely(left <= -period)) {
1379	left = period;
1380	local64_set(&hwc->period_left, left);
1381	hwc->last_period = period;
1382	ret = 1;
1383	}
1384
1385	if (unlikely(left <= 0)) {
1386	left += period;
1387	local64_set(&hwc->period_left, left);
1388	hwc->last_period = period;
1389	ret = 1;
1390	}
1391	/*
1392	* Quirk: certain CPUs dont like it if just 1 hw_event is left:
1393	*/
1394	if (unlikely(left < 2))
1395	left = 2;
1396
1397	if (left > x86_pmu.max_period)
1398	left = x86_pmu.max_period;
1399
1400	static_call_cond(x86_pmu_limit_period)(event, &left);
1401
1402	this_cpu_write(pmc_prev_left[idx], left);
1403
1404	/*
1405	* The hw event starts counting from this event offset,
1406	* mark it to be able to extra future deltas:
1407	*/
1408	local64_set(&hwc->prev_count, (u64)-left);
1409
1410	wrmsrl(msr: hwc->event_base, val: (u64)(-left) & x86_pmu.cntval_mask);
1411
1412	/*
1413	* Sign extend the Merge event counter's upper 16 bits since
1414	* we currently declare a 48-bit counter width
1415	*/
1416	if (is_counter_pair(hwc))
1417	wrmsrl(msr: x86_pmu_event_addr(index: idx + 1), val: 0xffff);
1418
1419	perf_event_update_userpage(event);
1420
1421	return ret;
1422	}
1423
1424	void x86_pmu_enable_event(struct perf_event *event)
1425	{
1426	if (__this_cpu_read(cpu_hw_events.enabled))
1427	__x86_pmu_enable_event(hwc: &event->hw,
1428	ARCH_PERFMON_EVENTSEL_ENABLE);
1429	}
1430
1431	/*
1432	* Add a single event to the PMU.
1433	*
1434	* The event is added to the group of enabled events
1435	* but only if it can be scheduled with existing events.
1436	*/
1437	static int x86_pmu_add(struct perf_event *event, int flags)
1438	{
1439	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1440	struct hw_perf_event *hwc;
1441	int assign[X86_PMC_IDX_MAX];
1442	int n, n0, ret;
1443
1444	hwc = &event->hw;
1445
1446	n0 = cpuc->n_events;
1447	ret = n = collect_events(cpuc, leader: event, dogrp: false);
1448	if (ret < 0)
1449	goto out;
1450
1451	hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
1452	if (!(flags & PERF_EF_START))
1453	hwc->state |= PERF_HES_ARCH;
1454
1455	/*
1456	* If group events scheduling transaction was started,
1457	* skip the schedulability test here, it will be performed
1458	* at commit time (->commit_txn) as a whole.
1459	*
1460	* If commit fails, we'll call ->del() on all events
1461	* for which ->add() was called.
1462	*/
1463	if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
1464	goto done_collect;
1465
1466	ret = static_call(x86_pmu_schedule_events)(cpuc, n, assign);
1467	if (ret)
1468	goto out;
1469	/*
1470	* copy new assignment, now we know it is possible
1471	* will be used by hw_perf_enable()
1472	*/
1473	memcpy(cpuc->assign, assign, n*sizeof(int));
1474
1475	done_collect:
1476	/*
1477	* Commit the collect_events() state. See x86_pmu_del() and
1478	* x86_pmu_*_txn().
1479	*/
1480	cpuc->n_events = n;
1481	cpuc->n_added += n - n0;
1482	cpuc->n_txn += n - n0;
1483
1484	/*
1485	* This is before x86_pmu_enable() will call x86_pmu_start(),
1486	* so we enable LBRs before an event needs them etc..
1487	*/
1488	static_call_cond(x86_pmu_add)(event);
1489
1490	ret = 0;
1491	out:
1492	return ret;
1493	}
1494
1495	static void x86_pmu_start(struct perf_event *event, int flags)
1496	{
1497	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1498	int idx = event->hw.idx;
1499
1500	if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
1501	return;
1502
1503	if (WARN_ON_ONCE(idx == -1))
1504	return;
1505
1506	if (flags & PERF_EF_RELOAD) {
1507	WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1508	static_call(x86_pmu_set_period)(event);
1509	}
1510
1511	event->hw.state = 0;
1512
1513	cpuc->events[idx] = event;
1514	__set_bit(idx, cpuc->active_mask);
1515	static_call(x86_pmu_enable)(event);
1516	perf_event_update_userpage(event);
1517	}
1518
1519	void perf_event_print_debug(void)
1520	{
1521	u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1522	u64 pebs, debugctl;
1523	int cpu = smp_processor_id();
1524	struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1525	int num_counters = hybrid(cpuc->pmu, num_counters);
1526	int num_counters_fixed = hybrid(cpuc->pmu, num_counters_fixed);
1527	struct event_constraint *pebs_constraints = hybrid(cpuc->pmu, pebs_constraints);
1528	unsigned long flags;
1529	int idx;
1530
1531	if (!num_counters)
1532	return;
1533
1534	local_irq_save(flags);
1535
1536	if (x86_pmu.version >= 2) {
1537	rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1538	rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1539	rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1540	rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1541
1542	pr_info("\n");
1543	pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl);
1544	pr_info("CPU#%d: status: %016llx\n", cpu, status);
1545	pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow);
1546	pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed);
1547	if (pebs_constraints) {
1548	rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1549	pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs);
1550	}
1551	if (x86_pmu.lbr_nr) {
1552	rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
1553	pr_info("CPU#%d: debugctl: %016llx\n", cpu, debugctl);
1554	}
1555	}
1556	pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1557
1558	for (idx = 0; idx < num_counters; idx++) {
1559	rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl);
1560	rdmsrl(x86_pmu_event_addr(idx), pmc_count);
1561
1562	prev_left = per_cpu(pmc_prev_left[idx], cpu);
1563
1564	pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
1565	cpu, idx, pmc_ctrl);
1566	pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
1567	cpu, idx, pmc_count);
1568	pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1569	cpu, idx, prev_left);
1570	}
1571	for (idx = 0; idx < num_counters_fixed; idx++) {
1572	if (fixed_counter_disabled(i: idx, pmu: cpuc->pmu))
1573	continue;
1574	rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1575
1576	pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1577	cpu, idx, pmc_count);
1578	}
1579	local_irq_restore(flags);
1580	}
1581
1582	void x86_pmu_stop(struct perf_event *event, int flags)
1583	{
1584	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1585	struct hw_perf_event *hwc = &event->hw;
1586
1587	if (test_bit(hwc->idx, cpuc->active_mask)) {
1588	static_call(x86_pmu_disable)(event);
1589	__clear_bit(hwc->idx, cpuc->active_mask);
1590	cpuc->events[hwc->idx] = NULL;
1591	WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
1592	hwc->state |= PERF_HES_STOPPED;
1593	}
1594
1595	if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
1596	/*
1597	* Drain the remaining delta count out of a event
1598	* that we are disabling:
1599	*/
1600	static_call(x86_pmu_update)(event);
1601	hwc->state |= PERF_HES_UPTODATE;
1602	}
1603	}
1604
1605	static void x86_pmu_del(struct perf_event *event, int flags)
1606	{
1607	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1608	union perf_capabilities intel_cap = hybrid(cpuc->pmu, intel_cap);
1609	int i;
1610
1611	/*
1612	* If we're called during a txn, we only need to undo x86_pmu.add.
1613	* The events never got scheduled and ->cancel_txn will truncate
1614	* the event_list.
1615	*
1616	* XXX assumes any ->del() called during a TXN will only be on
1617	* an event added during that same TXN.
1618	*/
1619	if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
1620	goto do_del;
1621
1622	__set_bit(event->hw.idx, cpuc->dirty);
1623
1624	/*
1625	* Not a TXN, therefore cleanup properly.
1626	*/
1627	x86_pmu_stop(event, PERF_EF_UPDATE);
1628
1629	for (i = 0; i < cpuc->n_events; i++) {
1630	if (event == cpuc->event_list[i])
1631	break;
1632	}
1633
1634	if (WARN_ON_ONCE(i == cpuc->n_events)) /* called ->del() without ->add() ? */
1635	return;
1636
1637	/* If we have a newly added event; make sure to decrease n_added. */
1638	if (i >= cpuc->n_events - cpuc->n_added)
1639	--cpuc->n_added;
1640
1641	static_call_cond(x86_pmu_put_event_constraints)(cpuc, event);
1642
1643	/* Delete the array entry. */
1644	while (++i < cpuc->n_events) {
1645	cpuc->event_list[i-1] = cpuc->event_list[i];
1646	cpuc->event_constraint[i-1] = cpuc->event_constraint[i];
1647	cpuc->assign[i-1] = cpuc->assign[i];
1648	}
1649	cpuc->event_constraint[i-1] = NULL;
1650	--cpuc->n_events;
1651	if (intel_cap.perf_metrics)
1652	del_nr_metric_event(cpuc, event);
1653
1654	perf_event_update_userpage(event);
1655
1656	do_del:
1657
1658	/*
1659	* This is after x86_pmu_stop(); so we disable LBRs after any
1660	* event can need them etc..
1661	*/
1662	static_call_cond(x86_pmu_del)(event);
1663	}
1664
1665	int x86_pmu_handle_irq(struct pt_regs *regs)
1666	{
1667	struct perf_sample_data data;
1668	struct cpu_hw_events *cpuc;
1669	struct perf_event *event;
1670	int idx, handled = 0;
1671	u64 val;
1672
1673	cpuc = this_cpu_ptr(&cpu_hw_events);
1674
1675	/*
1676	* Some chipsets need to unmask the LVTPC in a particular spot
1677	* inside the nmi handler. As a result, the unmasking was pushed
1678	* into all the nmi handlers.
1679	*
1680	* This generic handler doesn't seem to have any issues where the
1681	* unmasking occurs so it was left at the top.
1682	*/
1683	apic_write(APIC_LVTPC, APIC_DM_NMI);
1684
1685	for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1686	if (!test_bit(idx, cpuc->active_mask))
1687	continue;
1688
1689	event = cpuc->events[idx];
1690
1691	val = static_call(x86_pmu_update)(event);
1692	if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1693	continue;
1694
1695	/*
1696	* event overflow
1697	*/
1698	handled++;
1699
1700	if (!static_call(x86_pmu_set_period)(event))
1701	continue;
1702
1703	perf_sample_data_init(data: &data, addr: 0, period: event->hw.last_period);
1704
1705	if (has_branch_stack(event))
1706	perf_sample_save_brstack(data: &data, event, brs: &cpuc->lbr_stack, NULL);
1707
1708	if (perf_event_overflow(event, data: &data, regs))
1709	x86_pmu_stop(event, flags: 0);
1710	}
1711
1712	if (handled)
1713	inc_irq_stat(apic_perf_irqs);
1714
1715	return handled;
1716	}
1717
1718	void perf_events_lapic_init(void)
1719	{
1720	if (!x86_pmu.apic || !x86_pmu_initialized())
1721	return;
1722
1723	/*
1724	* Always use NMI for PMU
1725	*/
1726	apic_write(APIC_LVTPC, APIC_DM_NMI);
1727	}
1728
1729	static int
1730	perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs)
1731	{
1732	u64 start_clock;
1733	u64 finish_clock;
1734	int ret;
1735
1736	/*
1737	* All PMUs/events that share this PMI handler should make sure to
1738	* increment active_events for their events.
1739	*/
1740	if (!atomic_read(v: &active_events))
1741	return NMI_DONE;
1742
1743	start_clock = sched_clock();
1744	ret = static_call(x86_pmu_handle_irq)(regs);
1745	finish_clock = sched_clock();
1746
1747	perf_sample_event_took(sample_len_ns: finish_clock - start_clock);
1748
1749	return ret;
1750	}
1751	NOKPROBE_SYMBOL(perf_event_nmi_handler);
1752
1753	struct event_constraint emptyconstraint;
1754	struct event_constraint unconstrained;
1755
1756	static int x86_pmu_prepare_cpu(unsigned int cpu)
1757	{
1758	struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1759	int i;
1760
1761	for (i = 0 ; i < X86_PERF_KFREE_MAX; i++)
1762	cpuc->kfree_on_online[i] = NULL;
1763	if (x86_pmu.cpu_prepare)
1764	return x86_pmu.cpu_prepare(cpu);
1765	return 0;
1766	}
1767
1768	static int x86_pmu_dead_cpu(unsigned int cpu)
1769	{
1770	if (x86_pmu.cpu_dead)
1771	x86_pmu.cpu_dead(cpu);
1772	return 0;
1773	}
1774
1775	static int x86_pmu_online_cpu(unsigned int cpu)
1776	{
1777	struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1778	int i;
1779
1780	for (i = 0 ; i < X86_PERF_KFREE_MAX; i++) {
1781	kfree(objp: cpuc->kfree_on_online[i]);
1782	cpuc->kfree_on_online[i] = NULL;
1783	}
1784	return 0;
1785	}
1786
1787	static int x86_pmu_starting_cpu(unsigned int cpu)
1788	{
1789	if (x86_pmu.cpu_starting)
1790	x86_pmu.cpu_starting(cpu);
1791	return 0;
1792	}
1793
1794	static int x86_pmu_dying_cpu(unsigned int cpu)
1795	{
1796	if (x86_pmu.cpu_dying)
1797	x86_pmu.cpu_dying(cpu);
1798	return 0;
1799	}
1800
1801	static void __init pmu_check_apic(void)
1802	{
1803	if (boot_cpu_has(X86_FEATURE_APIC))
1804	return;
1805
1806	x86_pmu.apic = 0;
1807	pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1808	pr_info("no hardware sampling interrupt available.\n");
1809
1810	/*
1811	* If we have a PMU initialized but no APIC
1812	* interrupts, we cannot sample hardware
1813	* events (user-space has to fall back and
1814	* sample via a hrtimer based software event):
1815	*/
1816	pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
1817
1818	}
1819
1820	static struct attribute_group x86_pmu_format_group __ro_after_init = {
1821	.name = "format",
1822	.attrs = NULL,
1823	};
1824
1825	ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr, char *page)
1826	{
1827	struct perf_pmu_events_attr *pmu_attr =
1828	container_of(attr, struct perf_pmu_events_attr, attr);
1829	u64 config = 0;
1830
1831	if (pmu_attr->id < x86_pmu.max_events)
1832	config = x86_pmu.event_map(pmu_attr->id);
1833
1834	/* string trumps id */
1835	if (pmu_attr->event_str)
1836	return sprintf(buf: page, fmt: "%s\n", pmu_attr->event_str);
1837
1838	return x86_pmu.events_sysfs_show(page, config);
1839	}
1840	EXPORT_SYMBOL_GPL(events_sysfs_show);
1841
1842	ssize_t events_ht_sysfs_show(struct device *dev, struct device_attribute *attr,
1843	char *page)
1844	{
1845	struct perf_pmu_events_ht_attr *pmu_attr =
1846	container_of(attr, struct perf_pmu_events_ht_attr, attr);
1847
1848	/*
1849	* Report conditional events depending on Hyper-Threading.
1850	*
1851	* This is overly conservative as usually the HT special
1852	* handling is not needed if the other CPU thread is idle.
1853	*
1854	* Note this does not (and cannot) handle the case when thread
1855	* siblings are invisible, for example with virtualization
1856	* if they are owned by some other guest. The user tool
1857	* has to re-read when a thread sibling gets onlined later.
1858	*/
1859	return sprintf(buf: page, fmt: "%s",
1860	topology_max_smt_threads() > 1 ?
1861	pmu_attr->event_str_ht :
1862	pmu_attr->event_str_noht);
1863	}
1864
1865	ssize_t events_hybrid_sysfs_show(struct device *dev,
1866	struct device_attribute *attr,
1867	char *page)
1868	{
1869	struct perf_pmu_events_hybrid_attr *pmu_attr =
1870	container_of(attr, struct perf_pmu_events_hybrid_attr, attr);
1871	struct x86_hybrid_pmu *pmu;
1872	const char *str, *next_str;
1873	int i;
1874
1875	if (hweight64(pmu_attr->pmu_type) == 1)
1876	return sprintf(buf: page, fmt: "%s", pmu_attr->event_str);
1877
1878	/*
1879	* Hybrid PMUs may support the same event name, but with different
1880	* event encoding, e.g., the mem-loads event on an Atom PMU has
1881	* different event encoding from a Core PMU.
1882	*
1883	* The event_str includes all event encodings. Each event encoding
1884	* is divided by ";". The order of the event encodings must follow
1885	* the order of the hybrid PMU index.
1886	*/
1887	pmu = container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
1888
1889	str = pmu_attr->event_str;
1890	for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) {
1891	if (!(x86_pmu.hybrid_pmu[i].pmu_type & pmu_attr->pmu_type))
1892	continue;
1893	if (x86_pmu.hybrid_pmu[i].pmu_type & pmu->pmu_type) {
1894	next_str = strchr(str, ';');
1895	if (next_str)
1896	return snprintf(buf: page, size: next_str - str + 1, fmt: "%s", str);
1897	else
1898	return sprintf(buf: page, fmt: "%s", str);
1899	}
1900	str = strchr(str, ';');
1901	str++;
1902	}
1903
1904	return 0;
1905	}
1906	EXPORT_SYMBOL_GPL(events_hybrid_sysfs_show);
1907
1908	EVENT_ATTR(cpu-cycles, CPU_CYCLES );
1909	EVENT_ATTR(instructions, INSTRUCTIONS );
1910	EVENT_ATTR(cache-references, CACHE_REFERENCES );
1911	EVENT_ATTR(cache-misses, CACHE_MISSES );
1912	EVENT_ATTR(branch-instructions, BRANCH_INSTRUCTIONS );
1913	EVENT_ATTR(branch-misses, BRANCH_MISSES );
1914	EVENT_ATTR(bus-cycles, BUS_CYCLES );
1915	EVENT_ATTR(stalled-cycles-frontend, STALLED_CYCLES_FRONTEND );
1916	EVENT_ATTR(stalled-cycles-backend, STALLED_CYCLES_BACKEND );
1917	EVENT_ATTR(ref-cycles, REF_CPU_CYCLES );
1918
1919	static struct attribute *empty_attrs;
1920
1921	static struct attribute *events_attr[] = {
1922	EVENT_PTR(CPU_CYCLES),
1923	EVENT_PTR(INSTRUCTIONS),
1924	EVENT_PTR(CACHE_REFERENCES),
1925	EVENT_PTR(CACHE_MISSES),
1926	EVENT_PTR(BRANCH_INSTRUCTIONS),
1927	EVENT_PTR(BRANCH_MISSES),
1928	EVENT_PTR(BUS_CYCLES),
1929	EVENT_PTR(STALLED_CYCLES_FRONTEND),
1930	EVENT_PTR(STALLED_CYCLES_BACKEND),
1931	EVENT_PTR(REF_CPU_CYCLES),
1932	NULL,
1933	};
1934
1935	/*
1936	* Remove all undefined events (x86_pmu.event_map(id) == 0)
1937	* out of events_attr attributes.
1938	*/
1939	static umode_t
1940	is_visible(struct kobject *kobj, struct attribute *attr, int idx)
1941	{
1942	struct perf_pmu_events_attr *pmu_attr;
1943
1944	if (idx >= x86_pmu.max_events)
1945	return 0;
1946
1947	pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr.attr);
1948	/* str trumps id */
1949	return pmu_attr->event_str || x86_pmu.event_map(idx) ? attr->mode : 0;
1950	}
1951
1952	static struct attribute_group x86_pmu_events_group __ro_after_init = {
1953	.name = "events",
1954	.attrs = events_attr,
1955	.is_visible = is_visible,
1956	};
1957
1958	ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event)
1959	{
1960	u64 umask = (config & ARCH_PERFMON_EVENTSEL_UMASK) >> 8;
1961	u64 cmask = (config & ARCH_PERFMON_EVENTSEL_CMASK) >> 24;
1962	bool edge = (config & ARCH_PERFMON_EVENTSEL_EDGE);
1963	bool pc = (config & ARCH_PERFMON_EVENTSEL_PIN_CONTROL);
1964	bool any = (config & ARCH_PERFMON_EVENTSEL_ANY);
1965	bool inv = (config & ARCH_PERFMON_EVENTSEL_INV);
1966	ssize_t ret;
1967
1968	/*
1969	* We have whole page size to spend and just little data
1970	* to write, so we can safely use sprintf.
1971	*/
1972	ret = sprintf(buf: page, fmt: "event=0x%02llx", event);
1973
1974	if (umask)
1975	ret += sprintf(buf: page + ret, fmt: ",umask=0x%02llx", umask);
1976
1977	if (edge)
1978	ret += sprintf(buf: page + ret, fmt: ",edge");
1979
1980	if (pc)
1981	ret += sprintf(buf: page + ret, fmt: ",pc");
1982
1983	if (any)
1984	ret += sprintf(buf: page + ret, fmt: ",any");
1985
1986	if (inv)
1987	ret += sprintf(buf: page + ret, fmt: ",inv");
1988
1989	if (cmask)
1990	ret += sprintf(buf: page + ret, fmt: ",cmask=0x%02llx", cmask);
1991
1992	ret += sprintf(buf: page + ret, fmt: "\n");
1993
1994	return ret;
1995	}
1996
1997	static struct attribute_group x86_pmu_attr_group;
1998	static struct attribute_group x86_pmu_caps_group;
1999
2000	static void x86_pmu_static_call_update(void)
2001	{
2002	static_call_update(x86_pmu_handle_irq, x86_pmu.handle_irq);
2003	static_call_update(x86_pmu_disable_all, x86_pmu.disable_all);
2004	static_call_update(x86_pmu_enable_all, x86_pmu.enable_all);
2005	static_call_update(x86_pmu_enable, x86_pmu.enable);
2006	static_call_update(x86_pmu_disable, x86_pmu.disable);
2007
2008	static_call_update(x86_pmu_assign, x86_pmu.assign);
2009
2010	static_call_update(x86_pmu_add, x86_pmu.add);
2011	static_call_update(x86_pmu_del, x86_pmu.del);
2012	static_call_update(x86_pmu_read, x86_pmu.read);
2013
2014	static_call_update(x86_pmu_set_period, x86_pmu.set_period);
2015	static_call_update(x86_pmu_update, x86_pmu.update);
2016	static_call_update(x86_pmu_limit_period, x86_pmu.limit_period);
2017
2018	static_call_update(x86_pmu_schedule_events, x86_pmu.schedule_events);
2019	static_call_update(x86_pmu_get_event_constraints, x86_pmu.get_event_constraints);
2020	static_call_update(x86_pmu_put_event_constraints, x86_pmu.put_event_constraints);
2021
2022	static_call_update(x86_pmu_start_scheduling, x86_pmu.start_scheduling);
2023	static_call_update(x86_pmu_commit_scheduling, x86_pmu.commit_scheduling);
2024	static_call_update(x86_pmu_stop_scheduling, x86_pmu.stop_scheduling);
2025
2026	static_call_update(x86_pmu_sched_task, x86_pmu.sched_task);
2027	static_call_update(x86_pmu_swap_task_ctx, x86_pmu.swap_task_ctx);
2028
2029	static_call_update(x86_pmu_drain_pebs, x86_pmu.drain_pebs);
2030	static_call_update(x86_pmu_pebs_aliases, x86_pmu.pebs_aliases);
2031
2032	static_call_update(x86_pmu_guest_get_msrs, x86_pmu.guest_get_msrs);
2033	static_call_update(x86_pmu_filter, x86_pmu.filter);
2034	}
2035
2036	static void _x86_pmu_read(struct perf_event *event)
2037	{
2038	static_call(x86_pmu_update)(event);
2039	}
2040
2041	void x86_pmu_show_pmu_cap(int num_counters, int num_counters_fixed,
2042	u64 intel_ctrl)
2043	{
2044	pr_info("... version: %d\n", x86_pmu.version);
2045	pr_info("... bit width: %d\n", x86_pmu.cntval_bits);
2046	pr_info("... generic registers: %d\n", num_counters);
2047	pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask);
2048	pr_info("... max period: %016Lx\n", x86_pmu.max_period);
2049	pr_info("... fixed-purpose events: %lu\n",
2050	hweight64((((1ULL << num_counters_fixed) - 1)
2051	<< INTEL_PMC_IDX_FIXED) & intel_ctrl));
2052	pr_info("... event mask: %016Lx\n", intel_ctrl);
2053	}
2054
2055	static int __init init_hw_perf_events(void)
2056	{
2057	struct x86_pmu_quirk *quirk;
2058	int err;
2059
2060	pr_info("Performance Events: ");
2061
2062	switch (boot_cpu_data.x86_vendor) {
2063	case X86_VENDOR_INTEL:
2064	err = intel_pmu_init();
2065	break;
2066	case X86_VENDOR_AMD:
2067	err = amd_pmu_init();
2068	break;
2069	case X86_VENDOR_HYGON:
2070	err = amd_pmu_init();
2071	x86_pmu.name = "HYGON";
2072	break;
2073	case X86_VENDOR_ZHAOXIN:
2074	case X86_VENDOR_CENTAUR:
2075	err = zhaoxin_pmu_init();
2076	break;
2077	default:
2078	err = -ENOTSUPP;
2079	}
2080	if (err != 0) {
2081	pr_cont("no PMU driver, software events only.\n");
2082	err = 0;
2083	goto out_bad_pmu;
2084	}
2085
2086	pmu_check_apic();
2087
2088	/* sanity check that the hardware exists or is emulated */
2089	if (!check_hw_exists(pmu: &pmu, num_counters: x86_pmu.num_counters, num_counters_fixed: x86_pmu.num_counters_fixed))
2090	goto out_bad_pmu;
2091
2092	pr_cont("%s PMU driver.\n", x86_pmu.name);
2093
2094	x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */
2095
2096	for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next)
2097	quirk->func();
2098
2099	if (!x86_pmu.intel_ctrl)
2100	x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
2101
2102	perf_events_lapic_init();
2103	register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI");
2104
2105	unconstrained = (struct event_constraint)
2106	__EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
2107	0, x86_pmu.num_counters, 0, 0);
2108
2109	x86_pmu_format_group.attrs = x86_pmu.format_attrs;
2110
2111	if (!x86_pmu.events_sysfs_show)
2112	x86_pmu_events_group.attrs = &empty_attrs;
2113
2114	pmu.attr_update = x86_pmu.attr_update;
2115
2116	if (!is_hybrid()) {
2117	x86_pmu_show_pmu_cap(num_counters: x86_pmu.num_counters,
2118	num_counters_fixed: x86_pmu.num_counters_fixed,
2119	intel_ctrl: x86_pmu.intel_ctrl);
2120	}
2121
2122	if (!x86_pmu.read)
2123	x86_pmu.read = _x86_pmu_read;
2124
2125	if (!x86_pmu.guest_get_msrs)
2126	x86_pmu.guest_get_msrs = (void *)&__static_call_return0;
2127
2128	if (!x86_pmu.set_period)
2129	x86_pmu.set_period = x86_perf_event_set_period;
2130
2131	if (!x86_pmu.update)
2132	x86_pmu.update = x86_perf_event_update;
2133
2134	x86_pmu_static_call_update();
2135
2136	/*
2137	* Install callbacks. Core will call them for each online
2138	* cpu.
2139	*/
2140	err = cpuhp_setup_state(state: CPUHP_PERF_X86_PREPARE, name: "perf/x86:prepare",
2141	startup: x86_pmu_prepare_cpu, teardown: x86_pmu_dead_cpu);
2142	if (err)
2143	return err;
2144
2145	err = cpuhp_setup_state(state: CPUHP_AP_PERF_X86_STARTING,
2146	name: "perf/x86:starting", startup: x86_pmu_starting_cpu,
2147	teardown: x86_pmu_dying_cpu);
2148	if (err)
2149	goto out;
2150
2151	err = cpuhp_setup_state(state: CPUHP_AP_PERF_X86_ONLINE, name: "perf/x86:online",
2152	startup: x86_pmu_online_cpu, NULL);
2153	if (err)
2154	goto out1;
2155
2156	if (!is_hybrid()) {
2157	err = perf_pmu_register(pmu: &pmu, name: "cpu", type: PERF_TYPE_RAW);
2158	if (err)
2159	goto out2;
2160	} else {
2161	struct x86_hybrid_pmu *hybrid_pmu;
2162	int i, j;
2163
2164	for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) {
2165	hybrid_pmu = &x86_pmu.hybrid_pmu[i];
2166
2167	hybrid_pmu->pmu = pmu;
2168	hybrid_pmu->pmu.type = -1;
2169	hybrid_pmu->pmu.attr_update = x86_pmu.attr_update;
2170	hybrid_pmu->pmu.capabilities |= PERF_PMU_CAP_EXTENDED_HW_TYPE;
2171
2172	err = perf_pmu_register(pmu: &hybrid_pmu->pmu, name: hybrid_pmu->name,
2173	type: (hybrid_pmu->pmu_type == hybrid_big) ? PERF_TYPE_RAW : -1);
2174	if (err)
2175	break;
2176	}
2177
2178	if (i < x86_pmu.num_hybrid_pmus) {
2179	for (j = 0; j < i; j++)
2180	perf_pmu_unregister(pmu: &x86_pmu.hybrid_pmu[j].pmu);
2181	pr_warn("Failed to register hybrid PMUs\n");
2182	kfree(objp: x86_pmu.hybrid_pmu);
2183	x86_pmu.hybrid_pmu = NULL;
2184	x86_pmu.num_hybrid_pmus = 0;
2185	goto out2;
2186	}
2187	}
2188
2189	return 0;
2190
2191	out2:
2192	cpuhp_remove_state(state: CPUHP_AP_PERF_X86_ONLINE);
2193	out1:
2194	cpuhp_remove_state(state: CPUHP_AP_PERF_X86_STARTING);
2195	out:
2196	cpuhp_remove_state(state: CPUHP_PERF_X86_PREPARE);
2197	out_bad_pmu:
2198	memset(&x86_pmu, 0, sizeof(x86_pmu));
2199	return err;
2200	}
2201	early_initcall(init_hw_perf_events);
2202
2203	static void x86_pmu_read(struct perf_event *event)
2204	{
2205	static_call(x86_pmu_read)(event);
2206	}
2207
2208	/*
2209	* Start group events scheduling transaction
2210	* Set the flag to make pmu::enable() not perform the
2211	* schedulability test, it will be performed at commit time
2212	*
2213	* We only support PERF_PMU_TXN_ADD transactions. Save the
2214	* transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD
2215	* transactions.
2216	*/
2217	static void x86_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags)
2218	{
2219	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2220
2221	WARN_ON_ONCE(cpuc->txn_flags); /* txn already in flight */
2222
2223	cpuc->txn_flags = txn_flags;
2224	if (txn_flags & ~PERF_PMU_TXN_ADD)
2225	return;
2226
2227	perf_pmu_disable(pmu);
2228	__this_cpu_write(cpu_hw_events.n_txn, 0);
2229	__this_cpu_write(cpu_hw_events.n_txn_pair, 0);
2230	__this_cpu_write(cpu_hw_events.n_txn_metric, 0);
2231	}
2232
2233	/*
2234	* Stop group events scheduling transaction
2235	* Clear the flag and pmu::enable() will perform the
2236	* schedulability test.
2237	*/
2238	static void x86_pmu_cancel_txn(struct pmu *pmu)
2239	{
2240	unsigned int txn_flags;
2241	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2242
2243	WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */
2244
2245	txn_flags = cpuc->txn_flags;
2246	cpuc->txn_flags = 0;
2247	if (txn_flags & ~PERF_PMU_TXN_ADD)
2248	return;
2249
2250	/*
2251	* Truncate collected array by the number of events added in this
2252	* transaction. See x86_pmu_add() and x86_pmu_*_txn().
2253	*/
2254	__this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn));
2255	__this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn));
2256	__this_cpu_sub(cpu_hw_events.n_pair, __this_cpu_read(cpu_hw_events.n_txn_pair));
2257	__this_cpu_sub(cpu_hw_events.n_metric, __this_cpu_read(cpu_hw_events.n_txn_metric));
2258	perf_pmu_enable(pmu);
2259	}
2260
2261	/*
2262	* Commit group events scheduling transaction
2263	* Perform the group schedulability test as a whole
2264	* Return 0 if success
2265	*
2266	* Does not cancel the transaction on failure; expects the caller to do this.
2267	*/
2268	static int x86_pmu_commit_txn(struct pmu *pmu)
2269	{
2270	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2271	int assign[X86_PMC_IDX_MAX];
2272	int n, ret;
2273
2274	WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */
2275
2276	if (cpuc->txn_flags & ~PERF_PMU_TXN_ADD) {
2277	cpuc->txn_flags = 0;
2278	return 0;
2279	}
2280
2281	n = cpuc->n_events;
2282
2283	if (!x86_pmu_initialized())
2284	return -EAGAIN;
2285
2286	ret = static_call(x86_pmu_schedule_events)(cpuc, n, assign);
2287	if (ret)
2288	return ret;
2289
2290	/*
2291	* copy new assignment, now we know it is possible
2292	* will be used by hw_perf_enable()
2293	*/
2294	memcpy(cpuc->assign, assign, n*sizeof(int));
2295
2296	cpuc->txn_flags = 0;
2297	perf_pmu_enable(pmu);
2298	return 0;
2299	}
2300	/*
2301	* a fake_cpuc is used to validate event groups. Due to
2302	* the extra reg logic, we need to also allocate a fake
2303	* per_core and per_cpu structure. Otherwise, group events
2304	* using extra reg may conflict without the kernel being
2305	* able to catch this when the last event gets added to
2306	* the group.
2307	*/
2308	static void free_fake_cpuc(struct cpu_hw_events *cpuc)
2309	{
2310	intel_cpuc_finish(cpuc);
2311	kfree(objp: cpuc);
2312	}
2313
2314	static struct cpu_hw_events *allocate_fake_cpuc(struct pmu *event_pmu)
2315	{
2316	struct cpu_hw_events *cpuc;
2317	int cpu;
2318
2319	cpuc = kzalloc(size: sizeof(*cpuc), GFP_KERNEL);
2320	if (!cpuc)
2321	return ERR_PTR(error: -ENOMEM);
2322	cpuc->is_fake = 1;
2323
2324	if (is_hybrid()) {
2325	struct x86_hybrid_pmu *h_pmu;
2326
2327	h_pmu = hybrid_pmu(pmu: event_pmu);
2328	if (cpumask_empty(srcp: &h_pmu->supported_cpus))
2329	goto error;
2330	cpu = cpumask_first(srcp: &h_pmu->supported_cpus);
2331	} else
2332	cpu = raw_smp_processor_id();
2333	cpuc->pmu = event_pmu;
2334
2335	if (intel_cpuc_prepare(cpuc, cpu))
2336	goto error;
2337
2338	return cpuc;
2339	error:
2340	free_fake_cpuc(cpuc);
2341	return ERR_PTR(error: -ENOMEM);
2342	}
2343
2344	/*
2345	* validate that we can schedule this event
2346	*/
2347	static int validate_event(struct perf_event *event)
2348	{
2349	struct cpu_hw_events *fake_cpuc;
2350	struct event_constraint *c;
2351	int ret = 0;
2352
2353	fake_cpuc = allocate_fake_cpuc(event_pmu: event->pmu);
2354	if (IS_ERR(ptr: fake_cpuc))
2355	return PTR_ERR(ptr: fake_cpuc);
2356
2357	c = x86_pmu.get_event_constraints(fake_cpuc, 0, event);
2358
2359	if (!c || !c->weight)
2360	ret = -EINVAL;
2361
2362	if (x86_pmu.put_event_constraints)
2363	x86_pmu.put_event_constraints(fake_cpuc, event);
2364
2365	free_fake_cpuc(cpuc: fake_cpuc);
2366
2367	return ret;
2368	}
2369
2370	/*
2371	* validate a single event group
2372	*
2373	* validation include:
2374	* - check events are compatible which each other
2375	* - events do not compete for the same counter
2376	* - number of events <= number of counters
2377	*
2378	* validation ensures the group can be loaded onto the
2379	* PMU if it was the only group available.
2380	*/
2381	static int validate_group(struct perf_event *event)
2382	{
2383	struct perf_event *leader = event->group_leader;
2384	struct cpu_hw_events *fake_cpuc;
2385	int ret = -EINVAL, n;
2386
2387	/*
2388	* Reject events from different hybrid PMUs.
2389	*/
2390	if (is_hybrid()) {
2391	struct perf_event *sibling;
2392	struct pmu *pmu = NULL;
2393
2394	if (is_x86_event(event: leader))
2395	pmu = leader->pmu;
2396
2397	for_each_sibling_event(sibling, leader) {
2398	if (!is_x86_event(event: sibling))
2399	continue;
2400	if (!pmu)
2401	pmu = sibling->pmu;
2402	else if (pmu != sibling->pmu)
2403	return ret;
2404	}
2405	}
2406
2407	fake_cpuc = allocate_fake_cpuc(event_pmu: event->pmu);
2408	if (IS_ERR(ptr: fake_cpuc))
2409	return PTR_ERR(ptr: fake_cpuc);
2410	/*
2411	* the event is not yet connected with its
2412	* siblings therefore we must first collect
2413	* existing siblings, then add the new event
2414	* before we can simulate the scheduling
2415	*/
2416	n = collect_events(cpuc: fake_cpuc, leader, dogrp: true);
2417	if (n < 0)
2418	goto out;
2419
2420	fake_cpuc->n_events = n;
2421	n = collect_events(cpuc: fake_cpuc, leader: event, dogrp: false);
2422	if (n < 0)
2423	goto out;
2424
2425	fake_cpuc->n_events = 0;
2426	ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
2427
2428	out:
2429	free_fake_cpuc(cpuc: fake_cpuc);
2430	return ret;
2431	}
2432
2433	static int x86_pmu_event_init(struct perf_event *event)
2434	{
2435	struct x86_hybrid_pmu *pmu = NULL;
2436	int err;
2437
2438	if ((event->attr.type != event->pmu->type) &&
2439	(event->attr.type != PERF_TYPE_HARDWARE) &&
2440	(event->attr.type != PERF_TYPE_HW_CACHE))
2441	return -ENOENT;
2442
2443	if (is_hybrid() && (event->cpu != -1)) {
2444	pmu = hybrid_pmu(pmu: event->pmu);
2445	if (!cpumask_test_cpu(cpu: event->cpu, cpumask: &pmu->supported_cpus))
2446	return -ENOENT;
2447	}
2448
2449	err = __x86_pmu_event_init(event);
2450	if (!err) {
2451	if (event->group_leader != event)
2452	err = validate_group(event);
2453	else
2454	err = validate_event(event);
2455	}
2456	if (err) {
2457	if (event->destroy)
2458	event->destroy(event);
2459	event->destroy = NULL;
2460	}
2461
2462	if (READ_ONCE(x86_pmu.attr_rdpmc) &&
2463	!(event->hw.flags & PERF_X86_EVENT_LARGE_PEBS))
2464	event->hw.flags |= PERF_EVENT_FLAG_USER_READ_CNT;
2465
2466	return err;
2467	}
2468
2469	void perf_clear_dirty_counters(void)
2470	{
2471	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2472	int i;
2473
2474	/* Don't need to clear the assigned counter. */
2475	for (i = 0; i < cpuc->n_events; i++)
2476	__clear_bit(cpuc->assign[i], cpuc->dirty);
2477
2478	if (bitmap_empty(src: cpuc->dirty, X86_PMC_IDX_MAX))
2479	return;
2480
2481	for_each_set_bit(i, cpuc->dirty, X86_PMC_IDX_MAX) {
2482	if (i >= INTEL_PMC_IDX_FIXED) {
2483	/* Metrics and fake events don't have corresponding HW counters. */
2484	if ((i - INTEL_PMC_IDX_FIXED) >= hybrid(cpuc->pmu, num_counters_fixed))
2485	continue;
2486
2487	wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + (i - INTEL_PMC_IDX_FIXED), val: 0);
2488	} else {
2489	wrmsrl(msr: x86_pmu_event_addr(index: i), val: 0);
2490	}
2491	}
2492
2493	bitmap_zero(dst: cpuc->dirty, X86_PMC_IDX_MAX);
2494	}
2495
2496	static void x86_pmu_event_mapped(struct perf_event *event, struct mm_struct *mm)
2497	{
2498	if (!(event->hw.flags & PERF_EVENT_FLAG_USER_READ_CNT))
2499	return;
2500
2501	/*
2502	* This function relies on not being called concurrently in two
2503	* tasks in the same mm. Otherwise one task could observe
2504	* perf_rdpmc_allowed > 1 and return all the way back to
2505	* userspace with CR4.PCE clear while another task is still
2506	* doing on_each_cpu_mask() to propagate CR4.PCE.
2507	*
2508	* For now, this can't happen because all callers hold mmap_lock
2509	* for write. If this changes, we'll need a different solution.
2510	*/
2511	mmap_assert_write_locked(mm);
2512
2513	if (atomic_inc_return(v: &mm->context.perf_rdpmc_allowed) == 1)
2514	on_each_cpu_mask(mask: mm_cpumask(mm), func: cr4_update_pce, NULL, wait: 1);
2515	}
2516
2517	static void x86_pmu_event_unmapped(struct perf_event *event, struct mm_struct *mm)
2518	{
2519	if (!(event->hw.flags & PERF_EVENT_FLAG_USER_READ_CNT))
2520	return;
2521
2522	if (atomic_dec_and_test(v: &mm->context.perf_rdpmc_allowed))
2523	on_each_cpu_mask(mask: mm_cpumask(mm), func: cr4_update_pce, NULL, wait: 1);
2524	}
2525
2526	static int x86_pmu_event_idx(struct perf_event *event)
2527	{
2528	struct hw_perf_event *hwc = &event->hw;
2529
2530	if (!(hwc->flags & PERF_EVENT_FLAG_USER_READ_CNT))
2531	return 0;
2532
2533	if (is_metric_idx(idx: hwc->idx))
2534	return INTEL_PMC_FIXED_RDPMC_METRICS + 1;
2535	else
2536	return hwc->event_base_rdpmc + 1;
2537	}
2538
2539	static ssize_t get_attr_rdpmc(struct device *cdev,
2540	struct device_attribute *attr,
2541	char *buf)
2542	{
2543	return snprintf(buf, size: 40, fmt: "%d\n", x86_pmu.attr_rdpmc);
2544	}
2545
2546	static ssize_t set_attr_rdpmc(struct device *cdev,
2547	struct device_attribute *attr,
2548	const char *buf, size_t count)
2549	{
2550	unsigned long val;
2551	ssize_t ret;
2552
2553	ret = kstrtoul(s: buf, base: 0, res: &val);
2554	if (ret)
2555	return ret;
2556
2557	if (val > 2)
2558	return -EINVAL;
2559
2560	if (x86_pmu.attr_rdpmc_broken)
2561	return -ENOTSUPP;
2562
2563	if (val != x86_pmu.attr_rdpmc) {
2564	/*
2565	* Changing into or out of never available or always available,
2566	* aka perf-event-bypassing mode. This path is extremely slow,
2567	* but only root can trigger it, so it's okay.
2568	*/
2569	if (val == 0)
2570	static_branch_inc(&rdpmc_never_available_key);
2571	else if (x86_pmu.attr_rdpmc == 0)
2572	static_branch_dec(&rdpmc_never_available_key);
2573
2574	if (val == 2)
2575	static_branch_inc(&rdpmc_always_available_key);
2576	else if (x86_pmu.attr_rdpmc == 2)
2577	static_branch_dec(&rdpmc_always_available_key);
2578
2579	on_each_cpu(func: cr4_update_pce, NULL, wait: 1);
2580	x86_pmu.attr_rdpmc = val;
2581	}
2582
2583	return count;
2584	}
2585
2586	static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc);
2587
2588	static struct attribute *x86_pmu_attrs[] = {
2589	&dev_attr_rdpmc.attr,
2590	NULL,
2591	};
2592
2593	static struct attribute_group x86_pmu_attr_group __ro_after_init = {
2594	.attrs = x86_pmu_attrs,
2595	};
2596
2597	static ssize_t max_precise_show(struct device *cdev,
2598	struct device_attribute *attr,
2599	char *buf)
2600	{
2601	return snprintf(buf, PAGE_SIZE, fmt: "%d\n", x86_pmu_max_precise());
2602	}
2603
2604	static DEVICE_ATTR_RO(max_precise);
2605
2606	static struct attribute *x86_pmu_caps_attrs[] = {
2607	&dev_attr_max_precise.attr,
2608	NULL
2609	};
2610
2611	static struct attribute_group x86_pmu_caps_group __ro_after_init = {
2612	.name = "caps",
2613	.attrs = x86_pmu_caps_attrs,
2614	};
2615
2616	static const struct attribute_group *x86_pmu_attr_groups[] = {
2617	&x86_pmu_attr_group,
2618	&x86_pmu_format_group,
2619	&x86_pmu_events_group,
2620	&x86_pmu_caps_group,
2621	NULL,
2622	};
2623
2624	static void x86_pmu_sched_task(struct perf_event_pmu_context *pmu_ctx, bool sched_in)
2625	{
2626	static_call_cond(x86_pmu_sched_task)(pmu_ctx, sched_in);
2627	}
2628
2629	static void x86_pmu_swap_task_ctx(struct perf_event_pmu_context *prev_epc,
2630	struct perf_event_pmu_context *next_epc)
2631	{
2632	static_call_cond(x86_pmu_swap_task_ctx)(prev_epc, next_epc);
2633	}
2634
2635	void perf_check_microcode(void)
2636	{
2637	if (x86_pmu.check_microcode)
2638	x86_pmu.check_microcode();
2639	}
2640
2641	static int x86_pmu_check_period(struct perf_event *event, u64 value)
2642	{
2643	if (x86_pmu.check_period && x86_pmu.check_period(event, value))
2644	return -EINVAL;
2645
2646	if (value && x86_pmu.limit_period) {
2647	s64 left = value;
2648	x86_pmu.limit_period(event, &left);
2649	if (left > value)
2650	return -EINVAL;
2651	}
2652
2653	return 0;
2654	}
2655
2656	static int x86_pmu_aux_output_match(struct perf_event *event)
2657	{
2658	if (!(pmu.capabilities & PERF_PMU_CAP_AUX_OUTPUT))
2659	return 0;
2660
2661	if (x86_pmu.aux_output_match)
2662	return x86_pmu.aux_output_match(event);
2663
2664	return 0;
2665	}
2666
2667	static bool x86_pmu_filter(struct pmu *pmu, int cpu)
2668	{
2669	bool ret = false;
2670
2671	static_call_cond(x86_pmu_filter)(pmu, cpu, &ret);
2672
2673	return ret;
2674	}
2675
2676	static struct pmu pmu = {
2677	.pmu_enable = x86_pmu_enable,
2678	.pmu_disable = x86_pmu_disable,
2679
2680	.attr_groups = x86_pmu_attr_groups,
2681
2682	.event_init = x86_pmu_event_init,
2683
2684	.event_mapped = x86_pmu_event_mapped,
2685	.event_unmapped = x86_pmu_event_unmapped,
2686
2687	.add = x86_pmu_add,
2688	.del = x86_pmu_del,
2689	.start = x86_pmu_start,
2690	.stop = x86_pmu_stop,
2691	.read = x86_pmu_read,
2692
2693	.start_txn = x86_pmu_start_txn,
2694	.cancel_txn = x86_pmu_cancel_txn,
2695	.commit_txn = x86_pmu_commit_txn,
2696
2697	.event_idx = x86_pmu_event_idx,
2698	.sched_task = x86_pmu_sched_task,
2699	.swap_task_ctx = x86_pmu_swap_task_ctx,
2700	.check_period = x86_pmu_check_period,
2701
2702	.aux_output_match = x86_pmu_aux_output_match,
2703
2704	.filter = x86_pmu_filter,
2705	};
2706
2707	void arch_perf_update_userpage(struct perf_event *event,
2708	struct perf_event_mmap_page *userpg, u64 now)
2709	{
2710	struct cyc2ns_data data;
2711	u64 offset;
2712
2713	userpg->cap_user_time = 0;
2714	userpg->cap_user_time_zero = 0;
2715	userpg->cap_user_rdpmc =
2716	!!(event->hw.flags & PERF_EVENT_FLAG_USER_READ_CNT);
2717	userpg->pmc_width = x86_pmu.cntval_bits;
2718
2719	if (!using_native_sched_clock() || !sched_clock_stable())
2720	return;
2721
2722	cyc2ns_read_begin(&data);
2723
2724	offset = data.cyc2ns_offset + __sched_clock_offset;
2725
2726	/*
2727	* Internal timekeeping for enabled/running/stopped times
2728	* is always in the local_clock domain.
2729	*/
2730	userpg->cap_user_time = 1;
2731	userpg->time_mult = data.cyc2ns_mul;
2732	userpg->time_shift = data.cyc2ns_shift;
2733	userpg->time_offset = offset - now;
2734
2735	/*
2736	* cap_user_time_zero doesn't make sense when we're using a different
2737	* time base for the records.
2738	*/
2739	if (!event->attr.use_clockid) {
2740	userpg->cap_user_time_zero = 1;
2741	userpg->time_zero = offset;
2742	}
2743
2744	cyc2ns_read_end();
2745	}
2746
2747	/*
2748	* Determine whether the regs were taken from an irq/exception handler rather
2749	* than from perf_arch_fetch_caller_regs().
2750	*/
2751	static bool perf_hw_regs(struct pt_regs *regs)
2752	{
2753	return regs->flags & X86_EFLAGS_FIXED;
2754	}
2755
2756	void
2757	perf_callchain_kernel(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs)
2758	{
2759	struct unwind_state state;
2760	unsigned long addr;
2761
2762	if (perf_guest_state()) {
2763	/* TODO: We don't support guest os callchain now */
2764	return;
2765	}
2766
2767	if (perf_callchain_store(ctx: entry, ip: regs->ip))
2768	return;
2769
2770	if (perf_hw_regs(regs))
2771	unwind_start(state: &state, current, regs, NULL);
2772	else
2773	unwind_start(state: &state, current, NULL, first_frame: (void *)regs->sp);
2774
2775	for (; !unwind_done(state: &state); unwind_next_frame(state: &state)) {
2776	addr = unwind_get_return_address(state: &state);
2777	if (!addr || perf_callchain_store(ctx: entry, ip: addr))
2778	return;
2779	}
2780	}
2781
2782	static inline int
2783	valid_user_frame(const void __user *fp, unsigned long size)
2784	{
2785	return __access_ok(ptr: fp, size);
2786	}
2787
2788	static unsigned long get_segment_base(unsigned int segment)
2789	{
2790	struct desc_struct *desc;
2791	unsigned int idx = segment >> 3;
2792
2793	if ((segment & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2794	#ifdef CONFIG_MODIFY_LDT_SYSCALL
2795	struct ldt_struct *ldt;
2796
2797	/* IRQs are off, so this synchronizes with smp_store_release */
2798	ldt = READ_ONCE(current->active_mm->context.ldt);
2799	if (!ldt || idx >= ldt->nr_entries)
2800	return 0;
2801
2802	desc = &ldt->entries[idx];
2803	#else
2804	return 0;
2805	#endif
2806	} else {
2807	if (idx >= GDT_ENTRIES)
2808	return 0;
2809
2810	desc = raw_cpu_ptr(gdt_page.gdt) + idx;
2811	}
2812
2813	return get_desc_base(desc);
2814	}
2815
2816	#ifdef CONFIG_IA32_EMULATION
2817
2818	#include <linux/compat.h>
2819
2820	static inline int
2821	perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry_ctx *entry)
2822	{
2823	/* 32-bit process in 64-bit kernel. */
2824	unsigned long ss_base, cs_base;
2825	struct stack_frame_ia32 frame;
2826	const struct stack_frame_ia32 __user *fp;
2827
2828	if (user_64bit_mode(regs))
2829	return 0;
2830
2831	cs_base = get_segment_base(segment: regs->cs);
2832	ss_base = get_segment_base(segment: regs->ss);
2833
2834	fp = compat_ptr(uptr: ss_base + regs->bp);
2835	pagefault_disable();
2836	while (entry->nr < entry->max_stack) {
2837	if (!valid_user_frame(fp, size: sizeof(frame)))
2838	break;
2839
2840	if (__get_user(frame.next_frame, &fp->next_frame))
2841	break;
2842	if (__get_user(frame.return_address, &fp->return_address))
2843	break;
2844
2845	perf_callchain_store(ctx: entry, ip: cs_base + frame.return_address);
2846	fp = compat_ptr(uptr: ss_base + frame.next_frame);
2847	}
2848	pagefault_enable();
2849	return 1;
2850	}
2851	#else
2852	static inline int
2853	perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry_ctx *entry)
2854	{
2855	return 0;
2856	}
2857	#endif
2858
2859	void
2860	perf_callchain_user(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs)
2861	{
2862	struct stack_frame frame;
2863	const struct stack_frame __user *fp;
2864
2865	if (perf_guest_state()) {
2866	/* TODO: We don't support guest os callchain now */
2867	return;
2868	}
2869
2870	/*
2871	* We don't know what to do with VM86 stacks.. ignore them for now.
2872	*/
2873	if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM))
2874	return;
2875
2876	fp = (void __user *)regs->bp;
2877
2878	perf_callchain_store(ctx: entry, ip: regs->ip);
2879
2880	if (!nmi_uaccess_okay())
2881	return;
2882
2883	if (perf_callchain_user32(regs, entry))
2884	return;
2885
2886	pagefault_disable();
2887	while (entry->nr < entry->max_stack) {
2888	if (!valid_user_frame(fp, size: sizeof(frame)))
2889	break;
2890
2891	if (__get_user(frame.next_frame, &fp->next_frame))
2892	break;
2893	if (__get_user(frame.return_address, &fp->return_address))
2894	break;
2895
2896	perf_callchain_store(ctx: entry, ip: frame.return_address);
2897	fp = (void __user *)frame.next_frame;
2898	}
2899	pagefault_enable();
2900	}
2901
2902	/*
2903	* Deal with code segment offsets for the various execution modes:
2904	*
2905	* VM86 - the good olde 16 bit days, where the linear address is
2906	* 20 bits and we use regs->ip + 0x10 * regs->cs.
2907	*
2908	* IA32 - Where we need to look at GDT/LDT segment descriptor tables
2909	* to figure out what the 32bit base address is.
2910	*
2911	* X32 - has TIF_X32 set, but is running in x86_64
2912	*
2913	* X86_64 - CS,DS,SS,ES are all zero based.
2914	*/
2915	static unsigned long code_segment_base(struct pt_regs *regs)
2916	{
2917	/*
2918	* For IA32 we look at the GDT/LDT segment base to convert the
2919	* effective IP to a linear address.
2920	*/
2921
2922	#ifdef CONFIG_X86_32
2923	/*
2924	* If we are in VM86 mode, add the segment offset to convert to a
2925	* linear address.
2926	*/
2927	if (regs->flags & X86_VM_MASK)
2928	return 0x10 * regs->cs;
2929
2930	if (user_mode(regs) && regs->cs != __USER_CS)
2931	return get_segment_base(regs->cs);
2932	#else
2933	if (user_mode(regs) && !user_64bit_mode(regs) &&
2934	regs->cs != __USER32_CS)
2935	return get_segment_base(segment: regs->cs);
2936	#endif
2937	return 0;
2938	}
2939
2940	unsigned long perf_instruction_pointer(struct pt_regs *regs)
2941	{
2942	if (perf_guest_state())
2943	return perf_guest_get_ip();
2944
2945	return regs->ip + code_segment_base(regs);
2946	}
2947
2948	unsigned long perf_misc_flags(struct pt_regs *regs)
2949	{
2950	unsigned int guest_state = perf_guest_state();
2951	int misc = 0;
2952
2953	if (guest_state) {
2954	if (guest_state & PERF_GUEST_USER)
2955	misc |= PERF_RECORD_MISC_GUEST_USER;
2956	else
2957	misc |= PERF_RECORD_MISC_GUEST_KERNEL;
2958	} else {
2959	if (user_mode(regs))
2960	misc |= PERF_RECORD_MISC_USER;
2961	else
2962	misc |= PERF_RECORD_MISC_KERNEL;
2963	}
2964
2965	if (regs->flags & PERF_EFLAGS_EXACT)
2966	misc |= PERF_RECORD_MISC_EXACT_IP;
2967
2968	return misc;
2969	}
2970
2971	void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
2972	{
2973	/* This API doesn't currently support enumerating hybrid PMUs. */
2974	if (WARN_ON_ONCE(cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) ||
2975	!x86_pmu_initialized()) {
2976	memset(cap, 0, sizeof(*cap));
2977	return;
2978	}
2979
2980	/*
2981	* Note, hybrid CPU models get tracked as having hybrid PMUs even when
2982	* all E-cores are disabled via BIOS. When E-cores are disabled, the
2983	* base PMU holds the correct number of counters for P-cores.
2984	*/
2985	cap->version = x86_pmu.version;
2986	cap->num_counters_gp = x86_pmu.num_counters;
2987	cap->num_counters_fixed = x86_pmu.num_counters_fixed;
2988	cap->bit_width_gp = x86_pmu.cntval_bits;
2989	cap->bit_width_fixed = x86_pmu.cntval_bits;
2990	cap->events_mask = (unsigned int)x86_pmu.events_maskl;
2991	cap->events_mask_len = x86_pmu.events_mask_len;
2992	cap->pebs_ept = x86_pmu.pebs_ept;
2993	}
2994	EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability);
2995
2996	u64 perf_get_hw_event_config(int hw_event)
2997	{
2998	int max = x86_pmu.max_events;
2999
3000	if (hw_event < max)
3001	return x86_pmu.event_map(array_index_nospec(hw_event, max));
3002
3003	return 0;
3004	}
3005	EXPORT_SYMBOL_GPL(perf_get_hw_event_config);
3006