1//===-- LoongArchFrameLowering.cpp - LoongArch Frame Information -*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the LoongArch implementation of TargetFrameLowering class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "LoongArchFrameLowering.h"
14#include "LoongArchMachineFunctionInfo.h"
15#include "LoongArchSubtarget.h"
16#include "MCTargetDesc/LoongArchBaseInfo.h"
17#include "MCTargetDesc/LoongArchMCTargetDesc.h"
18#include "llvm/CodeGen/MachineFrameInfo.h"
19#include "llvm/CodeGen/MachineFunction.h"
20#include "llvm/CodeGen/MachineInstrBuilder.h"
21#include "llvm/CodeGen/MachineRegisterInfo.h"
22#include "llvm/CodeGen/RegisterScavenging.h"
23#include "llvm/IR/DiagnosticInfo.h"
24#include "llvm/MC/MCDwarf.h"
25
26using namespace llvm;
27
28#define DEBUG_TYPE "loongarch-frame-lowering"
29
30// Return true if the specified function should have a dedicated frame
31// pointer register. This is true if frame pointer elimination is
32// disabled, if it needs dynamic stack realignment, if the function has
33// variable sized allocas, or if the frame address is taken.
34bool LoongArchFrameLowering::hasFP(const MachineFunction &MF) const {
35 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
36
37 const MachineFrameInfo &MFI = MF.getFrameInfo();
38 return MF.getTarget().Options.DisableFramePointerElim(MF) ||
39 RegInfo->hasStackRealignment(MF) || MFI.hasVarSizedObjects() ||
40 MFI.isFrameAddressTaken();
41}
42
43bool LoongArchFrameLowering::hasBP(const MachineFunction &MF) const {
44 const MachineFrameInfo &MFI = MF.getFrameInfo();
45 const TargetRegisterInfo *TRI = STI.getRegisterInfo();
46
47 return MFI.hasVarSizedObjects() && TRI->hasStackRealignment(MF);
48}
49
50void LoongArchFrameLowering::adjustReg(MachineBasicBlock &MBB,
51 MachineBasicBlock::iterator MBBI,
52 const DebugLoc &DL, Register DestReg,
53 Register SrcReg, int64_t Val,
54 MachineInstr::MIFlag Flag) const {
55 const LoongArchInstrInfo *TII = STI.getInstrInfo();
56 bool IsLA64 = STI.is64Bit();
57 unsigned Addi = IsLA64 ? LoongArch::ADDI_D : LoongArch::ADDI_W;
58
59 if (DestReg == SrcReg && Val == 0)
60 return;
61
62 if (isInt<12>(x: Val)) {
63 // addi.w/d $DstReg, $SrcReg, Val
64 BuildMI(MBB, MBBI, DL, TII->get(Addi), DestReg)
65 .addReg(SrcReg)
66 .addImm(Val)
67 .setMIFlag(Flag);
68 return;
69 }
70
71 // Try to split the offset across two ADDIs. We need to keep the stack pointer
72 // aligned after each ADDI. We need to determine the maximum value we can put
73 // in each ADDI. In the negative direction, we can use -2048 which is always
74 // sufficiently aligned. In the positive direction, we need to find the
75 // largest 12-bit immediate that is aligned. Exclude -4096 since it can be
76 // created with LU12I.W.
77 assert(getStackAlign().value() < 2048 && "Stack alignment too large");
78 int64_t MaxPosAdjStep = 2048 - getStackAlign().value();
79 if (Val > -4096 && Val <= (2 * MaxPosAdjStep)) {
80 int64_t FirstAdj = Val < 0 ? -2048 : MaxPosAdjStep;
81 Val -= FirstAdj;
82 BuildMI(MBB, MBBI, DL, TII->get(Addi), DestReg)
83 .addReg(SrcReg)
84 .addImm(FirstAdj)
85 .setMIFlag(Flag);
86 BuildMI(MBB, MBBI, DL, TII->get(Addi), DestReg)
87 .addReg(DestReg, RegState::Kill)
88 .addImm(Val)
89 .setMIFlag(Flag);
90 return;
91 }
92
93 unsigned Opc = IsLA64 ? LoongArch::ADD_D : LoongArch::ADD_W;
94 if (Val < 0) {
95 Val = -Val;
96 Opc = IsLA64 ? LoongArch::SUB_D : LoongArch::SUB_W;
97 }
98
99 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
100 Register ScratchReg = MRI.createVirtualRegister(&LoongArch::GPRRegClass);
101 TII->movImm(MBB, MBBI, DL, DstReg: ScratchReg, Val, Flag);
102 BuildMI(MBB, MBBI, DL, TII->get(Opc), DestReg)
103 .addReg(SrcReg)
104 .addReg(ScratchReg, RegState::Kill)
105 .setMIFlag(Flag);
106}
107
108// Determine the size of the frame and maximum call frame size.
109void LoongArchFrameLowering::determineFrameLayout(MachineFunction &MF) const {
110 MachineFrameInfo &MFI = MF.getFrameInfo();
111
112 // Get the number of bytes to allocate from the FrameInfo.
113 uint64_t FrameSize = MFI.getStackSize();
114
115 // Make sure the frame is aligned.
116 FrameSize = alignTo(Size: FrameSize, A: getStackAlign());
117
118 // Update frame info.
119 MFI.setStackSize(FrameSize);
120}
121
122static uint64_t estimateFunctionSizeInBytes(const LoongArchInstrInfo *TII,
123 const MachineFunction &MF) {
124 uint64_t FuncSize = 0;
125 for (auto &MBB : MF)
126 for (auto &MI : MBB)
127 FuncSize += TII->getInstSizeInBytes(MI);
128 return FuncSize;
129}
130
131static bool needScavSlotForCFR(MachineFunction &MF) {
132 if (!MF.getSubtarget<LoongArchSubtarget>().hasBasicF())
133 return false;
134 for (auto &MBB : MF)
135 for (auto &MI : MBB)
136 if (MI.getOpcode() == LoongArch::PseudoST_CFR)
137 return true;
138 return false;
139}
140
141void LoongArchFrameLowering::processFunctionBeforeFrameFinalized(
142 MachineFunction &MF, RegScavenger *RS) const {
143 const LoongArchRegisterInfo *RI = STI.getRegisterInfo();
144 const TargetRegisterClass &RC = LoongArch::GPRRegClass;
145 const LoongArchInstrInfo *TII = STI.getInstrInfo();
146 LoongArchMachineFunctionInfo *LAFI =
147 MF.getInfo<LoongArchMachineFunctionInfo>();
148 MachineFrameInfo &MFI = MF.getFrameInfo();
149
150 unsigned ScavSlotsNum = 0;
151
152 // Far branches beyond 27-bit offset require a spill slot for scratch register.
153 bool IsLargeFunction = !isInt<27>(x: estimateFunctionSizeInBytes(TII, MF));
154 if (IsLargeFunction)
155 ScavSlotsNum = 1;
156
157 // estimateStackSize has been observed to under-estimate the final stack
158 // size, so give ourselves wiggle-room by checking for stack size
159 // representable an 11-bit signed field rather than 12-bits.
160 if (!isInt<11>(x: MFI.estimateStackSize(MF)))
161 ScavSlotsNum = std::max(a: ScavSlotsNum, b: 1u);
162
163 // For CFR spill.
164 if (needScavSlotForCFR(MF))
165 ++ScavSlotsNum;
166
167 // Create emergency spill slots.
168 for (unsigned i = 0; i < ScavSlotsNum; ++i) {
169 int FI = MFI.CreateStackObject(Size: RI->getSpillSize(RC), Alignment: RI->getSpillAlign(RC),
170 isSpillSlot: false);
171 RS->addScavengingFrameIndex(FI);
172 if (IsLargeFunction && LAFI->getBranchRelaxationSpillFrameIndex() == -1)
173 LAFI->setBranchRelaxationSpillFrameIndex(FI);
174 LLVM_DEBUG(dbgs() << "Allocated FI(" << FI
175 << ") as the emergency spill slot.\n");
176 }
177}
178
179void LoongArchFrameLowering::emitPrologue(MachineFunction &MF,
180 MachineBasicBlock &MBB) const {
181 MachineFrameInfo &MFI = MF.getFrameInfo();
182 auto *LoongArchFI = MF.getInfo<LoongArchMachineFunctionInfo>();
183 const LoongArchRegisterInfo *RI = STI.getRegisterInfo();
184 const LoongArchInstrInfo *TII = STI.getInstrInfo();
185 MachineBasicBlock::iterator MBBI = MBB.begin();
186 bool IsLA64 = STI.is64Bit();
187
188 Register SPReg = LoongArch::R3;
189 Register FPReg = LoongArch::R22;
190
191 // Debug location must be unknown since the first debug location is used
192 // to determine the end of the prologue.
193 DebugLoc DL;
194 // All calls are tail calls in GHC calling conv, and functions have no
195 // prologue/epilogue.
196 if (MF.getFunction().getCallingConv() == CallingConv::GHC)
197 return;
198 // Determine the correct frame layout
199 determineFrameLayout(MF);
200
201 // First, compute final stack size.
202 uint64_t StackSize = MFI.getStackSize();
203 uint64_t RealStackSize = StackSize;
204
205 // Early exit if there is no need to allocate space in the stack.
206 if (StackSize == 0 && !MFI.adjustsStack())
207 return;
208
209 uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount(MF);
210 // Split the SP adjustment to reduce the offsets of callee saved spill.
211 if (FirstSPAdjustAmount)
212 StackSize = FirstSPAdjustAmount;
213
214 // Adjust stack.
215 adjustReg(MBB, MBBI, DL, DestReg: SPReg, SrcReg: SPReg, Val: -StackSize, Flag: MachineInstr::FrameSetup);
216 // Emit ".cfi_def_cfa_offset StackSize".
217 unsigned CFIIndex =
218 MF.addFrameInst(Inst: MCCFIInstruction::cfiDefCfaOffset(L: nullptr, Offset: StackSize));
219 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
220 .addCFIIndex(CFIIndex)
221 .setMIFlag(MachineInstr::FrameSetup);
222
223 const auto &CSI = MFI.getCalleeSavedInfo();
224
225 // The frame pointer is callee-saved, and code has been generated for us to
226 // save it to the stack. We need to skip over the storing of callee-saved
227 // registers as the frame pointer must be modified after it has been saved
228 // to the stack, not before.
229 std::advance(i&: MBBI, n: CSI.size());
230
231 // Iterate over list of callee-saved registers and emit .cfi_offset
232 // directives.
233 for (const auto &Entry : CSI) {
234 int64_t Offset = MFI.getObjectOffset(ObjectIdx: Entry.getFrameIdx());
235 unsigned CFIIndex = MF.addFrameInst(Inst: MCCFIInstruction::createOffset(
236 L: nullptr, Register: RI->getDwarfRegNum(Entry.getReg(), true), Offset));
237 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
238 .addCFIIndex(CFIIndex)
239 .setMIFlag(MachineInstr::FrameSetup);
240 }
241
242 // Generate new FP.
243 if (hasFP(MF)) {
244 adjustReg(MBB, MBBI, DL, DestReg: FPReg, SrcReg: SPReg,
245 Val: StackSize - LoongArchFI->getVarArgsSaveSize(),
246 Flag: MachineInstr::FrameSetup);
247
248 // Emit ".cfi_def_cfa $fp, LoongArchFI->getVarArgsSaveSize()"
249 unsigned CFIIndex = MF.addFrameInst(
250 Inst: MCCFIInstruction::cfiDefCfa(L: nullptr, Register: RI->getDwarfRegNum(FPReg, true),
251 Offset: LoongArchFI->getVarArgsSaveSize()));
252 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
253 .addCFIIndex(CFIIndex)
254 .setMIFlag(MachineInstr::FrameSetup);
255 }
256
257 // Emit the second SP adjustment after saving callee saved registers.
258 if (FirstSPAdjustAmount) {
259 uint64_t SecondSPAdjustAmount = RealStackSize - FirstSPAdjustAmount;
260 assert(SecondSPAdjustAmount > 0 &&
261 "SecondSPAdjustAmount should be greater than zero");
262 adjustReg(MBB, MBBI, DL, DestReg: SPReg, SrcReg: SPReg, Val: -SecondSPAdjustAmount,
263 Flag: MachineInstr::FrameSetup);
264
265 if (!hasFP(MF)) {
266 // If we are using a frame-pointer, and thus emitted ".cfi_def_cfa fp, 0",
267 // don't emit an sp-based .cfi_def_cfa_offset
268 // Emit ".cfi_def_cfa_offset RealStackSize"
269 unsigned CFIIndex = MF.addFrameInst(
270 Inst: MCCFIInstruction::cfiDefCfaOffset(L: nullptr, Offset: RealStackSize));
271 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
272 .addCFIIndex(CFIIndex)
273 .setMIFlag(MachineInstr::FrameSetup);
274 }
275 }
276
277 if (hasFP(MF)) {
278 // Realign stack.
279 if (RI->hasStackRealignment(MF)) {
280 unsigned Align = Log2(A: MFI.getMaxAlign());
281 assert(Align > 0 && "The stack realignment size is invalid!");
282 BuildMI(MBB, MBBI, DL,
283 TII->get(IsLA64 ? LoongArch::BSTRINS_D : LoongArch::BSTRINS_W),
284 SPReg)
285 .addReg(SPReg)
286 .addReg(LoongArch::R0)
287 .addImm(Align - 1)
288 .addImm(0)
289 .setMIFlag(MachineInstr::FrameSetup);
290 // FP will be used to restore the frame in the epilogue, so we need
291 // another base register BP to record SP after re-alignment. SP will
292 // track the current stack after allocating variable sized objects.
293 if (hasBP(MF)) {
294 // move BP, $sp
295 BuildMI(MBB, MBBI, DL, TII->get(LoongArch::OR),
296 LoongArchABI::getBPReg())
297 .addReg(SPReg)
298 .addReg(LoongArch::R0)
299 .setMIFlag(MachineInstr::FrameSetup);
300 }
301 }
302 }
303}
304
305void LoongArchFrameLowering::emitEpilogue(MachineFunction &MF,
306 MachineBasicBlock &MBB) const {
307 const LoongArchRegisterInfo *RI = STI.getRegisterInfo();
308 MachineFrameInfo &MFI = MF.getFrameInfo();
309 auto *LoongArchFI = MF.getInfo<LoongArchMachineFunctionInfo>();
310 Register SPReg = LoongArch::R3;
311 // All calls are tail calls in GHC calling conv, and functions have no
312 // prologue/epilogue.
313 if (MF.getFunction().getCallingConv() == CallingConv::GHC)
314 return;
315 MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator();
316 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
317
318 const auto &CSI = MFI.getCalleeSavedInfo();
319 // Skip to before the restores of callee-saved registers.
320 auto LastFrameDestroy = MBBI;
321 if (!CSI.empty())
322 LastFrameDestroy = std::prev(x: MBBI, n: CSI.size());
323
324 // Get the number of bytes from FrameInfo.
325 uint64_t StackSize = MFI.getStackSize();
326
327 // Restore the stack pointer.
328 if (RI->hasStackRealignment(MF) || MFI.hasVarSizedObjects()) {
329 assert(hasFP(MF) && "frame pointer should not have been eliminated");
330 adjustReg(MBB, MBBI: LastFrameDestroy, DL, DestReg: SPReg, LoongArch::SrcReg: R22,
331 Val: -StackSize + LoongArchFI->getVarArgsSaveSize(),
332 Flag: MachineInstr::FrameDestroy);
333 }
334
335 uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount(MF);
336 if (FirstSPAdjustAmount) {
337 uint64_t SecondSPAdjustAmount = StackSize - FirstSPAdjustAmount;
338 assert(SecondSPAdjustAmount > 0 &&
339 "SecondSPAdjustAmount should be greater than zero");
340
341 adjustReg(MBB, MBBI: LastFrameDestroy, DL, DestReg: SPReg, SrcReg: SPReg, Val: SecondSPAdjustAmount,
342 Flag: MachineInstr::FrameDestroy);
343 StackSize = FirstSPAdjustAmount;
344 }
345
346 // Deallocate stack
347 adjustReg(MBB, MBBI, DL, DestReg: SPReg, SrcReg: SPReg, Val: StackSize, Flag: MachineInstr::FrameDestroy);
348}
349
350// We would like to split the SP adjustment to reduce prologue/epilogue
351// as following instructions. In this way, the offset of the callee saved
352// register could fit in a single store.
353// e.g.
354// addi.d $sp, $sp, -2032
355// st.d $ra, $sp, 2024
356// st.d $fp, $sp, 2016
357// addi.d $sp, $sp, -16
358uint64_t LoongArchFrameLowering::getFirstSPAdjustAmount(
359 const MachineFunction &MF) const {
360 const MachineFrameInfo &MFI = MF.getFrameInfo();
361 const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
362
363 // Return the FirstSPAdjustAmount if the StackSize can not fit in a signed
364 // 12-bit and there exists a callee-saved register needing to be pushed.
365 if (!isInt<12>(x: MFI.getStackSize()) && (CSI.size() > 0)) {
366 // FirstSPAdjustAmount is chosen as (2048 - StackAlign) because 2048 will
367 // cause sp = sp + 2048 in the epilogue to be split into multiple
368 // instructions. Offsets smaller than 2048 can fit in a single load/store
369 // instruction, and we have to stick with the stack alignment.
370 // So (2048 - StackAlign) will satisfy the stack alignment.
371 return 2048 - getStackAlign().value();
372 }
373 return 0;
374}
375
376void LoongArchFrameLowering::determineCalleeSaves(MachineFunction &MF,
377 BitVector &SavedRegs,
378 RegScavenger *RS) const {
379 TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
380 // Unconditionally spill RA and FP only if the function uses a frame
381 // pointer.
382 if (hasFP(MF)) {
383 SavedRegs.set(LoongArch::R1);
384 SavedRegs.set(LoongArch::R22);
385 }
386 // Mark BP as used if function has dedicated base pointer.
387 if (hasBP(MF))
388 SavedRegs.set(LoongArchABI::getBPReg());
389}
390
391// Do not preserve stack space within prologue for outgoing variables if the
392// function contains variable size objects.
393// Let eliminateCallFramePseudoInstr preserve stack space for it.
394bool LoongArchFrameLowering::hasReservedCallFrame(
395 const MachineFunction &MF) const {
396 return !MF.getFrameInfo().hasVarSizedObjects();
397}
398
399// Eliminate ADJCALLSTACKDOWN, ADJCALLSTACKUP pseudo instructions.
400MachineBasicBlock::iterator
401LoongArchFrameLowering::eliminateCallFramePseudoInstr(
402 MachineFunction &MF, MachineBasicBlock &MBB,
403 MachineBasicBlock::iterator MI) const {
404 Register SPReg = LoongArch::R3;
405 DebugLoc DL = MI->getDebugLoc();
406
407 if (!hasReservedCallFrame(MF)) {
408 // If space has not been reserved for a call frame, ADJCALLSTACKDOWN and
409 // ADJCALLSTACKUP must be converted to instructions manipulating the stack
410 // pointer. This is necessary when there is a variable length stack
411 // allocation (e.g. alloca), which means it's not possible to allocate
412 // space for outgoing arguments from within the function prologue.
413 int64_t Amount = MI->getOperand(i: 0).getImm();
414
415 if (Amount != 0) {
416 // Ensure the stack remains aligned after adjustment.
417 Amount = alignSPAdjust(SPAdj: Amount);
418
419 if (MI->getOpcode() == LoongArch::ADJCALLSTACKDOWN)
420 Amount = -Amount;
421
422 adjustReg(MBB, MBBI: MI, DL, DestReg: SPReg, SrcReg: SPReg, Val: Amount, Flag: MachineInstr::NoFlags);
423 }
424 }
425
426 return MBB.erase(I: MI);
427}
428
429bool LoongArchFrameLowering::spillCalleeSavedRegisters(
430 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
431 ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {
432 if (CSI.empty())
433 return true;
434
435 MachineFunction *MF = MBB.getParent();
436 const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();
437
438 // Insert the spill to the stack frame.
439 for (auto &CS : CSI) {
440 Register Reg = CS.getReg();
441 // If the register is RA and the return address is taken by method
442 // LoongArchTargetLowering::lowerRETURNADDR, don't set kill flag.
443 bool IsKill =
444 !(Reg == LoongArch::R1 && MF->getFrameInfo().isReturnAddressTaken());
445 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
446 TII.storeRegToStackSlot(MBB, MI, SrcReg: Reg, isKill: IsKill, FrameIndex: CS.getFrameIdx(), RC, TRI,
447 VReg: Register());
448 }
449
450 return true;
451}
452
453StackOffset LoongArchFrameLowering::getFrameIndexReference(
454 const MachineFunction &MF, int FI, Register &FrameReg) const {
455 const MachineFrameInfo &MFI = MF.getFrameInfo();
456 const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo();
457 auto *LoongArchFI = MF.getInfo<LoongArchMachineFunctionInfo>();
458 uint64_t StackSize = MFI.getStackSize();
459 uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount(MF);
460
461 // Callee-saved registers should be referenced relative to the stack
462 // pointer (positive offset), otherwise use the frame pointer (negative
463 // offset).
464 const auto &CSI = MFI.getCalleeSavedInfo();
465 int MinCSFI = 0;
466 int MaxCSFI = -1;
467 StackOffset Offset =
468 StackOffset::getFixed(Fixed: MFI.getObjectOffset(ObjectIdx: FI) - getOffsetOfLocalArea() +
469 MFI.getOffsetAdjustment());
470
471 if (CSI.size()) {
472 MinCSFI = CSI[0].getFrameIdx();
473 MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();
474 }
475
476 if (FI >= MinCSFI && FI <= MaxCSFI) {
477 FrameReg = LoongArch::R3;
478 if (FirstSPAdjustAmount)
479 Offset += StackOffset::getFixed(Fixed: FirstSPAdjustAmount);
480 else
481 Offset += StackOffset::getFixed(Fixed: StackSize);
482 } else if (RI->hasStackRealignment(MF) && !MFI.isFixedObjectIndex(ObjectIdx: FI)) {
483 // If the stack was realigned, the frame pointer is set in order to allow
484 // SP to be restored, so we need another base register to record the stack
485 // after realignment.
486 FrameReg = hasBP(MF) ? LoongArchABI::getBPReg() : LoongArch::R3;
487 Offset += StackOffset::getFixed(Fixed: StackSize);
488 } else {
489 FrameReg = RI->getFrameRegister(MF);
490 if (hasFP(MF))
491 Offset += StackOffset::getFixed(Fixed: LoongArchFI->getVarArgsSaveSize());
492 else
493 Offset += StackOffset::getFixed(Fixed: StackSize);
494 }
495
496 return Offset;
497}
498
499bool LoongArchFrameLowering::enableShrinkWrapping(
500 const MachineFunction &MF) const {
501 // Keep the conventional code flow when not optimizing.
502 if (MF.getFunction().hasOptNone())
503 return false;
504
505 return true;
506}
507

source code of llvm/lib/Target/LoongArch/LoongArchFrameLowering.cpp