1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Cadence MACB/GEM Ethernet Controller driver
4 *
5 * Copyright (C) 2004-2006 Atmel Corporation
6 */
7
8#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9#include <linux/clk.h>
10#include <linux/clk-provider.h>
11#include <linux/crc32.h>
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/kernel.h>
15#include <linux/types.h>
16#include <linux/circ_buf.h>
17#include <linux/slab.h>
18#include <linux/init.h>
19#include <linux/io.h>
20#include <linux/interrupt.h>
21#include <linux/netdevice.h>
22#include <linux/etherdevice.h>
23#include <linux/dma-mapping.h>
24#include <linux/platform_device.h>
25#include <linux/phylink.h>
26#include <linux/of.h>
27#include <linux/of_mdio.h>
28#include <linux/of_net.h>
29#include <linux/ip.h>
30#include <linux/udp.h>
31#include <linux/tcp.h>
32#include <linux/iopoll.h>
33#include <linux/phy/phy.h>
34#include <linux/pm_runtime.h>
35#include <linux/ptp_classify.h>
36#include <linux/reset.h>
37#include <linux/firmware/xlnx-zynqmp.h>
38#include <linux/inetdevice.h>
39#include "macb.h"
40
41/* This structure is only used for MACB on SiFive FU540 devices */
42struct sifive_fu540_macb_mgmt {
43 void __iomem *reg;
44 unsigned long rate;
45 struct clk_hw hw;
46};
47
48#define MACB_RX_BUFFER_SIZE 128
49#define RX_BUFFER_MULTIPLE 64 /* bytes */
50
51#define DEFAULT_RX_RING_SIZE 512 /* must be power of 2 */
52#define MIN_RX_RING_SIZE 64
53#define MAX_RX_RING_SIZE 8192
54#define RX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \
55 * (bp)->rx_ring_size)
56
57#define DEFAULT_TX_RING_SIZE 512 /* must be power of 2 */
58#define MIN_TX_RING_SIZE 64
59#define MAX_TX_RING_SIZE 4096
60#define TX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \
61 * (bp)->tx_ring_size)
62
63/* level of occupied TX descriptors under which we wake up TX process */
64#define MACB_TX_WAKEUP_THRESH(bp) (3 * (bp)->tx_ring_size / 4)
65
66#define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(ISR_ROVR))
67#define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \
68 | MACB_BIT(ISR_RLE) \
69 | MACB_BIT(TXERR))
70#define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP) \
71 | MACB_BIT(TXUBR))
72
73/* Max length of transmit frame must be a multiple of 8 bytes */
74#define MACB_TX_LEN_ALIGN 8
75#define MACB_MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN - 1)))
76/* Limit maximum TX length as per Cadence TSO errata. This is to avoid a
77 * false amba_error in TX path from the DMA assuming there is not enough
78 * space in the SRAM (16KB) even when there is.
79 */
80#define GEM_MAX_TX_LEN (unsigned int)(0x3FC0)
81
82#define GEM_MTU_MIN_SIZE ETH_MIN_MTU
83#define MACB_NETIF_LSO NETIF_F_TSO
84
85#define MACB_WOL_ENABLED BIT(0)
86
87#define HS_SPEED_10000M 4
88#define MACB_SERDES_RATE_10G 1
89
90/* Graceful stop timeouts in us. We should allow up to
91 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
92 */
93#define MACB_HALT_TIMEOUT 14000
94#define MACB_PM_TIMEOUT 100 /* ms */
95
96#define MACB_MDIO_TIMEOUT 1000000 /* in usecs */
97
98/* DMA buffer descriptor might be different size
99 * depends on hardware configuration:
100 *
101 * 1. dma address width 32 bits:
102 * word 1: 32 bit address of Data Buffer
103 * word 2: control
104 *
105 * 2. dma address width 64 bits:
106 * word 1: 32 bit address of Data Buffer
107 * word 2: control
108 * word 3: upper 32 bit address of Data Buffer
109 * word 4: unused
110 *
111 * 3. dma address width 32 bits with hardware timestamping:
112 * word 1: 32 bit address of Data Buffer
113 * word 2: control
114 * word 3: timestamp word 1
115 * word 4: timestamp word 2
116 *
117 * 4. dma address width 64 bits with hardware timestamping:
118 * word 1: 32 bit address of Data Buffer
119 * word 2: control
120 * word 3: upper 32 bit address of Data Buffer
121 * word 4: unused
122 * word 5: timestamp word 1
123 * word 6: timestamp word 2
124 */
125static unsigned int macb_dma_desc_get_size(struct macb *bp)
126{
127#ifdef MACB_EXT_DESC
128 unsigned int desc_size;
129
130 switch (bp->hw_dma_cap) {
131 case HW_DMA_CAP_64B:
132 desc_size = sizeof(struct macb_dma_desc)
133 + sizeof(struct macb_dma_desc_64);
134 break;
135 case HW_DMA_CAP_PTP:
136 desc_size = sizeof(struct macb_dma_desc)
137 + sizeof(struct macb_dma_desc_ptp);
138 break;
139 case HW_DMA_CAP_64B_PTP:
140 desc_size = sizeof(struct macb_dma_desc)
141 + sizeof(struct macb_dma_desc_64)
142 + sizeof(struct macb_dma_desc_ptp);
143 break;
144 default:
145 desc_size = sizeof(struct macb_dma_desc);
146 }
147 return desc_size;
148#endif
149 return sizeof(struct macb_dma_desc);
150}
151
152static unsigned int macb_adj_dma_desc_idx(struct macb *bp, unsigned int desc_idx)
153{
154#ifdef MACB_EXT_DESC
155 switch (bp->hw_dma_cap) {
156 case HW_DMA_CAP_64B:
157 case HW_DMA_CAP_PTP:
158 desc_idx <<= 1;
159 break;
160 case HW_DMA_CAP_64B_PTP:
161 desc_idx *= 3;
162 break;
163 default:
164 break;
165 }
166#endif
167 return desc_idx;
168}
169
170#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
171static struct macb_dma_desc_64 *macb_64b_desc(struct macb *bp, struct macb_dma_desc *desc)
172{
173 return (struct macb_dma_desc_64 *)((void *)desc
174 + sizeof(struct macb_dma_desc));
175}
176#endif
177
178/* Ring buffer accessors */
179static unsigned int macb_tx_ring_wrap(struct macb *bp, unsigned int index)
180{
181 return index & (bp->tx_ring_size - 1);
182}
183
184static struct macb_dma_desc *macb_tx_desc(struct macb_queue *queue,
185 unsigned int index)
186{
187 index = macb_tx_ring_wrap(bp: queue->bp, index);
188 index = macb_adj_dma_desc_idx(bp: queue->bp, desc_idx: index);
189 return &queue->tx_ring[index];
190}
191
192static struct macb_tx_skb *macb_tx_skb(struct macb_queue *queue,
193 unsigned int index)
194{
195 return &queue->tx_skb[macb_tx_ring_wrap(bp: queue->bp, index)];
196}
197
198static dma_addr_t macb_tx_dma(struct macb_queue *queue, unsigned int index)
199{
200 dma_addr_t offset;
201
202 offset = macb_tx_ring_wrap(bp: queue->bp, index) *
203 macb_dma_desc_get_size(bp: queue->bp);
204
205 return queue->tx_ring_dma + offset;
206}
207
208static unsigned int macb_rx_ring_wrap(struct macb *bp, unsigned int index)
209{
210 return index & (bp->rx_ring_size - 1);
211}
212
213static struct macb_dma_desc *macb_rx_desc(struct macb_queue *queue, unsigned int index)
214{
215 index = macb_rx_ring_wrap(bp: queue->bp, index);
216 index = macb_adj_dma_desc_idx(bp: queue->bp, desc_idx: index);
217 return &queue->rx_ring[index];
218}
219
220static void *macb_rx_buffer(struct macb_queue *queue, unsigned int index)
221{
222 return queue->rx_buffers + queue->bp->rx_buffer_size *
223 macb_rx_ring_wrap(bp: queue->bp, index);
224}
225
226/* I/O accessors */
227static u32 hw_readl_native(struct macb *bp, int offset)
228{
229 return __raw_readl(addr: bp->regs + offset);
230}
231
232static void hw_writel_native(struct macb *bp, int offset, u32 value)
233{
234 __raw_writel(val: value, addr: bp->regs + offset);
235}
236
237static u32 hw_readl(struct macb *bp, int offset)
238{
239 return readl_relaxed(bp->regs + offset);
240}
241
242static void hw_writel(struct macb *bp, int offset, u32 value)
243{
244 writel_relaxed(value, bp->regs + offset);
245}
246
247/* Find the CPU endianness by using the loopback bit of NCR register. When the
248 * CPU is in big endian we need to program swapped mode for management
249 * descriptor access.
250 */
251static bool hw_is_native_io(void __iomem *addr)
252{
253 u32 value = MACB_BIT(LLB);
254
255 __raw_writel(val: value, addr: addr + MACB_NCR);
256 value = __raw_readl(addr: addr + MACB_NCR);
257
258 /* Write 0 back to disable everything */
259 __raw_writel(val: 0, addr: addr + MACB_NCR);
260
261 return value == MACB_BIT(LLB);
262}
263
264static bool hw_is_gem(void __iomem *addr, bool native_io)
265{
266 u32 id;
267
268 if (native_io)
269 id = __raw_readl(addr: addr + MACB_MID);
270 else
271 id = readl_relaxed(addr + MACB_MID);
272
273 return MACB_BFEXT(IDNUM, id) >= 0x2;
274}
275
276static void macb_set_hwaddr(struct macb *bp)
277{
278 u32 bottom;
279 u16 top;
280
281 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
282 macb_or_gem_writel(bp, SA1B, bottom);
283 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
284 macb_or_gem_writel(bp, SA1T, top);
285
286 if (gem_has_ptp(bp)) {
287 gem_writel(bp, RXPTPUNI, bottom);
288 gem_writel(bp, TXPTPUNI, bottom);
289 }
290
291 /* Clear unused address register sets */
292 macb_or_gem_writel(bp, SA2B, 0);
293 macb_or_gem_writel(bp, SA2T, 0);
294 macb_or_gem_writel(bp, SA3B, 0);
295 macb_or_gem_writel(bp, SA3T, 0);
296 macb_or_gem_writel(bp, SA4B, 0);
297 macb_or_gem_writel(bp, SA4T, 0);
298}
299
300static void macb_get_hwaddr(struct macb *bp)
301{
302 u32 bottom;
303 u16 top;
304 u8 addr[6];
305 int i;
306
307 /* Check all 4 address register for valid address */
308 for (i = 0; i < 4; i++) {
309 bottom = macb_or_gem_readl(bp, SA1B + i * 8);
310 top = macb_or_gem_readl(bp, SA1T + i * 8);
311
312 addr[0] = bottom & 0xff;
313 addr[1] = (bottom >> 8) & 0xff;
314 addr[2] = (bottom >> 16) & 0xff;
315 addr[3] = (bottom >> 24) & 0xff;
316 addr[4] = top & 0xff;
317 addr[5] = (top >> 8) & 0xff;
318
319 if (is_valid_ether_addr(addr)) {
320 eth_hw_addr_set(dev: bp->dev, addr);
321 return;
322 }
323 }
324
325 dev_info(&bp->pdev->dev, "invalid hw address, using random\n");
326 eth_hw_addr_random(dev: bp->dev);
327}
328
329static int macb_mdio_wait_for_idle(struct macb *bp)
330{
331 u32 val;
332
333 return readx_poll_timeout(MACB_READ_NSR, bp, val, val & MACB_BIT(IDLE),
334 1, MACB_MDIO_TIMEOUT);
335}
336
337static int macb_mdio_read_c22(struct mii_bus *bus, int mii_id, int regnum)
338{
339 struct macb *bp = bus->priv;
340 int status;
341
342 status = pm_runtime_resume_and_get(dev: &bp->pdev->dev);
343 if (status < 0)
344 goto mdio_pm_exit;
345
346 status = macb_mdio_wait_for_idle(bp);
347 if (status < 0)
348 goto mdio_read_exit;
349
350 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C22_SOF)
351 | MACB_BF(RW, MACB_MAN_C22_READ)
352 | MACB_BF(PHYA, mii_id)
353 | MACB_BF(REGA, regnum)
354 | MACB_BF(CODE, MACB_MAN_C22_CODE)));
355
356 status = macb_mdio_wait_for_idle(bp);
357 if (status < 0)
358 goto mdio_read_exit;
359
360 status = MACB_BFEXT(DATA, macb_readl(bp, MAN));
361
362mdio_read_exit:
363 pm_runtime_mark_last_busy(dev: &bp->pdev->dev);
364 pm_runtime_put_autosuspend(dev: &bp->pdev->dev);
365mdio_pm_exit:
366 return status;
367}
368
369static int macb_mdio_read_c45(struct mii_bus *bus, int mii_id, int devad,
370 int regnum)
371{
372 struct macb *bp = bus->priv;
373 int status;
374
375 status = pm_runtime_get_sync(dev: &bp->pdev->dev);
376 if (status < 0) {
377 pm_runtime_put_noidle(dev: &bp->pdev->dev);
378 goto mdio_pm_exit;
379 }
380
381 status = macb_mdio_wait_for_idle(bp);
382 if (status < 0)
383 goto mdio_read_exit;
384
385 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
386 | MACB_BF(RW, MACB_MAN_C45_ADDR)
387 | MACB_BF(PHYA, mii_id)
388 | MACB_BF(REGA, devad & 0x1F)
389 | MACB_BF(DATA, regnum & 0xFFFF)
390 | MACB_BF(CODE, MACB_MAN_C45_CODE)));
391
392 status = macb_mdio_wait_for_idle(bp);
393 if (status < 0)
394 goto mdio_read_exit;
395
396 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
397 | MACB_BF(RW, MACB_MAN_C45_READ)
398 | MACB_BF(PHYA, mii_id)
399 | MACB_BF(REGA, devad & 0x1F)
400 | MACB_BF(CODE, MACB_MAN_C45_CODE)));
401
402 status = macb_mdio_wait_for_idle(bp);
403 if (status < 0)
404 goto mdio_read_exit;
405
406 status = MACB_BFEXT(DATA, macb_readl(bp, MAN));
407
408mdio_read_exit:
409 pm_runtime_mark_last_busy(dev: &bp->pdev->dev);
410 pm_runtime_put_autosuspend(dev: &bp->pdev->dev);
411mdio_pm_exit:
412 return status;
413}
414
415static int macb_mdio_write_c22(struct mii_bus *bus, int mii_id, int regnum,
416 u16 value)
417{
418 struct macb *bp = bus->priv;
419 int status;
420
421 status = pm_runtime_resume_and_get(dev: &bp->pdev->dev);
422 if (status < 0)
423 goto mdio_pm_exit;
424
425 status = macb_mdio_wait_for_idle(bp);
426 if (status < 0)
427 goto mdio_write_exit;
428
429 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C22_SOF)
430 | MACB_BF(RW, MACB_MAN_C22_WRITE)
431 | MACB_BF(PHYA, mii_id)
432 | MACB_BF(REGA, regnum)
433 | MACB_BF(CODE, MACB_MAN_C22_CODE)
434 | MACB_BF(DATA, value)));
435
436 status = macb_mdio_wait_for_idle(bp);
437 if (status < 0)
438 goto mdio_write_exit;
439
440mdio_write_exit:
441 pm_runtime_mark_last_busy(dev: &bp->pdev->dev);
442 pm_runtime_put_autosuspend(dev: &bp->pdev->dev);
443mdio_pm_exit:
444 return status;
445}
446
447static int macb_mdio_write_c45(struct mii_bus *bus, int mii_id,
448 int devad, int regnum,
449 u16 value)
450{
451 struct macb *bp = bus->priv;
452 int status;
453
454 status = pm_runtime_get_sync(dev: &bp->pdev->dev);
455 if (status < 0) {
456 pm_runtime_put_noidle(dev: &bp->pdev->dev);
457 goto mdio_pm_exit;
458 }
459
460 status = macb_mdio_wait_for_idle(bp);
461 if (status < 0)
462 goto mdio_write_exit;
463
464 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
465 | MACB_BF(RW, MACB_MAN_C45_ADDR)
466 | MACB_BF(PHYA, mii_id)
467 | MACB_BF(REGA, devad & 0x1F)
468 | MACB_BF(DATA, regnum & 0xFFFF)
469 | MACB_BF(CODE, MACB_MAN_C45_CODE)));
470
471 status = macb_mdio_wait_for_idle(bp);
472 if (status < 0)
473 goto mdio_write_exit;
474
475 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
476 | MACB_BF(RW, MACB_MAN_C45_WRITE)
477 | MACB_BF(PHYA, mii_id)
478 | MACB_BF(REGA, devad & 0x1F)
479 | MACB_BF(CODE, MACB_MAN_C45_CODE)
480 | MACB_BF(DATA, value)));
481
482 status = macb_mdio_wait_for_idle(bp);
483 if (status < 0)
484 goto mdio_write_exit;
485
486mdio_write_exit:
487 pm_runtime_mark_last_busy(dev: &bp->pdev->dev);
488 pm_runtime_put_autosuspend(dev: &bp->pdev->dev);
489mdio_pm_exit:
490 return status;
491}
492
493static void macb_init_buffers(struct macb *bp)
494{
495 struct macb_queue *queue;
496 unsigned int q;
497
498 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
499 queue_writel(queue, RBQP, lower_32_bits(queue->rx_ring_dma));
500#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
501 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
502 queue_writel(queue, RBQPH,
503 upper_32_bits(queue->rx_ring_dma));
504#endif
505 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
506#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
507 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
508 queue_writel(queue, TBQPH,
509 upper_32_bits(queue->tx_ring_dma));
510#endif
511 }
512}
513
514/**
515 * macb_set_tx_clk() - Set a clock to a new frequency
516 * @bp: pointer to struct macb
517 * @speed: New frequency in Hz
518 */
519static void macb_set_tx_clk(struct macb *bp, int speed)
520{
521 long ferr, rate, rate_rounded;
522
523 if (!bp->tx_clk || (bp->caps & MACB_CAPS_CLK_HW_CHG))
524 return;
525
526 /* In case of MII the PHY is the clock master */
527 if (bp->phy_interface == PHY_INTERFACE_MODE_MII)
528 return;
529
530 rate = rgmii_clock(speed);
531 if (rate < 0)
532 return;
533
534 rate_rounded = clk_round_rate(clk: bp->tx_clk, rate);
535 if (rate_rounded < 0)
536 return;
537
538 /* RGMII allows 50 ppm frequency error. Test and warn if this limit
539 * is not satisfied.
540 */
541 ferr = abs(rate_rounded - rate);
542 ferr = DIV_ROUND_UP(ferr, rate / 100000);
543 if (ferr > 5)
544 netdev_warn(dev: bp->dev,
545 format: "unable to generate target frequency: %ld Hz\n",
546 rate);
547
548 if (clk_set_rate(clk: bp->tx_clk, rate: rate_rounded))
549 netdev_err(dev: bp->dev, format: "adjusting tx_clk failed.\n");
550}
551
552static void macb_usx_pcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode,
553 phy_interface_t interface, int speed,
554 int duplex)
555{
556 struct macb *bp = container_of(pcs, struct macb, phylink_usx_pcs);
557 u32 config;
558
559 config = gem_readl(bp, USX_CONTROL);
560 config = GEM_BFINS(SERDES_RATE, MACB_SERDES_RATE_10G, config);
561 config = GEM_BFINS(USX_CTRL_SPEED, HS_SPEED_10000M, config);
562 config &= ~(GEM_BIT(TX_SCR_BYPASS) | GEM_BIT(RX_SCR_BYPASS));
563 config |= GEM_BIT(TX_EN);
564 gem_writel(bp, USX_CONTROL, config);
565}
566
567static void macb_usx_pcs_get_state(struct phylink_pcs *pcs,
568 unsigned int neg_mode,
569 struct phylink_link_state *state)
570{
571 struct macb *bp = container_of(pcs, struct macb, phylink_usx_pcs);
572 u32 val;
573
574 state->speed = SPEED_10000;
575 state->duplex = 1;
576 state->an_complete = 1;
577
578 val = gem_readl(bp, USX_STATUS);
579 state->link = !!(val & GEM_BIT(USX_BLOCK_LOCK));
580 val = gem_readl(bp, NCFGR);
581 if (val & GEM_BIT(PAE))
582 state->pause = MLO_PAUSE_RX;
583}
584
585static int macb_usx_pcs_config(struct phylink_pcs *pcs,
586 unsigned int neg_mode,
587 phy_interface_t interface,
588 const unsigned long *advertising,
589 bool permit_pause_to_mac)
590{
591 struct macb *bp = container_of(pcs, struct macb, phylink_usx_pcs);
592
593 gem_writel(bp, USX_CONTROL, gem_readl(bp, USX_CONTROL) |
594 GEM_BIT(SIGNAL_OK));
595
596 return 0;
597}
598
599static void macb_pcs_get_state(struct phylink_pcs *pcs, unsigned int neg_mode,
600 struct phylink_link_state *state)
601{
602 state->link = 0;
603}
604
605static void macb_pcs_an_restart(struct phylink_pcs *pcs)
606{
607 /* Not supported */
608}
609
610static int macb_pcs_config(struct phylink_pcs *pcs,
611 unsigned int neg_mode,
612 phy_interface_t interface,
613 const unsigned long *advertising,
614 bool permit_pause_to_mac)
615{
616 return 0;
617}
618
619static const struct phylink_pcs_ops macb_phylink_usx_pcs_ops = {
620 .pcs_get_state = macb_usx_pcs_get_state,
621 .pcs_config = macb_usx_pcs_config,
622 .pcs_link_up = macb_usx_pcs_link_up,
623};
624
625static const struct phylink_pcs_ops macb_phylink_pcs_ops = {
626 .pcs_get_state = macb_pcs_get_state,
627 .pcs_an_restart = macb_pcs_an_restart,
628 .pcs_config = macb_pcs_config,
629};
630
631static void macb_mac_config(struct phylink_config *config, unsigned int mode,
632 const struct phylink_link_state *state)
633{
634 struct net_device *ndev = to_net_dev(config->dev);
635 struct macb *bp = netdev_priv(dev: ndev);
636 unsigned long flags;
637 u32 old_ctrl, ctrl;
638 u32 old_ncr, ncr;
639
640 spin_lock_irqsave(&bp->lock, flags);
641
642 old_ctrl = ctrl = macb_or_gem_readl(bp, NCFGR);
643 old_ncr = ncr = macb_or_gem_readl(bp, NCR);
644
645 if (bp->caps & MACB_CAPS_MACB_IS_EMAC) {
646 if (state->interface == PHY_INTERFACE_MODE_RMII)
647 ctrl |= MACB_BIT(RM9200_RMII);
648 } else if (macb_is_gem(bp)) {
649 ctrl &= ~(GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL));
650 ncr &= ~GEM_BIT(ENABLE_HS_MAC);
651
652 if (state->interface == PHY_INTERFACE_MODE_SGMII) {
653 ctrl |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
654 } else if (state->interface == PHY_INTERFACE_MODE_10GBASER) {
655 ctrl |= GEM_BIT(PCSSEL);
656 ncr |= GEM_BIT(ENABLE_HS_MAC);
657 } else if (bp->caps & MACB_CAPS_MIIONRGMII &&
658 bp->phy_interface == PHY_INTERFACE_MODE_MII) {
659 ncr |= MACB_BIT(MIIONRGMII);
660 }
661 }
662
663 /* Apply the new configuration, if any */
664 if (old_ctrl ^ ctrl)
665 macb_or_gem_writel(bp, NCFGR, ctrl);
666
667 if (old_ncr ^ ncr)
668 macb_or_gem_writel(bp, NCR, ncr);
669
670 /* Disable AN for SGMII fixed link configuration, enable otherwise.
671 * Must be written after PCSSEL is set in NCFGR,
672 * otherwise writes will not take effect.
673 */
674 if (macb_is_gem(bp) && state->interface == PHY_INTERFACE_MODE_SGMII) {
675 u32 pcsctrl, old_pcsctrl;
676
677 old_pcsctrl = gem_readl(bp, PCSCNTRL);
678 if (mode == MLO_AN_FIXED)
679 pcsctrl = old_pcsctrl & ~GEM_BIT(PCSAUTONEG);
680 else
681 pcsctrl = old_pcsctrl | GEM_BIT(PCSAUTONEG);
682 if (old_pcsctrl != pcsctrl)
683 gem_writel(bp, PCSCNTRL, pcsctrl);
684 }
685
686 spin_unlock_irqrestore(lock: &bp->lock, flags);
687}
688
689static void macb_mac_link_down(struct phylink_config *config, unsigned int mode,
690 phy_interface_t interface)
691{
692 struct net_device *ndev = to_net_dev(config->dev);
693 struct macb *bp = netdev_priv(dev: ndev);
694 struct macb_queue *queue;
695 unsigned int q;
696 u32 ctrl;
697
698 if (!(bp->caps & MACB_CAPS_MACB_IS_EMAC))
699 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
700 queue_writel(queue, IDR,
701 bp->rx_intr_mask | MACB_TX_INT_FLAGS | MACB_BIT(HRESP));
702
703 /* Disable Rx and Tx */
704 ctrl = macb_readl(bp, NCR) & ~(MACB_BIT(RE) | MACB_BIT(TE));
705 macb_writel(bp, NCR, ctrl);
706
707 netif_tx_stop_all_queues(dev: ndev);
708}
709
710static void macb_mac_link_up(struct phylink_config *config,
711 struct phy_device *phy,
712 unsigned int mode, phy_interface_t interface,
713 int speed, int duplex,
714 bool tx_pause, bool rx_pause)
715{
716 struct net_device *ndev = to_net_dev(config->dev);
717 struct macb *bp = netdev_priv(dev: ndev);
718 struct macb_queue *queue;
719 unsigned long flags;
720 unsigned int q;
721 u32 ctrl;
722
723 spin_lock_irqsave(&bp->lock, flags);
724
725 ctrl = macb_or_gem_readl(bp, NCFGR);
726
727 ctrl &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
728
729 if (speed == SPEED_100)
730 ctrl |= MACB_BIT(SPD);
731
732 if (duplex)
733 ctrl |= MACB_BIT(FD);
734
735 if (!(bp->caps & MACB_CAPS_MACB_IS_EMAC)) {
736 ctrl &= ~MACB_BIT(PAE);
737 if (macb_is_gem(bp)) {
738 ctrl &= ~GEM_BIT(GBE);
739
740 if (speed == SPEED_1000)
741 ctrl |= GEM_BIT(GBE);
742 }
743
744 if (rx_pause)
745 ctrl |= MACB_BIT(PAE);
746
747 /* Initialize rings & buffers as clearing MACB_BIT(TE) in link down
748 * cleared the pipeline and control registers.
749 */
750 bp->macbgem_ops.mog_init_rings(bp);
751 macb_init_buffers(bp);
752
753 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
754 queue_writel(queue, IER,
755 bp->rx_intr_mask | MACB_TX_INT_FLAGS | MACB_BIT(HRESP));
756 }
757
758 macb_or_gem_writel(bp, NCFGR, ctrl);
759
760 if (bp->phy_interface == PHY_INTERFACE_MODE_10GBASER)
761 gem_writel(bp, HS_MAC_CONFIG, GEM_BFINS(HS_MAC_SPEED, HS_SPEED_10000M,
762 gem_readl(bp, HS_MAC_CONFIG)));
763
764 spin_unlock_irqrestore(lock: &bp->lock, flags);
765
766 if (!(bp->caps & MACB_CAPS_MACB_IS_EMAC))
767 macb_set_tx_clk(bp, speed);
768
769 /* Enable Rx and Tx; Enable PTP unicast */
770 ctrl = macb_readl(bp, NCR);
771 if (gem_has_ptp(bp))
772 ctrl |= MACB_BIT(PTPUNI);
773
774 macb_writel(bp, NCR, ctrl | MACB_BIT(RE) | MACB_BIT(TE));
775
776 netif_tx_wake_all_queues(dev: ndev);
777}
778
779static struct phylink_pcs *macb_mac_select_pcs(struct phylink_config *config,
780 phy_interface_t interface)
781{
782 struct net_device *ndev = to_net_dev(config->dev);
783 struct macb *bp = netdev_priv(dev: ndev);
784
785 if (interface == PHY_INTERFACE_MODE_10GBASER)
786 return &bp->phylink_usx_pcs;
787 else if (interface == PHY_INTERFACE_MODE_SGMII)
788 return &bp->phylink_sgmii_pcs;
789 else
790 return NULL;
791}
792
793static const struct phylink_mac_ops macb_phylink_ops = {
794 .mac_select_pcs = macb_mac_select_pcs,
795 .mac_config = macb_mac_config,
796 .mac_link_down = macb_mac_link_down,
797 .mac_link_up = macb_mac_link_up,
798};
799
800static bool macb_phy_handle_exists(struct device_node *dn)
801{
802 dn = of_parse_phandle(np: dn, phandle_name: "phy-handle", index: 0);
803 of_node_put(node: dn);
804 return dn != NULL;
805}
806
807static int macb_phylink_connect(struct macb *bp)
808{
809 struct device_node *dn = bp->pdev->dev.of_node;
810 struct net_device *dev = bp->dev;
811 struct phy_device *phydev;
812 int ret;
813
814 if (dn)
815 ret = phylink_of_phy_connect(bp->phylink, dn, flags: 0);
816
817 if (!dn || (ret && !macb_phy_handle_exists(dn))) {
818 phydev = phy_find_first(bus: bp->mii_bus);
819 if (!phydev) {
820 netdev_err(dev, format: "no PHY found\n");
821 return -ENXIO;
822 }
823
824 /* attach the mac to the phy */
825 ret = phylink_connect_phy(bp->phylink, phydev);
826 }
827
828 if (ret) {
829 netdev_err(dev, format: "Could not attach PHY (%d)\n", ret);
830 return ret;
831 }
832
833 phylink_start(bp->phylink);
834
835 return 0;
836}
837
838static void macb_get_pcs_fixed_state(struct phylink_config *config,
839 struct phylink_link_state *state)
840{
841 struct net_device *ndev = to_net_dev(config->dev);
842 struct macb *bp = netdev_priv(dev: ndev);
843
844 state->link = (macb_readl(bp, NSR) & MACB_BIT(NSR_LINK)) != 0;
845}
846
847/* based on au1000_eth. c*/
848static int macb_mii_probe(struct net_device *dev)
849{
850 struct macb *bp = netdev_priv(dev);
851
852 bp->phylink_sgmii_pcs.ops = &macb_phylink_pcs_ops;
853 bp->phylink_usx_pcs.ops = &macb_phylink_usx_pcs_ops;
854
855 bp->phylink_config.dev = &dev->dev;
856 bp->phylink_config.type = PHYLINK_NETDEV;
857 bp->phylink_config.mac_managed_pm = true;
858
859 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII) {
860 bp->phylink_config.poll_fixed_state = true;
861 bp->phylink_config.get_fixed_state = macb_get_pcs_fixed_state;
862 }
863
864 bp->phylink_config.mac_capabilities = MAC_ASYM_PAUSE |
865 MAC_10 | MAC_100;
866
867 __set_bit(PHY_INTERFACE_MODE_MII,
868 bp->phylink_config.supported_interfaces);
869 __set_bit(PHY_INTERFACE_MODE_RMII,
870 bp->phylink_config.supported_interfaces);
871
872 /* Determine what modes are supported */
873 if (macb_is_gem(bp) && (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)) {
874 bp->phylink_config.mac_capabilities |= MAC_1000FD;
875 if (!(bp->caps & MACB_CAPS_NO_GIGABIT_HALF))
876 bp->phylink_config.mac_capabilities |= MAC_1000HD;
877
878 __set_bit(PHY_INTERFACE_MODE_GMII,
879 bp->phylink_config.supported_interfaces);
880 phy_interface_set_rgmii(intf: bp->phylink_config.supported_interfaces);
881
882 if (bp->caps & MACB_CAPS_PCS)
883 __set_bit(PHY_INTERFACE_MODE_SGMII,
884 bp->phylink_config.supported_interfaces);
885
886 if (bp->caps & MACB_CAPS_HIGH_SPEED) {
887 __set_bit(PHY_INTERFACE_MODE_10GBASER,
888 bp->phylink_config.supported_interfaces);
889 bp->phylink_config.mac_capabilities |= MAC_10000FD;
890 }
891 }
892
893 bp->phylink = phylink_create(&bp->phylink_config, bp->pdev->dev.fwnode,
894 bp->phy_interface, &macb_phylink_ops);
895 if (IS_ERR(ptr: bp->phylink)) {
896 netdev_err(dev, format: "Could not create a phylink instance (%ld)\n",
897 PTR_ERR(ptr: bp->phylink));
898 return PTR_ERR(ptr: bp->phylink);
899 }
900
901 return 0;
902}
903
904static int macb_mdiobus_register(struct macb *bp, struct device_node *mdio_np)
905{
906 struct device_node *child, *np = bp->pdev->dev.of_node;
907
908 /* If we have a child named mdio, probe it instead of looking for PHYs
909 * directly under the MAC node
910 */
911 if (mdio_np)
912 return of_mdiobus_register(mdio: bp->mii_bus, np: mdio_np);
913
914 /* Only create the PHY from the device tree if at least one PHY is
915 * described. Otherwise scan the entire MDIO bus. We do this to support
916 * old device tree that did not follow the best practices and did not
917 * describe their network PHYs.
918 */
919 for_each_available_child_of_node(np, child)
920 if (of_mdiobus_child_is_phy(child)) {
921 /* The loop increments the child refcount,
922 * decrement it before returning.
923 */
924 of_node_put(node: child);
925
926 return of_mdiobus_register(mdio: bp->mii_bus, np);
927 }
928
929 return mdiobus_register(bp->mii_bus);
930}
931
932static int macb_mii_init(struct macb *bp)
933{
934 struct device_node *mdio_np, *np = bp->pdev->dev.of_node;
935 int err = -ENXIO;
936
937 /* With fixed-link, we don't need to register the MDIO bus,
938 * except if we have a child named "mdio" in the device tree.
939 * In that case, some devices may be attached to the MACB's MDIO bus.
940 */
941 mdio_np = of_get_child_by_name(node: np, name: "mdio");
942 if (!mdio_np && of_phy_is_fixed_link(np))
943 return macb_mii_probe(dev: bp->dev);
944
945 /* Enable management port */
946 macb_writel(bp, NCR, MACB_BIT(MPE));
947
948 bp->mii_bus = mdiobus_alloc();
949 if (!bp->mii_bus) {
950 err = -ENOMEM;
951 goto err_out;
952 }
953
954 bp->mii_bus->name = "MACB_mii_bus";
955 bp->mii_bus->read = &macb_mdio_read_c22;
956 bp->mii_bus->write = &macb_mdio_write_c22;
957 bp->mii_bus->read_c45 = &macb_mdio_read_c45;
958 bp->mii_bus->write_c45 = &macb_mdio_write_c45;
959 snprintf(buf: bp->mii_bus->id, MII_BUS_ID_SIZE, fmt: "%s-%x",
960 bp->pdev->name, bp->pdev->id);
961 bp->mii_bus->priv = bp;
962 bp->mii_bus->parent = &bp->pdev->dev;
963
964 dev_set_drvdata(dev: &bp->dev->dev, data: bp->mii_bus);
965
966 err = macb_mdiobus_register(bp, mdio_np);
967 if (err)
968 goto err_out_free_mdiobus;
969
970 err = macb_mii_probe(dev: bp->dev);
971 if (err)
972 goto err_out_unregister_bus;
973
974 return 0;
975
976err_out_unregister_bus:
977 mdiobus_unregister(bus: bp->mii_bus);
978err_out_free_mdiobus:
979 mdiobus_free(bus: bp->mii_bus);
980err_out:
981 of_node_put(node: mdio_np);
982
983 return err;
984}
985
986static void macb_update_stats(struct macb *bp)
987{
988 u64 *p = &bp->hw_stats.macb.rx_pause_frames;
989 u64 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
990 int offset = MACB_PFR;
991
992 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
993
994 for (; p < end; p++, offset += 4)
995 *p += bp->macb_reg_readl(bp, offset);
996}
997
998static int macb_halt_tx(struct macb *bp)
999{
1000 u32 status;
1001
1002 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT));
1003
1004 /* Poll TSR until TGO is cleared or timeout. */
1005 return read_poll_timeout_atomic(macb_readl, status,
1006 !(status & MACB_BIT(TGO)),
1007 250, MACB_HALT_TIMEOUT, false,
1008 bp, TSR);
1009}
1010
1011static void macb_tx_unmap(struct macb *bp, struct macb_tx_skb *tx_skb, int budget)
1012{
1013 if (tx_skb->mapping) {
1014 if (tx_skb->mapped_as_page)
1015 dma_unmap_page(&bp->pdev->dev, tx_skb->mapping,
1016 tx_skb->size, DMA_TO_DEVICE);
1017 else
1018 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping,
1019 tx_skb->size, DMA_TO_DEVICE);
1020 tx_skb->mapping = 0;
1021 }
1022
1023 if (tx_skb->skb) {
1024 napi_consume_skb(skb: tx_skb->skb, budget);
1025 tx_skb->skb = NULL;
1026 }
1027}
1028
1029static void macb_set_addr(struct macb *bp, struct macb_dma_desc *desc, dma_addr_t addr)
1030{
1031#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1032 struct macb_dma_desc_64 *desc_64;
1033
1034 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
1035 desc_64 = macb_64b_desc(bp, desc);
1036 desc_64->addrh = upper_32_bits(addr);
1037 /* The low bits of RX address contain the RX_USED bit, clearing
1038 * of which allows packet RX. Make sure the high bits are also
1039 * visible to HW at that point.
1040 */
1041 dma_wmb();
1042 }
1043#endif
1044 desc->addr = lower_32_bits(addr);
1045}
1046
1047static dma_addr_t macb_get_addr(struct macb *bp, struct macb_dma_desc *desc)
1048{
1049 dma_addr_t addr = 0;
1050#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1051 struct macb_dma_desc_64 *desc_64;
1052
1053 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
1054 desc_64 = macb_64b_desc(bp, desc);
1055 addr = ((u64)(desc_64->addrh) << 32);
1056 }
1057#endif
1058 addr |= MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr));
1059#ifdef CONFIG_MACB_USE_HWSTAMP
1060 if (bp->hw_dma_cap & HW_DMA_CAP_PTP)
1061 addr &= ~GEM_BIT(DMA_RXVALID);
1062#endif
1063 return addr;
1064}
1065
1066static void macb_tx_error_task(struct work_struct *work)
1067{
1068 struct macb_queue *queue = container_of(work, struct macb_queue,
1069 tx_error_task);
1070 bool halt_timeout = false;
1071 struct macb *bp = queue->bp;
1072 u32 queue_index;
1073 u32 packets = 0;
1074 u32 bytes = 0;
1075 struct macb_tx_skb *tx_skb;
1076 struct macb_dma_desc *desc;
1077 struct sk_buff *skb;
1078 unsigned int tail;
1079 unsigned long flags;
1080
1081 queue_index = queue - bp->queues;
1082 netdev_vdbg(bp->dev, "macb_tx_error_task: q = %u, t = %u, h = %u\n",
1083 queue_index, queue->tx_tail, queue->tx_head);
1084
1085 /* Prevent the queue NAPI TX poll from running, as it calls
1086 * macb_tx_complete(), which in turn may call netif_wake_subqueue().
1087 * As explained below, we have to halt the transmission before updating
1088 * TBQP registers so we call netif_tx_stop_all_queues() to notify the
1089 * network engine about the macb/gem being halted.
1090 */
1091 napi_disable(n: &queue->napi_tx);
1092 spin_lock_irqsave(&bp->lock, flags);
1093
1094 /* Make sure nobody is trying to queue up new packets */
1095 netif_tx_stop_all_queues(dev: bp->dev);
1096
1097 /* Stop transmission now
1098 * (in case we have just queued new packets)
1099 * macb/gem must be halted to write TBQP register
1100 */
1101 if (macb_halt_tx(bp)) {
1102 netdev_err(dev: bp->dev, format: "BUG: halt tx timed out\n");
1103 macb_writel(bp, NCR, macb_readl(bp, NCR) & (~MACB_BIT(TE)));
1104 halt_timeout = true;
1105 }
1106
1107 /* Treat frames in TX queue including the ones that caused the error.
1108 * Free transmit buffers in upper layer.
1109 */
1110 for (tail = queue->tx_tail; tail != queue->tx_head; tail++) {
1111 u32 ctrl;
1112
1113 desc = macb_tx_desc(queue, index: tail);
1114 ctrl = desc->ctrl;
1115 tx_skb = macb_tx_skb(queue, index: tail);
1116 skb = tx_skb->skb;
1117
1118 if (ctrl & MACB_BIT(TX_USED)) {
1119 /* skb is set for the last buffer of the frame */
1120 while (!skb) {
1121 macb_tx_unmap(bp, tx_skb, budget: 0);
1122 tail++;
1123 tx_skb = macb_tx_skb(queue, index: tail);
1124 skb = tx_skb->skb;
1125 }
1126
1127 /* ctrl still refers to the first buffer descriptor
1128 * since it's the only one written back by the hardware
1129 */
1130 if (!(ctrl & MACB_BIT(TX_BUF_EXHAUSTED))) {
1131 netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n",
1132 macb_tx_ring_wrap(bp, tail),
1133 skb->data);
1134 bp->dev->stats.tx_packets++;
1135 queue->stats.tx_packets++;
1136 packets++;
1137 bp->dev->stats.tx_bytes += skb->len;
1138 queue->stats.tx_bytes += skb->len;
1139 bytes += skb->len;
1140 }
1141 } else {
1142 /* "Buffers exhausted mid-frame" errors may only happen
1143 * if the driver is buggy, so complain loudly about
1144 * those. Statistics are updated by hardware.
1145 */
1146 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
1147 netdev_err(dev: bp->dev,
1148 format: "BUG: TX buffers exhausted mid-frame\n");
1149
1150 desc->ctrl = ctrl | MACB_BIT(TX_USED);
1151 }
1152
1153 macb_tx_unmap(bp, tx_skb, budget: 0);
1154 }
1155
1156 netdev_tx_completed_queue(dev_queue: netdev_get_tx_queue(dev: bp->dev, index: queue_index),
1157 pkts: packets, bytes);
1158
1159 /* Set end of TX queue */
1160 desc = macb_tx_desc(queue, index: 0);
1161 macb_set_addr(bp, desc, addr: 0);
1162 desc->ctrl = MACB_BIT(TX_USED);
1163
1164 /* Make descriptor updates visible to hardware */
1165 wmb();
1166
1167 /* Reinitialize the TX desc queue */
1168 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
1169#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1170 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
1171 queue_writel(queue, TBQPH, upper_32_bits(queue->tx_ring_dma));
1172#endif
1173 /* Make TX ring reflect state of hardware */
1174 queue->tx_head = 0;
1175 queue->tx_tail = 0;
1176
1177 /* Housework before enabling TX IRQ */
1178 macb_writel(bp, TSR, macb_readl(bp, TSR));
1179 queue_writel(queue, IER, MACB_TX_INT_FLAGS);
1180
1181 if (halt_timeout)
1182 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TE));
1183
1184 /* Now we are ready to start transmission again */
1185 netif_tx_start_all_queues(dev: bp->dev);
1186 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1187
1188 spin_unlock_irqrestore(lock: &bp->lock, flags);
1189 napi_enable(n: &queue->napi_tx);
1190}
1191
1192static bool ptp_one_step_sync(struct sk_buff *skb)
1193{
1194 struct ptp_header *hdr;
1195 unsigned int ptp_class;
1196 u8 msgtype;
1197
1198 /* No need to parse packet if PTP TS is not involved */
1199 if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)))
1200 goto not_oss;
1201
1202 /* Identify and return whether PTP one step sync is being processed */
1203 ptp_class = ptp_classify_raw(skb);
1204 if (ptp_class == PTP_CLASS_NONE)
1205 goto not_oss;
1206
1207 hdr = ptp_parse_header(skb, type: ptp_class);
1208 if (!hdr)
1209 goto not_oss;
1210
1211 if (hdr->flag_field[0] & PTP_FLAG_TWOSTEP)
1212 goto not_oss;
1213
1214 msgtype = ptp_get_msgtype(hdr, type: ptp_class);
1215 if (msgtype == PTP_MSGTYPE_SYNC)
1216 return true;
1217
1218not_oss:
1219 return false;
1220}
1221
1222static int macb_tx_complete(struct macb_queue *queue, int budget)
1223{
1224 struct macb *bp = queue->bp;
1225 u16 queue_index = queue - bp->queues;
1226 unsigned int tail;
1227 unsigned int head;
1228 int packets = 0;
1229 u32 bytes = 0;
1230
1231 spin_lock(lock: &queue->tx_ptr_lock);
1232 head = queue->tx_head;
1233 for (tail = queue->tx_tail; tail != head && packets < budget; tail++) {
1234 struct macb_tx_skb *tx_skb;
1235 struct sk_buff *skb;
1236 struct macb_dma_desc *desc;
1237 u32 ctrl;
1238
1239 desc = macb_tx_desc(queue, index: tail);
1240
1241 /* Make hw descriptor updates visible to CPU */
1242 rmb();
1243
1244 ctrl = desc->ctrl;
1245
1246 /* TX_USED bit is only set by hardware on the very first buffer
1247 * descriptor of the transmitted frame.
1248 */
1249 if (!(ctrl & MACB_BIT(TX_USED)))
1250 break;
1251
1252 /* Process all buffers of the current transmitted frame */
1253 for (;; tail++) {
1254 tx_skb = macb_tx_skb(queue, index: tail);
1255 skb = tx_skb->skb;
1256
1257 /* First, update TX stats if needed */
1258 if (skb) {
1259 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
1260 !ptp_one_step_sync(skb))
1261 gem_ptp_do_txstamp(bp, skb, desc);
1262
1263 netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
1264 macb_tx_ring_wrap(bp, tail),
1265 skb->data);
1266 bp->dev->stats.tx_packets++;
1267 queue->stats.tx_packets++;
1268 bp->dev->stats.tx_bytes += skb->len;
1269 queue->stats.tx_bytes += skb->len;
1270 packets++;
1271 bytes += skb->len;
1272 }
1273
1274 /* Now we can safely release resources */
1275 macb_tx_unmap(bp, tx_skb, budget);
1276
1277 /* skb is set only for the last buffer of the frame.
1278 * WARNING: at this point skb has been freed by
1279 * macb_tx_unmap().
1280 */
1281 if (skb)
1282 break;
1283 }
1284 }
1285
1286 netdev_tx_completed_queue(dev_queue: netdev_get_tx_queue(dev: bp->dev, index: queue_index),
1287 pkts: packets, bytes);
1288
1289 queue->tx_tail = tail;
1290 if (__netif_subqueue_stopped(dev: bp->dev, queue_index) &&
1291 CIRC_CNT(queue->tx_head, queue->tx_tail,
1292 bp->tx_ring_size) <= MACB_TX_WAKEUP_THRESH(bp))
1293 netif_wake_subqueue(dev: bp->dev, queue_index);
1294 spin_unlock(lock: &queue->tx_ptr_lock);
1295
1296 return packets;
1297}
1298
1299static void gem_rx_refill(struct macb_queue *queue)
1300{
1301 unsigned int entry;
1302 struct sk_buff *skb;
1303 dma_addr_t paddr;
1304 struct macb *bp = queue->bp;
1305 struct macb_dma_desc *desc;
1306
1307 while (CIRC_SPACE(queue->rx_prepared_head, queue->rx_tail,
1308 bp->rx_ring_size) > 0) {
1309 entry = macb_rx_ring_wrap(bp, index: queue->rx_prepared_head);
1310
1311 /* Make hw descriptor updates visible to CPU */
1312 rmb();
1313
1314 desc = macb_rx_desc(queue, index: entry);
1315
1316 if (!queue->rx_skbuff[entry]) {
1317 /* allocate sk_buff for this free entry in ring */
1318 skb = netdev_alloc_skb(dev: bp->dev, length: bp->rx_buffer_size);
1319 if (unlikely(!skb)) {
1320 netdev_err(dev: bp->dev,
1321 format: "Unable to allocate sk_buff\n");
1322 break;
1323 }
1324
1325 /* now fill corresponding descriptor entry */
1326 paddr = dma_map_single(&bp->pdev->dev, skb->data,
1327 bp->rx_buffer_size,
1328 DMA_FROM_DEVICE);
1329 if (dma_mapping_error(dev: &bp->pdev->dev, dma_addr: paddr)) {
1330 dev_kfree_skb(skb);
1331 break;
1332 }
1333
1334 queue->rx_skbuff[entry] = skb;
1335
1336 if (entry == bp->rx_ring_size - 1)
1337 paddr |= MACB_BIT(RX_WRAP);
1338 desc->ctrl = 0;
1339 /* Setting addr clears RX_USED and allows reception,
1340 * make sure ctrl is cleared first to avoid a race.
1341 */
1342 dma_wmb();
1343 macb_set_addr(bp, desc, addr: paddr);
1344
1345 /* properly align Ethernet header */
1346 skb_reserve(skb, NET_IP_ALIGN);
1347 } else {
1348 desc->ctrl = 0;
1349 dma_wmb();
1350 desc->addr &= ~MACB_BIT(RX_USED);
1351 }
1352 queue->rx_prepared_head++;
1353 }
1354
1355 /* Make descriptor updates visible to hardware */
1356 wmb();
1357
1358 netdev_vdbg(bp->dev, "rx ring: queue: %p, prepared head %d, tail %d\n",
1359 queue, queue->rx_prepared_head, queue->rx_tail);
1360}
1361
1362/* Mark DMA descriptors from begin up to and not including end as unused */
1363static void discard_partial_frame(struct macb_queue *queue, unsigned int begin,
1364 unsigned int end)
1365{
1366 unsigned int frag;
1367
1368 for (frag = begin; frag != end; frag++) {
1369 struct macb_dma_desc *desc = macb_rx_desc(queue, index: frag);
1370
1371 desc->addr &= ~MACB_BIT(RX_USED);
1372 }
1373
1374 /* Make descriptor updates visible to hardware */
1375 wmb();
1376
1377 /* When this happens, the hardware stats registers for
1378 * whatever caused this is updated, so we don't have to record
1379 * anything.
1380 */
1381}
1382
1383static int gem_rx(struct macb_queue *queue, struct napi_struct *napi,
1384 int budget)
1385{
1386 struct macb *bp = queue->bp;
1387 unsigned int len;
1388 unsigned int entry;
1389 struct sk_buff *skb;
1390 struct macb_dma_desc *desc;
1391 int count = 0;
1392
1393 while (count < budget) {
1394 u32 ctrl;
1395 dma_addr_t addr;
1396 bool rxused;
1397
1398 entry = macb_rx_ring_wrap(bp, index: queue->rx_tail);
1399 desc = macb_rx_desc(queue, index: entry);
1400
1401 /* Make hw descriptor updates visible to CPU */
1402 rmb();
1403
1404 rxused = (desc->addr & MACB_BIT(RX_USED)) ? true : false;
1405 addr = macb_get_addr(bp, desc);
1406
1407 if (!rxused)
1408 break;
1409
1410 /* Ensure ctrl is at least as up-to-date as rxused */
1411 dma_rmb();
1412
1413 ctrl = desc->ctrl;
1414
1415 queue->rx_tail++;
1416 count++;
1417
1418 if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) {
1419 netdev_err(dev: bp->dev,
1420 format: "not whole frame pointed by descriptor\n");
1421 bp->dev->stats.rx_dropped++;
1422 queue->stats.rx_dropped++;
1423 break;
1424 }
1425 skb = queue->rx_skbuff[entry];
1426 if (unlikely(!skb)) {
1427 netdev_err(dev: bp->dev,
1428 format: "inconsistent Rx descriptor chain\n");
1429 bp->dev->stats.rx_dropped++;
1430 queue->stats.rx_dropped++;
1431 break;
1432 }
1433 /* now everything is ready for receiving packet */
1434 queue->rx_skbuff[entry] = NULL;
1435 len = ctrl & bp->rx_frm_len_mask;
1436
1437 netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len);
1438
1439 skb_put(skb, len);
1440 dma_unmap_single(&bp->pdev->dev, addr,
1441 bp->rx_buffer_size, DMA_FROM_DEVICE);
1442
1443 skb->protocol = eth_type_trans(skb, dev: bp->dev);
1444 skb_checksum_none_assert(skb);
1445 if (bp->dev->features & NETIF_F_RXCSUM &&
1446 !(bp->dev->flags & IFF_PROMISC) &&
1447 GEM_BFEXT(RX_CSUM, ctrl) & GEM_RX_CSUM_CHECKED_MASK)
1448 skb->ip_summed = CHECKSUM_UNNECESSARY;
1449
1450 bp->dev->stats.rx_packets++;
1451 queue->stats.rx_packets++;
1452 bp->dev->stats.rx_bytes += skb->len;
1453 queue->stats.rx_bytes += skb->len;
1454
1455 gem_ptp_do_rxstamp(bp, skb, desc);
1456
1457#if defined(DEBUG) && defined(VERBOSE_DEBUG)
1458 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
1459 skb->len, skb->csum);
1460 print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1,
1461 skb_mac_header(skb), 16, true);
1462 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1,
1463 skb->data, 32, true);
1464#endif
1465
1466 napi_gro_receive(napi, skb);
1467 }
1468
1469 gem_rx_refill(queue);
1470
1471 return count;
1472}
1473
1474static int macb_rx_frame(struct macb_queue *queue, struct napi_struct *napi,
1475 unsigned int first_frag, unsigned int last_frag)
1476{
1477 unsigned int len;
1478 unsigned int frag;
1479 unsigned int offset;
1480 struct sk_buff *skb;
1481 struct macb_dma_desc *desc;
1482 struct macb *bp = queue->bp;
1483
1484 desc = macb_rx_desc(queue, index: last_frag);
1485 len = desc->ctrl & bp->rx_frm_len_mask;
1486
1487 netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
1488 macb_rx_ring_wrap(bp, first_frag),
1489 macb_rx_ring_wrap(bp, last_frag), len);
1490
1491 /* The ethernet header starts NET_IP_ALIGN bytes into the
1492 * first buffer. Since the header is 14 bytes, this makes the
1493 * payload word-aligned.
1494 *
1495 * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy
1496 * the two padding bytes into the skb so that we avoid hitting
1497 * the slowpath in memcpy(), and pull them off afterwards.
1498 */
1499 skb = netdev_alloc_skb(dev: bp->dev, length: len + NET_IP_ALIGN);
1500 if (!skb) {
1501 bp->dev->stats.rx_dropped++;
1502 for (frag = first_frag; ; frag++) {
1503 desc = macb_rx_desc(queue, index: frag);
1504 desc->addr &= ~MACB_BIT(RX_USED);
1505 if (frag == last_frag)
1506 break;
1507 }
1508
1509 /* Make descriptor updates visible to hardware */
1510 wmb();
1511
1512 return 1;
1513 }
1514
1515 offset = 0;
1516 len += NET_IP_ALIGN;
1517 skb_checksum_none_assert(skb);
1518 skb_put(skb, len);
1519
1520 for (frag = first_frag; ; frag++) {
1521 unsigned int frag_len = bp->rx_buffer_size;
1522
1523 if (offset + frag_len > len) {
1524 if (unlikely(frag != last_frag)) {
1525 dev_kfree_skb_any(skb);
1526 return -1;
1527 }
1528 frag_len = len - offset;
1529 }
1530 skb_copy_to_linear_data_offset(skb, offset,
1531 from: macb_rx_buffer(queue, index: frag),
1532 len: frag_len);
1533 offset += bp->rx_buffer_size;
1534 desc = macb_rx_desc(queue, index: frag);
1535 desc->addr &= ~MACB_BIT(RX_USED);
1536
1537 if (frag == last_frag)
1538 break;
1539 }
1540
1541 /* Make descriptor updates visible to hardware */
1542 wmb();
1543
1544 __skb_pull(skb, NET_IP_ALIGN);
1545 skb->protocol = eth_type_trans(skb, dev: bp->dev);
1546
1547 bp->dev->stats.rx_packets++;
1548 bp->dev->stats.rx_bytes += skb->len;
1549 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
1550 skb->len, skb->csum);
1551 napi_gro_receive(napi, skb);
1552
1553 return 0;
1554}
1555
1556static inline void macb_init_rx_ring(struct macb_queue *queue)
1557{
1558 struct macb *bp = queue->bp;
1559 dma_addr_t addr;
1560 struct macb_dma_desc *desc = NULL;
1561 int i;
1562
1563 addr = queue->rx_buffers_dma;
1564 for (i = 0; i < bp->rx_ring_size; i++) {
1565 desc = macb_rx_desc(queue, index: i);
1566 macb_set_addr(bp, desc, addr);
1567 desc->ctrl = 0;
1568 addr += bp->rx_buffer_size;
1569 }
1570 desc->addr |= MACB_BIT(RX_WRAP);
1571 queue->rx_tail = 0;
1572}
1573
1574static int macb_rx(struct macb_queue *queue, struct napi_struct *napi,
1575 int budget)
1576{
1577 struct macb *bp = queue->bp;
1578 bool reset_rx_queue = false;
1579 int received = 0;
1580 unsigned int tail;
1581 int first_frag = -1;
1582
1583 for (tail = queue->rx_tail; budget > 0; tail++) {
1584 struct macb_dma_desc *desc = macb_rx_desc(queue, index: tail);
1585 u32 ctrl;
1586
1587 /* Make hw descriptor updates visible to CPU */
1588 rmb();
1589
1590 if (!(desc->addr & MACB_BIT(RX_USED)))
1591 break;
1592
1593 /* Ensure ctrl is at least as up-to-date as addr */
1594 dma_rmb();
1595
1596 ctrl = desc->ctrl;
1597
1598 if (ctrl & MACB_BIT(RX_SOF)) {
1599 if (first_frag != -1)
1600 discard_partial_frame(queue, begin: first_frag, end: tail);
1601 first_frag = tail;
1602 }
1603
1604 if (ctrl & MACB_BIT(RX_EOF)) {
1605 int dropped;
1606
1607 if (unlikely(first_frag == -1)) {
1608 reset_rx_queue = true;
1609 continue;
1610 }
1611
1612 dropped = macb_rx_frame(queue, napi, first_frag, last_frag: tail);
1613 first_frag = -1;
1614 if (unlikely(dropped < 0)) {
1615 reset_rx_queue = true;
1616 continue;
1617 }
1618 if (!dropped) {
1619 received++;
1620 budget--;
1621 }
1622 }
1623 }
1624
1625 if (unlikely(reset_rx_queue)) {
1626 unsigned long flags;
1627 u32 ctrl;
1628
1629 netdev_err(dev: bp->dev, format: "RX queue corruption: reset it\n");
1630
1631 spin_lock_irqsave(&bp->lock, flags);
1632
1633 ctrl = macb_readl(bp, NCR);
1634 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1635
1636 macb_init_rx_ring(queue);
1637 queue_writel(queue, RBQP, queue->rx_ring_dma);
1638
1639 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1640
1641 spin_unlock_irqrestore(lock: &bp->lock, flags);
1642 return received;
1643 }
1644
1645 if (first_frag != -1)
1646 queue->rx_tail = first_frag;
1647 else
1648 queue->rx_tail = tail;
1649
1650 return received;
1651}
1652
1653static bool macb_rx_pending(struct macb_queue *queue)
1654{
1655 struct macb *bp = queue->bp;
1656 unsigned int entry;
1657 struct macb_dma_desc *desc;
1658
1659 entry = macb_rx_ring_wrap(bp, index: queue->rx_tail);
1660 desc = macb_rx_desc(queue, index: entry);
1661
1662 /* Make hw descriptor updates visible to CPU */
1663 rmb();
1664
1665 return (desc->addr & MACB_BIT(RX_USED)) != 0;
1666}
1667
1668static int macb_rx_poll(struct napi_struct *napi, int budget)
1669{
1670 struct macb_queue *queue = container_of(napi, struct macb_queue, napi_rx);
1671 struct macb *bp = queue->bp;
1672 int work_done;
1673
1674 work_done = bp->macbgem_ops.mog_rx(queue, napi, budget);
1675
1676 netdev_vdbg(bp->dev, "RX poll: queue = %u, work_done = %d, budget = %d\n",
1677 (unsigned int)(queue - bp->queues), work_done, budget);
1678
1679 if (work_done < budget && napi_complete_done(n: napi, work_done)) {
1680 queue_writel(queue, IER, bp->rx_intr_mask);
1681
1682 /* Packet completions only seem to propagate to raise
1683 * interrupts when interrupts are enabled at the time, so if
1684 * packets were received while interrupts were disabled,
1685 * they will not cause another interrupt to be generated when
1686 * interrupts are re-enabled.
1687 * Check for this case here to avoid losing a wakeup. This can
1688 * potentially race with the interrupt handler doing the same
1689 * actions if an interrupt is raised just after enabling them,
1690 * but this should be harmless.
1691 */
1692 if (macb_rx_pending(queue)) {
1693 queue_writel(queue, IDR, bp->rx_intr_mask);
1694 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1695 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1696 netdev_vdbg(bp->dev, "poll: packets pending, reschedule\n");
1697 napi_schedule(n: napi);
1698 }
1699 }
1700
1701 /* TODO: Handle errors */
1702
1703 return work_done;
1704}
1705
1706static void macb_tx_restart(struct macb_queue *queue)
1707{
1708 struct macb *bp = queue->bp;
1709 unsigned int head_idx, tbqp;
1710
1711 spin_lock(lock: &queue->tx_ptr_lock);
1712
1713 if (queue->tx_head == queue->tx_tail)
1714 goto out_tx_ptr_unlock;
1715
1716 tbqp = queue_readl(queue, TBQP) / macb_dma_desc_get_size(bp);
1717 tbqp = macb_adj_dma_desc_idx(bp, desc_idx: macb_tx_ring_wrap(bp, index: tbqp));
1718 head_idx = macb_adj_dma_desc_idx(bp, desc_idx: macb_tx_ring_wrap(bp, index: queue->tx_head));
1719
1720 if (tbqp == head_idx)
1721 goto out_tx_ptr_unlock;
1722
1723 spin_lock_irq(lock: &bp->lock);
1724 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1725 spin_unlock_irq(lock: &bp->lock);
1726
1727out_tx_ptr_unlock:
1728 spin_unlock(lock: &queue->tx_ptr_lock);
1729}
1730
1731static bool macb_tx_complete_pending(struct macb_queue *queue)
1732{
1733 bool retval = false;
1734
1735 spin_lock(lock: &queue->tx_ptr_lock);
1736 if (queue->tx_head != queue->tx_tail) {
1737 /* Make hw descriptor updates visible to CPU */
1738 rmb();
1739
1740 if (macb_tx_desc(queue, index: queue->tx_tail)->ctrl & MACB_BIT(TX_USED))
1741 retval = true;
1742 }
1743 spin_unlock(lock: &queue->tx_ptr_lock);
1744 return retval;
1745}
1746
1747static int macb_tx_poll(struct napi_struct *napi, int budget)
1748{
1749 struct macb_queue *queue = container_of(napi, struct macb_queue, napi_tx);
1750 struct macb *bp = queue->bp;
1751 int work_done;
1752
1753 work_done = macb_tx_complete(queue, budget);
1754
1755 rmb(); // ensure txubr_pending is up to date
1756 if (queue->txubr_pending) {
1757 queue->txubr_pending = false;
1758 netdev_vdbg(bp->dev, "poll: tx restart\n");
1759 macb_tx_restart(queue);
1760 }
1761
1762 netdev_vdbg(bp->dev, "TX poll: queue = %u, work_done = %d, budget = %d\n",
1763 (unsigned int)(queue - bp->queues), work_done, budget);
1764
1765 if (work_done < budget && napi_complete_done(n: napi, work_done)) {
1766 queue_writel(queue, IER, MACB_BIT(TCOMP));
1767
1768 /* Packet completions only seem to propagate to raise
1769 * interrupts when interrupts are enabled at the time, so if
1770 * packets were sent while interrupts were disabled,
1771 * they will not cause another interrupt to be generated when
1772 * interrupts are re-enabled.
1773 * Check for this case here to avoid losing a wakeup. This can
1774 * potentially race with the interrupt handler doing the same
1775 * actions if an interrupt is raised just after enabling them,
1776 * but this should be harmless.
1777 */
1778 if (macb_tx_complete_pending(queue)) {
1779 queue_writel(queue, IDR, MACB_BIT(TCOMP));
1780 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1781 queue_writel(queue, ISR, MACB_BIT(TCOMP));
1782 netdev_vdbg(bp->dev, "TX poll: packets pending, reschedule\n");
1783 napi_schedule(n: napi);
1784 }
1785 }
1786
1787 return work_done;
1788}
1789
1790static void macb_hresp_error_task(struct work_struct *work)
1791{
1792 struct macb *bp = from_work(bp, work, hresp_err_bh_work);
1793 struct net_device *dev = bp->dev;
1794 struct macb_queue *queue;
1795 unsigned int q;
1796 u32 ctrl;
1797
1798 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1799 queue_writel(queue, IDR, bp->rx_intr_mask |
1800 MACB_TX_INT_FLAGS |
1801 MACB_BIT(HRESP));
1802 }
1803 ctrl = macb_readl(bp, NCR);
1804 ctrl &= ~(MACB_BIT(RE) | MACB_BIT(TE));
1805 macb_writel(bp, NCR, ctrl);
1806
1807 netif_tx_stop_all_queues(dev);
1808 netif_carrier_off(dev);
1809
1810 bp->macbgem_ops.mog_init_rings(bp);
1811
1812 /* Initialize TX and RX buffers */
1813 macb_init_buffers(bp);
1814
1815 /* Enable interrupts */
1816 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
1817 queue_writel(queue, IER,
1818 bp->rx_intr_mask |
1819 MACB_TX_INT_FLAGS |
1820 MACB_BIT(HRESP));
1821
1822 ctrl |= MACB_BIT(RE) | MACB_BIT(TE);
1823 macb_writel(bp, NCR, ctrl);
1824
1825 netif_carrier_on(dev);
1826 netif_tx_start_all_queues(dev);
1827}
1828
1829static irqreturn_t macb_wol_interrupt(int irq, void *dev_id)
1830{
1831 struct macb_queue *queue = dev_id;
1832 struct macb *bp = queue->bp;
1833 u32 status;
1834
1835 status = queue_readl(queue, ISR);
1836
1837 if (unlikely(!status))
1838 return IRQ_NONE;
1839
1840 spin_lock(lock: &bp->lock);
1841
1842 if (status & MACB_BIT(WOL)) {
1843 queue_writel(queue, IDR, MACB_BIT(WOL));
1844 macb_writel(bp, WOL, 0);
1845 netdev_vdbg(bp->dev, "MACB WoL: queue = %u, isr = 0x%08lx\n",
1846 (unsigned int)(queue - bp->queues),
1847 (unsigned long)status);
1848 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1849 queue_writel(queue, ISR, MACB_BIT(WOL));
1850 pm_wakeup_event(dev: &bp->pdev->dev, msec: 0);
1851 }
1852
1853 spin_unlock(lock: &bp->lock);
1854
1855 return IRQ_HANDLED;
1856}
1857
1858static irqreturn_t gem_wol_interrupt(int irq, void *dev_id)
1859{
1860 struct macb_queue *queue = dev_id;
1861 struct macb *bp = queue->bp;
1862 u32 status;
1863
1864 status = queue_readl(queue, ISR);
1865
1866 if (unlikely(!status))
1867 return IRQ_NONE;
1868
1869 spin_lock(lock: &bp->lock);
1870
1871 if (status & GEM_BIT(WOL)) {
1872 queue_writel(queue, IDR, GEM_BIT(WOL));
1873 gem_writel(bp, WOL, 0);
1874 netdev_vdbg(bp->dev, "GEM WoL: queue = %u, isr = 0x%08lx\n",
1875 (unsigned int)(queue - bp->queues),
1876 (unsigned long)status);
1877 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1878 queue_writel(queue, ISR, GEM_BIT(WOL));
1879 pm_wakeup_event(dev: &bp->pdev->dev, msec: 0);
1880 }
1881
1882 spin_unlock(lock: &bp->lock);
1883
1884 return IRQ_HANDLED;
1885}
1886
1887static irqreturn_t macb_interrupt(int irq, void *dev_id)
1888{
1889 struct macb_queue *queue = dev_id;
1890 struct macb *bp = queue->bp;
1891 struct net_device *dev = bp->dev;
1892 u32 status, ctrl;
1893
1894 status = queue_readl(queue, ISR);
1895
1896 if (unlikely(!status))
1897 return IRQ_NONE;
1898
1899 spin_lock(lock: &bp->lock);
1900
1901 while (status) {
1902 /* close possible race with dev_close */
1903 if (unlikely(!netif_running(dev))) {
1904 queue_writel(queue, IDR, -1);
1905 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1906 queue_writel(queue, ISR, -1);
1907 break;
1908 }
1909
1910 netdev_vdbg(bp->dev, "queue = %u, isr = 0x%08lx\n",
1911 (unsigned int)(queue - bp->queues),
1912 (unsigned long)status);
1913
1914 if (status & bp->rx_intr_mask) {
1915 /* There's no point taking any more interrupts
1916 * until we have processed the buffers. The
1917 * scheduling call may fail if the poll routine
1918 * is already scheduled, so disable interrupts
1919 * now.
1920 */
1921 queue_writel(queue, IDR, bp->rx_intr_mask);
1922 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1923 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1924
1925 if (napi_schedule_prep(n: &queue->napi_rx)) {
1926 netdev_vdbg(bp->dev, "scheduling RX softirq\n");
1927 __napi_schedule(n: &queue->napi_rx);
1928 }
1929 }
1930
1931 if (status & (MACB_BIT(TCOMP) |
1932 MACB_BIT(TXUBR))) {
1933 queue_writel(queue, IDR, MACB_BIT(TCOMP));
1934 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1935 queue_writel(queue, ISR, MACB_BIT(TCOMP) |
1936 MACB_BIT(TXUBR));
1937
1938 if (status & MACB_BIT(TXUBR)) {
1939 queue->txubr_pending = true;
1940 wmb(); // ensure softirq can see update
1941 }
1942
1943 if (napi_schedule_prep(n: &queue->napi_tx)) {
1944 netdev_vdbg(bp->dev, "scheduling TX softirq\n");
1945 __napi_schedule(n: &queue->napi_tx);
1946 }
1947 }
1948
1949 if (unlikely(status & (MACB_TX_ERR_FLAGS))) {
1950 queue_writel(queue, IDR, MACB_TX_INT_FLAGS);
1951 schedule_work(work: &queue->tx_error_task);
1952
1953 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1954 queue_writel(queue, ISR, MACB_TX_ERR_FLAGS);
1955
1956 break;
1957 }
1958
1959 /* Link change detection isn't possible with RMII, so we'll
1960 * add that if/when we get our hands on a full-blown MII PHY.
1961 */
1962
1963 /* There is a hardware issue under heavy load where DMA can
1964 * stop, this causes endless "used buffer descriptor read"
1965 * interrupts but it can be cleared by re-enabling RX. See
1966 * the at91rm9200 manual, section 41.3.1 or the Zynq manual
1967 * section 16.7.4 for details. RXUBR is only enabled for
1968 * these two versions.
1969 */
1970 if (status & MACB_BIT(RXUBR)) {
1971 ctrl = macb_readl(bp, NCR);
1972 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1973 wmb();
1974 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1975
1976 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1977 queue_writel(queue, ISR, MACB_BIT(RXUBR));
1978 }
1979
1980 if (status & MACB_BIT(ISR_ROVR)) {
1981 /* We missed at least one packet */
1982 spin_lock(lock: &bp->stats_lock);
1983 if (macb_is_gem(bp))
1984 bp->hw_stats.gem.rx_overruns++;
1985 else
1986 bp->hw_stats.macb.rx_overruns++;
1987 spin_unlock(lock: &bp->stats_lock);
1988
1989 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1990 queue_writel(queue, ISR, MACB_BIT(ISR_ROVR));
1991 }
1992
1993 if (status & MACB_BIT(HRESP)) {
1994 queue_work(wq: system_bh_wq, work: &bp->hresp_err_bh_work);
1995 netdev_err(dev, format: "DMA bus error: HRESP not OK\n");
1996
1997 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1998 queue_writel(queue, ISR, MACB_BIT(HRESP));
1999 }
2000 status = queue_readl(queue, ISR);
2001 }
2002
2003 spin_unlock(lock: &bp->lock);
2004
2005 return IRQ_HANDLED;
2006}
2007
2008#ifdef CONFIG_NET_POLL_CONTROLLER
2009/* Polling receive - used by netconsole and other diagnostic tools
2010 * to allow network i/o with interrupts disabled.
2011 */
2012static void macb_poll_controller(struct net_device *dev)
2013{
2014 struct macb *bp = netdev_priv(dev);
2015 struct macb_queue *queue;
2016 unsigned long flags;
2017 unsigned int q;
2018
2019 local_irq_save(flags);
2020 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2021 macb_interrupt(irq: dev->irq, dev_id: queue);
2022 local_irq_restore(flags);
2023}
2024#endif
2025
2026static unsigned int macb_tx_map(struct macb *bp,
2027 struct macb_queue *queue,
2028 struct sk_buff *skb,
2029 unsigned int hdrlen)
2030{
2031 dma_addr_t mapping;
2032 unsigned int len, entry, i, tx_head = queue->tx_head;
2033 struct macb_tx_skb *tx_skb = NULL;
2034 struct macb_dma_desc *desc;
2035 unsigned int offset, size, count = 0;
2036 unsigned int f, nr_frags = skb_shinfo(skb)->nr_frags;
2037 unsigned int eof = 1, mss_mfs = 0;
2038 u32 ctrl, lso_ctrl = 0, seq_ctrl = 0;
2039
2040 /* LSO */
2041 if (skb_shinfo(skb)->gso_size != 0) {
2042 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
2043 /* UDP - UFO */
2044 lso_ctrl = MACB_LSO_UFO_ENABLE;
2045 else
2046 /* TCP - TSO */
2047 lso_ctrl = MACB_LSO_TSO_ENABLE;
2048 }
2049
2050 /* First, map non-paged data */
2051 len = skb_headlen(skb);
2052
2053 /* first buffer length */
2054 size = hdrlen;
2055
2056 offset = 0;
2057 while (len) {
2058 entry = macb_tx_ring_wrap(bp, index: tx_head);
2059 tx_skb = &queue->tx_skb[entry];
2060
2061 mapping = dma_map_single(&bp->pdev->dev,
2062 skb->data + offset,
2063 size, DMA_TO_DEVICE);
2064 if (dma_mapping_error(dev: &bp->pdev->dev, dma_addr: mapping))
2065 goto dma_error;
2066
2067 /* Save info to properly release resources */
2068 tx_skb->skb = NULL;
2069 tx_skb->mapping = mapping;
2070 tx_skb->size = size;
2071 tx_skb->mapped_as_page = false;
2072
2073 len -= size;
2074 offset += size;
2075 count++;
2076 tx_head++;
2077
2078 size = min(len, bp->max_tx_length);
2079 }
2080
2081 /* Then, map paged data from fragments */
2082 for (f = 0; f < nr_frags; f++) {
2083 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
2084
2085 len = skb_frag_size(frag);
2086 offset = 0;
2087 while (len) {
2088 size = min(len, bp->max_tx_length);
2089 entry = macb_tx_ring_wrap(bp, index: tx_head);
2090 tx_skb = &queue->tx_skb[entry];
2091
2092 mapping = skb_frag_dma_map(&bp->pdev->dev, frag,
2093 offset, size, DMA_TO_DEVICE);
2094 if (dma_mapping_error(dev: &bp->pdev->dev, dma_addr: mapping))
2095 goto dma_error;
2096
2097 /* Save info to properly release resources */
2098 tx_skb->skb = NULL;
2099 tx_skb->mapping = mapping;
2100 tx_skb->size = size;
2101 tx_skb->mapped_as_page = true;
2102
2103 len -= size;
2104 offset += size;
2105 count++;
2106 tx_head++;
2107 }
2108 }
2109
2110 /* Should never happen */
2111 if (unlikely(!tx_skb)) {
2112 netdev_err(dev: bp->dev, format: "BUG! empty skb!\n");
2113 return 0;
2114 }
2115
2116 /* This is the last buffer of the frame: save socket buffer */
2117 tx_skb->skb = skb;
2118
2119 /* Update TX ring: update buffer descriptors in reverse order
2120 * to avoid race condition
2121 */
2122
2123 /* Set 'TX_USED' bit in buffer descriptor at tx_head position
2124 * to set the end of TX queue
2125 */
2126 i = tx_head;
2127 entry = macb_tx_ring_wrap(bp, index: i);
2128 ctrl = MACB_BIT(TX_USED);
2129 desc = macb_tx_desc(queue, index: entry);
2130 desc->ctrl = ctrl;
2131
2132 if (lso_ctrl) {
2133 if (lso_ctrl == MACB_LSO_UFO_ENABLE)
2134 /* include header and FCS in value given to h/w */
2135 mss_mfs = skb_shinfo(skb)->gso_size +
2136 skb_transport_offset(skb) +
2137 ETH_FCS_LEN;
2138 else /* TSO */ {
2139 mss_mfs = skb_shinfo(skb)->gso_size;
2140 /* TCP Sequence Number Source Select
2141 * can be set only for TSO
2142 */
2143 seq_ctrl = 0;
2144 }
2145 }
2146
2147 do {
2148 i--;
2149 entry = macb_tx_ring_wrap(bp, index: i);
2150 tx_skb = &queue->tx_skb[entry];
2151 desc = macb_tx_desc(queue, index: entry);
2152
2153 ctrl = (u32)tx_skb->size;
2154 if (eof) {
2155 ctrl |= MACB_BIT(TX_LAST);
2156 eof = 0;
2157 }
2158 if (unlikely(entry == (bp->tx_ring_size - 1)))
2159 ctrl |= MACB_BIT(TX_WRAP);
2160
2161 /* First descriptor is header descriptor */
2162 if (i == queue->tx_head) {
2163 ctrl |= MACB_BF(TX_LSO, lso_ctrl);
2164 ctrl |= MACB_BF(TX_TCP_SEQ_SRC, seq_ctrl);
2165 if ((bp->dev->features & NETIF_F_HW_CSUM) &&
2166 skb->ip_summed != CHECKSUM_PARTIAL && !lso_ctrl &&
2167 !ptp_one_step_sync(skb))
2168 ctrl |= MACB_BIT(TX_NOCRC);
2169 } else
2170 /* Only set MSS/MFS on payload descriptors
2171 * (second or later descriptor)
2172 */
2173 ctrl |= MACB_BF(MSS_MFS, mss_mfs);
2174
2175 /* Set TX buffer descriptor */
2176 macb_set_addr(bp, desc, addr: tx_skb->mapping);
2177 /* desc->addr must be visible to hardware before clearing
2178 * 'TX_USED' bit in desc->ctrl.
2179 */
2180 wmb();
2181 desc->ctrl = ctrl;
2182 } while (i != queue->tx_head);
2183
2184 queue->tx_head = tx_head;
2185
2186 return count;
2187
2188dma_error:
2189 netdev_err(dev: bp->dev, format: "TX DMA map failed\n");
2190
2191 for (i = queue->tx_head; i != tx_head; i++) {
2192 tx_skb = macb_tx_skb(queue, index: i);
2193
2194 macb_tx_unmap(bp, tx_skb, budget: 0);
2195 }
2196
2197 return 0;
2198}
2199
2200static netdev_features_t macb_features_check(struct sk_buff *skb,
2201 struct net_device *dev,
2202 netdev_features_t features)
2203{
2204 unsigned int nr_frags, f;
2205 unsigned int hdrlen;
2206
2207 /* Validate LSO compatibility */
2208
2209 /* there is only one buffer or protocol is not UDP */
2210 if (!skb_is_nonlinear(skb) || (ip_hdr(skb)->protocol != IPPROTO_UDP))
2211 return features;
2212
2213 /* length of header */
2214 hdrlen = skb_transport_offset(skb);
2215
2216 /* For UFO only:
2217 * When software supplies two or more payload buffers all payload buffers
2218 * apart from the last must be a multiple of 8 bytes in size.
2219 */
2220 if (!IS_ALIGNED(skb_headlen(skb) - hdrlen, MACB_TX_LEN_ALIGN))
2221 return features & ~MACB_NETIF_LSO;
2222
2223 nr_frags = skb_shinfo(skb)->nr_frags;
2224 /* No need to check last fragment */
2225 nr_frags--;
2226 for (f = 0; f < nr_frags; f++) {
2227 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
2228
2229 if (!IS_ALIGNED(skb_frag_size(frag), MACB_TX_LEN_ALIGN))
2230 return features & ~MACB_NETIF_LSO;
2231 }
2232 return features;
2233}
2234
2235static inline int macb_clear_csum(struct sk_buff *skb)
2236{
2237 /* no change for packets without checksum offloading */
2238 if (skb->ip_summed != CHECKSUM_PARTIAL)
2239 return 0;
2240
2241 /* make sure we can modify the header */
2242 if (unlikely(skb_cow_head(skb, 0)))
2243 return -1;
2244
2245 /* initialize checksum field
2246 * This is required - at least for Zynq, which otherwise calculates
2247 * wrong UDP header checksums for UDP packets with UDP data len <=2
2248 */
2249 *(__sum16 *)(skb_checksum_start(skb) + skb->csum_offset) = 0;
2250 return 0;
2251}
2252
2253static int macb_pad_and_fcs(struct sk_buff **skb, struct net_device *ndev)
2254{
2255 bool cloned = skb_cloned(skb: *skb) || skb_header_cloned(skb: *skb) ||
2256 skb_is_nonlinear(skb: *skb);
2257 int padlen = ETH_ZLEN - (*skb)->len;
2258 int tailroom = skb_tailroom(skb: *skb);
2259 struct sk_buff *nskb;
2260 u32 fcs;
2261
2262 if (!(ndev->features & NETIF_F_HW_CSUM) ||
2263 !((*skb)->ip_summed != CHECKSUM_PARTIAL) ||
2264 skb_shinfo(*skb)->gso_size || ptp_one_step_sync(skb: *skb))
2265 return 0;
2266
2267 if (padlen <= 0) {
2268 /* FCS could be appeded to tailroom. */
2269 if (tailroom >= ETH_FCS_LEN)
2270 goto add_fcs;
2271 /* No room for FCS, need to reallocate skb. */
2272 else
2273 padlen = ETH_FCS_LEN;
2274 } else {
2275 /* Add room for FCS. */
2276 padlen += ETH_FCS_LEN;
2277 }
2278
2279 if (cloned || tailroom < padlen) {
2280 nskb = skb_copy_expand(skb: *skb, newheadroom: 0, newtailroom: padlen, GFP_ATOMIC);
2281 if (!nskb)
2282 return -ENOMEM;
2283
2284 dev_consume_skb_any(skb: *skb);
2285 *skb = nskb;
2286 }
2287
2288 if (padlen > ETH_FCS_LEN)
2289 skb_put_zero(skb: *skb, len: padlen - ETH_FCS_LEN);
2290
2291add_fcs:
2292 /* set FCS to packet */
2293 fcs = crc32_le(crc: ~0, p: (*skb)->data, len: (*skb)->len);
2294 fcs = ~fcs;
2295
2296 skb_put_u8(skb: *skb, val: fcs & 0xff);
2297 skb_put_u8(skb: *skb, val: (fcs >> 8) & 0xff);
2298 skb_put_u8(skb: *skb, val: (fcs >> 16) & 0xff);
2299 skb_put_u8(skb: *skb, val: (fcs >> 24) & 0xff);
2300
2301 return 0;
2302}
2303
2304static netdev_tx_t macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
2305{
2306 u16 queue_index = skb_get_queue_mapping(skb);
2307 struct macb *bp = netdev_priv(dev);
2308 struct macb_queue *queue = &bp->queues[queue_index];
2309 unsigned int desc_cnt, nr_frags, frag_size, f;
2310 unsigned int hdrlen;
2311 bool is_lso;
2312 netdev_tx_t ret = NETDEV_TX_OK;
2313
2314 if (macb_clear_csum(skb)) {
2315 dev_kfree_skb_any(skb);
2316 return ret;
2317 }
2318
2319 if (macb_pad_and_fcs(skb: &skb, ndev: dev)) {
2320 dev_kfree_skb_any(skb);
2321 return ret;
2322 }
2323
2324#ifdef CONFIG_MACB_USE_HWSTAMP
2325 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2326 (bp->hw_dma_cap & HW_DMA_CAP_PTP))
2327 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2328#endif
2329
2330 is_lso = (skb_shinfo(skb)->gso_size != 0);
2331
2332 if (is_lso) {
2333 /* length of headers */
2334 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
2335 /* only queue eth + ip headers separately for UDP */
2336 hdrlen = skb_transport_offset(skb);
2337 else
2338 hdrlen = skb_tcp_all_headers(skb);
2339 if (skb_headlen(skb) < hdrlen) {
2340 netdev_err(dev: bp->dev, format: "Error - LSO headers fragmented!!!\n");
2341 /* if this is required, would need to copy to single buffer */
2342 return NETDEV_TX_BUSY;
2343 }
2344 } else
2345 hdrlen = min(skb_headlen(skb), bp->max_tx_length);
2346
2347#if defined(DEBUG) && defined(VERBOSE_DEBUG)
2348 netdev_vdbg(bp->dev,
2349 "start_xmit: queue %hu len %u head %p data %p tail %p end %p\n",
2350 queue_index, skb->len, skb->head, skb->data,
2351 skb_tail_pointer(skb), skb_end_pointer(skb));
2352 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
2353 skb->data, 16, true);
2354#endif
2355
2356 /* Count how many TX buffer descriptors are needed to send this
2357 * socket buffer: skb fragments of jumbo frames may need to be
2358 * split into many buffer descriptors.
2359 */
2360 if (is_lso && (skb_headlen(skb) > hdrlen))
2361 /* extra header descriptor if also payload in first buffer */
2362 desc_cnt = DIV_ROUND_UP((skb_headlen(skb) - hdrlen), bp->max_tx_length) + 1;
2363 else
2364 desc_cnt = DIV_ROUND_UP(skb_headlen(skb), bp->max_tx_length);
2365 nr_frags = skb_shinfo(skb)->nr_frags;
2366 for (f = 0; f < nr_frags; f++) {
2367 frag_size = skb_frag_size(frag: &skb_shinfo(skb)->frags[f]);
2368 desc_cnt += DIV_ROUND_UP(frag_size, bp->max_tx_length);
2369 }
2370
2371 spin_lock_bh(lock: &queue->tx_ptr_lock);
2372
2373 /* This is a hard error, log it. */
2374 if (CIRC_SPACE(queue->tx_head, queue->tx_tail,
2375 bp->tx_ring_size) < desc_cnt) {
2376 netif_stop_subqueue(dev, queue_index);
2377 netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
2378 queue->tx_head, queue->tx_tail);
2379 ret = NETDEV_TX_BUSY;
2380 goto unlock;
2381 }
2382
2383 /* Map socket buffer for DMA transfer */
2384 if (!macb_tx_map(bp, queue, skb, hdrlen)) {
2385 dev_kfree_skb_any(skb);
2386 goto unlock;
2387 }
2388
2389 /* Make newly initialized descriptor visible to hardware */
2390 wmb();
2391 skb_tx_timestamp(skb);
2392 netdev_tx_sent_queue(dev_queue: netdev_get_tx_queue(dev: bp->dev, index: queue_index),
2393 bytes: skb->len);
2394
2395 spin_lock_irq(lock: &bp->lock);
2396 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
2397 spin_unlock_irq(lock: &bp->lock);
2398
2399 if (CIRC_SPACE(queue->tx_head, queue->tx_tail, bp->tx_ring_size) < 1)
2400 netif_stop_subqueue(dev, queue_index);
2401
2402unlock:
2403 spin_unlock_bh(lock: &queue->tx_ptr_lock);
2404
2405 return ret;
2406}
2407
2408static void macb_init_rx_buffer_size(struct macb *bp, size_t size)
2409{
2410 if (!macb_is_gem(bp)) {
2411 bp->rx_buffer_size = MACB_RX_BUFFER_SIZE;
2412 } else {
2413 bp->rx_buffer_size = size;
2414
2415 if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) {
2416 netdev_dbg(bp->dev,
2417 "RX buffer must be multiple of %d bytes, expanding\n",
2418 RX_BUFFER_MULTIPLE);
2419 bp->rx_buffer_size =
2420 roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE);
2421 }
2422 }
2423
2424 netdev_dbg(bp->dev, "mtu [%u] rx_buffer_size [%zu]\n",
2425 bp->dev->mtu, bp->rx_buffer_size);
2426}
2427
2428static void gem_free_rx_buffers(struct macb *bp)
2429{
2430 struct sk_buff *skb;
2431 struct macb_dma_desc *desc;
2432 struct macb_queue *queue;
2433 dma_addr_t addr;
2434 unsigned int q;
2435 int i;
2436
2437 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2438 if (!queue->rx_skbuff)
2439 continue;
2440
2441 for (i = 0; i < bp->rx_ring_size; i++) {
2442 skb = queue->rx_skbuff[i];
2443
2444 if (!skb)
2445 continue;
2446
2447 desc = macb_rx_desc(queue, index: i);
2448 addr = macb_get_addr(bp, desc);
2449
2450 dma_unmap_single(&bp->pdev->dev, addr, bp->rx_buffer_size,
2451 DMA_FROM_DEVICE);
2452 dev_kfree_skb_any(skb);
2453 skb = NULL;
2454 }
2455
2456 kfree(objp: queue->rx_skbuff);
2457 queue->rx_skbuff = NULL;
2458 }
2459}
2460
2461static void macb_free_rx_buffers(struct macb *bp)
2462{
2463 struct macb_queue *queue = &bp->queues[0];
2464
2465 if (queue->rx_buffers) {
2466 dma_free_coherent(dev: &bp->pdev->dev,
2467 size: bp->rx_ring_size * bp->rx_buffer_size,
2468 cpu_addr: queue->rx_buffers, dma_handle: queue->rx_buffers_dma);
2469 queue->rx_buffers = NULL;
2470 }
2471}
2472
2473static void macb_free_consistent(struct macb *bp)
2474{
2475 struct macb_queue *queue;
2476 unsigned int q;
2477 int size;
2478
2479 if (bp->rx_ring_tieoff) {
2480 dma_free_coherent(dev: &bp->pdev->dev, size: macb_dma_desc_get_size(bp),
2481 cpu_addr: bp->rx_ring_tieoff, dma_handle: bp->rx_ring_tieoff_dma);
2482 bp->rx_ring_tieoff = NULL;
2483 }
2484
2485 bp->macbgem_ops.mog_free_rx_buffers(bp);
2486
2487 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2488 kfree(objp: queue->tx_skb);
2489 queue->tx_skb = NULL;
2490 if (queue->tx_ring) {
2491 size = TX_RING_BYTES(bp) + bp->tx_bd_rd_prefetch;
2492 dma_free_coherent(dev: &bp->pdev->dev, size,
2493 cpu_addr: queue->tx_ring, dma_handle: queue->tx_ring_dma);
2494 queue->tx_ring = NULL;
2495 }
2496 if (queue->rx_ring) {
2497 size = RX_RING_BYTES(bp) + bp->rx_bd_rd_prefetch;
2498 dma_free_coherent(dev: &bp->pdev->dev, size,
2499 cpu_addr: queue->rx_ring, dma_handle: queue->rx_ring_dma);
2500 queue->rx_ring = NULL;
2501 }
2502 }
2503}
2504
2505static int gem_alloc_rx_buffers(struct macb *bp)
2506{
2507 struct macb_queue *queue;
2508 unsigned int q;
2509 int size;
2510
2511 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2512 size = bp->rx_ring_size * sizeof(struct sk_buff *);
2513 queue->rx_skbuff = kzalloc(size, GFP_KERNEL);
2514 if (!queue->rx_skbuff)
2515 return -ENOMEM;
2516 else
2517 netdev_dbg(bp->dev,
2518 "Allocated %d RX struct sk_buff entries at %p\n",
2519 bp->rx_ring_size, queue->rx_skbuff);
2520 }
2521 return 0;
2522}
2523
2524static int macb_alloc_rx_buffers(struct macb *bp)
2525{
2526 struct macb_queue *queue = &bp->queues[0];
2527 int size;
2528
2529 size = bp->rx_ring_size * bp->rx_buffer_size;
2530 queue->rx_buffers = dma_alloc_coherent(dev: &bp->pdev->dev, size,
2531 dma_handle: &queue->rx_buffers_dma, GFP_KERNEL);
2532 if (!queue->rx_buffers)
2533 return -ENOMEM;
2534
2535 netdev_dbg(bp->dev,
2536 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
2537 size, (unsigned long)queue->rx_buffers_dma, queue->rx_buffers);
2538 return 0;
2539}
2540
2541static int macb_alloc_consistent(struct macb *bp)
2542{
2543 struct macb_queue *queue;
2544 unsigned int q;
2545 int size;
2546
2547 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2548 size = TX_RING_BYTES(bp) + bp->tx_bd_rd_prefetch;
2549 queue->tx_ring = dma_alloc_coherent(dev: &bp->pdev->dev, size,
2550 dma_handle: &queue->tx_ring_dma,
2551 GFP_KERNEL);
2552 if (!queue->tx_ring)
2553 goto out_err;
2554 netdev_dbg(bp->dev,
2555 "Allocated TX ring for queue %u of %d bytes at %08lx (mapped %p)\n",
2556 q, size, (unsigned long)queue->tx_ring_dma,
2557 queue->tx_ring);
2558
2559 size = bp->tx_ring_size * sizeof(struct macb_tx_skb);
2560 queue->tx_skb = kmalloc(size, GFP_KERNEL);
2561 if (!queue->tx_skb)
2562 goto out_err;
2563
2564 size = RX_RING_BYTES(bp) + bp->rx_bd_rd_prefetch;
2565 queue->rx_ring = dma_alloc_coherent(dev: &bp->pdev->dev, size,
2566 dma_handle: &queue->rx_ring_dma, GFP_KERNEL);
2567 if (!queue->rx_ring)
2568 goto out_err;
2569 netdev_dbg(bp->dev,
2570 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
2571 size, (unsigned long)queue->rx_ring_dma, queue->rx_ring);
2572 }
2573 if (bp->macbgem_ops.mog_alloc_rx_buffers(bp))
2574 goto out_err;
2575
2576 /* Required for tie off descriptor for PM cases */
2577 if (!(bp->caps & MACB_CAPS_QUEUE_DISABLE)) {
2578 bp->rx_ring_tieoff = dma_alloc_coherent(dev: &bp->pdev->dev,
2579 size: macb_dma_desc_get_size(bp),
2580 dma_handle: &bp->rx_ring_tieoff_dma,
2581 GFP_KERNEL);
2582 if (!bp->rx_ring_tieoff)
2583 goto out_err;
2584 }
2585
2586 return 0;
2587
2588out_err:
2589 macb_free_consistent(bp);
2590 return -ENOMEM;
2591}
2592
2593static void macb_init_tieoff(struct macb *bp)
2594{
2595 struct macb_dma_desc *desc = bp->rx_ring_tieoff;
2596
2597 if (bp->caps & MACB_CAPS_QUEUE_DISABLE)
2598 return;
2599 /* Setup a wrapping descriptor with no free slots
2600 * (WRAP and USED) to tie off/disable unused RX queues.
2601 */
2602 macb_set_addr(bp, desc, MACB_BIT(RX_WRAP) | MACB_BIT(RX_USED));
2603 desc->ctrl = 0;
2604}
2605
2606static void gem_init_rings(struct macb *bp)
2607{
2608 struct macb_queue *queue;
2609 struct macb_dma_desc *desc = NULL;
2610 unsigned int q;
2611 int i;
2612
2613 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2614 for (i = 0; i < bp->tx_ring_size; i++) {
2615 desc = macb_tx_desc(queue, index: i);
2616 macb_set_addr(bp, desc, addr: 0);
2617 desc->ctrl = MACB_BIT(TX_USED);
2618 }
2619 desc->ctrl |= MACB_BIT(TX_WRAP);
2620 queue->tx_head = 0;
2621 queue->tx_tail = 0;
2622
2623 queue->rx_tail = 0;
2624 queue->rx_prepared_head = 0;
2625
2626 gem_rx_refill(queue);
2627 }
2628
2629 macb_init_tieoff(bp);
2630}
2631
2632static void macb_init_rings(struct macb *bp)
2633{
2634 int i;
2635 struct macb_dma_desc *desc = NULL;
2636
2637 macb_init_rx_ring(queue: &bp->queues[0]);
2638
2639 for (i = 0; i < bp->tx_ring_size; i++) {
2640 desc = macb_tx_desc(queue: &bp->queues[0], index: i);
2641 macb_set_addr(bp, desc, addr: 0);
2642 desc->ctrl = MACB_BIT(TX_USED);
2643 }
2644 bp->queues[0].tx_head = 0;
2645 bp->queues[0].tx_tail = 0;
2646 desc->ctrl |= MACB_BIT(TX_WRAP);
2647
2648 macb_init_tieoff(bp);
2649}
2650
2651static void macb_reset_hw(struct macb *bp)
2652{
2653 struct macb_queue *queue;
2654 unsigned int q;
2655 u32 ctrl = macb_readl(bp, NCR);
2656
2657 /* Disable RX and TX (XXX: Should we halt the transmission
2658 * more gracefully?)
2659 */
2660 ctrl &= ~(MACB_BIT(RE) | MACB_BIT(TE));
2661
2662 /* Clear the stats registers (XXX: Update stats first?) */
2663 ctrl |= MACB_BIT(CLRSTAT);
2664
2665 macb_writel(bp, NCR, ctrl);
2666
2667 /* Clear all status flags */
2668 macb_writel(bp, TSR, -1);
2669 macb_writel(bp, RSR, -1);
2670
2671 /* Disable RX partial store and forward and reset watermark value */
2672 gem_writel(bp, PBUFRXCUT, 0);
2673
2674 /* Disable all interrupts */
2675 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2676 queue_writel(queue, IDR, -1);
2677 queue_readl(queue, ISR);
2678 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
2679 queue_writel(queue, ISR, -1);
2680 }
2681}
2682
2683static u32 gem_mdc_clk_div(struct macb *bp)
2684{
2685 u32 config;
2686 unsigned long pclk_hz = clk_get_rate(clk: bp->pclk);
2687
2688 if (pclk_hz <= 20000000)
2689 config = GEM_BF(CLK, GEM_CLK_DIV8);
2690 else if (pclk_hz <= 40000000)
2691 config = GEM_BF(CLK, GEM_CLK_DIV16);
2692 else if (pclk_hz <= 80000000)
2693 config = GEM_BF(CLK, GEM_CLK_DIV32);
2694 else if (pclk_hz <= 120000000)
2695 config = GEM_BF(CLK, GEM_CLK_DIV48);
2696 else if (pclk_hz <= 160000000)
2697 config = GEM_BF(CLK, GEM_CLK_DIV64);
2698 else if (pclk_hz <= 240000000)
2699 config = GEM_BF(CLK, GEM_CLK_DIV96);
2700 else if (pclk_hz <= 320000000)
2701 config = GEM_BF(CLK, GEM_CLK_DIV128);
2702 else
2703 config = GEM_BF(CLK, GEM_CLK_DIV224);
2704
2705 return config;
2706}
2707
2708static u32 macb_mdc_clk_div(struct macb *bp)
2709{
2710 u32 config;
2711 unsigned long pclk_hz;
2712
2713 if (macb_is_gem(bp))
2714 return gem_mdc_clk_div(bp);
2715
2716 pclk_hz = clk_get_rate(clk: bp->pclk);
2717 if (pclk_hz <= 20000000)
2718 config = MACB_BF(CLK, MACB_CLK_DIV8);
2719 else if (pclk_hz <= 40000000)
2720 config = MACB_BF(CLK, MACB_CLK_DIV16);
2721 else if (pclk_hz <= 80000000)
2722 config = MACB_BF(CLK, MACB_CLK_DIV32);
2723 else
2724 config = MACB_BF(CLK, MACB_CLK_DIV64);
2725
2726 return config;
2727}
2728
2729/* Get the DMA bus width field of the network configuration register that we
2730 * should program. We find the width from decoding the design configuration
2731 * register to find the maximum supported data bus width.
2732 */
2733static u32 macb_dbw(struct macb *bp)
2734{
2735 if (!macb_is_gem(bp))
2736 return 0;
2737
2738 switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
2739 case 4:
2740 return GEM_BF(DBW, GEM_DBW128);
2741 case 2:
2742 return GEM_BF(DBW, GEM_DBW64);
2743 case 1:
2744 default:
2745 return GEM_BF(DBW, GEM_DBW32);
2746 }
2747}
2748
2749/* Configure the receive DMA engine
2750 * - use the correct receive buffer size
2751 * - set best burst length for DMA operations
2752 * (if not supported by FIFO, it will fallback to default)
2753 * - set both rx/tx packet buffers to full memory size
2754 * These are configurable parameters for GEM.
2755 */
2756static void macb_configure_dma(struct macb *bp)
2757{
2758 struct macb_queue *queue;
2759 u32 buffer_size;
2760 unsigned int q;
2761 u32 dmacfg;
2762
2763 buffer_size = bp->rx_buffer_size / RX_BUFFER_MULTIPLE;
2764 if (macb_is_gem(bp)) {
2765 dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
2766 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2767 if (q)
2768 queue_writel(queue, RBQS, buffer_size);
2769 else
2770 dmacfg |= GEM_BF(RXBS, buffer_size);
2771 }
2772 if (bp->dma_burst_length)
2773 dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg);
2774 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
2775 dmacfg &= ~GEM_BIT(ENDIA_PKT);
2776
2777 if (bp->native_io)
2778 dmacfg &= ~GEM_BIT(ENDIA_DESC);
2779 else
2780 dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */
2781
2782 if (bp->dev->features & NETIF_F_HW_CSUM)
2783 dmacfg |= GEM_BIT(TXCOEN);
2784 else
2785 dmacfg &= ~GEM_BIT(TXCOEN);
2786
2787 dmacfg &= ~GEM_BIT(ADDR64);
2788#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
2789 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
2790 dmacfg |= GEM_BIT(ADDR64);
2791#endif
2792#ifdef CONFIG_MACB_USE_HWSTAMP
2793 if (bp->hw_dma_cap & HW_DMA_CAP_PTP)
2794 dmacfg |= GEM_BIT(RXEXT) | GEM_BIT(TXEXT);
2795#endif
2796 netdev_dbg(bp->dev, "Cadence configure DMA with 0x%08x\n",
2797 dmacfg);
2798 gem_writel(bp, DMACFG, dmacfg);
2799 }
2800}
2801
2802static void macb_init_hw(struct macb *bp)
2803{
2804 u32 config;
2805
2806 macb_reset_hw(bp);
2807 macb_set_hwaddr(bp);
2808
2809 config = macb_mdc_clk_div(bp);
2810 config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */
2811 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
2812 if (bp->caps & MACB_CAPS_JUMBO)
2813 config |= MACB_BIT(JFRAME); /* Enable jumbo frames */
2814 else
2815 config |= MACB_BIT(BIG); /* Receive oversized frames */
2816 if (bp->dev->flags & IFF_PROMISC)
2817 config |= MACB_BIT(CAF); /* Copy All Frames */
2818 else if (macb_is_gem(bp) && bp->dev->features & NETIF_F_RXCSUM)
2819 config |= GEM_BIT(RXCOEN);
2820 if (!(bp->dev->flags & IFF_BROADCAST))
2821 config |= MACB_BIT(NBC); /* No BroadCast */
2822 config |= macb_dbw(bp);
2823 macb_writel(bp, NCFGR, config);
2824 if ((bp->caps & MACB_CAPS_JUMBO) && bp->jumbo_max_len)
2825 gem_writel(bp, JML, bp->jumbo_max_len);
2826 bp->rx_frm_len_mask = MACB_RX_FRMLEN_MASK;
2827 if (bp->caps & MACB_CAPS_JUMBO)
2828 bp->rx_frm_len_mask = MACB_RX_JFRMLEN_MASK;
2829
2830 macb_configure_dma(bp);
2831
2832 /* Enable RX partial store and forward and set watermark */
2833 if (bp->rx_watermark)
2834 gem_writel(bp, PBUFRXCUT, (bp->rx_watermark | GEM_BIT(ENCUTTHRU)));
2835}
2836
2837/* The hash address register is 64 bits long and takes up two
2838 * locations in the memory map. The least significant bits are stored
2839 * in EMAC_HSL and the most significant bits in EMAC_HSH.
2840 *
2841 * The unicast hash enable and the multicast hash enable bits in the
2842 * network configuration register enable the reception of hash matched
2843 * frames. The destination address is reduced to a 6 bit index into
2844 * the 64 bit hash register using the following hash function. The
2845 * hash function is an exclusive or of every sixth bit of the
2846 * destination address.
2847 *
2848 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
2849 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
2850 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
2851 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
2852 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
2853 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
2854 *
2855 * da[0] represents the least significant bit of the first byte
2856 * received, that is, the multicast/unicast indicator, and da[47]
2857 * represents the most significant bit of the last byte received. If
2858 * the hash index, hi[n], points to a bit that is set in the hash
2859 * register then the frame will be matched according to whether the
2860 * frame is multicast or unicast. A multicast match will be signalled
2861 * if the multicast hash enable bit is set, da[0] is 1 and the hash
2862 * index points to a bit set in the hash register. A unicast match
2863 * will be signalled if the unicast hash enable bit is set, da[0] is 0
2864 * and the hash index points to a bit set in the hash register. To
2865 * receive all multicast frames, the hash register should be set with
2866 * all ones and the multicast hash enable bit should be set in the
2867 * network configuration register.
2868 */
2869
2870static inline int hash_bit_value(int bitnr, __u8 *addr)
2871{
2872 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
2873 return 1;
2874 return 0;
2875}
2876
2877/* Return the hash index value for the specified address. */
2878static int hash_get_index(__u8 *addr)
2879{
2880 int i, j, bitval;
2881 int hash_index = 0;
2882
2883 for (j = 0; j < 6; j++) {
2884 for (i = 0, bitval = 0; i < 8; i++)
2885 bitval ^= hash_bit_value(bitnr: i * 6 + j, addr);
2886
2887 hash_index |= (bitval << j);
2888 }
2889
2890 return hash_index;
2891}
2892
2893/* Add multicast addresses to the internal multicast-hash table. */
2894static void macb_sethashtable(struct net_device *dev)
2895{
2896 struct netdev_hw_addr *ha;
2897 unsigned long mc_filter[2];
2898 unsigned int bitnr;
2899 struct macb *bp = netdev_priv(dev);
2900
2901 mc_filter[0] = 0;
2902 mc_filter[1] = 0;
2903
2904 netdev_for_each_mc_addr(ha, dev) {
2905 bitnr = hash_get_index(addr: ha->addr);
2906 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
2907 }
2908
2909 macb_or_gem_writel(bp, HRB, mc_filter[0]);
2910 macb_or_gem_writel(bp, HRT, mc_filter[1]);
2911}
2912
2913/* Enable/Disable promiscuous and multicast modes. */
2914static void macb_set_rx_mode(struct net_device *dev)
2915{
2916 unsigned long cfg;
2917 struct macb *bp = netdev_priv(dev);
2918
2919 cfg = macb_readl(bp, NCFGR);
2920
2921 if (dev->flags & IFF_PROMISC) {
2922 /* Enable promiscuous mode */
2923 cfg |= MACB_BIT(CAF);
2924
2925 /* Disable RX checksum offload */
2926 if (macb_is_gem(bp))
2927 cfg &= ~GEM_BIT(RXCOEN);
2928 } else {
2929 /* Disable promiscuous mode */
2930 cfg &= ~MACB_BIT(CAF);
2931
2932 /* Enable RX checksum offload only if requested */
2933 if (macb_is_gem(bp) && dev->features & NETIF_F_RXCSUM)
2934 cfg |= GEM_BIT(RXCOEN);
2935 }
2936
2937 if (dev->flags & IFF_ALLMULTI) {
2938 /* Enable all multicast mode */
2939 macb_or_gem_writel(bp, HRB, -1);
2940 macb_or_gem_writel(bp, HRT, -1);
2941 cfg |= MACB_BIT(NCFGR_MTI);
2942 } else if (!netdev_mc_empty(dev)) {
2943 /* Enable specific multicasts */
2944 macb_sethashtable(dev);
2945 cfg |= MACB_BIT(NCFGR_MTI);
2946 } else if (dev->flags & (~IFF_ALLMULTI)) {
2947 /* Disable all multicast mode */
2948 macb_or_gem_writel(bp, HRB, 0);
2949 macb_or_gem_writel(bp, HRT, 0);
2950 cfg &= ~MACB_BIT(NCFGR_MTI);
2951 }
2952
2953 macb_writel(bp, NCFGR, cfg);
2954}
2955
2956static int macb_open(struct net_device *dev)
2957{
2958 size_t bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN;
2959 struct macb *bp = netdev_priv(dev);
2960 struct macb_queue *queue;
2961 unsigned int q;
2962 int err;
2963
2964 netdev_dbg(bp->dev, "open\n");
2965
2966 err = pm_runtime_resume_and_get(dev: &bp->pdev->dev);
2967 if (err < 0)
2968 return err;
2969
2970 /* RX buffers initialization */
2971 macb_init_rx_buffer_size(bp, size: bufsz);
2972
2973 err = macb_alloc_consistent(bp);
2974 if (err) {
2975 netdev_err(dev, format: "Unable to allocate DMA memory (error %d)\n",
2976 err);
2977 goto pm_exit;
2978 }
2979
2980 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2981 napi_enable(n: &queue->napi_rx);
2982 napi_enable(n: &queue->napi_tx);
2983 }
2984
2985 macb_init_hw(bp);
2986
2987 err = phy_power_on(phy: bp->sgmii_phy);
2988 if (err)
2989 goto reset_hw;
2990
2991 err = macb_phylink_connect(bp);
2992 if (err)
2993 goto phy_off;
2994
2995 netif_tx_start_all_queues(dev);
2996
2997 if (bp->ptp_info)
2998 bp->ptp_info->ptp_init(dev);
2999
3000 return 0;
3001
3002phy_off:
3003 phy_power_off(phy: bp->sgmii_phy);
3004
3005reset_hw:
3006 macb_reset_hw(bp);
3007 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
3008 napi_disable(n: &queue->napi_rx);
3009 napi_disable(n: &queue->napi_tx);
3010 }
3011 macb_free_consistent(bp);
3012pm_exit:
3013 pm_runtime_put_sync(dev: &bp->pdev->dev);
3014 return err;
3015}
3016
3017static int macb_close(struct net_device *dev)
3018{
3019 struct macb *bp = netdev_priv(dev);
3020 struct macb_queue *queue;
3021 unsigned long flags;
3022 unsigned int q;
3023
3024 netif_tx_stop_all_queues(dev);
3025
3026 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
3027 napi_disable(n: &queue->napi_rx);
3028 napi_disable(n: &queue->napi_tx);
3029 netdev_tx_reset_queue(q: netdev_get_tx_queue(dev, index: q));
3030 }
3031
3032 phylink_stop(bp->phylink);
3033 phylink_disconnect_phy(bp->phylink);
3034
3035 phy_power_off(phy: bp->sgmii_phy);
3036
3037 spin_lock_irqsave(&bp->lock, flags);
3038 macb_reset_hw(bp);
3039 netif_carrier_off(dev);
3040 spin_unlock_irqrestore(lock: &bp->lock, flags);
3041
3042 macb_free_consistent(bp);
3043
3044 if (bp->ptp_info)
3045 bp->ptp_info->ptp_remove(dev);
3046
3047 pm_runtime_put(dev: &bp->pdev->dev);
3048
3049 return 0;
3050}
3051
3052static int macb_change_mtu(struct net_device *dev, int new_mtu)
3053{
3054 if (netif_running(dev))
3055 return -EBUSY;
3056
3057 WRITE_ONCE(dev->mtu, new_mtu);
3058
3059 return 0;
3060}
3061
3062static int macb_set_mac_addr(struct net_device *dev, void *addr)
3063{
3064 int err;
3065
3066 err = eth_mac_addr(dev, p: addr);
3067 if (err < 0)
3068 return err;
3069
3070 macb_set_hwaddr(bp: netdev_priv(dev));
3071 return 0;
3072}
3073
3074static void gem_update_stats(struct macb *bp)
3075{
3076 struct macb_queue *queue;
3077 unsigned int i, q, idx;
3078 unsigned long *stat;
3079
3080 u64 *p = &bp->hw_stats.gem.tx_octets;
3081
3082 for (i = 0; i < GEM_STATS_LEN; ++i, ++p) {
3083 u32 offset = gem_statistics[i].offset;
3084 u64 val = bp->macb_reg_readl(bp, offset);
3085
3086 bp->ethtool_stats[i] += val;
3087 *p += val;
3088
3089 if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) {
3090 /* Add GEM_OCTTXH, GEM_OCTRXH */
3091 val = bp->macb_reg_readl(bp, offset + 4);
3092 bp->ethtool_stats[i] += ((u64)val) << 32;
3093 *(p++) += ((u64)val) << 32;
3094 }
3095 }
3096
3097 idx = GEM_STATS_LEN;
3098 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
3099 for (i = 0, stat = &queue->stats.first; i < QUEUE_STATS_LEN; ++i, ++stat)
3100 bp->ethtool_stats[idx++] = *stat;
3101}
3102
3103static void gem_get_stats(struct macb *bp, struct rtnl_link_stats64 *nstat)
3104{
3105 struct gem_stats *hwstat = &bp->hw_stats.gem;
3106
3107 spin_lock_irq(lock: &bp->stats_lock);
3108 if (netif_running(dev: bp->dev))
3109 gem_update_stats(bp);
3110
3111 nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
3112 hwstat->rx_alignment_errors +
3113 hwstat->rx_resource_errors +
3114 hwstat->rx_overruns +
3115 hwstat->rx_oversize_frames +
3116 hwstat->rx_jabbers +
3117 hwstat->rx_undersized_frames +
3118 hwstat->rx_length_field_frame_errors);
3119 nstat->tx_errors = (hwstat->tx_late_collisions +
3120 hwstat->tx_excessive_collisions +
3121 hwstat->tx_underrun +
3122 hwstat->tx_carrier_sense_errors);
3123 nstat->multicast = hwstat->rx_multicast_frames;
3124 nstat->collisions = (hwstat->tx_single_collision_frames +
3125 hwstat->tx_multiple_collision_frames +
3126 hwstat->tx_excessive_collisions);
3127 nstat->rx_length_errors = (hwstat->rx_oversize_frames +
3128 hwstat->rx_jabbers +
3129 hwstat->rx_undersized_frames +
3130 hwstat->rx_length_field_frame_errors);
3131 nstat->rx_over_errors = hwstat->rx_resource_errors;
3132 nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
3133 nstat->rx_frame_errors = hwstat->rx_alignment_errors;
3134 nstat->rx_fifo_errors = hwstat->rx_overruns;
3135 nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
3136 nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
3137 nstat->tx_fifo_errors = hwstat->tx_underrun;
3138 spin_unlock_irq(lock: &bp->stats_lock);
3139}
3140
3141static void gem_get_ethtool_stats(struct net_device *dev,
3142 struct ethtool_stats *stats, u64 *data)
3143{
3144 struct macb *bp = netdev_priv(dev);
3145
3146 spin_lock_irq(lock: &bp->stats_lock);
3147 gem_update_stats(bp);
3148 memcpy(data, &bp->ethtool_stats, sizeof(u64)
3149 * (GEM_STATS_LEN + QUEUE_STATS_LEN * MACB_MAX_QUEUES));
3150 spin_unlock_irq(lock: &bp->stats_lock);
3151}
3152
3153static int gem_get_sset_count(struct net_device *dev, int sset)
3154{
3155 struct macb *bp = netdev_priv(dev);
3156
3157 switch (sset) {
3158 case ETH_SS_STATS:
3159 return GEM_STATS_LEN + bp->num_queues * QUEUE_STATS_LEN;
3160 default:
3161 return -EOPNOTSUPP;
3162 }
3163}
3164
3165static void gem_get_ethtool_strings(struct net_device *dev, u32 sset, u8 *p)
3166{
3167 char stat_string[ETH_GSTRING_LEN];
3168 struct macb *bp = netdev_priv(dev);
3169 struct macb_queue *queue;
3170 unsigned int i;
3171 unsigned int q;
3172
3173 switch (sset) {
3174 case ETH_SS_STATS:
3175 for (i = 0; i < GEM_STATS_LEN; i++, p += ETH_GSTRING_LEN)
3176 memcpy(p, gem_statistics[i].stat_string,
3177 ETH_GSTRING_LEN);
3178
3179 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
3180 for (i = 0; i < QUEUE_STATS_LEN; i++, p += ETH_GSTRING_LEN) {
3181 snprintf(buf: stat_string, ETH_GSTRING_LEN, fmt: "q%d_%s",
3182 q, queue_statistics[i].stat_string);
3183 memcpy(p, stat_string, ETH_GSTRING_LEN);
3184 }
3185 }
3186 break;
3187 }
3188}
3189
3190static void macb_get_stats(struct net_device *dev,
3191 struct rtnl_link_stats64 *nstat)
3192{
3193 struct macb *bp = netdev_priv(dev);
3194 struct macb_stats *hwstat = &bp->hw_stats.macb;
3195
3196 netdev_stats_to_stats64(stats64: nstat, netdev_stats: &bp->dev->stats);
3197 if (macb_is_gem(bp)) {
3198 gem_get_stats(bp, nstat);
3199 return;
3200 }
3201
3202 /* read stats from hardware */
3203 spin_lock_irq(lock: &bp->stats_lock);
3204 macb_update_stats(bp);
3205
3206 /* Convert HW stats into netdevice stats */
3207 nstat->rx_errors = (hwstat->rx_fcs_errors +
3208 hwstat->rx_align_errors +
3209 hwstat->rx_resource_errors +
3210 hwstat->rx_overruns +
3211 hwstat->rx_oversize_pkts +
3212 hwstat->rx_jabbers +
3213 hwstat->rx_undersize_pkts +
3214 hwstat->rx_length_mismatch);
3215 nstat->tx_errors = (hwstat->tx_late_cols +
3216 hwstat->tx_excessive_cols +
3217 hwstat->tx_underruns +
3218 hwstat->tx_carrier_errors +
3219 hwstat->sqe_test_errors);
3220 nstat->collisions = (hwstat->tx_single_cols +
3221 hwstat->tx_multiple_cols +
3222 hwstat->tx_excessive_cols);
3223 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
3224 hwstat->rx_jabbers +
3225 hwstat->rx_undersize_pkts +
3226 hwstat->rx_length_mismatch);
3227 nstat->rx_over_errors = hwstat->rx_resource_errors +
3228 hwstat->rx_overruns;
3229 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
3230 nstat->rx_frame_errors = hwstat->rx_align_errors;
3231 nstat->rx_fifo_errors = hwstat->rx_overruns;
3232 /* XXX: What does "missed" mean? */
3233 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
3234 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
3235 nstat->tx_fifo_errors = hwstat->tx_underruns;
3236 /* Don't know about heartbeat or window errors... */
3237 spin_unlock_irq(lock: &bp->stats_lock);
3238}
3239
3240static void macb_get_pause_stats(struct net_device *dev,
3241 struct ethtool_pause_stats *pause_stats)
3242{
3243 struct macb *bp = netdev_priv(dev);
3244 struct macb_stats *hwstat = &bp->hw_stats.macb;
3245
3246 spin_lock_irq(lock: &bp->stats_lock);
3247 macb_update_stats(bp);
3248 pause_stats->tx_pause_frames = hwstat->tx_pause_frames;
3249 pause_stats->rx_pause_frames = hwstat->rx_pause_frames;
3250 spin_unlock_irq(lock: &bp->stats_lock);
3251}
3252
3253static void gem_get_pause_stats(struct net_device *dev,
3254 struct ethtool_pause_stats *pause_stats)
3255{
3256 struct macb *bp = netdev_priv(dev);
3257 struct gem_stats *hwstat = &bp->hw_stats.gem;
3258
3259 spin_lock_irq(lock: &bp->stats_lock);
3260 gem_update_stats(bp);
3261 pause_stats->tx_pause_frames = hwstat->tx_pause_frames;
3262 pause_stats->rx_pause_frames = hwstat->rx_pause_frames;
3263 spin_unlock_irq(lock: &bp->stats_lock);
3264}
3265
3266static void macb_get_eth_mac_stats(struct net_device *dev,
3267 struct ethtool_eth_mac_stats *mac_stats)
3268{
3269 struct macb *bp = netdev_priv(dev);
3270 struct macb_stats *hwstat = &bp->hw_stats.macb;
3271
3272 spin_lock_irq(lock: &bp->stats_lock);
3273 macb_update_stats(bp);
3274 mac_stats->FramesTransmittedOK = hwstat->tx_ok;
3275 mac_stats->SingleCollisionFrames = hwstat->tx_single_cols;
3276 mac_stats->MultipleCollisionFrames = hwstat->tx_multiple_cols;
3277 mac_stats->FramesReceivedOK = hwstat->rx_ok;
3278 mac_stats->FrameCheckSequenceErrors = hwstat->rx_fcs_errors;
3279 mac_stats->AlignmentErrors = hwstat->rx_align_errors;
3280 mac_stats->FramesWithDeferredXmissions = hwstat->tx_deferred;
3281 mac_stats->LateCollisions = hwstat->tx_late_cols;
3282 mac_stats->FramesAbortedDueToXSColls = hwstat->tx_excessive_cols;
3283 mac_stats->FramesLostDueToIntMACXmitError = hwstat->tx_underruns;
3284 mac_stats->CarrierSenseErrors = hwstat->tx_carrier_errors;
3285 mac_stats->FramesLostDueToIntMACRcvError = hwstat->rx_overruns;
3286 mac_stats->InRangeLengthErrors = hwstat->rx_length_mismatch;
3287 mac_stats->FrameTooLongErrors = hwstat->rx_oversize_pkts;
3288 spin_unlock_irq(lock: &bp->stats_lock);
3289}
3290
3291static void gem_get_eth_mac_stats(struct net_device *dev,
3292 struct ethtool_eth_mac_stats *mac_stats)
3293{
3294 struct macb *bp = netdev_priv(dev);
3295 struct gem_stats *hwstat = &bp->hw_stats.gem;
3296
3297 spin_lock_irq(lock: &bp->stats_lock);
3298 gem_update_stats(bp);
3299 mac_stats->FramesTransmittedOK = hwstat->tx_frames;
3300 mac_stats->SingleCollisionFrames = hwstat->tx_single_collision_frames;
3301 mac_stats->MultipleCollisionFrames =
3302 hwstat->tx_multiple_collision_frames;
3303 mac_stats->FramesReceivedOK = hwstat->rx_frames;
3304 mac_stats->FrameCheckSequenceErrors =
3305 hwstat->rx_frame_check_sequence_errors;
3306 mac_stats->AlignmentErrors = hwstat->rx_alignment_errors;
3307 mac_stats->OctetsTransmittedOK = hwstat->tx_octets;
3308 mac_stats->FramesWithDeferredXmissions = hwstat->tx_deferred_frames;
3309 mac_stats->LateCollisions = hwstat->tx_late_collisions;
3310 mac_stats->FramesAbortedDueToXSColls = hwstat->tx_excessive_collisions;
3311 mac_stats->FramesLostDueToIntMACXmitError = hwstat->tx_underrun;
3312 mac_stats->CarrierSenseErrors = hwstat->tx_carrier_sense_errors;
3313 mac_stats->OctetsReceivedOK = hwstat->rx_octets;
3314 mac_stats->MulticastFramesXmittedOK = hwstat->tx_multicast_frames;
3315 mac_stats->BroadcastFramesXmittedOK = hwstat->tx_broadcast_frames;
3316 mac_stats->MulticastFramesReceivedOK = hwstat->rx_multicast_frames;
3317 mac_stats->BroadcastFramesReceivedOK = hwstat->rx_broadcast_frames;
3318 mac_stats->InRangeLengthErrors = hwstat->rx_length_field_frame_errors;
3319 mac_stats->FrameTooLongErrors = hwstat->rx_oversize_frames;
3320 spin_unlock_irq(lock: &bp->stats_lock);
3321}
3322
3323/* TODO: Report SQE test errors when added to phy_stats */
3324static void macb_get_eth_phy_stats(struct net_device *dev,
3325 struct ethtool_eth_phy_stats *phy_stats)
3326{
3327 struct macb *bp = netdev_priv(dev);
3328 struct macb_stats *hwstat = &bp->hw_stats.macb;
3329
3330 spin_lock_irq(lock: &bp->stats_lock);
3331 macb_update_stats(bp);
3332 phy_stats->SymbolErrorDuringCarrier = hwstat->rx_symbol_errors;
3333 spin_unlock_irq(lock: &bp->stats_lock);
3334}
3335
3336static void gem_get_eth_phy_stats(struct net_device *dev,
3337 struct ethtool_eth_phy_stats *phy_stats)
3338{
3339 struct macb *bp = netdev_priv(dev);
3340 struct gem_stats *hwstat = &bp->hw_stats.gem;
3341
3342 spin_lock_irq(lock: &bp->stats_lock);
3343 gem_update_stats(bp);
3344 phy_stats->SymbolErrorDuringCarrier = hwstat->rx_symbol_errors;
3345 spin_unlock_irq(lock: &bp->stats_lock);
3346}
3347
3348static void macb_get_rmon_stats(struct net_device *dev,
3349 struct ethtool_rmon_stats *rmon_stats,
3350 const struct ethtool_rmon_hist_range **ranges)
3351{
3352 struct macb *bp = netdev_priv(dev);
3353 struct macb_stats *hwstat = &bp->hw_stats.macb;
3354
3355 spin_lock_irq(lock: &bp->stats_lock);
3356 macb_update_stats(bp);
3357 rmon_stats->undersize_pkts = hwstat->rx_undersize_pkts;
3358 rmon_stats->oversize_pkts = hwstat->rx_oversize_pkts;
3359 rmon_stats->jabbers = hwstat->rx_jabbers;
3360 spin_unlock_irq(lock: &bp->stats_lock);
3361}
3362
3363static const struct ethtool_rmon_hist_range gem_rmon_ranges[] = {
3364 { 64, 64 },
3365 { 65, 127 },
3366 { 128, 255 },
3367 { 256, 511 },
3368 { 512, 1023 },
3369 { 1024, 1518 },
3370 { 1519, 16384 },
3371 { },
3372};
3373
3374static void gem_get_rmon_stats(struct net_device *dev,
3375 struct ethtool_rmon_stats *rmon_stats,
3376 const struct ethtool_rmon_hist_range **ranges)
3377{
3378 struct macb *bp = netdev_priv(dev);
3379 struct gem_stats *hwstat = &bp->hw_stats.gem;
3380
3381 spin_lock_irq(lock: &bp->stats_lock);
3382 gem_update_stats(bp);
3383 rmon_stats->undersize_pkts = hwstat->rx_undersized_frames;
3384 rmon_stats->oversize_pkts = hwstat->rx_oversize_frames;
3385 rmon_stats->jabbers = hwstat->rx_jabbers;
3386 rmon_stats->hist[0] = hwstat->rx_64_byte_frames;
3387 rmon_stats->hist[1] = hwstat->rx_65_127_byte_frames;
3388 rmon_stats->hist[2] = hwstat->rx_128_255_byte_frames;
3389 rmon_stats->hist[3] = hwstat->rx_256_511_byte_frames;
3390 rmon_stats->hist[4] = hwstat->rx_512_1023_byte_frames;
3391 rmon_stats->hist[5] = hwstat->rx_1024_1518_byte_frames;
3392 rmon_stats->hist[6] = hwstat->rx_greater_than_1518_byte_frames;
3393 rmon_stats->hist_tx[0] = hwstat->tx_64_byte_frames;
3394 rmon_stats->hist_tx[1] = hwstat->tx_65_127_byte_frames;
3395 rmon_stats->hist_tx[2] = hwstat->tx_128_255_byte_frames;
3396 rmon_stats->hist_tx[3] = hwstat->tx_256_511_byte_frames;
3397 rmon_stats->hist_tx[4] = hwstat->tx_512_1023_byte_frames;
3398 rmon_stats->hist_tx[5] = hwstat->tx_1024_1518_byte_frames;
3399 rmon_stats->hist_tx[6] = hwstat->tx_greater_than_1518_byte_frames;
3400 spin_unlock_irq(lock: &bp->stats_lock);
3401 *ranges = gem_rmon_ranges;
3402}
3403
3404static int macb_get_regs_len(struct net_device *netdev)
3405{
3406 return MACB_GREGS_NBR * sizeof(u32);
3407}
3408
3409static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3410 void *p)
3411{
3412 struct macb *bp = netdev_priv(dev);
3413 unsigned int tail, head;
3414 u32 *regs_buff = p;
3415
3416 regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1))
3417 | MACB_GREGS_VERSION;
3418
3419 tail = macb_tx_ring_wrap(bp, index: bp->queues[0].tx_tail);
3420 head = macb_tx_ring_wrap(bp, index: bp->queues[0].tx_head);
3421
3422 regs_buff[0] = macb_readl(bp, NCR);
3423 regs_buff[1] = macb_or_gem_readl(bp, NCFGR);
3424 regs_buff[2] = macb_readl(bp, NSR);
3425 regs_buff[3] = macb_readl(bp, TSR);
3426 regs_buff[4] = macb_readl(bp, RBQP);
3427 regs_buff[5] = macb_readl(bp, TBQP);
3428 regs_buff[6] = macb_readl(bp, RSR);
3429 regs_buff[7] = macb_readl(bp, IMR);
3430
3431 regs_buff[8] = tail;
3432 regs_buff[9] = head;
3433 regs_buff[10] = macb_tx_dma(queue: &bp->queues[0], index: tail);
3434 regs_buff[11] = macb_tx_dma(queue: &bp->queues[0], index: head);
3435
3436 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
3437 regs_buff[12] = macb_or_gem_readl(bp, USRIO);
3438 if (macb_is_gem(bp))
3439 regs_buff[13] = gem_readl(bp, DMACFG);
3440}
3441
3442static void macb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
3443{
3444 struct macb *bp = netdev_priv(dev: netdev);
3445
3446 phylink_ethtool_get_wol(bp->phylink, wol);
3447 wol->supported |= (WAKE_MAGIC | WAKE_ARP);
3448
3449 /* Add macb wolopts to phy wolopts */
3450 wol->wolopts |= bp->wolopts;
3451}
3452
3453static int macb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
3454{
3455 struct macb *bp = netdev_priv(dev: netdev);
3456 int ret;
3457
3458 /* Pass the order to phylink layer */
3459 ret = phylink_ethtool_set_wol(bp->phylink, wol);
3460 /* Don't manage WoL on MAC, if PHY set_wol() fails */
3461 if (ret && ret != -EOPNOTSUPP)
3462 return ret;
3463
3464 bp->wolopts = (wol->wolopts & WAKE_MAGIC) ? WAKE_MAGIC : 0;
3465 bp->wolopts |= (wol->wolopts & WAKE_ARP) ? WAKE_ARP : 0;
3466 bp->wol = (wol->wolopts) ? MACB_WOL_ENABLED : 0;
3467
3468 device_set_wakeup_enable(dev: &bp->pdev->dev, enable: bp->wol);
3469
3470 return 0;
3471}
3472
3473static int macb_get_link_ksettings(struct net_device *netdev,
3474 struct ethtool_link_ksettings *kset)
3475{
3476 struct macb *bp = netdev_priv(dev: netdev);
3477
3478 return phylink_ethtool_ksettings_get(bp->phylink, kset);
3479}
3480
3481static int macb_set_link_ksettings(struct net_device *netdev,
3482 const struct ethtool_link_ksettings *kset)
3483{
3484 struct macb *bp = netdev_priv(dev: netdev);
3485
3486 return phylink_ethtool_ksettings_set(bp->phylink, kset);
3487}
3488
3489static void macb_get_ringparam(struct net_device *netdev,
3490 struct ethtool_ringparam *ring,
3491 struct kernel_ethtool_ringparam *kernel_ring,
3492 struct netlink_ext_ack *extack)
3493{
3494 struct macb *bp = netdev_priv(dev: netdev);
3495
3496 ring->rx_max_pending = MAX_RX_RING_SIZE;
3497 ring->tx_max_pending = MAX_TX_RING_SIZE;
3498
3499 ring->rx_pending = bp->rx_ring_size;
3500 ring->tx_pending = bp->tx_ring_size;
3501}
3502
3503static int macb_set_ringparam(struct net_device *netdev,
3504 struct ethtool_ringparam *ring,
3505 struct kernel_ethtool_ringparam *kernel_ring,
3506 struct netlink_ext_ack *extack)
3507{
3508 struct macb *bp = netdev_priv(dev: netdev);
3509 u32 new_rx_size, new_tx_size;
3510 unsigned int reset = 0;
3511
3512 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
3513 return -EINVAL;
3514
3515 new_rx_size = clamp_t(u32, ring->rx_pending,
3516 MIN_RX_RING_SIZE, MAX_RX_RING_SIZE);
3517 new_rx_size = roundup_pow_of_two(new_rx_size);
3518
3519 new_tx_size = clamp_t(u32, ring->tx_pending,
3520 MIN_TX_RING_SIZE, MAX_TX_RING_SIZE);
3521 new_tx_size = roundup_pow_of_two(new_tx_size);
3522
3523 if ((new_tx_size == bp->tx_ring_size) &&
3524 (new_rx_size == bp->rx_ring_size)) {
3525 /* nothing to do */
3526 return 0;
3527 }
3528
3529 if (netif_running(dev: bp->dev)) {
3530 reset = 1;
3531 macb_close(dev: bp->dev);
3532 }
3533
3534 bp->rx_ring_size = new_rx_size;
3535 bp->tx_ring_size = new_tx_size;
3536
3537 if (reset)
3538 macb_open(dev: bp->dev);
3539
3540 return 0;
3541}
3542
3543#ifdef CONFIG_MACB_USE_HWSTAMP
3544static unsigned int gem_get_tsu_rate(struct macb *bp)
3545{
3546 struct clk *tsu_clk;
3547 unsigned int tsu_rate;
3548
3549 tsu_clk = devm_clk_get(dev: &bp->pdev->dev, id: "tsu_clk");
3550 if (!IS_ERR(ptr: tsu_clk))
3551 tsu_rate = clk_get_rate(clk: tsu_clk);
3552 /* try pclk instead */
3553 else if (!IS_ERR(ptr: bp->pclk)) {
3554 tsu_clk = bp->pclk;
3555 tsu_rate = clk_get_rate(clk: tsu_clk);
3556 } else
3557 return -ENOTSUPP;
3558 return tsu_rate;
3559}
3560
3561static s32 gem_get_ptp_max_adj(void)
3562{
3563 return 64000000;
3564}
3565
3566static int gem_get_ts_info(struct net_device *dev,
3567 struct kernel_ethtool_ts_info *info)
3568{
3569 struct macb *bp = netdev_priv(dev);
3570
3571 if ((bp->hw_dma_cap & HW_DMA_CAP_PTP) == 0) {
3572 ethtool_op_get_ts_info(dev, eti: info);
3573 return 0;
3574 }
3575
3576 info->so_timestamping =
3577 SOF_TIMESTAMPING_TX_SOFTWARE |
3578 SOF_TIMESTAMPING_TX_HARDWARE |
3579 SOF_TIMESTAMPING_RX_HARDWARE |
3580 SOF_TIMESTAMPING_RAW_HARDWARE;
3581 info->tx_types =
3582 (1 << HWTSTAMP_TX_ONESTEP_SYNC) |
3583 (1 << HWTSTAMP_TX_OFF) |
3584 (1 << HWTSTAMP_TX_ON);
3585 info->rx_filters =
3586 (1 << HWTSTAMP_FILTER_NONE) |
3587 (1 << HWTSTAMP_FILTER_ALL);
3588
3589 if (bp->ptp_clock)
3590 info->phc_index = ptp_clock_index(ptp: bp->ptp_clock);
3591
3592 return 0;
3593}
3594
3595static struct macb_ptp_info gem_ptp_info = {
3596 .ptp_init = gem_ptp_init,
3597 .ptp_remove = gem_ptp_remove,
3598 .get_ptp_max_adj = gem_get_ptp_max_adj,
3599 .get_tsu_rate = gem_get_tsu_rate,
3600 .get_ts_info = gem_get_ts_info,
3601 .get_hwtst = gem_get_hwtst,
3602 .set_hwtst = gem_set_hwtst,
3603};
3604#endif
3605
3606static int macb_get_ts_info(struct net_device *netdev,
3607 struct kernel_ethtool_ts_info *info)
3608{
3609 struct macb *bp = netdev_priv(dev: netdev);
3610
3611 if (bp->ptp_info)
3612 return bp->ptp_info->get_ts_info(netdev, info);
3613
3614 return ethtool_op_get_ts_info(dev: netdev, eti: info);
3615}
3616
3617static void gem_enable_flow_filters(struct macb *bp, bool enable)
3618{
3619 struct net_device *netdev = bp->dev;
3620 struct ethtool_rx_fs_item *item;
3621 u32 t2_scr;
3622 int num_t2_scr;
3623
3624 if (!(netdev->features & NETIF_F_NTUPLE))
3625 return;
3626
3627 num_t2_scr = GEM_BFEXT(T2SCR, gem_readl(bp, DCFG8));
3628
3629 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3630 struct ethtool_rx_flow_spec *fs = &item->fs;
3631 struct ethtool_tcpip4_spec *tp4sp_m;
3632
3633 if (fs->location >= num_t2_scr)
3634 continue;
3635
3636 t2_scr = gem_readl_n(bp, SCRT2, fs->location);
3637
3638 /* enable/disable screener regs for the flow entry */
3639 t2_scr = GEM_BFINS(ETHTEN, enable, t2_scr);
3640
3641 /* only enable fields with no masking */
3642 tp4sp_m = &(fs->m_u.tcp_ip4_spec);
3643
3644 if (enable && (tp4sp_m->ip4src == 0xFFFFFFFF))
3645 t2_scr = GEM_BFINS(CMPAEN, 1, t2_scr);
3646 else
3647 t2_scr = GEM_BFINS(CMPAEN, 0, t2_scr);
3648
3649 if (enable && (tp4sp_m->ip4dst == 0xFFFFFFFF))
3650 t2_scr = GEM_BFINS(CMPBEN, 1, t2_scr);
3651 else
3652 t2_scr = GEM_BFINS(CMPBEN, 0, t2_scr);
3653
3654 if (enable && ((tp4sp_m->psrc == 0xFFFF) || (tp4sp_m->pdst == 0xFFFF)))
3655 t2_scr = GEM_BFINS(CMPCEN, 1, t2_scr);
3656 else
3657 t2_scr = GEM_BFINS(CMPCEN, 0, t2_scr);
3658
3659 gem_writel_n(bp, SCRT2, fs->location, t2_scr);
3660 }
3661}
3662
3663static void gem_prog_cmp_regs(struct macb *bp, struct ethtool_rx_flow_spec *fs)
3664{
3665 struct ethtool_tcpip4_spec *tp4sp_v, *tp4sp_m;
3666 uint16_t index = fs->location;
3667 u32 w0, w1, t2_scr;
3668 bool cmp_a = false;
3669 bool cmp_b = false;
3670 bool cmp_c = false;
3671
3672 if (!macb_is_gem(bp))
3673 return;
3674
3675 tp4sp_v = &(fs->h_u.tcp_ip4_spec);
3676 tp4sp_m = &(fs->m_u.tcp_ip4_spec);
3677
3678 /* ignore field if any masking set */
3679 if (tp4sp_m->ip4src == 0xFFFFFFFF) {
3680 /* 1st compare reg - IP source address */
3681 w0 = 0;
3682 w1 = 0;
3683 w0 = tp4sp_v->ip4src;
3684 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
3685 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_ETYPE, w1);
3686 w1 = GEM_BFINS(T2OFST, ETYPE_SRCIP_OFFSET, w1);
3687 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_IP4SRC_CMP(index)), w0);
3688 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_IP4SRC_CMP(index)), w1);
3689 cmp_a = true;
3690 }
3691
3692 /* ignore field if any masking set */
3693 if (tp4sp_m->ip4dst == 0xFFFFFFFF) {
3694 /* 2nd compare reg - IP destination address */
3695 w0 = 0;
3696 w1 = 0;
3697 w0 = tp4sp_v->ip4dst;
3698 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
3699 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_ETYPE, w1);
3700 w1 = GEM_BFINS(T2OFST, ETYPE_DSTIP_OFFSET, w1);
3701 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_IP4DST_CMP(index)), w0);
3702 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_IP4DST_CMP(index)), w1);
3703 cmp_b = true;
3704 }
3705
3706 /* ignore both port fields if masking set in both */
3707 if ((tp4sp_m->psrc == 0xFFFF) || (tp4sp_m->pdst == 0xFFFF)) {
3708 /* 3rd compare reg - source port, destination port */
3709 w0 = 0;
3710 w1 = 0;
3711 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_IPHDR, w1);
3712 if (tp4sp_m->psrc == tp4sp_m->pdst) {
3713 w0 = GEM_BFINS(T2MASK, tp4sp_v->psrc, w0);
3714 w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0);
3715 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
3716 w1 = GEM_BFINS(T2OFST, IPHDR_SRCPORT_OFFSET, w1);
3717 } else {
3718 /* only one port definition */
3719 w1 = GEM_BFINS(T2DISMSK, 0, w1); /* 16-bit compare */
3720 w0 = GEM_BFINS(T2MASK, 0xFFFF, w0);
3721 if (tp4sp_m->psrc == 0xFFFF) { /* src port */
3722 w0 = GEM_BFINS(T2CMP, tp4sp_v->psrc, w0);
3723 w1 = GEM_BFINS(T2OFST, IPHDR_SRCPORT_OFFSET, w1);
3724 } else { /* dst port */
3725 w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0);
3726 w1 = GEM_BFINS(T2OFST, IPHDR_DSTPORT_OFFSET, w1);
3727 }
3728 }
3729 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_PORT_CMP(index)), w0);
3730 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_PORT_CMP(index)), w1);
3731 cmp_c = true;
3732 }
3733
3734 t2_scr = 0;
3735 t2_scr = GEM_BFINS(QUEUE, (fs->ring_cookie) & 0xFF, t2_scr);
3736 t2_scr = GEM_BFINS(ETHT2IDX, SCRT2_ETHT, t2_scr);
3737 if (cmp_a)
3738 t2_scr = GEM_BFINS(CMPA, GEM_IP4SRC_CMP(index), t2_scr);
3739 if (cmp_b)
3740 t2_scr = GEM_BFINS(CMPB, GEM_IP4DST_CMP(index), t2_scr);
3741 if (cmp_c)
3742 t2_scr = GEM_BFINS(CMPC, GEM_PORT_CMP(index), t2_scr);
3743 gem_writel_n(bp, SCRT2, index, t2_scr);
3744}
3745
3746static int gem_add_flow_filter(struct net_device *netdev,
3747 struct ethtool_rxnfc *cmd)
3748{
3749 struct macb *bp = netdev_priv(dev: netdev);
3750 struct ethtool_rx_flow_spec *fs = &cmd->fs;
3751 struct ethtool_rx_fs_item *item, *newfs;
3752 unsigned long flags;
3753 int ret = -EINVAL;
3754 bool added = false;
3755
3756 newfs = kmalloc(sizeof(*newfs), GFP_KERNEL);
3757 if (newfs == NULL)
3758 return -ENOMEM;
3759 memcpy(&newfs->fs, fs, sizeof(newfs->fs));
3760
3761 netdev_dbg(netdev,
3762 "Adding flow filter entry,type=%u,queue=%u,loc=%u,src=%08X,dst=%08X,ps=%u,pd=%u\n",
3763 fs->flow_type, (int)fs->ring_cookie, fs->location,
3764 htonl(fs->h_u.tcp_ip4_spec.ip4src),
3765 htonl(fs->h_u.tcp_ip4_spec.ip4dst),
3766 be16_to_cpu(fs->h_u.tcp_ip4_spec.psrc),
3767 be16_to_cpu(fs->h_u.tcp_ip4_spec.pdst));
3768
3769 spin_lock_irqsave(&bp->rx_fs_lock, flags);
3770
3771 /* find correct place to add in list */
3772 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3773 if (item->fs.location > newfs->fs.location) {
3774 list_add_tail(new: &newfs->list, head: &item->list);
3775 added = true;
3776 break;
3777 } else if (item->fs.location == fs->location) {
3778 netdev_err(dev: netdev, format: "Rule not added: location %d not free!\n",
3779 fs->location);
3780 ret = -EBUSY;
3781 goto err;
3782 }
3783 }
3784 if (!added)
3785 list_add_tail(new: &newfs->list, head: &bp->rx_fs_list.list);
3786
3787 gem_prog_cmp_regs(bp, fs);
3788 bp->rx_fs_list.count++;
3789 /* enable filtering if NTUPLE on */
3790 gem_enable_flow_filters(bp, enable: 1);
3791
3792 spin_unlock_irqrestore(lock: &bp->rx_fs_lock, flags);
3793 return 0;
3794
3795err:
3796 spin_unlock_irqrestore(lock: &bp->rx_fs_lock, flags);
3797 kfree(objp: newfs);
3798 return ret;
3799}
3800
3801static int gem_del_flow_filter(struct net_device *netdev,
3802 struct ethtool_rxnfc *cmd)
3803{
3804 struct macb *bp = netdev_priv(dev: netdev);
3805 struct ethtool_rx_fs_item *item;
3806 struct ethtool_rx_flow_spec *fs;
3807 unsigned long flags;
3808
3809 spin_lock_irqsave(&bp->rx_fs_lock, flags);
3810
3811 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3812 if (item->fs.location == cmd->fs.location) {
3813 /* disable screener regs for the flow entry */
3814 fs = &(item->fs);
3815 netdev_dbg(netdev,
3816 "Deleting flow filter entry,type=%u,queue=%u,loc=%u,src=%08X,dst=%08X,ps=%u,pd=%u\n",
3817 fs->flow_type, (int)fs->ring_cookie, fs->location,
3818 htonl(fs->h_u.tcp_ip4_spec.ip4src),
3819 htonl(fs->h_u.tcp_ip4_spec.ip4dst),
3820 be16_to_cpu(fs->h_u.tcp_ip4_spec.psrc),
3821 be16_to_cpu(fs->h_u.tcp_ip4_spec.pdst));
3822
3823 gem_writel_n(bp, SCRT2, fs->location, 0);
3824
3825 list_del(entry: &item->list);
3826 bp->rx_fs_list.count--;
3827 spin_unlock_irqrestore(lock: &bp->rx_fs_lock, flags);
3828 kfree(objp: item);
3829 return 0;
3830 }
3831 }
3832
3833 spin_unlock_irqrestore(lock: &bp->rx_fs_lock, flags);
3834 return -EINVAL;
3835}
3836
3837static int gem_get_flow_entry(struct net_device *netdev,
3838 struct ethtool_rxnfc *cmd)
3839{
3840 struct macb *bp = netdev_priv(dev: netdev);
3841 struct ethtool_rx_fs_item *item;
3842
3843 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3844 if (item->fs.location == cmd->fs.location) {
3845 memcpy(&cmd->fs, &item->fs, sizeof(cmd->fs));
3846 return 0;
3847 }
3848 }
3849 return -EINVAL;
3850}
3851
3852static int gem_get_all_flow_entries(struct net_device *netdev,
3853 struct ethtool_rxnfc *cmd, u32 *rule_locs)
3854{
3855 struct macb *bp = netdev_priv(dev: netdev);
3856 struct ethtool_rx_fs_item *item;
3857 uint32_t cnt = 0;
3858
3859 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3860 if (cnt == cmd->rule_cnt)
3861 return -EMSGSIZE;
3862 rule_locs[cnt] = item->fs.location;
3863 cnt++;
3864 }
3865 cmd->data = bp->max_tuples;
3866 cmd->rule_cnt = cnt;
3867
3868 return 0;
3869}
3870
3871static int gem_get_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd,
3872 u32 *rule_locs)
3873{
3874 struct macb *bp = netdev_priv(dev: netdev);
3875 int ret = 0;
3876
3877 switch (cmd->cmd) {
3878 case ETHTOOL_GRXRINGS:
3879 cmd->data = bp->num_queues;
3880 break;
3881 case ETHTOOL_GRXCLSRLCNT:
3882 cmd->rule_cnt = bp->rx_fs_list.count;
3883 break;
3884 case ETHTOOL_GRXCLSRULE:
3885 ret = gem_get_flow_entry(netdev, cmd);
3886 break;
3887 case ETHTOOL_GRXCLSRLALL:
3888 ret = gem_get_all_flow_entries(netdev, cmd, rule_locs);
3889 break;
3890 default:
3891 netdev_err(dev: netdev,
3892 format: "Command parameter %d is not supported\n", cmd->cmd);
3893 ret = -EOPNOTSUPP;
3894 }
3895
3896 return ret;
3897}
3898
3899static int gem_set_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd)
3900{
3901 struct macb *bp = netdev_priv(dev: netdev);
3902 int ret;
3903
3904 switch (cmd->cmd) {
3905 case ETHTOOL_SRXCLSRLINS:
3906 if ((cmd->fs.location >= bp->max_tuples)
3907 || (cmd->fs.ring_cookie >= bp->num_queues)) {
3908 ret = -EINVAL;
3909 break;
3910 }
3911 ret = gem_add_flow_filter(netdev, cmd);
3912 break;
3913 case ETHTOOL_SRXCLSRLDEL:
3914 ret = gem_del_flow_filter(netdev, cmd);
3915 break;
3916 default:
3917 netdev_err(dev: netdev,
3918 format: "Command parameter %d is not supported\n", cmd->cmd);
3919 ret = -EOPNOTSUPP;
3920 }
3921
3922 return ret;
3923}
3924
3925static const struct ethtool_ops macb_ethtool_ops = {
3926 .get_regs_len = macb_get_regs_len,
3927 .get_regs = macb_get_regs,
3928 .get_link = ethtool_op_get_link,
3929 .get_ts_info = ethtool_op_get_ts_info,
3930 .get_pause_stats = macb_get_pause_stats,
3931 .get_eth_mac_stats = macb_get_eth_mac_stats,
3932 .get_eth_phy_stats = macb_get_eth_phy_stats,
3933 .get_rmon_stats = macb_get_rmon_stats,
3934 .get_wol = macb_get_wol,
3935 .set_wol = macb_set_wol,
3936 .get_link_ksettings = macb_get_link_ksettings,
3937 .set_link_ksettings = macb_set_link_ksettings,
3938 .get_ringparam = macb_get_ringparam,
3939 .set_ringparam = macb_set_ringparam,
3940};
3941
3942static const struct ethtool_ops gem_ethtool_ops = {
3943 .get_regs_len = macb_get_regs_len,
3944 .get_regs = macb_get_regs,
3945 .get_wol = macb_get_wol,
3946 .set_wol = macb_set_wol,
3947 .get_link = ethtool_op_get_link,
3948 .get_ts_info = macb_get_ts_info,
3949 .get_ethtool_stats = gem_get_ethtool_stats,
3950 .get_strings = gem_get_ethtool_strings,
3951 .get_sset_count = gem_get_sset_count,
3952 .get_pause_stats = gem_get_pause_stats,
3953 .get_eth_mac_stats = gem_get_eth_mac_stats,
3954 .get_eth_phy_stats = gem_get_eth_phy_stats,
3955 .get_rmon_stats = gem_get_rmon_stats,
3956 .get_link_ksettings = macb_get_link_ksettings,
3957 .set_link_ksettings = macb_set_link_ksettings,
3958 .get_ringparam = macb_get_ringparam,
3959 .set_ringparam = macb_set_ringparam,
3960 .get_rxnfc = gem_get_rxnfc,
3961 .set_rxnfc = gem_set_rxnfc,
3962};
3963
3964static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3965{
3966 struct macb *bp = netdev_priv(dev);
3967
3968 if (!netif_running(dev))
3969 return -EINVAL;
3970
3971 return phylink_mii_ioctl(bp->phylink, rq, cmd);
3972}
3973
3974static int macb_hwtstamp_get(struct net_device *dev,
3975 struct kernel_hwtstamp_config *cfg)
3976{
3977 struct macb *bp = netdev_priv(dev);
3978
3979 if (!netif_running(dev))
3980 return -EINVAL;
3981
3982 if (!bp->ptp_info)
3983 return -EOPNOTSUPP;
3984
3985 return bp->ptp_info->get_hwtst(dev, cfg);
3986}
3987
3988static int macb_hwtstamp_set(struct net_device *dev,
3989 struct kernel_hwtstamp_config *cfg,
3990 struct netlink_ext_ack *extack)
3991{
3992 struct macb *bp = netdev_priv(dev);
3993
3994 if (!netif_running(dev))
3995 return -EINVAL;
3996
3997 if (!bp->ptp_info)
3998 return -EOPNOTSUPP;
3999
4000 return bp->ptp_info->set_hwtst(dev, cfg, extack);
4001}
4002
4003static inline void macb_set_txcsum_feature(struct macb *bp,
4004 netdev_features_t features)
4005{
4006 u32 val;
4007
4008 if (!macb_is_gem(bp))
4009 return;
4010
4011 val = gem_readl(bp, DMACFG);
4012 if (features & NETIF_F_HW_CSUM)
4013 val |= GEM_BIT(TXCOEN);
4014 else
4015 val &= ~GEM_BIT(TXCOEN);
4016
4017 gem_writel(bp, DMACFG, val);
4018}
4019
4020static inline void macb_set_rxcsum_feature(struct macb *bp,
4021 netdev_features_t features)
4022{
4023 struct net_device *netdev = bp->dev;
4024 u32 val;
4025
4026 if (!macb_is_gem(bp))
4027 return;
4028
4029 val = gem_readl(bp, NCFGR);
4030 if ((features & NETIF_F_RXCSUM) && !(netdev->flags & IFF_PROMISC))
4031 val |= GEM_BIT(RXCOEN);
4032 else
4033 val &= ~GEM_BIT(RXCOEN);
4034
4035 gem_writel(bp, NCFGR, val);
4036}
4037
4038static inline void macb_set_rxflow_feature(struct macb *bp,
4039 netdev_features_t features)
4040{
4041 if (!macb_is_gem(bp))
4042 return;
4043
4044 gem_enable_flow_filters(bp, enable: !!(features & NETIF_F_NTUPLE));
4045}
4046
4047static int macb_set_features(struct net_device *netdev,
4048 netdev_features_t features)
4049{
4050 struct macb *bp = netdev_priv(dev: netdev);
4051 netdev_features_t changed = features ^ netdev->features;
4052
4053 /* TX checksum offload */
4054 if (changed & NETIF_F_HW_CSUM)
4055 macb_set_txcsum_feature(bp, features);
4056
4057 /* RX checksum offload */
4058 if (changed & NETIF_F_RXCSUM)
4059 macb_set_rxcsum_feature(bp, features);
4060
4061 /* RX Flow Filters */
4062 if (changed & NETIF_F_NTUPLE)
4063 macb_set_rxflow_feature(bp, features);
4064
4065 return 0;
4066}
4067
4068static void macb_restore_features(struct macb *bp)
4069{
4070 struct net_device *netdev = bp->dev;
4071 netdev_features_t features = netdev->features;
4072 struct ethtool_rx_fs_item *item;
4073
4074 /* TX checksum offload */
4075 macb_set_txcsum_feature(bp, features);
4076
4077 /* RX checksum offload */
4078 macb_set_rxcsum_feature(bp, features);
4079
4080 /* RX Flow Filters */
4081 list_for_each_entry(item, &bp->rx_fs_list.list, list)
4082 gem_prog_cmp_regs(bp, fs: &item->fs);
4083
4084 macb_set_rxflow_feature(bp, features);
4085}
4086
4087static const struct net_device_ops macb_netdev_ops = {
4088 .ndo_open = macb_open,
4089 .ndo_stop = macb_close,
4090 .ndo_start_xmit = macb_start_xmit,
4091 .ndo_set_rx_mode = macb_set_rx_mode,
4092 .ndo_get_stats64 = macb_get_stats,
4093 .ndo_eth_ioctl = macb_ioctl,
4094 .ndo_validate_addr = eth_validate_addr,
4095 .ndo_change_mtu = macb_change_mtu,
4096 .ndo_set_mac_address = macb_set_mac_addr,
4097#ifdef CONFIG_NET_POLL_CONTROLLER
4098 .ndo_poll_controller = macb_poll_controller,
4099#endif
4100 .ndo_set_features = macb_set_features,
4101 .ndo_features_check = macb_features_check,
4102 .ndo_hwtstamp_set = macb_hwtstamp_set,
4103 .ndo_hwtstamp_get = macb_hwtstamp_get,
4104};
4105
4106/* Configure peripheral capabilities according to device tree
4107 * and integration options used
4108 */
4109static void macb_configure_caps(struct macb *bp,
4110 const struct macb_config *dt_conf)
4111{
4112 u32 dcfg;
4113
4114 if (dt_conf)
4115 bp->caps = dt_conf->caps;
4116
4117 if (hw_is_gem(addr: bp->regs, native_io: bp->native_io)) {
4118 bp->caps |= MACB_CAPS_MACB_IS_GEM;
4119
4120 dcfg = gem_readl(bp, DCFG1);
4121 if (GEM_BFEXT(IRQCOR, dcfg) == 0)
4122 bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
4123 if (GEM_BFEXT(NO_PCS, dcfg) == 0)
4124 bp->caps |= MACB_CAPS_PCS;
4125 dcfg = gem_readl(bp, DCFG12);
4126 if (GEM_BFEXT(HIGH_SPEED, dcfg) == 1)
4127 bp->caps |= MACB_CAPS_HIGH_SPEED;
4128 dcfg = gem_readl(bp, DCFG2);
4129 if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0)
4130 bp->caps |= MACB_CAPS_FIFO_MODE;
4131 if (gem_has_ptp(bp)) {
4132 if (!GEM_BFEXT(TSU, gem_readl(bp, DCFG5)))
4133 dev_err(&bp->pdev->dev,
4134 "GEM doesn't support hardware ptp.\n");
4135 else {
4136#ifdef CONFIG_MACB_USE_HWSTAMP
4137 bp->hw_dma_cap |= HW_DMA_CAP_PTP;
4138 bp->ptp_info = &gem_ptp_info;
4139#endif
4140 }
4141 }
4142 }
4143
4144 dev_dbg(&bp->pdev->dev, "Cadence caps 0x%08x\n", bp->caps);
4145}
4146
4147static void macb_probe_queues(void __iomem *mem,
4148 bool native_io,
4149 unsigned int *queue_mask,
4150 unsigned int *num_queues)
4151{
4152 *queue_mask = 0x1;
4153 *num_queues = 1;
4154
4155 /* is it macb or gem ?
4156 *
4157 * We need to read directly from the hardware here because
4158 * we are early in the probe process and don't have the
4159 * MACB_CAPS_MACB_IS_GEM flag positioned
4160 */
4161 if (!hw_is_gem(addr: mem, native_io))
4162 return;
4163
4164 /* bit 0 is never set but queue 0 always exists */
4165 *queue_mask |= readl_relaxed(mem + GEM_DCFG6) & 0xff;
4166 *num_queues = hweight32(*queue_mask);
4167}
4168
4169static void macb_clks_disable(struct clk *pclk, struct clk *hclk, struct clk *tx_clk,
4170 struct clk *rx_clk, struct clk *tsu_clk)
4171{
4172 struct clk_bulk_data clks[] = {
4173 { .clk = tsu_clk, },
4174 { .clk = rx_clk, },
4175 { .clk = pclk, },
4176 { .clk = hclk, },
4177 { .clk = tx_clk },
4178 };
4179
4180 clk_bulk_disable_unprepare(ARRAY_SIZE(clks), clks);
4181}
4182
4183static int macb_clk_init(struct platform_device *pdev, struct clk **pclk,
4184 struct clk **hclk, struct clk **tx_clk,
4185 struct clk **rx_clk, struct clk **tsu_clk)
4186{
4187 struct macb_platform_data *pdata;
4188 int err;
4189
4190 pdata = dev_get_platdata(dev: &pdev->dev);
4191 if (pdata) {
4192 *pclk = pdata->pclk;
4193 *hclk = pdata->hclk;
4194 } else {
4195 *pclk = devm_clk_get(dev: &pdev->dev, id: "pclk");
4196 *hclk = devm_clk_get(dev: &pdev->dev, id: "hclk");
4197 }
4198
4199 if (IS_ERR_OR_NULL(ptr: *pclk))
4200 return dev_err_probe(dev: &pdev->dev,
4201 err: IS_ERR(ptr: *pclk) ? PTR_ERR(ptr: *pclk) : -ENODEV,
4202 fmt: "failed to get pclk\n");
4203
4204 if (IS_ERR_OR_NULL(ptr: *hclk))
4205 return dev_err_probe(dev: &pdev->dev,
4206 err: IS_ERR(ptr: *hclk) ? PTR_ERR(ptr: *hclk) : -ENODEV,
4207 fmt: "failed to get hclk\n");
4208
4209 *tx_clk = devm_clk_get_optional(dev: &pdev->dev, id: "tx_clk");
4210 if (IS_ERR(ptr: *tx_clk))
4211 return PTR_ERR(ptr: *tx_clk);
4212
4213 *rx_clk = devm_clk_get_optional(dev: &pdev->dev, id: "rx_clk");
4214 if (IS_ERR(ptr: *rx_clk))
4215 return PTR_ERR(ptr: *rx_clk);
4216
4217 *tsu_clk = devm_clk_get_optional(dev: &pdev->dev, id: "tsu_clk");
4218 if (IS_ERR(ptr: *tsu_clk))
4219 return PTR_ERR(ptr: *tsu_clk);
4220
4221 err = clk_prepare_enable(clk: *pclk);
4222 if (err) {
4223 dev_err(&pdev->dev, "failed to enable pclk (%d)\n", err);
4224 return err;
4225 }
4226
4227 err = clk_prepare_enable(clk: *hclk);
4228 if (err) {
4229 dev_err(&pdev->dev, "failed to enable hclk (%d)\n", err);
4230 goto err_disable_pclk;
4231 }
4232
4233 err = clk_prepare_enable(clk: *tx_clk);
4234 if (err) {
4235 dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err);
4236 goto err_disable_hclk;
4237 }
4238
4239 err = clk_prepare_enable(clk: *rx_clk);
4240 if (err) {
4241 dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err);
4242 goto err_disable_txclk;
4243 }
4244
4245 err = clk_prepare_enable(clk: *tsu_clk);
4246 if (err) {
4247 dev_err(&pdev->dev, "failed to enable tsu_clk (%d)\n", err);
4248 goto err_disable_rxclk;
4249 }
4250
4251 return 0;
4252
4253err_disable_rxclk:
4254 clk_disable_unprepare(clk: *rx_clk);
4255
4256err_disable_txclk:
4257 clk_disable_unprepare(clk: *tx_clk);
4258
4259err_disable_hclk:
4260 clk_disable_unprepare(clk: *hclk);
4261
4262err_disable_pclk:
4263 clk_disable_unprepare(clk: *pclk);
4264
4265 return err;
4266}
4267
4268static int macb_init(struct platform_device *pdev)
4269{
4270 struct net_device *dev = platform_get_drvdata(pdev);
4271 unsigned int hw_q, q;
4272 struct macb *bp = netdev_priv(dev);
4273 struct macb_queue *queue;
4274 int err;
4275 u32 val, reg;
4276
4277 bp->tx_ring_size = DEFAULT_TX_RING_SIZE;
4278 bp->rx_ring_size = DEFAULT_RX_RING_SIZE;
4279
4280 /* set the queue register mapping once for all: queue0 has a special
4281 * register mapping but we don't want to test the queue index then
4282 * compute the corresponding register offset at run time.
4283 */
4284 for (hw_q = 0, q = 0; hw_q < MACB_MAX_QUEUES; ++hw_q) {
4285 if (!(bp->queue_mask & (1 << hw_q)))
4286 continue;
4287
4288 queue = &bp->queues[q];
4289 queue->bp = bp;
4290 spin_lock_init(&queue->tx_ptr_lock);
4291 netif_napi_add(dev, napi: &queue->napi_rx, poll: macb_rx_poll);
4292 netif_napi_add(dev, napi: &queue->napi_tx, poll: macb_tx_poll);
4293 if (hw_q) {
4294 queue->ISR = GEM_ISR(hw_q - 1);
4295 queue->IER = GEM_IER(hw_q - 1);
4296 queue->IDR = GEM_IDR(hw_q - 1);
4297 queue->IMR = GEM_IMR(hw_q - 1);
4298 queue->TBQP = GEM_TBQP(hw_q - 1);
4299 queue->RBQP = GEM_RBQP(hw_q - 1);
4300 queue->RBQS = GEM_RBQS(hw_q - 1);
4301#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
4302 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
4303 queue->TBQPH = GEM_TBQPH(hw_q - 1);
4304 queue->RBQPH = GEM_RBQPH(hw_q - 1);
4305 }
4306#endif
4307 } else {
4308 /* queue0 uses legacy registers */
4309 queue->ISR = MACB_ISR;
4310 queue->IER = MACB_IER;
4311 queue->IDR = MACB_IDR;
4312 queue->IMR = MACB_IMR;
4313 queue->TBQP = MACB_TBQP;
4314 queue->RBQP = MACB_RBQP;
4315#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
4316 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
4317 queue->TBQPH = MACB_TBQPH;
4318 queue->RBQPH = MACB_RBQPH;
4319 }
4320#endif
4321 }
4322
4323 /* get irq: here we use the linux queue index, not the hardware
4324 * queue index. the queue irq definitions in the device tree
4325 * must remove the optional gaps that could exist in the
4326 * hardware queue mask.
4327 */
4328 queue->irq = platform_get_irq(pdev, q);
4329 err = devm_request_irq(dev: &pdev->dev, irq: queue->irq, handler: macb_interrupt,
4330 IRQF_SHARED, devname: dev->name, dev_id: queue);
4331 if (err) {
4332 dev_err(&pdev->dev,
4333 "Unable to request IRQ %d (error %d)\n",
4334 queue->irq, err);
4335 return err;
4336 }
4337
4338 INIT_WORK(&queue->tx_error_task, macb_tx_error_task);
4339 q++;
4340 }
4341
4342 dev->netdev_ops = &macb_netdev_ops;
4343
4344 /* setup appropriated routines according to adapter type */
4345 if (macb_is_gem(bp)) {
4346 bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers;
4347 bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers;
4348 bp->macbgem_ops.mog_init_rings = gem_init_rings;
4349 bp->macbgem_ops.mog_rx = gem_rx;
4350 dev->ethtool_ops = &gem_ethtool_ops;
4351 } else {
4352 bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers;
4353 bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers;
4354 bp->macbgem_ops.mog_init_rings = macb_init_rings;
4355 bp->macbgem_ops.mog_rx = macb_rx;
4356 dev->ethtool_ops = &macb_ethtool_ops;
4357 }
4358
4359 netdev_sw_irq_coalesce_default_on(dev);
4360
4361 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
4362
4363 /* Set features */
4364 dev->hw_features = NETIF_F_SG;
4365
4366 /* Check LSO capability */
4367 if (GEM_BFEXT(PBUF_LSO, gem_readl(bp, DCFG6)))
4368 dev->hw_features |= MACB_NETIF_LSO;
4369
4370 /* Checksum offload is only available on gem with packet buffer */
4371 if (macb_is_gem(bp) && !(bp->caps & MACB_CAPS_FIFO_MODE))
4372 dev->hw_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
4373 if (bp->caps & MACB_CAPS_SG_DISABLED)
4374 dev->hw_features &= ~NETIF_F_SG;
4375 dev->features = dev->hw_features;
4376
4377 /* Check RX Flow Filters support.
4378 * Max Rx flows set by availability of screeners & compare regs:
4379 * each 4-tuple define requires 1 T2 screener reg + 3 compare regs
4380 */
4381 reg = gem_readl(bp, DCFG8);
4382 bp->max_tuples = min((GEM_BFEXT(SCR2CMP, reg) / 3),
4383 GEM_BFEXT(T2SCR, reg));
4384 INIT_LIST_HEAD(list: &bp->rx_fs_list.list);
4385 if (bp->max_tuples > 0) {
4386 /* also needs one ethtype match to check IPv4 */
4387 if (GEM_BFEXT(SCR2ETH, reg) > 0) {
4388 /* program this reg now */
4389 reg = 0;
4390 reg = GEM_BFINS(ETHTCMP, (uint16_t)ETH_P_IP, reg);
4391 gem_writel_n(bp, ETHT, SCRT2_ETHT, reg);
4392 /* Filtering is supported in hw but don't enable it in kernel now */
4393 dev->hw_features |= NETIF_F_NTUPLE;
4394 /* init Rx flow definitions */
4395 bp->rx_fs_list.count = 0;
4396 spin_lock_init(&bp->rx_fs_lock);
4397 } else
4398 bp->max_tuples = 0;
4399 }
4400
4401 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) {
4402 val = 0;
4403 if (phy_interface_mode_is_rgmii(mode: bp->phy_interface))
4404 val = bp->usrio->rgmii;
4405 else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII &&
4406 (bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
4407 val = bp->usrio->rmii;
4408 else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
4409 val = bp->usrio->mii;
4410
4411 if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN)
4412 val |= bp->usrio->refclk;
4413
4414 macb_or_gem_writel(bp, USRIO, val);
4415 }
4416
4417 /* Set MII management clock divider */
4418 val = macb_mdc_clk_div(bp);
4419 val |= macb_dbw(bp);
4420 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII)
4421 val |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
4422 macb_writel(bp, NCFGR, val);
4423
4424 return 0;
4425}
4426
4427static const struct macb_usrio_config macb_default_usrio = {
4428 .mii = MACB_BIT(MII),
4429 .rmii = MACB_BIT(RMII),
4430 .rgmii = GEM_BIT(RGMII),
4431 .refclk = MACB_BIT(CLKEN),
4432};
4433
4434#if defined(CONFIG_OF)
4435/* 1518 rounded up */
4436#define AT91ETHER_MAX_RBUFF_SZ 0x600
4437/* max number of receive buffers */
4438#define AT91ETHER_MAX_RX_DESCR 9
4439
4440static struct sifive_fu540_macb_mgmt *mgmt;
4441
4442static int at91ether_alloc_coherent(struct macb *lp)
4443{
4444 struct macb_queue *q = &lp->queues[0];
4445
4446 q->rx_ring = dma_alloc_coherent(dev: &lp->pdev->dev,
4447 size: (AT91ETHER_MAX_RX_DESCR *
4448 macb_dma_desc_get_size(bp: lp)),
4449 dma_handle: &q->rx_ring_dma, GFP_KERNEL);
4450 if (!q->rx_ring)
4451 return -ENOMEM;
4452
4453 q->rx_buffers = dma_alloc_coherent(dev: &lp->pdev->dev,
4454 AT91ETHER_MAX_RX_DESCR *
4455 AT91ETHER_MAX_RBUFF_SZ,
4456 dma_handle: &q->rx_buffers_dma, GFP_KERNEL);
4457 if (!q->rx_buffers) {
4458 dma_free_coherent(dev: &lp->pdev->dev,
4459 AT91ETHER_MAX_RX_DESCR *
4460 macb_dma_desc_get_size(bp: lp),
4461 cpu_addr: q->rx_ring, dma_handle: q->rx_ring_dma);
4462 q->rx_ring = NULL;
4463 return -ENOMEM;
4464 }
4465
4466 return 0;
4467}
4468
4469static void at91ether_free_coherent(struct macb *lp)
4470{
4471 struct macb_queue *q = &lp->queues[0];
4472
4473 if (q->rx_ring) {
4474 dma_free_coherent(dev: &lp->pdev->dev,
4475 AT91ETHER_MAX_RX_DESCR *
4476 macb_dma_desc_get_size(bp: lp),
4477 cpu_addr: q->rx_ring, dma_handle: q->rx_ring_dma);
4478 q->rx_ring = NULL;
4479 }
4480
4481 if (q->rx_buffers) {
4482 dma_free_coherent(dev: &lp->pdev->dev,
4483 AT91ETHER_MAX_RX_DESCR *
4484 AT91ETHER_MAX_RBUFF_SZ,
4485 cpu_addr: q->rx_buffers, dma_handle: q->rx_buffers_dma);
4486 q->rx_buffers = NULL;
4487 }
4488}
4489
4490/* Initialize and start the Receiver and Transmit subsystems */
4491static int at91ether_start(struct macb *lp)
4492{
4493 struct macb_queue *q = &lp->queues[0];
4494 struct macb_dma_desc *desc;
4495 dma_addr_t addr;
4496 u32 ctl;
4497 int i, ret;
4498
4499 ret = at91ether_alloc_coherent(lp);
4500 if (ret)
4501 return ret;
4502
4503 addr = q->rx_buffers_dma;
4504 for (i = 0; i < AT91ETHER_MAX_RX_DESCR; i++) {
4505 desc = macb_rx_desc(queue: q, index: i);
4506 macb_set_addr(bp: lp, desc, addr);
4507 desc->ctrl = 0;
4508 addr += AT91ETHER_MAX_RBUFF_SZ;
4509 }
4510
4511 /* Set the Wrap bit on the last descriptor */
4512 desc->addr |= MACB_BIT(RX_WRAP);
4513
4514 /* Reset buffer index */
4515 q->rx_tail = 0;
4516
4517 /* Program address of descriptor list in Rx Buffer Queue register */
4518 macb_writel(lp, RBQP, q->rx_ring_dma);
4519
4520 /* Enable Receive and Transmit */
4521 ctl = macb_readl(lp, NCR);
4522 macb_writel(lp, NCR, ctl | MACB_BIT(RE) | MACB_BIT(TE));
4523
4524 /* Enable MAC interrupts */
4525 macb_writel(lp, IER, MACB_BIT(RCOMP) |
4526 MACB_BIT(RXUBR) |
4527 MACB_BIT(ISR_TUND) |
4528 MACB_BIT(ISR_RLE) |
4529 MACB_BIT(TCOMP) |
4530 MACB_BIT(ISR_ROVR) |
4531 MACB_BIT(HRESP));
4532
4533 return 0;
4534}
4535
4536static void at91ether_stop(struct macb *lp)
4537{
4538 u32 ctl;
4539
4540 /* Disable MAC interrupts */
4541 macb_writel(lp, IDR, MACB_BIT(RCOMP) |
4542 MACB_BIT(RXUBR) |
4543 MACB_BIT(ISR_TUND) |
4544 MACB_BIT(ISR_RLE) |
4545 MACB_BIT(TCOMP) |
4546 MACB_BIT(ISR_ROVR) |
4547 MACB_BIT(HRESP));
4548
4549 /* Disable Receiver and Transmitter */
4550 ctl = macb_readl(lp, NCR);
4551 macb_writel(lp, NCR, ctl & ~(MACB_BIT(TE) | MACB_BIT(RE)));
4552
4553 /* Free resources. */
4554 at91ether_free_coherent(lp);
4555}
4556
4557/* Open the ethernet interface */
4558static int at91ether_open(struct net_device *dev)
4559{
4560 struct macb *lp = netdev_priv(dev);
4561 u32 ctl;
4562 int ret;
4563
4564 ret = pm_runtime_resume_and_get(dev: &lp->pdev->dev);
4565 if (ret < 0)
4566 return ret;
4567
4568 /* Clear internal statistics */
4569 ctl = macb_readl(lp, NCR);
4570 macb_writel(lp, NCR, ctl | MACB_BIT(CLRSTAT));
4571
4572 macb_set_hwaddr(bp: lp);
4573
4574 ret = at91ether_start(lp);
4575 if (ret)
4576 goto pm_exit;
4577
4578 ret = macb_phylink_connect(bp: lp);
4579 if (ret)
4580 goto stop;
4581
4582 netif_start_queue(dev);
4583
4584 return 0;
4585
4586stop:
4587 at91ether_stop(lp);
4588pm_exit:
4589 pm_runtime_put_sync(dev: &lp->pdev->dev);
4590 return ret;
4591}
4592
4593/* Close the interface */
4594static int at91ether_close(struct net_device *dev)
4595{
4596 struct macb *lp = netdev_priv(dev);
4597
4598 netif_stop_queue(dev);
4599
4600 phylink_stop(lp->phylink);
4601 phylink_disconnect_phy(lp->phylink);
4602
4603 at91ether_stop(lp);
4604
4605 return pm_runtime_put(dev: &lp->pdev->dev);
4606}
4607
4608/* Transmit packet */
4609static netdev_tx_t at91ether_start_xmit(struct sk_buff *skb,
4610 struct net_device *dev)
4611{
4612 struct macb *lp = netdev_priv(dev);
4613
4614 if (macb_readl(lp, TSR) & MACB_BIT(RM9200_BNQ)) {
4615 int desc = 0;
4616
4617 netif_stop_queue(dev);
4618
4619 /* Store packet information (to free when Tx completed) */
4620 lp->rm9200_txq[desc].skb = skb;
4621 lp->rm9200_txq[desc].size = skb->len;
4622 lp->rm9200_txq[desc].mapping = dma_map_single(&lp->pdev->dev, skb->data,
4623 skb->len, DMA_TO_DEVICE);
4624 if (dma_mapping_error(dev: &lp->pdev->dev, dma_addr: lp->rm9200_txq[desc].mapping)) {
4625 dev_kfree_skb_any(skb);
4626 dev->stats.tx_dropped++;
4627 netdev_err(dev, format: "%s: DMA mapping error\n", __func__);
4628 return NETDEV_TX_OK;
4629 }
4630
4631 /* Set address of the data in the Transmit Address register */
4632 macb_writel(lp, TAR, lp->rm9200_txq[desc].mapping);
4633 /* Set length of the packet in the Transmit Control register */
4634 macb_writel(lp, TCR, skb->len);
4635
4636 } else {
4637 netdev_err(dev, format: "%s called, but device is busy!\n", __func__);
4638 return NETDEV_TX_BUSY;
4639 }
4640
4641 return NETDEV_TX_OK;
4642}
4643
4644/* Extract received frame from buffer descriptors and sent to upper layers.
4645 * (Called from interrupt context)
4646 */
4647static void at91ether_rx(struct net_device *dev)
4648{
4649 struct macb *lp = netdev_priv(dev);
4650 struct macb_queue *q = &lp->queues[0];
4651 struct macb_dma_desc *desc;
4652 unsigned char *p_recv;
4653 struct sk_buff *skb;
4654 unsigned int pktlen;
4655
4656 desc = macb_rx_desc(queue: q, index: q->rx_tail);
4657 while (desc->addr & MACB_BIT(RX_USED)) {
4658 p_recv = q->rx_buffers + q->rx_tail * AT91ETHER_MAX_RBUFF_SZ;
4659 pktlen = MACB_BF(RX_FRMLEN, desc->ctrl);
4660 skb = netdev_alloc_skb(dev, length: pktlen + 2);
4661 if (skb) {
4662 skb_reserve(skb, len: 2);
4663 skb_put_data(skb, data: p_recv, len: pktlen);
4664
4665 skb->protocol = eth_type_trans(skb, dev);
4666 dev->stats.rx_packets++;
4667 dev->stats.rx_bytes += pktlen;
4668 netif_rx(skb);
4669 } else {
4670 dev->stats.rx_dropped++;
4671 }
4672
4673 if (desc->ctrl & MACB_BIT(RX_MHASH_MATCH))
4674 dev->stats.multicast++;
4675
4676 /* reset ownership bit */
4677 desc->addr &= ~MACB_BIT(RX_USED);
4678
4679 /* wrap after last buffer */
4680 if (q->rx_tail == AT91ETHER_MAX_RX_DESCR - 1)
4681 q->rx_tail = 0;
4682 else
4683 q->rx_tail++;
4684
4685 desc = macb_rx_desc(queue: q, index: q->rx_tail);
4686 }
4687}
4688
4689/* MAC interrupt handler */
4690static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
4691{
4692 struct net_device *dev = dev_id;
4693 struct macb *lp = netdev_priv(dev);
4694 u32 intstatus, ctl;
4695 unsigned int desc;
4696
4697 /* MAC Interrupt Status register indicates what interrupts are pending.
4698 * It is automatically cleared once read.
4699 */
4700 intstatus = macb_readl(lp, ISR);
4701
4702 /* Receive complete */
4703 if (intstatus & MACB_BIT(RCOMP))
4704 at91ether_rx(dev);
4705
4706 /* Transmit complete */
4707 if (intstatus & MACB_BIT(TCOMP)) {
4708 /* The TCOM bit is set even if the transmission failed */
4709 if (intstatus & (MACB_BIT(ISR_TUND) | MACB_BIT(ISR_RLE)))
4710 dev->stats.tx_errors++;
4711
4712 desc = 0;
4713 if (lp->rm9200_txq[desc].skb) {
4714 dev_consume_skb_irq(skb: lp->rm9200_txq[desc].skb);
4715 lp->rm9200_txq[desc].skb = NULL;
4716 dma_unmap_single(&lp->pdev->dev, lp->rm9200_txq[desc].mapping,
4717 lp->rm9200_txq[desc].size, DMA_TO_DEVICE);
4718 dev->stats.tx_packets++;
4719 dev->stats.tx_bytes += lp->rm9200_txq[desc].size;
4720 }
4721 netif_wake_queue(dev);
4722 }
4723
4724 /* Work-around for EMAC Errata section 41.3.1 */
4725 if (intstatus & MACB_BIT(RXUBR)) {
4726 ctl = macb_readl(lp, NCR);
4727 macb_writel(lp, NCR, ctl & ~MACB_BIT(RE));
4728 wmb();
4729 macb_writel(lp, NCR, ctl | MACB_BIT(RE));
4730 }
4731
4732 if (intstatus & MACB_BIT(ISR_ROVR))
4733 netdev_err(dev, format: "ROVR error\n");
4734
4735 return IRQ_HANDLED;
4736}
4737
4738#ifdef CONFIG_NET_POLL_CONTROLLER
4739static void at91ether_poll_controller(struct net_device *dev)
4740{
4741 unsigned long flags;
4742
4743 local_irq_save(flags);
4744 at91ether_interrupt(irq: dev->irq, dev_id: dev);
4745 local_irq_restore(flags);
4746}
4747#endif
4748
4749static const struct net_device_ops at91ether_netdev_ops = {
4750 .ndo_open = at91ether_open,
4751 .ndo_stop = at91ether_close,
4752 .ndo_start_xmit = at91ether_start_xmit,
4753 .ndo_get_stats64 = macb_get_stats,
4754 .ndo_set_rx_mode = macb_set_rx_mode,
4755 .ndo_set_mac_address = eth_mac_addr,
4756 .ndo_eth_ioctl = macb_ioctl,
4757 .ndo_validate_addr = eth_validate_addr,
4758#ifdef CONFIG_NET_POLL_CONTROLLER
4759 .ndo_poll_controller = at91ether_poll_controller,
4760#endif
4761 .ndo_hwtstamp_set = macb_hwtstamp_set,
4762 .ndo_hwtstamp_get = macb_hwtstamp_get,
4763};
4764
4765static int at91ether_clk_init(struct platform_device *pdev, struct clk **pclk,
4766 struct clk **hclk, struct clk **tx_clk,
4767 struct clk **rx_clk, struct clk **tsu_clk)
4768{
4769 int err;
4770
4771 *hclk = NULL;
4772 *tx_clk = NULL;
4773 *rx_clk = NULL;
4774 *tsu_clk = NULL;
4775
4776 *pclk = devm_clk_get(dev: &pdev->dev, id: "ether_clk");
4777 if (IS_ERR(ptr: *pclk))
4778 return PTR_ERR(ptr: *pclk);
4779
4780 err = clk_prepare_enable(clk: *pclk);
4781 if (err) {
4782 dev_err(&pdev->dev, "failed to enable pclk (%d)\n", err);
4783 return err;
4784 }
4785
4786 return 0;
4787}
4788
4789static int at91ether_init(struct platform_device *pdev)
4790{
4791 struct net_device *dev = platform_get_drvdata(pdev);
4792 struct macb *bp = netdev_priv(dev);
4793 int err;
4794
4795 bp->queues[0].bp = bp;
4796
4797 dev->netdev_ops = &at91ether_netdev_ops;
4798 dev->ethtool_ops = &macb_ethtool_ops;
4799
4800 err = devm_request_irq(dev: &pdev->dev, irq: dev->irq, handler: at91ether_interrupt,
4801 irqflags: 0, devname: dev->name, dev_id: dev);
4802 if (err)
4803 return err;
4804
4805 macb_writel(bp, NCR, 0);
4806
4807 macb_writel(bp, NCFGR, MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG));
4808
4809 return 0;
4810}
4811
4812static unsigned long fu540_macb_tx_recalc_rate(struct clk_hw *hw,
4813 unsigned long parent_rate)
4814{
4815 return mgmt->rate;
4816}
4817
4818static long fu540_macb_tx_round_rate(struct clk_hw *hw, unsigned long rate,
4819 unsigned long *parent_rate)
4820{
4821 if (WARN_ON(rate < 2500000))
4822 return 2500000;
4823 else if (rate == 2500000)
4824 return 2500000;
4825 else if (WARN_ON(rate < 13750000))
4826 return 2500000;
4827 else if (WARN_ON(rate < 25000000))
4828 return 25000000;
4829 else if (rate == 25000000)
4830 return 25000000;
4831 else if (WARN_ON(rate < 75000000))
4832 return 25000000;
4833 else if (WARN_ON(rate < 125000000))
4834 return 125000000;
4835 else if (rate == 125000000)
4836 return 125000000;
4837
4838 WARN_ON(rate > 125000000);
4839
4840 return 125000000;
4841}
4842
4843static int fu540_macb_tx_set_rate(struct clk_hw *hw, unsigned long rate,
4844 unsigned long parent_rate)
4845{
4846 rate = fu540_macb_tx_round_rate(hw, rate, parent_rate: &parent_rate);
4847 if (rate != 125000000)
4848 iowrite32(1, mgmt->reg);
4849 else
4850 iowrite32(0, mgmt->reg);
4851 mgmt->rate = rate;
4852
4853 return 0;
4854}
4855
4856static const struct clk_ops fu540_c000_ops = {
4857 .recalc_rate = fu540_macb_tx_recalc_rate,
4858 .round_rate = fu540_macb_tx_round_rate,
4859 .set_rate = fu540_macb_tx_set_rate,
4860};
4861
4862static int fu540_c000_clk_init(struct platform_device *pdev, struct clk **pclk,
4863 struct clk **hclk, struct clk **tx_clk,
4864 struct clk **rx_clk, struct clk **tsu_clk)
4865{
4866 struct clk_init_data init;
4867 int err = 0;
4868
4869 err = macb_clk_init(pdev, pclk, hclk, tx_clk, rx_clk, tsu_clk);
4870 if (err)
4871 return err;
4872
4873 mgmt = devm_kzalloc(dev: &pdev->dev, size: sizeof(*mgmt), GFP_KERNEL);
4874 if (!mgmt) {
4875 err = -ENOMEM;
4876 goto err_disable_clks;
4877 }
4878
4879 init.name = "sifive-gemgxl-mgmt";
4880 init.ops = &fu540_c000_ops;
4881 init.flags = 0;
4882 init.num_parents = 0;
4883
4884 mgmt->rate = 0;
4885 mgmt->hw.init = &init;
4886
4887 *tx_clk = devm_clk_register(dev: &pdev->dev, hw: &mgmt->hw);
4888 if (IS_ERR(ptr: *tx_clk)) {
4889 err = PTR_ERR(ptr: *tx_clk);
4890 goto err_disable_clks;
4891 }
4892
4893 err = clk_prepare_enable(clk: *tx_clk);
4894 if (err) {
4895 dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n", err);
4896 *tx_clk = NULL;
4897 goto err_disable_clks;
4898 } else {
4899 dev_info(&pdev->dev, "Registered clk switch '%s'\n", init.name);
4900 }
4901
4902 return 0;
4903
4904err_disable_clks:
4905 macb_clks_disable(pclk: *pclk, hclk: *hclk, tx_clk: *tx_clk, rx_clk: *rx_clk, tsu_clk: *tsu_clk);
4906
4907 return err;
4908}
4909
4910static int fu540_c000_init(struct platform_device *pdev)
4911{
4912 mgmt->reg = devm_platform_ioremap_resource(pdev, index: 1);
4913 if (IS_ERR(ptr: mgmt->reg))
4914 return PTR_ERR(ptr: mgmt->reg);
4915
4916 return macb_init(pdev);
4917}
4918
4919static int init_reset_optional(struct platform_device *pdev)
4920{
4921 struct net_device *dev = platform_get_drvdata(pdev);
4922 struct macb *bp = netdev_priv(dev);
4923 int ret;
4924
4925 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII) {
4926 /* Ensure PHY device used in SGMII mode is ready */
4927 bp->sgmii_phy = devm_phy_optional_get(dev: &pdev->dev, NULL);
4928
4929 if (IS_ERR(ptr: bp->sgmii_phy))
4930 return dev_err_probe(dev: &pdev->dev, err: PTR_ERR(ptr: bp->sgmii_phy),
4931 fmt: "failed to get SGMII PHY\n");
4932
4933 ret = phy_init(phy: bp->sgmii_phy);
4934 if (ret)
4935 return dev_err_probe(dev: &pdev->dev, err: ret,
4936 fmt: "failed to init SGMII PHY\n");
4937
4938 ret = zynqmp_pm_is_function_supported(api_id: PM_IOCTL, id: IOCTL_SET_GEM_CONFIG);
4939 if (!ret) {
4940 u32 pm_info[2];
4941
4942 ret = of_property_read_u32_array(np: pdev->dev.of_node, propname: "power-domains",
4943 out_values: pm_info, ARRAY_SIZE(pm_info));
4944 if (ret) {
4945 dev_err(&pdev->dev, "Failed to read power management information\n");
4946 goto err_out_phy_exit;
4947 }
4948 ret = zynqmp_pm_set_gem_config(node: pm_info[1], config: GEM_CONFIG_FIXED, value: 0);
4949 if (ret)
4950 goto err_out_phy_exit;
4951
4952 ret = zynqmp_pm_set_gem_config(node: pm_info[1], config: GEM_CONFIG_SGMII_MODE, value: 1);
4953 if (ret)
4954 goto err_out_phy_exit;
4955 }
4956
4957 }
4958
4959 /* Fully reset controller at hardware level if mapped in device tree */
4960 ret = device_reset_optional(dev: &pdev->dev);
4961 if (ret) {
4962 phy_exit(phy: bp->sgmii_phy);
4963 return dev_err_probe(dev: &pdev->dev, err: ret, fmt: "failed to reset controller");
4964 }
4965
4966 ret = macb_init(pdev);
4967
4968err_out_phy_exit:
4969 if (ret)
4970 phy_exit(phy: bp->sgmii_phy);
4971
4972 return ret;
4973}
4974
4975static const struct macb_usrio_config sama7g5_usrio = {
4976 .mii = 0,
4977 .rmii = 1,
4978 .rgmii = 2,
4979 .refclk = BIT(2),
4980 .hdfctlen = BIT(6),
4981};
4982
4983static const struct macb_config fu540_c000_config = {
4984 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO |
4985 MACB_CAPS_GEM_HAS_PTP,
4986 .dma_burst_length = 16,
4987 .clk_init = fu540_c000_clk_init,
4988 .init = fu540_c000_init,
4989 .jumbo_max_len = 10240,
4990 .usrio = &macb_default_usrio,
4991};
4992
4993static const struct macb_config at91sam9260_config = {
4994 .caps = MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4995 .clk_init = macb_clk_init,
4996 .init = macb_init,
4997 .usrio = &macb_default_usrio,
4998};
4999
5000static const struct macb_config sama5d3macb_config = {
5001 .caps = MACB_CAPS_SG_DISABLED |
5002 MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
5003 .clk_init = macb_clk_init,
5004 .init = macb_init,
5005 .usrio = &macb_default_usrio,
5006};
5007
5008static const struct macb_config pc302gem_config = {
5009 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
5010 .dma_burst_length = 16,
5011 .clk_init = macb_clk_init,
5012 .init = macb_init,
5013 .usrio = &macb_default_usrio,
5014};
5015
5016static const struct macb_config sama5d2_config = {
5017 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | MACB_CAPS_JUMBO,
5018 .dma_burst_length = 16,
5019 .clk_init = macb_clk_init,
5020 .init = macb_init,
5021 .jumbo_max_len = 10240,
5022 .usrio = &macb_default_usrio,
5023};
5024
5025static const struct macb_config sama5d29_config = {
5026 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | MACB_CAPS_GEM_HAS_PTP,
5027 .dma_burst_length = 16,
5028 .clk_init = macb_clk_init,
5029 .init = macb_init,
5030 .usrio = &macb_default_usrio,
5031};
5032
5033static const struct macb_config sama5d3_config = {
5034 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE |
5035 MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | MACB_CAPS_JUMBO,
5036 .dma_burst_length = 16,
5037 .clk_init = macb_clk_init,
5038 .init = macb_init,
5039 .jumbo_max_len = 10240,
5040 .usrio = &macb_default_usrio,
5041};
5042
5043static const struct macb_config sama5d4_config = {
5044 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
5045 .dma_burst_length = 4,
5046 .clk_init = macb_clk_init,
5047 .init = macb_init,
5048 .usrio = &macb_default_usrio,
5049};
5050
5051static const struct macb_config emac_config = {
5052 .caps = MACB_CAPS_NEEDS_RSTONUBR | MACB_CAPS_MACB_IS_EMAC,
5053 .clk_init = at91ether_clk_init,
5054 .init = at91ether_init,
5055 .usrio = &macb_default_usrio,
5056};
5057
5058static const struct macb_config np4_config = {
5059 .caps = MACB_CAPS_USRIO_DISABLED,
5060 .clk_init = macb_clk_init,
5061 .init = macb_init,
5062 .usrio = &macb_default_usrio,
5063};
5064
5065static const struct macb_config zynqmp_config = {
5066 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
5067 MACB_CAPS_JUMBO |
5068 MACB_CAPS_GEM_HAS_PTP | MACB_CAPS_BD_RD_PREFETCH,
5069 .dma_burst_length = 16,
5070 .clk_init = macb_clk_init,
5071 .init = init_reset_optional,
5072 .jumbo_max_len = 10240,
5073 .usrio = &macb_default_usrio,
5074};
5075
5076static const struct macb_config zynq_config = {
5077 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_NO_GIGABIT_HALF |
5078 MACB_CAPS_NEEDS_RSTONUBR,
5079 .dma_burst_length = 16,
5080 .clk_init = macb_clk_init,
5081 .init = macb_init,
5082 .usrio = &macb_default_usrio,
5083};
5084
5085static const struct macb_config mpfs_config = {
5086 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
5087 MACB_CAPS_JUMBO |
5088 MACB_CAPS_GEM_HAS_PTP,
5089 .dma_burst_length = 16,
5090 .clk_init = macb_clk_init,
5091 .init = init_reset_optional,
5092 .usrio = &macb_default_usrio,
5093 .max_tx_length = 4040, /* Cadence Erratum 1686 */
5094 .jumbo_max_len = 4040,
5095};
5096
5097static const struct macb_config sama7g5_gem_config = {
5098 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_CLK_HW_CHG |
5099 MACB_CAPS_MIIONRGMII | MACB_CAPS_GEM_HAS_PTP,
5100 .dma_burst_length = 16,
5101 .clk_init = macb_clk_init,
5102 .init = macb_init,
5103 .usrio = &sama7g5_usrio,
5104};
5105
5106static const struct macb_config sama7g5_emac_config = {
5107 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII |
5108 MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_MIIONRGMII |
5109 MACB_CAPS_GEM_HAS_PTP,
5110 .dma_burst_length = 16,
5111 .clk_init = macb_clk_init,
5112 .init = macb_init,
5113 .usrio = &sama7g5_usrio,
5114};
5115
5116static const struct macb_config versal_config = {
5117 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO |
5118 MACB_CAPS_GEM_HAS_PTP | MACB_CAPS_BD_RD_PREFETCH | MACB_CAPS_NEED_TSUCLK |
5119 MACB_CAPS_QUEUE_DISABLE,
5120 .dma_burst_length = 16,
5121 .clk_init = macb_clk_init,
5122 .init = init_reset_optional,
5123 .jumbo_max_len = 10240,
5124 .usrio = &macb_default_usrio,
5125};
5126
5127static const struct of_device_id macb_dt_ids[] = {
5128 { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config },
5129 { .compatible = "cdns,macb" },
5130 { .compatible = "cdns,np4-macb", .data = &np4_config },
5131 { .compatible = "cdns,pc302-gem", .data = &pc302gem_config },
5132 { .compatible = "cdns,gem", .data = &pc302gem_config },
5133 { .compatible = "cdns,sam9x60-macb", .data = &at91sam9260_config },
5134 { .compatible = "atmel,sama5d2-gem", .data = &sama5d2_config },
5135 { .compatible = "atmel,sama5d29-gem", .data = &sama5d29_config },
5136 { .compatible = "atmel,sama5d3-gem", .data = &sama5d3_config },
5137 { .compatible = "atmel,sama5d3-macb", .data = &sama5d3macb_config },
5138 { .compatible = "atmel,sama5d4-gem", .data = &sama5d4_config },
5139 { .compatible = "cdns,at91rm9200-emac", .data = &emac_config },
5140 { .compatible = "cdns,emac", .data = &emac_config },
5141 { .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config}, /* deprecated */
5142 { .compatible = "cdns,zynq-gem", .data = &zynq_config }, /* deprecated */
5143 { .compatible = "sifive,fu540-c000-gem", .data = &fu540_c000_config },
5144 { .compatible = "microchip,mpfs-macb", .data = &mpfs_config },
5145 { .compatible = "microchip,sama7g5-gem", .data = &sama7g5_gem_config },
5146 { .compatible = "microchip,sama7g5-emac", .data = &sama7g5_emac_config },
5147 { .compatible = "xlnx,zynqmp-gem", .data = &zynqmp_config},
5148 { .compatible = "xlnx,zynq-gem", .data = &zynq_config },
5149 { .compatible = "xlnx,versal-gem", .data = &versal_config},
5150 { /* sentinel */ }
5151};
5152MODULE_DEVICE_TABLE(of, macb_dt_ids);
5153#endif /* CONFIG_OF */
5154
5155static const struct macb_config default_gem_config = {
5156 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
5157 MACB_CAPS_JUMBO |
5158 MACB_CAPS_GEM_HAS_PTP,
5159 .dma_burst_length = 16,
5160 .clk_init = macb_clk_init,
5161 .init = macb_init,
5162 .usrio = &macb_default_usrio,
5163 .jumbo_max_len = 10240,
5164};
5165
5166static int macb_probe(struct platform_device *pdev)
5167{
5168 const struct macb_config *macb_config = &default_gem_config;
5169 int (*clk_init)(struct platform_device *, struct clk **,
5170 struct clk **, struct clk **, struct clk **,
5171 struct clk **) = macb_config->clk_init;
5172 int (*init)(struct platform_device *) = macb_config->init;
5173 struct device_node *np = pdev->dev.of_node;
5174 struct clk *pclk, *hclk = NULL, *tx_clk = NULL, *rx_clk = NULL;
5175 struct clk *tsu_clk = NULL;
5176 unsigned int queue_mask, num_queues;
5177 bool native_io;
5178 phy_interface_t interface;
5179 struct net_device *dev;
5180 struct resource *regs;
5181 u32 wtrmrk_rst_val;
5182 void __iomem *mem;
5183 struct macb *bp;
5184 int err, val;
5185
5186 mem = devm_platform_get_and_ioremap_resource(pdev, index: 0, res: &regs);
5187 if (IS_ERR(ptr: mem))
5188 return PTR_ERR(ptr: mem);
5189
5190 if (np) {
5191 const struct of_device_id *match;
5192
5193 match = of_match_node(matches: macb_dt_ids, node: np);
5194 if (match && match->data) {
5195 macb_config = match->data;
5196 clk_init = macb_config->clk_init;
5197 init = macb_config->init;
5198 }
5199 }
5200
5201 err = clk_init(pdev, &pclk, &hclk, &tx_clk, &rx_clk, &tsu_clk);
5202 if (err)
5203 return err;
5204
5205 pm_runtime_set_autosuspend_delay(dev: &pdev->dev, MACB_PM_TIMEOUT);
5206 pm_runtime_use_autosuspend(dev: &pdev->dev);
5207 pm_runtime_get_noresume(dev: &pdev->dev);
5208 pm_runtime_set_active(dev: &pdev->dev);
5209 pm_runtime_enable(dev: &pdev->dev);
5210 native_io = hw_is_native_io(addr: mem);
5211
5212 macb_probe_queues(mem, native_io, queue_mask: &queue_mask, num_queues: &num_queues);
5213 dev = alloc_etherdev_mq(sizeof(*bp), num_queues);
5214 if (!dev) {
5215 err = -ENOMEM;
5216 goto err_disable_clocks;
5217 }
5218
5219 dev->base_addr = regs->start;
5220
5221 SET_NETDEV_DEV(dev, &pdev->dev);
5222
5223 bp = netdev_priv(dev);
5224 bp->pdev = pdev;
5225 bp->dev = dev;
5226 bp->regs = mem;
5227 bp->native_io = native_io;
5228 if (native_io) {
5229 bp->macb_reg_readl = hw_readl_native;
5230 bp->macb_reg_writel = hw_writel_native;
5231 } else {
5232 bp->macb_reg_readl = hw_readl;
5233 bp->macb_reg_writel = hw_writel;
5234 }
5235 bp->num_queues = num_queues;
5236 bp->queue_mask = queue_mask;
5237 if (macb_config)
5238 bp->dma_burst_length = macb_config->dma_burst_length;
5239 bp->pclk = pclk;
5240 bp->hclk = hclk;
5241 bp->tx_clk = tx_clk;
5242 bp->rx_clk = rx_clk;
5243 bp->tsu_clk = tsu_clk;
5244 if (macb_config)
5245 bp->jumbo_max_len = macb_config->jumbo_max_len;
5246
5247 if (!hw_is_gem(addr: bp->regs, native_io: bp->native_io))
5248 bp->max_tx_length = MACB_MAX_TX_LEN;
5249 else if (macb_config->max_tx_length)
5250 bp->max_tx_length = macb_config->max_tx_length;
5251 else
5252 bp->max_tx_length = GEM_MAX_TX_LEN;
5253
5254 bp->wol = 0;
5255 device_set_wakeup_capable(dev: &pdev->dev, capable: 1);
5256
5257 bp->usrio = macb_config->usrio;
5258
5259 /* By default we set to partial store and forward mode for zynqmp.
5260 * Disable if not set in devicetree.
5261 */
5262 if (GEM_BFEXT(PBUF_CUTTHRU, gem_readl(bp, DCFG6))) {
5263 err = of_property_read_u32(np: bp->pdev->dev.of_node,
5264 propname: "cdns,rx-watermark",
5265 out_value: &bp->rx_watermark);
5266
5267 if (!err) {
5268 /* Disable partial store and forward in case of error or
5269 * invalid watermark value
5270 */
5271 wtrmrk_rst_val = (1 << (GEM_BFEXT(RX_PBUF_ADDR, gem_readl(bp, DCFG2)))) - 1;
5272 if (bp->rx_watermark > wtrmrk_rst_val || !bp->rx_watermark) {
5273 dev_info(&bp->pdev->dev, "Invalid watermark value\n");
5274 bp->rx_watermark = 0;
5275 }
5276 }
5277 }
5278 spin_lock_init(&bp->lock);
5279 spin_lock_init(&bp->stats_lock);
5280
5281 /* setup capabilities */
5282 macb_configure_caps(bp, dt_conf: macb_config);
5283
5284#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
5285 if (GEM_BFEXT(DAW64, gem_readl(bp, DCFG6))) {
5286 err = dma_set_mask_and_coherent(dev: &pdev->dev, DMA_BIT_MASK(44));
5287 if (err) {
5288 dev_err(&pdev->dev, "failed to set DMA mask\n");
5289 goto err_out_free_netdev;
5290 }
5291 bp->hw_dma_cap |= HW_DMA_CAP_64B;
5292 }
5293#endif
5294 platform_set_drvdata(pdev, data: dev);
5295
5296 dev->irq = platform_get_irq(pdev, 0);
5297 if (dev->irq < 0) {
5298 err = dev->irq;
5299 goto err_out_free_netdev;
5300 }
5301
5302 /* MTU range: 68 - 1518 or 10240 */
5303 dev->min_mtu = GEM_MTU_MIN_SIZE;
5304 if ((bp->caps & MACB_CAPS_JUMBO) && bp->jumbo_max_len)
5305 dev->max_mtu = bp->jumbo_max_len - ETH_HLEN - ETH_FCS_LEN;
5306 else
5307 dev->max_mtu = 1536 - ETH_HLEN - ETH_FCS_LEN;
5308
5309 if (bp->caps & MACB_CAPS_BD_RD_PREFETCH) {
5310 val = GEM_BFEXT(RXBD_RDBUFF, gem_readl(bp, DCFG10));
5311 if (val)
5312 bp->rx_bd_rd_prefetch = (2 << (val - 1)) *
5313 macb_dma_desc_get_size(bp);
5314
5315 val = GEM_BFEXT(TXBD_RDBUFF, gem_readl(bp, DCFG10));
5316 if (val)
5317 bp->tx_bd_rd_prefetch = (2 << (val - 1)) *
5318 macb_dma_desc_get_size(bp);
5319 }
5320
5321 bp->rx_intr_mask = MACB_RX_INT_FLAGS;
5322 if (bp->caps & MACB_CAPS_NEEDS_RSTONUBR)
5323 bp->rx_intr_mask |= MACB_BIT(RXUBR);
5324
5325 err = of_get_ethdev_address(np, dev: bp->dev);
5326 if (err == -EPROBE_DEFER)
5327 goto err_out_free_netdev;
5328 else if (err)
5329 macb_get_hwaddr(bp);
5330
5331 err = of_get_phy_mode(np, interface: &interface);
5332 if (err)
5333 /* not found in DT, MII by default */
5334 bp->phy_interface = PHY_INTERFACE_MODE_MII;
5335 else
5336 bp->phy_interface = interface;
5337
5338 /* IP specific init */
5339 err = init(pdev);
5340 if (err)
5341 goto err_out_free_netdev;
5342
5343 err = macb_mii_init(bp);
5344 if (err)
5345 goto err_out_phy_exit;
5346
5347 netif_carrier_off(dev);
5348
5349 err = register_netdev(dev);
5350 if (err) {
5351 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
5352 goto err_out_unregister_mdio;
5353 }
5354
5355 INIT_WORK(&bp->hresp_err_bh_work, macb_hresp_error_task);
5356
5357 netdev_info(dev, format: "Cadence %s rev 0x%08x at 0x%08lx irq %d (%pM)\n",
5358 macb_is_gem(bp) ? "GEM" : "MACB", macb_readl(bp, MID),
5359 dev->base_addr, dev->irq, dev->dev_addr);
5360
5361 pm_runtime_mark_last_busy(dev: &bp->pdev->dev);
5362 pm_runtime_put_autosuspend(dev: &bp->pdev->dev);
5363
5364 return 0;
5365
5366err_out_unregister_mdio:
5367 mdiobus_unregister(bus: bp->mii_bus);
5368 mdiobus_free(bus: bp->mii_bus);
5369
5370err_out_phy_exit:
5371 phy_exit(phy: bp->sgmii_phy);
5372
5373err_out_free_netdev:
5374 free_netdev(dev);
5375
5376err_disable_clocks:
5377 macb_clks_disable(pclk, hclk, tx_clk, rx_clk, tsu_clk);
5378 pm_runtime_disable(dev: &pdev->dev);
5379 pm_runtime_set_suspended(dev: &pdev->dev);
5380 pm_runtime_dont_use_autosuspend(dev: &pdev->dev);
5381
5382 return err;
5383}
5384
5385static void macb_remove(struct platform_device *pdev)
5386{
5387 struct net_device *dev;
5388 struct macb *bp;
5389
5390 dev = platform_get_drvdata(pdev);
5391
5392 if (dev) {
5393 bp = netdev_priv(dev);
5394 phy_exit(phy: bp->sgmii_phy);
5395 mdiobus_unregister(bus: bp->mii_bus);
5396 mdiobus_free(bus: bp->mii_bus);
5397
5398 unregister_netdev(dev);
5399 cancel_work_sync(work: &bp->hresp_err_bh_work);
5400 pm_runtime_disable(dev: &pdev->dev);
5401 pm_runtime_dont_use_autosuspend(dev: &pdev->dev);
5402 if (!pm_runtime_suspended(dev: &pdev->dev)) {
5403 macb_clks_disable(pclk: bp->pclk, hclk: bp->hclk, tx_clk: bp->tx_clk,
5404 rx_clk: bp->rx_clk, tsu_clk: bp->tsu_clk);
5405 pm_runtime_set_suspended(dev: &pdev->dev);
5406 }
5407 phylink_destroy(bp->phylink);
5408 free_netdev(dev);
5409 }
5410}
5411
5412static int __maybe_unused macb_suspend(struct device *dev)
5413{
5414 struct net_device *netdev = dev_get_drvdata(dev);
5415 struct macb *bp = netdev_priv(dev: netdev);
5416 struct in_ifaddr *ifa = NULL;
5417 struct macb_queue *queue;
5418 struct in_device *idev;
5419 unsigned long flags;
5420 unsigned int q;
5421 int err;
5422 u32 tmp;
5423
5424 if (!device_may_wakeup(dev: &bp->dev->dev))
5425 phy_exit(phy: bp->sgmii_phy);
5426
5427 if (!netif_running(dev: netdev))
5428 return 0;
5429
5430 if (bp->wol & MACB_WOL_ENABLED) {
5431 /* Check for IP address in WOL ARP mode */
5432 idev = __in_dev_get_rcu(dev: bp->dev);
5433 if (idev)
5434 ifa = rcu_dereference(idev->ifa_list);
5435 if ((bp->wolopts & WAKE_ARP) && !ifa) {
5436 netdev_err(dev: netdev, format: "IP address not assigned as required by WoL walk ARP\n");
5437 return -EOPNOTSUPP;
5438 }
5439 spin_lock_irqsave(&bp->lock, flags);
5440
5441 /* Disable Tx and Rx engines before disabling the queues,
5442 * this is mandatory as per the IP spec sheet
5443 */
5444 tmp = macb_readl(bp, NCR);
5445 macb_writel(bp, NCR, tmp & ~(MACB_BIT(TE) | MACB_BIT(RE)));
5446 for (q = 0, queue = bp->queues; q < bp->num_queues;
5447 ++q, ++queue) {
5448 /* Disable RX queues */
5449 if (bp->caps & MACB_CAPS_QUEUE_DISABLE) {
5450 queue_writel(queue, RBQP, MACB_BIT(QUEUE_DISABLE));
5451 } else {
5452 /* Tie off RX queues */
5453 queue_writel(queue, RBQP,
5454 lower_32_bits(bp->rx_ring_tieoff_dma));
5455#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
5456 queue_writel(queue, RBQPH,
5457 upper_32_bits(bp->rx_ring_tieoff_dma));
5458#endif
5459 }
5460 /* Disable all interrupts */
5461 queue_writel(queue, IDR, -1);
5462 queue_readl(queue, ISR);
5463 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
5464 queue_writel(queue, ISR, -1);
5465 }
5466 /* Enable Receive engine */
5467 macb_writel(bp, NCR, tmp | MACB_BIT(RE));
5468 /* Flush all status bits */
5469 macb_writel(bp, TSR, -1);
5470 macb_writel(bp, RSR, -1);
5471
5472 tmp = (bp->wolopts & WAKE_MAGIC) ? MACB_BIT(MAG) : 0;
5473 if (bp->wolopts & WAKE_ARP) {
5474 tmp |= MACB_BIT(ARP);
5475 /* write IP address into register */
5476 tmp |= MACB_BFEXT(IP, be32_to_cpu(ifa->ifa_local));
5477 }
5478
5479 /* Change interrupt handler and
5480 * Enable WoL IRQ on queue 0
5481 */
5482 devm_free_irq(dev, irq: bp->queues[0].irq, dev_id: bp->queues);
5483 if (macb_is_gem(bp)) {
5484 err = devm_request_irq(dev, irq: bp->queues[0].irq, handler: gem_wol_interrupt,
5485 IRQF_SHARED, devname: netdev->name, dev_id: bp->queues);
5486 if (err) {
5487 dev_err(dev,
5488 "Unable to request IRQ %d (error %d)\n",
5489 bp->queues[0].irq, err);
5490 spin_unlock_irqrestore(lock: &bp->lock, flags);
5491 return err;
5492 }
5493 queue_writel(bp->queues, IER, GEM_BIT(WOL));
5494 gem_writel(bp, WOL, tmp);
5495 } else {
5496 err = devm_request_irq(dev, irq: bp->queues[0].irq, handler: macb_wol_interrupt,
5497 IRQF_SHARED, devname: netdev->name, dev_id: bp->queues);
5498 if (err) {
5499 dev_err(dev,
5500 "Unable to request IRQ %d (error %d)\n",
5501 bp->queues[0].irq, err);
5502 spin_unlock_irqrestore(lock: &bp->lock, flags);
5503 return err;
5504 }
5505 queue_writel(bp->queues, IER, MACB_BIT(WOL));
5506 macb_writel(bp, WOL, tmp);
5507 }
5508 spin_unlock_irqrestore(lock: &bp->lock, flags);
5509
5510 enable_irq_wake(irq: bp->queues[0].irq);
5511 }
5512
5513 netif_device_detach(dev: netdev);
5514 for (q = 0, queue = bp->queues; q < bp->num_queues;
5515 ++q, ++queue) {
5516 napi_disable(n: &queue->napi_rx);
5517 napi_disable(n: &queue->napi_tx);
5518 }
5519
5520 if (!(bp->wol & MACB_WOL_ENABLED)) {
5521 rtnl_lock();
5522 phylink_stop(bp->phylink);
5523 rtnl_unlock();
5524 spin_lock_irqsave(&bp->lock, flags);
5525 macb_reset_hw(bp);
5526 spin_unlock_irqrestore(lock: &bp->lock, flags);
5527 }
5528
5529 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
5530 bp->pm_data.usrio = macb_or_gem_readl(bp, USRIO);
5531
5532 if (netdev->hw_features & NETIF_F_NTUPLE)
5533 bp->pm_data.scrt2 = gem_readl_n(bp, ETHT, SCRT2_ETHT);
5534
5535 if (bp->ptp_info)
5536 bp->ptp_info->ptp_remove(netdev);
5537 if (!device_may_wakeup(dev))
5538 pm_runtime_force_suspend(dev);
5539
5540 return 0;
5541}
5542
5543static int __maybe_unused macb_resume(struct device *dev)
5544{
5545 struct net_device *netdev = dev_get_drvdata(dev);
5546 struct macb *bp = netdev_priv(dev: netdev);
5547 struct macb_queue *queue;
5548 unsigned long flags;
5549 unsigned int q;
5550 int err;
5551
5552 if (!device_may_wakeup(dev: &bp->dev->dev))
5553 phy_init(phy: bp->sgmii_phy);
5554
5555 if (!netif_running(dev: netdev))
5556 return 0;
5557
5558 if (!device_may_wakeup(dev))
5559 pm_runtime_force_resume(dev);
5560
5561 if (bp->wol & MACB_WOL_ENABLED) {
5562 spin_lock_irqsave(&bp->lock, flags);
5563 /* Disable WoL */
5564 if (macb_is_gem(bp)) {
5565 queue_writel(bp->queues, IDR, GEM_BIT(WOL));
5566 gem_writel(bp, WOL, 0);
5567 } else {
5568 queue_writel(bp->queues, IDR, MACB_BIT(WOL));
5569 macb_writel(bp, WOL, 0);
5570 }
5571 /* Clear ISR on queue 0 */
5572 queue_readl(bp->queues, ISR);
5573 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
5574 queue_writel(bp->queues, ISR, -1);
5575 /* Replace interrupt handler on queue 0 */
5576 devm_free_irq(dev, irq: bp->queues[0].irq, dev_id: bp->queues);
5577 err = devm_request_irq(dev, irq: bp->queues[0].irq, handler: macb_interrupt,
5578 IRQF_SHARED, devname: netdev->name, dev_id: bp->queues);
5579 if (err) {
5580 dev_err(dev,
5581 "Unable to request IRQ %d (error %d)\n",
5582 bp->queues[0].irq, err);
5583 spin_unlock_irqrestore(lock: &bp->lock, flags);
5584 return err;
5585 }
5586 spin_unlock_irqrestore(lock: &bp->lock, flags);
5587
5588 disable_irq_wake(irq: bp->queues[0].irq);
5589
5590 /* Now make sure we disable phy before moving
5591 * to common restore path
5592 */
5593 rtnl_lock();
5594 phylink_stop(bp->phylink);
5595 rtnl_unlock();
5596 }
5597
5598 for (q = 0, queue = bp->queues; q < bp->num_queues;
5599 ++q, ++queue) {
5600 napi_enable(n: &queue->napi_rx);
5601 napi_enable(n: &queue->napi_tx);
5602 }
5603
5604 if (netdev->hw_features & NETIF_F_NTUPLE)
5605 gem_writel_n(bp, ETHT, SCRT2_ETHT, bp->pm_data.scrt2);
5606
5607 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
5608 macb_or_gem_writel(bp, USRIO, bp->pm_data.usrio);
5609
5610 macb_writel(bp, NCR, MACB_BIT(MPE));
5611 macb_init_hw(bp);
5612 macb_set_rx_mode(dev: netdev);
5613 macb_restore_features(bp);
5614 rtnl_lock();
5615
5616 phylink_start(bp->phylink);
5617 rtnl_unlock();
5618
5619 netif_device_attach(dev: netdev);
5620 if (bp->ptp_info)
5621 bp->ptp_info->ptp_init(netdev);
5622
5623 return 0;
5624}
5625
5626static int __maybe_unused macb_runtime_suspend(struct device *dev)
5627{
5628 struct net_device *netdev = dev_get_drvdata(dev);
5629 struct macb *bp = netdev_priv(dev: netdev);
5630
5631 if (!(device_may_wakeup(dev)))
5632 macb_clks_disable(pclk: bp->pclk, hclk: bp->hclk, tx_clk: bp->tx_clk, rx_clk: bp->rx_clk, tsu_clk: bp->tsu_clk);
5633 else if (!(bp->caps & MACB_CAPS_NEED_TSUCLK))
5634 macb_clks_disable(NULL, NULL, NULL, NULL, tsu_clk: bp->tsu_clk);
5635
5636 return 0;
5637}
5638
5639static int __maybe_unused macb_runtime_resume(struct device *dev)
5640{
5641 struct net_device *netdev = dev_get_drvdata(dev);
5642 struct macb *bp = netdev_priv(dev: netdev);
5643
5644 if (!(device_may_wakeup(dev))) {
5645 clk_prepare_enable(clk: bp->pclk);
5646 clk_prepare_enable(clk: bp->hclk);
5647 clk_prepare_enable(clk: bp->tx_clk);
5648 clk_prepare_enable(clk: bp->rx_clk);
5649 clk_prepare_enable(clk: bp->tsu_clk);
5650 } else if (!(bp->caps & MACB_CAPS_NEED_TSUCLK)) {
5651 clk_prepare_enable(clk: bp->tsu_clk);
5652 }
5653
5654 return 0;
5655}
5656
5657static const struct dev_pm_ops macb_pm_ops = {
5658 SET_SYSTEM_SLEEP_PM_OPS(macb_suspend, macb_resume)
5659 SET_RUNTIME_PM_OPS(macb_runtime_suspend, macb_runtime_resume, NULL)
5660};
5661
5662static struct platform_driver macb_driver = {
5663 .probe = macb_probe,
5664 .remove = macb_remove,
5665 .driver = {
5666 .name = "macb",
5667 .of_match_table = of_match_ptr(macb_dt_ids),
5668 .pm = &macb_pm_ops,
5669 },
5670};
5671
5672module_platform_driver(macb_driver);
5673
5674MODULE_LICENSE("GPL");
5675MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
5676MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
5677MODULE_ALIAS("platform:macb");
5678

source code of linux/drivers/net/ethernet/cadence/macb_main.c