1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 *
5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
7 * Copyright (c) a lot of people too. Please respect their work.
8 *
9 * See MAINTAINERS file for support contact information.
10 */
11
12#include <linux/module.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/clk.h>
17#include <linux/delay.h>
18#include <linux/ethtool.h>
19#include <linux/phy.h>
20#include <linux/if_vlan.h>
21#include <linux/in.h>
22#include <linux/io.h>
23#include <linux/ip.h>
24#include <linux/tcp.h>
25#include <linux/interrupt.h>
26#include <linux/dma-mapping.h>
27#include <linux/pm_runtime.h>
28#include <linux/bitfield.h>
29#include <linux/prefetch.h>
30#include <linux/ipv6.h>
31#include <linux/unaligned.h>
32#include <net/ip6_checksum.h>
33#include <net/netdev_queues.h>
34
35#include "r8169.h"
36#include "r8169_firmware.h"
37
38#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
39#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
40#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
41#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
42#define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
43#define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
44#define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
45#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
46#define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
47#define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
48#define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
49#define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
50#define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
51#define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
52#define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
53#define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
54#define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw"
55#define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
56#define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw"
57#define FIRMWARE_8125B_2 "rtl_nic/rtl8125b-2.fw"
58#define FIRMWARE_8125D_1 "rtl_nic/rtl8125d-1.fw"
59#define FIRMWARE_8125D_2 "rtl_nic/rtl8125d-2.fw"
60#define FIRMWARE_8125K_1 "rtl_nic/rtl8125k-1.fw"
61#define FIRMWARE_8125BP_2 "rtl_nic/rtl8125bp-2.fw"
62#define FIRMWARE_9151A_1 "rtl_nic/rtl9151a-1.fw"
63#define FIRMWARE_8126A_2 "rtl_nic/rtl8126a-2.fw"
64#define FIRMWARE_8126A_3 "rtl_nic/rtl8126a-3.fw"
65#define FIRMWARE_8127A_1 "rtl_nic/rtl8127a-1.fw"
66
67#define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
68#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
69
70#define R8169_REGS_SIZE 256
71#define R8169_RX_BUF_SIZE (SZ_16K - 1)
72#define NUM_TX_DESC 256 /* Number of Tx descriptor registers */
73#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
74#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
75#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
76#define R8169_TX_STOP_THRS (MAX_SKB_FRAGS + 1)
77#define R8169_TX_START_THRS (2 * R8169_TX_STOP_THRS)
78
79#define OCP_STD_PHY_BASE 0xa400
80
81#define RTL_CFG_NO_GBIT 1
82
83/* write/read MMIO register */
84#define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg))
85#define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
86#define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
87#define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg))
88#define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg))
89#define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg))
90
91#define JUMBO_4K (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
92#define JUMBO_6K (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
93#define JUMBO_7K (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
94#define JUMBO_9K (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
95#define JUMBO_16K (SZ_16K - VLAN_ETH_HLEN - ETH_FCS_LEN)
96
97static const struct rtl_chip_info {
98 u16 mask;
99 u16 val;
100 enum mac_version mac_version;
101 const char *name;
102 const char *fw_name;
103} rtl_chip_infos[] = {
104 /* 8127A family. */
105 { 0x7cf, 0x6c9, RTL_GIGA_MAC_VER_80, "RTL8127A", FIRMWARE_8127A_1 },
106
107 /* 8126A family. */
108 { 0x7cf, 0x64a, RTL_GIGA_MAC_VER_70, "RTL8126A", FIRMWARE_8126A_3 },
109 { 0x7cf, 0x649, RTL_GIGA_MAC_VER_70, "RTL8126A", FIRMWARE_8126A_2 },
110
111 /* 8125BP family. */
112 { 0x7cf, 0x681, RTL_GIGA_MAC_VER_66, "RTL8125BP", FIRMWARE_8125BP_2 },
113
114 /* 8125D family. */
115 { 0x7cf, 0x68b, RTL_GIGA_MAC_VER_64, "RTL9151A", FIRMWARE_9151A_1 },
116 { 0x7cf, 0x68a, RTL_GIGA_MAC_VER_64, "RTL8125K", FIRMWARE_8125K_1 },
117 { 0x7cf, 0x689, RTL_GIGA_MAC_VER_64, "RTL8125D", FIRMWARE_8125D_2 },
118 { 0x7cf, 0x688, RTL_GIGA_MAC_VER_64, "RTL8125D", FIRMWARE_8125D_1 },
119
120 /* 8125B family. */
121 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63, "RTL8125B", FIRMWARE_8125B_2 },
122
123 /* 8125A family. */
124 { 0x7cf, 0x609, RTL_GIGA_MAC_VER_61, "RTL8125A", FIRMWARE_8125A_3 },
125
126 /* RTL8117 */
127 { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_52, "RTL8168fp/RTL8117" },
128 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52, "RTL8168fp/RTL8117",
129 FIRMWARE_8168FP_3 },
130
131 /* 8168EP family. */
132 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51, "RTL8168ep/8111ep" },
133
134 /* 8168H family. */
135 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46, "RTL8168h/8111h",
136 FIRMWARE_8168H_2 },
137 /* Realtek calls it RTL8168M, but it's handled like RTL8168H */
138 { 0x7cf, 0x6c0, RTL_GIGA_MAC_VER_46, "RTL8168M", FIRMWARE_8168H_2 },
139
140 /* 8168G family. */
141 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44, "RTL8411b", FIRMWARE_8411_2 },
142 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42, "RTL8168gu/8111gu",
143 FIRMWARE_8168G_3 },
144 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40, "RTL8168g/8111g",
145 FIRMWARE_8168G_2 },
146
147 /* 8168F family. */
148 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38, "RTL8411", FIRMWARE_8411_1 },
149 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36, "RTL8168f/8111f",
150 FIRMWARE_8168F_2 },
151 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35, "RTL8168f/8111f",
152 FIRMWARE_8168F_1 },
153
154 /* 8168E family. */
155 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34, "RTL8168evl/8111evl",
156 FIRMWARE_8168E_3 },
157 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32, "RTL8168e/8111e",
158 FIRMWARE_8168E_1 },
159 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33, "RTL8168e/8111e",
160 FIRMWARE_8168E_2 },
161
162 /* 8168D family. */
163 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25, "RTL8168d/8111d",
164 FIRMWARE_8168D_1 },
165 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26, "RTL8168d/8111d",
166 FIRMWARE_8168D_2 },
167
168 /* 8168DP family. */
169 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28, "RTL8168dp/8111dp" },
170 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31, "RTL8168dp/8111dp" },
171
172 /* 8168C family. */
173 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23, "RTL8168cp/8111cp" },
174 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18, "RTL8168cp/8111cp" },
175 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24, "RTL8168cp/8111cp" },
176 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19, "RTL8168c/8111c" },
177 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20, "RTL8168c/8111c" },
178 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21, "RTL8168c/8111c" },
179 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22, "RTL8168c/8111c" },
180
181 /* 8168B family. */
182 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17, "RTL8168b/8111b" },
183 /* This one is very old and rare, support has been removed.
184 * { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11, "RTL8168b/8111b" },
185 */
186
187 /* 8101 family. */
188 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39, "RTL8106e", FIRMWARE_8106E_1 },
189 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37, "RTL8402", FIRMWARE_8402_1 },
190 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29, "RTL8105e", FIRMWARE_8105E_1 },
191 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30, "RTL8105e", FIRMWARE_8105E_1 },
192 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08, "RTL8102e" },
193 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08, "RTL8102e" },
194 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07, "RTL8102e" },
195 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07, "RTL8102e" },
196 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14, "RTL8401" },
197 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09, "RTL8102e/RTL8103e" },
198 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09, "RTL8102e/RTL8103e" },
199 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_10, "RTL8101e/RTL8100e" },
200
201 /* 8110 family. */
202 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06, "RTL8169sc/8110sc" },
203 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05, "RTL8169sc/8110sc" },
204 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04, "RTL8169sb/8110sb" },
205 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03, "RTL8110s" },
206 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02, "RTL8169s" },
207
208 /* Catch-all */
209 { 0x000, 0x000, RTL_GIGA_MAC_NONE }
210};
211
212static const struct pci_device_id rtl8169_pci_tbl[] = {
213 { PCI_VDEVICE(REALTEK, 0x2502) },
214 { PCI_VDEVICE(REALTEK, 0x2600) },
215 { PCI_VDEVICE(REALTEK, 0x8129) },
216 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT },
217 { PCI_VDEVICE(REALTEK, 0x8161) },
218 { PCI_VDEVICE(REALTEK, 0x8162) },
219 { PCI_VDEVICE(REALTEK, 0x8167) },
220 { PCI_VDEVICE(REALTEK, 0x8168) },
221 { PCI_VDEVICE(NCUBE, 0x8168) },
222 { PCI_VDEVICE(REALTEK, 0x8169) },
223 { PCI_VDEVICE(DLINK, 0x4300) },
224 { PCI_VDEVICE(DLINK, 0x4302) },
225 { PCI_VDEVICE(AT, 0xc107) },
226 { PCI_VDEVICE(USR, 0x0116) },
227 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 },
228 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 },
229 { PCI_VDEVICE(REALTEK, 0x8125) },
230 { PCI_VDEVICE(REALTEK, 0x8126) },
231 { PCI_VDEVICE(REALTEK, 0x8127) },
232 { PCI_VDEVICE(REALTEK, 0x3000) },
233 { PCI_VDEVICE(REALTEK, 0x5000) },
234 { PCI_VDEVICE(REALTEK, 0x0e10) },
235 {}
236};
237
238MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
239
240enum rtl_registers {
241 MAC0 = 0, /* Ethernet hardware address. */
242 MAC4 = 4,
243 MAR0 = 8, /* Multicast filter. */
244 CounterAddrLow = 0x10,
245 CounterAddrHigh = 0x14,
246 TxDescStartAddrLow = 0x20,
247 TxDescStartAddrHigh = 0x24,
248 TxHDescStartAddrLow = 0x28,
249 TxHDescStartAddrHigh = 0x2c,
250 FLASH = 0x30,
251 ERSR = 0x36,
252 ChipCmd = 0x37,
253 TxPoll = 0x38,
254 IntrMask = 0x3c,
255 IntrStatus = 0x3e,
256
257 TxConfig = 0x40,
258#define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
259#define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
260
261 RxConfig = 0x44,
262#define RX128_INT_EN (1 << 15) /* 8111c and later */
263#define RX_MULTI_EN (1 << 14) /* 8111c only */
264#define RXCFG_FIFO_SHIFT 13
265 /* No threshold before first PCI xfer */
266#define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
267#define RX_EARLY_OFF (1 << 11)
268#define RX_PAUSE_SLOT_ON (1 << 11) /* 8125b and later */
269#define RXCFG_DMA_SHIFT 8
270 /* Unlimited maximum PCI burst. */
271#define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
272
273 Cfg9346 = 0x50,
274 Config0 = 0x51,
275 Config1 = 0x52,
276 Config2 = 0x53,
277#define PME_SIGNAL (1 << 5) /* 8168c and later */
278
279 Config3 = 0x54,
280 Config4 = 0x55,
281 Config5 = 0x56,
282 PHYAR = 0x60,
283 PHYstatus = 0x6c,
284 RxMaxSize = 0xda,
285 CPlusCmd = 0xe0,
286 IntrMitigate = 0xe2,
287
288#define RTL_COALESCE_TX_USECS GENMASK(15, 12)
289#define RTL_COALESCE_TX_FRAMES GENMASK(11, 8)
290#define RTL_COALESCE_RX_USECS GENMASK(7, 4)
291#define RTL_COALESCE_RX_FRAMES GENMASK(3, 0)
292
293#define RTL_COALESCE_T_MAX 0x0fU
294#define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_T_MAX * 4)
295
296 RxDescAddrLow = 0xe4,
297 RxDescAddrHigh = 0xe8,
298 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
299
300#define NoEarlyTx 0x3f /* Max value : no early transmit. */
301
302 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
303
304#define TxPacketMax (8064 >> 7)
305#define EarlySize 0x27
306
307 FuncEvent = 0xf0,
308 FuncEventMask = 0xf4,
309 FuncPresetState = 0xf8,
310 IBCR0 = 0xf8,
311 IBCR2 = 0xf9,
312 IBIMR0 = 0xfa,
313 IBISR0 = 0xfb,
314 FuncForceEvent = 0xfc,
315};
316
317enum rtl8168_8101_registers {
318 CSIDR = 0x64,
319 CSIAR = 0x68,
320#define CSIAR_FLAG 0x80000000
321#define CSIAR_WRITE_CMD 0x80000000
322#define CSIAR_BYTE_ENABLE 0x0000f000
323#define CSIAR_ADDR_MASK 0x00000fff
324 PMCH = 0x6f,
325#define D3COLD_NO_PLL_DOWN BIT(7)
326#define D3HOT_NO_PLL_DOWN BIT(6)
327#define D3_NO_PLL_DOWN (BIT(7) | BIT(6))
328 EPHYAR = 0x80,
329#define EPHYAR_FLAG 0x80000000
330#define EPHYAR_WRITE_CMD 0x80000000
331#define EPHYAR_REG_MASK 0x1f
332#define EPHYAR_REG_SHIFT 16
333#define EPHYAR_DATA_MASK 0xffff
334 DLLPR = 0xd0,
335#define PFM_EN (1 << 6)
336#define TX_10M_PS_EN (1 << 7)
337 DBG_REG = 0xd1,
338#define FIX_NAK_1 (1 << 4)
339#define FIX_NAK_2 (1 << 3)
340 TWSI = 0xd2,
341 MCU = 0xd3,
342#define NOW_IS_OOB (1 << 7)
343#define TX_EMPTY (1 << 5)
344#define RX_EMPTY (1 << 4)
345#define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
346#define EN_NDP (1 << 3)
347#define EN_OOB_RESET (1 << 2)
348#define LINK_LIST_RDY (1 << 1)
349 EFUSEAR = 0xdc,
350#define EFUSEAR_FLAG 0x80000000
351#define EFUSEAR_WRITE_CMD 0x80000000
352#define EFUSEAR_READ_CMD 0x00000000
353#define EFUSEAR_REG_MASK 0x03ff
354#define EFUSEAR_REG_SHIFT 8
355#define EFUSEAR_DATA_MASK 0xff
356 MISC_1 = 0xf2,
357#define PFM_D3COLD_EN (1 << 6)
358};
359
360enum rtl8168_registers {
361 LED_CTRL = 0x18,
362 LED_FREQ = 0x1a,
363 EEE_LED = 0x1b,
364 ERIDR = 0x70,
365 ERIAR = 0x74,
366#define ERIAR_FLAG 0x80000000
367#define ERIAR_WRITE_CMD 0x80000000
368#define ERIAR_READ_CMD 0x00000000
369#define ERIAR_ADDR_BYTE_ALIGN 4
370#define ERIAR_TYPE_SHIFT 16
371#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
372#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
373#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
374#define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
375#define ERIAR_MASK_SHIFT 12
376#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
377#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
378#define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
379#define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
380#define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
381 EPHY_RXER_NUM = 0x7c,
382 OCPDR = 0xb0, /* OCP GPHY access */
383#define OCPDR_WRITE_CMD 0x80000000
384#define OCPDR_READ_CMD 0x00000000
385#define OCPDR_REG_MASK 0x7f
386#define OCPDR_GPHY_REG_SHIFT 16
387#define OCPDR_DATA_MASK 0xffff
388 OCPAR = 0xb4,
389#define OCPAR_FLAG 0x80000000
390#define OCPAR_GPHY_WRITE_CMD 0x8000f060
391#define OCPAR_GPHY_READ_CMD 0x0000f060
392 GPHY_OCP = 0xb8,
393 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
394 MISC = 0xf0, /* 8168e only. */
395#define TXPLA_RST (1 << 29)
396#define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
397#define PWM_EN (1 << 22)
398#define RXDV_GATED_EN (1 << 19)
399#define EARLY_TALLY_EN (1 << 16)
400};
401
402enum rtl8125_registers {
403 LEDSEL0 = 0x18,
404 INT_CFG0_8125 = 0x34,
405#define INT_CFG0_ENABLE_8125 BIT(0)
406#define INT_CFG0_CLKREQEN BIT(3)
407 IntrMask_8125 = 0x38,
408 IntrStatus_8125 = 0x3c,
409 INT_CFG1_8125 = 0x7a,
410 LEDSEL2 = 0x84,
411 LEDSEL1 = 0x86,
412 TxPoll_8125 = 0x90,
413 LEDSEL3 = 0x96,
414 MAC0_BKP = 0x19e0,
415 RSS_CTRL_8125 = 0x4500,
416 Q_NUM_CTRL_8125 = 0x4800,
417 EEE_TXIDLE_TIMER_8125 = 0x6048,
418};
419
420#define LEDSEL_MASK_8125 0x23f
421
422#define RX_VLAN_INNER_8125 BIT(22)
423#define RX_VLAN_OUTER_8125 BIT(23)
424#define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125)
425
426#define RX_FETCH_DFLT_8125 (8 << 27)
427
428enum rtl_register_content {
429 /* InterruptStatusBits */
430 SYSErr = 0x8000,
431 PCSTimeout = 0x4000,
432 SWInt = 0x0100,
433 TxDescUnavail = 0x0080,
434 RxFIFOOver = 0x0040,
435 LinkChg = 0x0020,
436 RxOverflow = 0x0010,
437 TxErr = 0x0008,
438 TxOK = 0x0004,
439 RxErr = 0x0002,
440 RxOK = 0x0001,
441
442 /* RxStatusDesc */
443 RxRWT = (1 << 22),
444 RxRES = (1 << 21),
445 RxRUNT = (1 << 20),
446 RxCRC = (1 << 19),
447
448 /* ChipCmdBits */
449 StopReq = 0x80,
450 CmdReset = 0x10,
451 CmdRxEnb = 0x08,
452 CmdTxEnb = 0x04,
453 RxBufEmpty = 0x01,
454
455 /* TXPoll register p.5 */
456 HPQ = 0x80, /* Poll cmd on the high prio queue */
457 NPQ = 0x40, /* Poll cmd on the low prio queue */
458 FSWInt = 0x01, /* Forced software interrupt */
459
460 /* Cfg9346Bits */
461 Cfg9346_Lock = 0x00,
462 Cfg9346_Unlock = 0xc0,
463
464 /* rx_mode_bits */
465 AcceptErr = 0x20,
466 AcceptRunt = 0x10,
467#define RX_CONFIG_ACCEPT_ERR_MASK 0x30
468 AcceptBroadcast = 0x08,
469 AcceptMulticast = 0x04,
470 AcceptMyPhys = 0x02,
471 AcceptAllPhys = 0x01,
472#define RX_CONFIG_ACCEPT_OK_MASK 0x0f
473#define RX_CONFIG_ACCEPT_MASK 0x3f
474
475 /* TxConfigBits */
476 TxInterFrameGapShift = 24,
477 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
478
479 /* Config1 register p.24 */
480 LEDS1 = (1 << 7),
481 LEDS0 = (1 << 6),
482 Speed_down = (1 << 4),
483 MEMMAP = (1 << 3),
484 IOMAP = (1 << 2),
485 VPD = (1 << 1),
486 PMEnable = (1 << 0), /* Power Management Enable */
487
488 /* Config2 register p. 25 */
489 ClkReqEn = (1 << 7), /* Clock Request Enable */
490 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
491 PCI_Clock_66MHz = 0x01,
492 PCI_Clock_33MHz = 0x00,
493
494 /* Config3 register p.25 */
495 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
496 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
497 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
498 Rdy_to_L23 = (1 << 1), /* L23 Enable */
499 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
500
501 /* Config4 register */
502 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
503
504 /* Config5 register p.27 */
505 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
506 MWF = (1 << 5), /* Accept Multicast wakeup frame */
507 UWF = (1 << 4), /* Accept Unicast wakeup frame */
508 Spi_en = (1 << 3),
509 LanWake = (1 << 1), /* LanWake enable/disable */
510 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
511 ASPM_en = (1 << 0), /* ASPM enable */
512
513 /* CPlusCmd p.31 */
514 EnableBist = (1 << 15), // 8168 8101
515 Mac_dbgo_oe = (1 << 14), // 8168 8101
516 EnAnaPLL = (1 << 14), // 8169
517 Normal_mode = (1 << 13), // unused
518 Force_half_dup = (1 << 12), // 8168 8101
519 Force_rxflow_en = (1 << 11), // 8168 8101
520 Force_txflow_en = (1 << 10), // 8168 8101
521 Cxpl_dbg_sel = (1 << 9), // 8168 8101
522 ASF = (1 << 8), // 8168 8101
523 PktCntrDisable = (1 << 7), // 8168 8101
524 Mac_dbgo_sel = 0x001c, // 8168
525 RxVlan = (1 << 6),
526 RxChkSum = (1 << 5),
527 PCIDAC = (1 << 4),
528 PCIMulRW = (1 << 3),
529#define INTT_MASK GENMASK(1, 0)
530#define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
531
532 /* rtl8169_PHYstatus */
533 TBI_Enable = 0x80,
534 TxFlowCtrl = 0x40,
535 RxFlowCtrl = 0x20,
536 _1000bpsF = 0x10,
537 _100bps = 0x08,
538 _10bps = 0x04,
539 LinkStatus = 0x02,
540 FullDup = 0x01,
541
542 /* ResetCounterCommand */
543 CounterReset = 0x1,
544
545 /* DumpCounterCommand */
546 CounterDump = 0x8,
547
548 /* magic enable v2 */
549 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
550};
551
552enum rtl_desc_bit {
553 /* First doubleword. */
554 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
555 RingEnd = (1 << 30), /* End of descriptor ring */
556 FirstFrag = (1 << 29), /* First segment of a packet */
557 LastFrag = (1 << 28), /* Final segment of a packet */
558};
559
560/* Generic case. */
561enum rtl_tx_desc_bit {
562 /* First doubleword. */
563 TD_LSO = (1 << 27), /* Large Send Offload */
564#define TD_MSS_MAX 0x07ffu /* MSS value */
565
566 /* Second doubleword. */
567 TxVlanTag = (1 << 17), /* Add VLAN tag */
568};
569
570/* 8169, 8168b and 810x except 8102e. */
571enum rtl_tx_desc_bit_0 {
572 /* First doubleword. */
573#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
574 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
575 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
576 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
577};
578
579/* 8102e, 8168c and beyond. */
580enum rtl_tx_desc_bit_1 {
581 /* First doubleword. */
582 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
583 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
584#define GTTCPHO_SHIFT 18
585#define GTTCPHO_MAX 0x7f
586
587 /* Second doubleword. */
588#define TCPHO_SHIFT 18
589#define TCPHO_MAX 0x3ff
590#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
591 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
592 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
593 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
594 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
595};
596
597enum rtl_rx_desc_bit {
598 /* Rx private */
599 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
600 PID0 = (1 << 17), /* Protocol ID bit 0/2 */
601
602#define RxProtoUDP (PID1)
603#define RxProtoTCP (PID0)
604#define RxProtoIP (PID1 | PID0)
605#define RxProtoMask RxProtoIP
606
607 IPFail = (1 << 16), /* IP checksum failed */
608 UDPFail = (1 << 15), /* UDP/IP checksum failed */
609 TCPFail = (1 << 14), /* TCP/IP checksum failed */
610
611#define RxCSFailMask (IPFail | UDPFail | TCPFail)
612
613 RxVlanTag = (1 << 16), /* VLAN tag available */
614};
615
616#define RTL_GSO_MAX_SIZE_V1 32000
617#define RTL_GSO_MAX_SEGS_V1 24
618#define RTL_GSO_MAX_SIZE_V2 64000
619#define RTL_GSO_MAX_SEGS_V2 64
620
621struct TxDesc {
622 __le32 opts1;
623 __le32 opts2;
624 __le64 addr;
625};
626
627struct RxDesc {
628 __le32 opts1;
629 __le32 opts2;
630 __le64 addr;
631};
632
633struct ring_info {
634 struct sk_buff *skb;
635 u32 len;
636};
637
638struct rtl8169_counters {
639 __le64 tx_packets;
640 __le64 rx_packets;
641 __le64 tx_errors;
642 __le32 rx_errors;
643 __le16 rx_missed;
644 __le16 align_errors;
645 __le32 tx_one_collision;
646 __le32 tx_multi_collision;
647 __le64 rx_unicast;
648 __le64 rx_broadcast;
649 __le32 rx_multicast;
650 __le16 tx_aborted;
651 __le16 tx_underrun;
652 /* new since RTL8125 */
653 __le64 tx_octets;
654 __le64 rx_octets;
655 __le64 rx_multicast64;
656 __le64 tx_unicast64;
657 __le64 tx_broadcast64;
658 __le64 tx_multicast64;
659 __le32 tx_pause_on;
660 __le32 tx_pause_off;
661 __le32 tx_pause_all;
662 __le32 tx_deferred;
663 __le32 tx_late_collision;
664 __le32 tx_all_collision;
665 __le32 tx_aborted32;
666 __le32 align_errors32;
667 __le32 rx_frame_too_long;
668 __le32 rx_runt;
669 __le32 rx_pause_on;
670 __le32 rx_pause_off;
671 __le32 rx_pause_all;
672 __le32 rx_unknown_opcode;
673 __le32 rx_mac_error;
674 __le32 tx_underrun32;
675 __le32 rx_mac_missed;
676 __le32 rx_tcam_dropped;
677 __le32 tdu;
678 __le32 rdu;
679};
680
681struct rtl8169_tc_offsets {
682 bool inited;
683 __le64 tx_errors;
684 __le32 tx_multi_collision;
685 __le16 tx_aborted;
686 __le16 rx_missed;
687};
688
689enum rtl_flag {
690 RTL_FLAG_TASK_RESET_PENDING,
691 RTL_FLAG_TASK_TX_TIMEOUT,
692 RTL_FLAG_MAX
693};
694
695enum rtl_dash_type {
696 RTL_DASH_NONE,
697 RTL_DASH_DP,
698 RTL_DASH_EP,
699 RTL_DASH_25_BP,
700};
701
702struct rtl8169_private {
703 void __iomem *mmio_addr; /* memory map physical address */
704 struct pci_dev *pci_dev;
705 struct net_device *dev;
706 struct phy_device *phydev;
707 struct napi_struct napi;
708 enum mac_version mac_version;
709 enum rtl_dash_type dash_type;
710 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
711 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
712 u32 dirty_tx;
713 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
714 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
715 dma_addr_t TxPhyAddr;
716 dma_addr_t RxPhyAddr;
717 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
718 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
719 u16 cp_cmd;
720 u16 tx_lpi_timer;
721 u32 irq_mask;
722 int irq;
723 struct clk *clk;
724
725 struct {
726 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
727 struct work_struct work;
728 } wk;
729
730 raw_spinlock_t mac_ocp_lock;
731 struct mutex led_lock; /* serialize LED ctrl RMW access */
732
733 unsigned supports_gmii:1;
734 unsigned aspm_manageable:1;
735 unsigned dash_enabled:1;
736 dma_addr_t counters_phys_addr;
737 struct rtl8169_counters *counters;
738 struct rtl8169_tc_offsets tc_offset;
739 u32 saved_wolopts;
740
741 const char *fw_name;
742 struct rtl_fw *rtl_fw;
743
744 struct r8169_led_classdev *leds;
745
746 u32 ocp_base;
747};
748
749typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
750
751MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
752MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
753MODULE_SOFTDEP("pre: realtek");
754MODULE_LICENSE("GPL");
755MODULE_FIRMWARE(FIRMWARE_8168D_1);
756MODULE_FIRMWARE(FIRMWARE_8168D_2);
757MODULE_FIRMWARE(FIRMWARE_8168E_1);
758MODULE_FIRMWARE(FIRMWARE_8168E_2);
759MODULE_FIRMWARE(FIRMWARE_8168E_3);
760MODULE_FIRMWARE(FIRMWARE_8105E_1);
761MODULE_FIRMWARE(FIRMWARE_8168F_1);
762MODULE_FIRMWARE(FIRMWARE_8168F_2);
763MODULE_FIRMWARE(FIRMWARE_8402_1);
764MODULE_FIRMWARE(FIRMWARE_8411_1);
765MODULE_FIRMWARE(FIRMWARE_8411_2);
766MODULE_FIRMWARE(FIRMWARE_8106E_1);
767MODULE_FIRMWARE(FIRMWARE_8106E_2);
768MODULE_FIRMWARE(FIRMWARE_8168G_2);
769MODULE_FIRMWARE(FIRMWARE_8168G_3);
770MODULE_FIRMWARE(FIRMWARE_8168H_2);
771MODULE_FIRMWARE(FIRMWARE_8168FP_3);
772MODULE_FIRMWARE(FIRMWARE_8107E_2);
773MODULE_FIRMWARE(FIRMWARE_8125A_3);
774MODULE_FIRMWARE(FIRMWARE_8125B_2);
775MODULE_FIRMWARE(FIRMWARE_8125D_1);
776MODULE_FIRMWARE(FIRMWARE_8125D_2);
777MODULE_FIRMWARE(FIRMWARE_8125K_1);
778MODULE_FIRMWARE(FIRMWARE_8125BP_2);
779MODULE_FIRMWARE(FIRMWARE_9151A_1);
780MODULE_FIRMWARE(FIRMWARE_8126A_2);
781MODULE_FIRMWARE(FIRMWARE_8126A_3);
782MODULE_FIRMWARE(FIRMWARE_8127A_1);
783
784static inline struct device *tp_to_dev(struct rtl8169_private *tp)
785{
786 return &tp->pci_dev->dev;
787}
788
789static void rtl_lock_config_regs(struct rtl8169_private *tp)
790{
791 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
792}
793
794static void rtl_unlock_config_regs(struct rtl8169_private *tp)
795{
796 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
797}
798
799static void rtl_pci_commit(struct rtl8169_private *tp)
800{
801 /* Read an arbitrary register to commit a preceding PCI write */
802 RTL_R8(tp, ChipCmd);
803}
804
805static void rtl_mod_config2(struct rtl8169_private *tp, u8 clear, u8 set)
806{
807 u8 val;
808
809 val = RTL_R8(tp, Config2);
810 RTL_W8(tp, Config2, (val & ~clear) | set);
811}
812
813static void rtl_mod_config5(struct rtl8169_private *tp, u8 clear, u8 set)
814{
815 u8 val;
816
817 val = RTL_R8(tp, Config5);
818 RTL_W8(tp, Config5, (val & ~clear) | set);
819}
820
821static void r8169_mod_reg8_cond(struct rtl8169_private *tp, int reg,
822 u8 bits, bool cond)
823{
824 u8 val, old_val;
825
826 old_val = RTL_R8(tp, reg);
827 if (cond)
828 val = old_val | bits;
829 else
830 val = old_val & ~bits;
831 if (val != old_val)
832 RTL_W8(tp, reg, val);
833}
834
835static bool rtl_is_8125(struct rtl8169_private *tp)
836{
837 return tp->mac_version >= RTL_GIGA_MAC_VER_61;
838}
839
840static bool rtl_is_8168evl_up(struct rtl8169_private *tp)
841{
842 return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
843 tp->mac_version != RTL_GIGA_MAC_VER_39 &&
844 tp->mac_version <= RTL_GIGA_MAC_VER_52;
845}
846
847static bool rtl_supports_eee(struct rtl8169_private *tp)
848{
849 return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
850 tp->mac_version != RTL_GIGA_MAC_VER_37 &&
851 tp->mac_version != RTL_GIGA_MAC_VER_39;
852}
853
854static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg)
855{
856 int i;
857
858 for (i = 0; i < ETH_ALEN; i++)
859 mac[i] = RTL_R8(tp, reg + i);
860}
861
862struct rtl_cond {
863 bool (*check)(struct rtl8169_private *);
864 const char *msg;
865};
866
867static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
868 unsigned long usecs, int n, bool high)
869{
870 int i;
871
872 for (i = 0; i < n; i++) {
873 if (c->check(tp) == high)
874 return true;
875 fsleep(usecs);
876 }
877
878 if (net_ratelimit())
879 netdev_err(dev: tp->dev, format: "%s == %d (loop: %d, delay: %lu).\n",
880 c->msg, !high, n, usecs);
881 return false;
882}
883
884static bool rtl_loop_wait_high(struct rtl8169_private *tp,
885 const struct rtl_cond *c,
886 unsigned long d, int n)
887{
888 return rtl_loop_wait(tp, c, usecs: d, n, high: true);
889}
890
891static bool rtl_loop_wait_low(struct rtl8169_private *tp,
892 const struct rtl_cond *c,
893 unsigned long d, int n)
894{
895 return rtl_loop_wait(tp, c, usecs: d, n, high: false);
896}
897
898#define DECLARE_RTL_COND(name) \
899static bool name ## _check(struct rtl8169_private *); \
900 \
901static const struct rtl_cond name = { \
902 .check = name ## _check, \
903 .msg = #name \
904}; \
905 \
906static bool name ## _check(struct rtl8169_private *tp)
907
908int rtl8168_led_mod_ctrl(struct rtl8169_private *tp, u16 mask, u16 val)
909{
910 struct device *dev = tp_to_dev(tp);
911 int ret;
912
913 ret = pm_runtime_resume_and_get(dev);
914 if (ret < 0)
915 return ret;
916
917 mutex_lock(&tp->led_lock);
918 RTL_W16(tp, LED_CTRL, (RTL_R16(tp, LED_CTRL) & ~mask) | val);
919 mutex_unlock(lock: &tp->led_lock);
920
921 pm_runtime_put_sync(dev);
922
923 return 0;
924}
925
926int rtl8168_get_led_mode(struct rtl8169_private *tp)
927{
928 struct device *dev = tp_to_dev(tp);
929 int ret;
930
931 ret = pm_runtime_resume_and_get(dev);
932 if (ret < 0)
933 return ret;
934
935 ret = RTL_R16(tp, LED_CTRL);
936
937 pm_runtime_put_sync(dev);
938
939 return ret;
940}
941
942static int rtl8125_get_led_reg(int index)
943{
944 static const int led_regs[] = { LEDSEL0, LEDSEL1, LEDSEL2, LEDSEL3 };
945
946 return led_regs[index];
947}
948
949int rtl8125_set_led_mode(struct rtl8169_private *tp, int index, u16 mode)
950{
951 int reg = rtl8125_get_led_reg(index);
952 struct device *dev = tp_to_dev(tp);
953 int ret;
954 u16 val;
955
956 ret = pm_runtime_resume_and_get(dev);
957 if (ret < 0)
958 return ret;
959
960 mutex_lock(&tp->led_lock);
961 val = RTL_R16(tp, reg) & ~LEDSEL_MASK_8125;
962 RTL_W16(tp, reg, val | mode);
963 mutex_unlock(lock: &tp->led_lock);
964
965 pm_runtime_put_sync(dev);
966
967 return 0;
968}
969
970int rtl8125_get_led_mode(struct rtl8169_private *tp, int index)
971{
972 int reg = rtl8125_get_led_reg(index);
973 struct device *dev = tp_to_dev(tp);
974 int ret;
975
976 ret = pm_runtime_resume_and_get(dev);
977 if (ret < 0)
978 return ret;
979
980 ret = RTL_R16(tp, reg);
981
982 pm_runtime_put_sync(dev);
983
984 return ret;
985}
986
987void r8169_get_led_name(struct rtl8169_private *tp, int idx,
988 char *buf, int buf_len)
989{
990 struct pci_dev *pdev = tp->pci_dev;
991 char pdom[8], pfun[8];
992 int domain;
993
994 domain = pci_domain_nr(bus: pdev->bus);
995 if (domain)
996 snprintf(buf: pdom, size: sizeof(pdom), fmt: "P%d", domain);
997 else
998 pdom[0] = '\0';
999
1000 if (pdev->multifunction)
1001 snprintf(buf: pfun, size: sizeof(pfun), fmt: "f%d", PCI_FUNC(pdev->devfn));
1002 else
1003 pfun[0] = '\0';
1004
1005 snprintf(buf, size: buf_len, fmt: "en%sp%ds%d%s-%d::lan", pdom, pdev->bus->number,
1006 PCI_SLOT(pdev->devfn), pfun, idx);
1007}
1008
1009static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type)
1010{
1011 /* based on RTL8168FP_OOBMAC_BASE in vendor driver */
1012 if (type == ERIAR_OOB && tp->mac_version == RTL_GIGA_MAC_VER_52)
1013 *cmd |= 0xf70 << 18;
1014}
1015
1016DECLARE_RTL_COND(rtl_eriar_cond)
1017{
1018 return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1019}
1020
1021static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1022 u32 val, int type)
1023{
1024 u32 cmd = ERIAR_WRITE_CMD | type | mask | addr;
1025
1026 if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n", addr, mask))
1027 return;
1028
1029 RTL_W32(tp, ERIDR, val);
1030 r8168fp_adjust_ocp_cmd(tp, cmd: &cmd, type);
1031 RTL_W32(tp, ERIAR, cmd);
1032
1033 rtl_loop_wait_low(tp, c: &rtl_eriar_cond, d: 100, n: 100);
1034}
1035
1036static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1037 u32 val)
1038{
1039 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
1040}
1041
1042static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1043{
1044 u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr;
1045
1046 r8168fp_adjust_ocp_cmd(tp, cmd: &cmd, type);
1047 RTL_W32(tp, ERIAR, cmd);
1048
1049 return rtl_loop_wait_high(tp, c: &rtl_eriar_cond, d: 100, n: 100) ?
1050 RTL_R32(tp, ERIDR) : ~0;
1051}
1052
1053static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
1054{
1055 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
1056}
1057
1058static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m)
1059{
1060 u32 val = rtl_eri_read(tp, addr);
1061
1062 rtl_eri_write(tp, addr, ERIAR_MASK_1111, val: (val & ~m) | p);
1063}
1064
1065static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p)
1066{
1067 rtl_w0w1_eri(tp, addr, p, m: 0);
1068}
1069
1070static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m)
1071{
1072 rtl_w0w1_eri(tp, addr, p: 0, m);
1073}
1074
1075static bool rtl_ocp_reg_failure(u32 reg)
1076{
1077 return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n", reg);
1078}
1079
1080DECLARE_RTL_COND(rtl_ocp_gphy_cond)
1081{
1082 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
1083}
1084
1085static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1086{
1087 if (rtl_ocp_reg_failure(reg))
1088 return;
1089
1090 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
1091
1092 rtl_loop_wait_low(tp, c: &rtl_ocp_gphy_cond, d: 25, n: 10);
1093}
1094
1095static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
1096{
1097 if (rtl_ocp_reg_failure(reg))
1098 return 0;
1099
1100 RTL_W32(tp, GPHY_OCP, reg << 15);
1101
1102 return rtl_loop_wait_high(tp, c: &rtl_ocp_gphy_cond, d: 25, n: 10) ?
1103 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT;
1104}
1105
1106static void __r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1107{
1108 if (rtl_ocp_reg_failure(reg))
1109 return;
1110
1111 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
1112}
1113
1114static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1115{
1116 unsigned long flags;
1117
1118 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags);
1119 __r8168_mac_ocp_write(tp, reg, data);
1120 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags);
1121}
1122
1123static u16 __r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1124{
1125 if (rtl_ocp_reg_failure(reg))
1126 return 0;
1127
1128 RTL_W32(tp, OCPDR, reg << 15);
1129
1130 return RTL_R32(tp, OCPDR);
1131}
1132
1133static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1134{
1135 unsigned long flags;
1136 u16 val;
1137
1138 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags);
1139 val = __r8168_mac_ocp_read(tp, reg);
1140 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags);
1141
1142 return val;
1143}
1144
1145static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask,
1146 u16 set)
1147{
1148 unsigned long flags;
1149 u16 data;
1150
1151 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags);
1152 data = __r8168_mac_ocp_read(tp, reg);
1153 __r8168_mac_ocp_write(tp, reg, data: (data & ~mask) | set);
1154 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags);
1155}
1156
1157/* Work around a hw issue with RTL8168g PHY, the quirk disables
1158 * PHY MCU interrupts before PHY power-down.
1159 */
1160static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value)
1161{
1162 switch (tp->mac_version) {
1163 case RTL_GIGA_MAC_VER_40:
1164 if (value & BMCR_RESET || !(value & BMCR_PDOWN))
1165 rtl_eri_set_bits(tp, addr: 0x1a8, p: 0xfc000000);
1166 else
1167 rtl_eri_clear_bits(tp, addr: 0x1a8, m: 0xfc000000);
1168 break;
1169 default:
1170 break;
1171 }
1172};
1173
1174static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1175{
1176 if (reg == 0x1f) {
1177 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1178 return;
1179 }
1180
1181 if (tp->ocp_base != OCP_STD_PHY_BASE)
1182 reg -= 0x10;
1183
1184 if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR)
1185 rtl8168g_phy_suspend_quirk(tp, value);
1186
1187 r8168_phy_ocp_write(tp, reg: tp->ocp_base + reg * 2, data: value);
1188}
1189
1190static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1191{
1192 if (reg == 0x1f)
1193 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4;
1194
1195 if (tp->ocp_base != OCP_STD_PHY_BASE)
1196 reg -= 0x10;
1197
1198 return r8168_phy_ocp_read(tp, reg: tp->ocp_base + reg * 2);
1199}
1200
1201static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
1202{
1203 if (reg == 0x1f) {
1204 tp->ocp_base = value << 4;
1205 return;
1206 }
1207
1208 r8168_mac_ocp_write(tp, reg: tp->ocp_base + reg, data: value);
1209}
1210
1211static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1212{
1213 return r8168_mac_ocp_read(tp, reg: tp->ocp_base + reg);
1214}
1215
1216DECLARE_RTL_COND(rtl_phyar_cond)
1217{
1218 return RTL_R32(tp, PHYAR) & 0x80000000;
1219}
1220
1221static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1222{
1223 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1224
1225 rtl_loop_wait_low(tp, c: &rtl_phyar_cond, d: 25, n: 20);
1226 /*
1227 * According to hardware specs a 20us delay is required after write
1228 * complete indication, but before sending next command.
1229 */
1230 udelay(usec: 20);
1231}
1232
1233static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1234{
1235 int value;
1236
1237 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
1238
1239 value = rtl_loop_wait_high(tp, c: &rtl_phyar_cond, d: 25, n: 20) ?
1240 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT;
1241
1242 /*
1243 * According to hardware specs a 20us delay is required after read
1244 * complete indication, but before sending next command.
1245 */
1246 udelay(usec: 20);
1247
1248 return value;
1249}
1250
1251DECLARE_RTL_COND(rtl_ocpar_cond)
1252{
1253 return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
1254}
1255
1256#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1257
1258static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
1259{
1260 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1261}
1262
1263static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
1264{
1265 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1266}
1267
1268static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1269{
1270 r8168dp_2_mdio_start(tp);
1271
1272 r8169_mdio_write(tp, reg, value);
1273
1274 r8168dp_2_mdio_stop(tp);
1275}
1276
1277static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1278{
1279 int value;
1280
1281 /* Work around issue with chip reporting wrong PHY ID */
1282 if (reg == MII_PHYSID2)
1283 return 0xc912;
1284
1285 r8168dp_2_mdio_start(tp);
1286
1287 value = r8169_mdio_read(tp, reg);
1288
1289 r8168dp_2_mdio_stop(tp);
1290
1291 return value;
1292}
1293
1294static void rtl_writephy(struct rtl8169_private *tp, int location, int val)
1295{
1296 switch (tp->mac_version) {
1297 case RTL_GIGA_MAC_VER_28:
1298 case RTL_GIGA_MAC_VER_31:
1299 r8168dp_2_mdio_write(tp, reg: location, value: val);
1300 break;
1301 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_LAST:
1302 r8168g_mdio_write(tp, reg: location, value: val);
1303 break;
1304 default:
1305 r8169_mdio_write(tp, reg: location, value: val);
1306 break;
1307 }
1308}
1309
1310static int rtl_readphy(struct rtl8169_private *tp, int location)
1311{
1312 switch (tp->mac_version) {
1313 case RTL_GIGA_MAC_VER_28:
1314 case RTL_GIGA_MAC_VER_31:
1315 return r8168dp_2_mdio_read(tp, reg: location);
1316 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_LAST:
1317 return r8168g_mdio_read(tp, reg: location);
1318 default:
1319 return r8169_mdio_read(tp, reg: location);
1320 }
1321}
1322
1323DECLARE_RTL_COND(rtl_ephyar_cond)
1324{
1325 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1326}
1327
1328static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1329{
1330 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1331 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1332
1333 rtl_loop_wait_low(tp, c: &rtl_ephyar_cond, d: 10, n: 100);
1334
1335 udelay(usec: 10);
1336}
1337
1338static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1339{
1340 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1341
1342 return rtl_loop_wait_high(tp, c: &rtl_ephyar_cond, d: 10, n: 100) ?
1343 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1344}
1345
1346static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg)
1347{
1348 RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff));
1349 return rtl_loop_wait_high(tp, c: &rtl_ocpar_cond, d: 100, n: 20) ?
1350 RTL_R32(tp, OCPDR) : ~0;
1351}
1352
1353static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg)
1354{
1355 return _rtl_eri_read(tp, addr: reg, ERIAR_OOB);
1356}
1357
1358static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1359 u32 data)
1360{
1361 RTL_W32(tp, OCPDR, data);
1362 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1363 rtl_loop_wait_low(tp, c: &rtl_ocpar_cond, d: 100, n: 20);
1364}
1365
1366static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1367 u32 data)
1368{
1369 _rtl_eri_write(tp, addr: reg, mask: ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1370 val: data, ERIAR_OOB);
1371}
1372
1373static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1374{
1375 rtl_eri_write(tp, addr: 0xe8, ERIAR_MASK_0001, val: cmd);
1376
1377 r8168dp_ocp_write(tp, mask: 0x1, reg: 0x30, data: 0x00000001);
1378}
1379
1380#define OOB_CMD_RESET 0x00
1381#define OOB_CMD_DRIVER_START 0x05
1382#define OOB_CMD_DRIVER_STOP 0x06
1383
1384static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1385{
1386 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1387}
1388
1389DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
1390{
1391 u16 reg;
1392
1393 reg = rtl8168_get_ocp_reg(tp);
1394
1395 return r8168dp_ocp_read(tp, reg) & 0x00000800;
1396}
1397
1398DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1399{
1400 return r8168ep_ocp_read(tp, reg: 0x124) & 0x00000001;
1401}
1402
1403DECLARE_RTL_COND(rtl_ocp_tx_cond)
1404{
1405 return RTL_R8(tp, IBISR0) & 0x20;
1406}
1407
1408static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1409{
1410 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1411 rtl_loop_wait_high(tp, c: &rtl_ocp_tx_cond, d: 50000, n: 2000);
1412 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1413 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1414}
1415
1416static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1417{
1418 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1419 if (tp->dash_enabled)
1420 rtl_loop_wait_high(tp, c: &rtl_dp_ocp_read_cond, d: 10000, n: 10);
1421}
1422
1423static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1424{
1425 r8168ep_ocp_write(tp, mask: 0x01, reg: 0x180, OOB_CMD_DRIVER_START);
1426 r8168ep_ocp_write(tp, mask: 0x01, reg: 0x30, data: r8168ep_ocp_read(tp, reg: 0x30) | 0x01);
1427 if (tp->dash_enabled)
1428 rtl_loop_wait_high(tp, c: &rtl_ep_ocp_read_cond, d: 10000, n: 30);
1429}
1430
1431static void rtl8125bp_driver_start(struct rtl8169_private *tp)
1432{
1433 r8168ep_ocp_write(tp, mask: 0x01, reg: 0x14, OOB_CMD_DRIVER_START);
1434 r8168ep_ocp_write(tp, mask: 0x01, reg: 0x18, data: 0x00);
1435 r8168ep_ocp_write(tp, mask: 0x01, reg: 0x10, data: 0x01);
1436}
1437
1438static void rtl8168_driver_start(struct rtl8169_private *tp)
1439{
1440 if (tp->dash_type == RTL_DASH_DP)
1441 rtl8168dp_driver_start(tp);
1442 else if (tp->dash_type == RTL_DASH_25_BP)
1443 rtl8125bp_driver_start(tp);
1444 else
1445 rtl8168ep_driver_start(tp);
1446}
1447
1448static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1449{
1450 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1451 if (tp->dash_enabled)
1452 rtl_loop_wait_low(tp, c: &rtl_dp_ocp_read_cond, d: 10000, n: 10);
1453}
1454
1455static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1456{
1457 rtl8168ep_stop_cmac(tp);
1458 r8168ep_ocp_write(tp, mask: 0x01, reg: 0x180, OOB_CMD_DRIVER_STOP);
1459 r8168ep_ocp_write(tp, mask: 0x01, reg: 0x30, data: r8168ep_ocp_read(tp, reg: 0x30) | 0x01);
1460 if (tp->dash_enabled)
1461 rtl_loop_wait_low(tp, c: &rtl_ep_ocp_read_cond, d: 10000, n: 10);
1462}
1463
1464static void rtl8125bp_driver_stop(struct rtl8169_private *tp)
1465{
1466 r8168ep_ocp_write(tp, mask: 0x01, reg: 0x14, OOB_CMD_DRIVER_STOP);
1467 r8168ep_ocp_write(tp, mask: 0x01, reg: 0x18, data: 0x00);
1468 r8168ep_ocp_write(tp, mask: 0x01, reg: 0x10, data: 0x01);
1469}
1470
1471static void rtl8168_driver_stop(struct rtl8169_private *tp)
1472{
1473 if (tp->dash_type == RTL_DASH_DP)
1474 rtl8168dp_driver_stop(tp);
1475 else if (tp->dash_type == RTL_DASH_25_BP)
1476 rtl8125bp_driver_stop(tp);
1477 else
1478 rtl8168ep_driver_stop(tp);
1479}
1480
1481static bool r8168dp_check_dash(struct rtl8169_private *tp)
1482{
1483 u16 reg = rtl8168_get_ocp_reg(tp);
1484
1485 return r8168dp_ocp_read(tp, reg) & BIT(15);
1486}
1487
1488static bool r8168ep_check_dash(struct rtl8169_private *tp)
1489{
1490 return r8168ep_ocp_read(tp, reg: 0x128) & BIT(0);
1491}
1492
1493static bool rtl_dash_is_enabled(struct rtl8169_private *tp)
1494{
1495 switch (tp->dash_type) {
1496 case RTL_DASH_DP:
1497 return r8168dp_check_dash(tp);
1498 case RTL_DASH_EP:
1499 case RTL_DASH_25_BP:
1500 return r8168ep_check_dash(tp);
1501 default:
1502 return false;
1503 }
1504}
1505
1506static enum rtl_dash_type rtl_get_dash_type(struct rtl8169_private *tp)
1507{
1508 switch (tp->mac_version) {
1509 case RTL_GIGA_MAC_VER_28:
1510 case RTL_GIGA_MAC_VER_31:
1511 return RTL_DASH_DP;
1512 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_52:
1513 return RTL_DASH_EP;
1514 case RTL_GIGA_MAC_VER_66:
1515 return RTL_DASH_25_BP;
1516 default:
1517 return RTL_DASH_NONE;
1518 }
1519}
1520
1521static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable)
1522{
1523 switch (tp->mac_version) {
1524 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_24:
1525 case RTL_GIGA_MAC_VER_28:
1526 case RTL_GIGA_MAC_VER_31:
1527 case RTL_GIGA_MAC_VER_38:
1528 break;
1529 case RTL_GIGA_MAC_VER_80:
1530 r8169_mod_reg8_cond(tp, reg: PMCH, D3_NO_PLL_DOWN, cond: true);
1531 break;
1532 default:
1533 r8169_mod_reg8_cond(tp, reg: PMCH, D3HOT_NO_PLL_DOWN, cond: true);
1534 r8169_mod_reg8_cond(tp, reg: PMCH, D3COLD_NO_PLL_DOWN, cond: !enable);
1535 break;
1536 }
1537}
1538
1539static void rtl_reset_packet_filter(struct rtl8169_private *tp)
1540{
1541 rtl_eri_clear_bits(tp, addr: 0xdc, BIT(0));
1542 rtl_eri_set_bits(tp, addr: 0xdc, BIT(0));
1543}
1544
1545DECLARE_RTL_COND(rtl_efusear_cond)
1546{
1547 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1548}
1549
1550u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1551{
1552 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1553
1554 return rtl_loop_wait_high(tp, c: &rtl_efusear_cond, d: 100, n: 300) ?
1555 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1556}
1557
1558static u32 rtl_get_events(struct rtl8169_private *tp)
1559{
1560 if (rtl_is_8125(tp))
1561 return RTL_R32(tp, IntrStatus_8125);
1562 else
1563 return RTL_R16(tp, IntrStatus);
1564}
1565
1566static void rtl_ack_events(struct rtl8169_private *tp, u32 bits)
1567{
1568 if (rtl_is_8125(tp))
1569 RTL_W32(tp, IntrStatus_8125, bits);
1570 else
1571 RTL_W16(tp, IntrStatus, bits);
1572}
1573
1574static void rtl_irq_disable(struct rtl8169_private *tp)
1575{
1576 if (rtl_is_8125(tp))
1577 RTL_W32(tp, IntrMask_8125, 0);
1578 else
1579 RTL_W16(tp, IntrMask, 0);
1580}
1581
1582static void rtl_irq_enable(struct rtl8169_private *tp)
1583{
1584 if (rtl_is_8125(tp))
1585 RTL_W32(tp, IntrMask_8125, tp->irq_mask);
1586 else
1587 RTL_W16(tp, IntrMask, tp->irq_mask);
1588}
1589
1590static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1591{
1592 rtl_irq_disable(tp);
1593 rtl_ack_events(tp, bits: 0xffffffff);
1594 rtl_pci_commit(tp);
1595}
1596
1597static void rtl_link_chg_patch(struct rtl8169_private *tp)
1598{
1599 struct phy_device *phydev = tp->phydev;
1600
1601 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1602 tp->mac_version == RTL_GIGA_MAC_VER_38) {
1603 if (phydev->speed == SPEED_1000) {
1604 rtl_eri_write(tp, addr: 0x1bc, ERIAR_MASK_1111, val: 0x00000011);
1605 rtl_eri_write(tp, addr: 0x1dc, ERIAR_MASK_1111, val: 0x00000005);
1606 } else if (phydev->speed == SPEED_100) {
1607 rtl_eri_write(tp, addr: 0x1bc, ERIAR_MASK_1111, val: 0x0000001f);
1608 rtl_eri_write(tp, addr: 0x1dc, ERIAR_MASK_1111, val: 0x00000005);
1609 } else {
1610 rtl_eri_write(tp, addr: 0x1bc, ERIAR_MASK_1111, val: 0x0000001f);
1611 rtl_eri_write(tp, addr: 0x1dc, ERIAR_MASK_1111, val: 0x0000003f);
1612 }
1613 rtl_reset_packet_filter(tp);
1614 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1615 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1616 if (phydev->speed == SPEED_1000) {
1617 rtl_eri_write(tp, addr: 0x1bc, ERIAR_MASK_1111, val: 0x00000011);
1618 rtl_eri_write(tp, addr: 0x1dc, ERIAR_MASK_1111, val: 0x00000005);
1619 } else {
1620 rtl_eri_write(tp, addr: 0x1bc, ERIAR_MASK_1111, val: 0x0000001f);
1621 rtl_eri_write(tp, addr: 0x1dc, ERIAR_MASK_1111, val: 0x0000003f);
1622 }
1623 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1624 if (phydev->speed == SPEED_10) {
1625 rtl_eri_write(tp, addr: 0x1d0, ERIAR_MASK_0011, val: 0x4d02);
1626 rtl_eri_write(tp, addr: 0x1dc, ERIAR_MASK_0011, val: 0x0060a);
1627 } else {
1628 rtl_eri_write(tp, addr: 0x1d0, ERIAR_MASK_0011, val: 0x0000);
1629 }
1630 }
1631}
1632
1633#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1634
1635static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1636{
1637 struct rtl8169_private *tp = netdev_priv(dev);
1638
1639 wol->supported = WAKE_ANY;
1640 wol->wolopts = tp->saved_wolopts;
1641}
1642
1643static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1644{
1645 rtl_unlock_config_regs(tp);
1646
1647 if (rtl_is_8168evl_up(tp)) {
1648 if (wolopts & WAKE_MAGIC)
1649 rtl_eri_set_bits(tp, addr: 0x0dc, p: MagicPacket_v2);
1650 else
1651 rtl_eri_clear_bits(tp, addr: 0x0dc, m: MagicPacket_v2);
1652 } else if (rtl_is_8125(tp)) {
1653 if (wolopts & WAKE_MAGIC)
1654 r8168_mac_ocp_modify(tp, reg: 0xc0b6, mask: 0, BIT(0));
1655 else
1656 r8168_mac_ocp_modify(tp, reg: 0xc0b6, BIT(0), set: 0);
1657 } else {
1658 r8169_mod_reg8_cond(tp, reg: Config3, bits: MagicPacket,
1659 cond: wolopts & WAKE_MAGIC);
1660 }
1661
1662 r8169_mod_reg8_cond(tp, reg: Config3, bits: LinkUp, cond: wolopts & WAKE_PHY);
1663 if (rtl_is_8125(tp))
1664 r8168_mac_ocp_modify(tp, reg: 0xe0c6, mask: 0x3f,
1665 set: wolopts & WAKE_PHY ? 0x13 : 0);
1666 r8169_mod_reg8_cond(tp, reg: Config5, bits: UWF, cond: wolopts & WAKE_UCAST);
1667 r8169_mod_reg8_cond(tp, reg: Config5, bits: BWF, cond: wolopts & WAKE_BCAST);
1668 r8169_mod_reg8_cond(tp, reg: Config5, bits: MWF, cond: wolopts & WAKE_MCAST);
1669 r8169_mod_reg8_cond(tp, reg: Config5, bits: LanWake, cond: wolopts);
1670
1671 switch (tp->mac_version) {
1672 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
1673 r8169_mod_reg8_cond(tp, reg: Config1, bits: PMEnable, cond: wolopts);
1674 break;
1675 case RTL_GIGA_MAC_VER_34:
1676 case RTL_GIGA_MAC_VER_37:
1677 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_LAST:
1678 r8169_mod_reg8_cond(tp, reg: Config2, PME_SIGNAL, cond: wolopts);
1679 break;
1680 default:
1681 break;
1682 }
1683
1684 rtl_lock_config_regs(tp);
1685
1686 device_set_wakeup_enable(dev: tp_to_dev(tp), enable: wolopts);
1687
1688 if (!tp->dash_enabled) {
1689 rtl_set_d3_pll_down(tp, enable: !wolopts);
1690 tp->dev->ethtool->wol_enabled = wolopts ? 1 : 0;
1691 }
1692}
1693
1694static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1695{
1696 struct rtl8169_private *tp = netdev_priv(dev);
1697
1698 if (wol->wolopts & ~WAKE_ANY)
1699 return -EINVAL;
1700
1701 tp->saved_wolopts = wol->wolopts;
1702 __rtl8169_set_wol(tp, wolopts: tp->saved_wolopts);
1703
1704 return 0;
1705}
1706
1707static void rtl8169_get_drvinfo(struct net_device *dev,
1708 struct ethtool_drvinfo *info)
1709{
1710 struct rtl8169_private *tp = netdev_priv(dev);
1711 struct rtl_fw *rtl_fw = tp->rtl_fw;
1712
1713 strscpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
1714 strscpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1715 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1716 if (rtl_fw)
1717 strscpy(info->fw_version, rtl_fw->version,
1718 sizeof(info->fw_version));
1719}
1720
1721static int rtl8169_get_regs_len(struct net_device *dev)
1722{
1723 return R8169_REGS_SIZE;
1724}
1725
1726static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1727 netdev_features_t features)
1728{
1729 struct rtl8169_private *tp = netdev_priv(dev);
1730
1731 if (dev->mtu > TD_MSS_MAX)
1732 features &= ~NETIF_F_ALL_TSO;
1733
1734 if (dev->mtu > ETH_DATA_LEN &&
1735 tp->mac_version > RTL_GIGA_MAC_VER_06)
1736 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO);
1737
1738 return features;
1739}
1740
1741static void rtl_set_rx_config_features(struct rtl8169_private *tp,
1742 netdev_features_t features)
1743{
1744 u32 rx_config = RTL_R32(tp, RxConfig);
1745
1746 if (features & NETIF_F_RXALL)
1747 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK;
1748 else
1749 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK;
1750
1751 if (rtl_is_8125(tp)) {
1752 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1753 rx_config |= RX_VLAN_8125;
1754 else
1755 rx_config &= ~RX_VLAN_8125;
1756 }
1757
1758 RTL_W32(tp, RxConfig, rx_config);
1759}
1760
1761static int rtl8169_set_features(struct net_device *dev,
1762 netdev_features_t features)
1763{
1764 struct rtl8169_private *tp = netdev_priv(dev);
1765
1766 rtl_set_rx_config_features(tp, features);
1767
1768 if (features & NETIF_F_RXCSUM)
1769 tp->cp_cmd |= RxChkSum;
1770 else
1771 tp->cp_cmd &= ~RxChkSum;
1772
1773 if (!rtl_is_8125(tp)) {
1774 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1775 tp->cp_cmd |= RxVlan;
1776 else
1777 tp->cp_cmd &= ~RxVlan;
1778 }
1779
1780 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1781 rtl_pci_commit(tp);
1782
1783 return 0;
1784}
1785
1786static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1787{
1788 return (skb_vlan_tag_present(skb)) ?
1789 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1790}
1791
1792static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1793{
1794 u32 opts2 = le32_to_cpu(desc->opts2);
1795
1796 if (opts2 & RxVlanTag)
1797 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1798}
1799
1800static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1801 void *p)
1802{
1803 struct rtl8169_private *tp = netdev_priv(dev);
1804 u32 __iomem *data = tp->mmio_addr;
1805 u32 *dw = p;
1806 int i;
1807
1808 for (i = 0; i < R8169_REGS_SIZE; i += 4)
1809 memcpy_fromio(dw++, data++, 4);
1810}
1811
1812static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1813 "tx_packets",
1814 "rx_packets",
1815 "tx_errors",
1816 "rx_errors",
1817 "rx_missed",
1818 "align_errors",
1819 "tx_single_collisions",
1820 "tx_multi_collisions",
1821 "unicast",
1822 "broadcast",
1823 "multicast",
1824 "tx_aborted",
1825 "tx_underrun",
1826};
1827
1828static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1829{
1830 switch (sset) {
1831 case ETH_SS_STATS:
1832 return ARRAY_SIZE(rtl8169_gstrings);
1833 default:
1834 return -EOPNOTSUPP;
1835 }
1836}
1837
1838DECLARE_RTL_COND(rtl_counters_cond)
1839{
1840 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1841}
1842
1843static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1844{
1845 u32 cmd = lower_32_bits(tp->counters_phys_addr);
1846
1847 RTL_W32(tp, CounterAddrHigh, upper_32_bits(tp->counters_phys_addr));
1848 rtl_pci_commit(tp);
1849 RTL_W32(tp, CounterAddrLow, cmd);
1850 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1851
1852 rtl_loop_wait_low(tp, c: &rtl_counters_cond, d: 10, n: 1000);
1853}
1854
1855static void rtl8169_update_counters(struct rtl8169_private *tp)
1856{
1857 u8 val = RTL_R8(tp, ChipCmd);
1858
1859 /*
1860 * Some chips are unable to dump tally counters when the receiver
1861 * is disabled. If 0xff chip may be in a PCI power-save state.
1862 */
1863 if (val & CmdRxEnb && val != 0xff)
1864 rtl8169_do_counters(tp, counter_cmd: CounterDump);
1865}
1866
1867static void rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1868{
1869 struct rtl8169_counters *counters = tp->counters;
1870
1871 /*
1872 * rtl8169_init_counter_offsets is called from rtl_open. On chip
1873 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1874 * reset by a power cycle, while the counter values collected by the
1875 * driver are reset at every driver unload/load cycle.
1876 *
1877 * To make sure the HW values returned by @get_stats64 match the SW
1878 * values, we collect the initial values at first open(*) and use them
1879 * as offsets to normalize the values returned by @get_stats64.
1880 *
1881 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1882 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1883 * set at open time by rtl_hw_start.
1884 */
1885
1886 if (tp->tc_offset.inited)
1887 return;
1888
1889 if (tp->mac_version >= RTL_GIGA_MAC_VER_19) {
1890 rtl8169_do_counters(tp, counter_cmd: CounterReset);
1891 } else {
1892 rtl8169_update_counters(tp);
1893 tp->tc_offset.tx_errors = counters->tx_errors;
1894 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1895 tp->tc_offset.tx_aborted = counters->tx_aborted;
1896 tp->tc_offset.rx_missed = counters->rx_missed;
1897 }
1898
1899 tp->tc_offset.inited = true;
1900}
1901
1902static void rtl8169_get_ethtool_stats(struct net_device *dev,
1903 struct ethtool_stats *stats, u64 *data)
1904{
1905 struct rtl8169_private *tp = netdev_priv(dev);
1906 struct rtl8169_counters *counters;
1907
1908 counters = tp->counters;
1909 rtl8169_update_counters(tp);
1910
1911 data[0] = le64_to_cpu(counters->tx_packets);
1912 data[1] = le64_to_cpu(counters->rx_packets);
1913 data[2] = le64_to_cpu(counters->tx_errors);
1914 data[3] = le32_to_cpu(counters->rx_errors);
1915 data[4] = le16_to_cpu(counters->rx_missed);
1916 data[5] = le16_to_cpu(counters->align_errors);
1917 data[6] = le32_to_cpu(counters->tx_one_collision);
1918 data[7] = le32_to_cpu(counters->tx_multi_collision);
1919 data[8] = le64_to_cpu(counters->rx_unicast);
1920 data[9] = le64_to_cpu(counters->rx_broadcast);
1921 data[10] = le32_to_cpu(counters->rx_multicast);
1922 data[11] = le16_to_cpu(counters->tx_aborted);
1923 data[12] = le16_to_cpu(counters->tx_underrun);
1924}
1925
1926static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1927{
1928 switch(stringset) {
1929 case ETH_SS_STATS:
1930 memcpy(data, rtl8169_gstrings, sizeof(rtl8169_gstrings));
1931 break;
1932 }
1933}
1934
1935/*
1936 * Interrupt coalescing
1937 *
1938 * > 1 - the availability of the IntrMitigate (0xe2) register through the
1939 * > 8169, 8168 and 810x line of chipsets
1940 *
1941 * 8169, 8168, and 8136(810x) serial chipsets support it.
1942 *
1943 * > 2 - the Tx timer unit at gigabit speed
1944 *
1945 * The unit of the timer depends on both the speed and the setting of CPlusCmd
1946 * (0xe0) bit 1 and bit 0.
1947 *
1948 * For 8169
1949 * bit[1:0] \ speed 1000M 100M 10M
1950 * 0 0 320ns 2.56us 40.96us
1951 * 0 1 2.56us 20.48us 327.7us
1952 * 1 0 5.12us 40.96us 655.4us
1953 * 1 1 10.24us 81.92us 1.31ms
1954 *
1955 * For the other
1956 * bit[1:0] \ speed 1000M 100M 10M
1957 * 0 0 5us 2.56us 40.96us
1958 * 0 1 40us 20.48us 327.7us
1959 * 1 0 80us 40.96us 655.4us
1960 * 1 1 160us 81.92us 1.31ms
1961 */
1962
1963/* rx/tx scale factors for all CPlusCmd[0:1] cases */
1964struct rtl_coalesce_info {
1965 u32 speed;
1966 u32 scale_nsecs[4];
1967};
1968
1969/* produce array with base delay *1, *8, *8*2, *8*2*2 */
1970#define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) }
1971
1972static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1973 { SPEED_1000, COALESCE_DELAY(320) },
1974 { SPEED_100, COALESCE_DELAY(2560) },
1975 { SPEED_10, COALESCE_DELAY(40960) },
1976 { 0 },
1977};
1978
1979static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1980 { SPEED_1000, COALESCE_DELAY(5000) },
1981 { SPEED_100, COALESCE_DELAY(2560) },
1982 { SPEED_10, COALESCE_DELAY(40960) },
1983 { 0 },
1984};
1985#undef COALESCE_DELAY
1986
1987/* get rx/tx scale vector corresponding to current speed */
1988static const struct rtl_coalesce_info *
1989rtl_coalesce_info(struct rtl8169_private *tp)
1990{
1991 const struct rtl_coalesce_info *ci;
1992
1993 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1994 ci = rtl_coalesce_info_8169;
1995 else
1996 ci = rtl_coalesce_info_8168_8136;
1997
1998 /* if speed is unknown assume highest one */
1999 if (tp->phydev->speed == SPEED_UNKNOWN)
2000 return ci;
2001
2002 for (; ci->speed; ci++) {
2003 if (tp->phydev->speed == ci->speed)
2004 return ci;
2005 }
2006
2007 return ERR_PTR(error: -ELNRNG);
2008}
2009
2010static int rtl_get_coalesce(struct net_device *dev,
2011 struct ethtool_coalesce *ec,
2012 struct kernel_ethtool_coalesce *kernel_coal,
2013 struct netlink_ext_ack *extack)
2014{
2015 struct rtl8169_private *tp = netdev_priv(dev);
2016 const struct rtl_coalesce_info *ci;
2017 u32 scale, c_us, c_fr;
2018 u16 intrmit;
2019
2020 if (rtl_is_8125(tp))
2021 return -EOPNOTSUPP;
2022
2023 memset(ec, 0, sizeof(*ec));
2024
2025 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
2026 ci = rtl_coalesce_info(tp);
2027 if (IS_ERR(ptr: ci))
2028 return PTR_ERR(ptr: ci);
2029
2030 scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK];
2031
2032 intrmit = RTL_R16(tp, IntrMitigate);
2033
2034 c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit);
2035 ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000);
2036
2037 c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit);
2038 /* ethtool_coalesce states usecs and max_frames must not both be 0 */
2039 ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1;
2040
2041 c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit);
2042 ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000);
2043
2044 c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit);
2045 ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1;
2046
2047 return 0;
2048}
2049
2050/* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */
2051static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec,
2052 u16 *cp01)
2053{
2054 const struct rtl_coalesce_info *ci;
2055 u16 i;
2056
2057 ci = rtl_coalesce_info(tp);
2058 if (IS_ERR(ptr: ci))
2059 return PTR_ERR(ptr: ci);
2060
2061 for (i = 0; i < 4; i++) {
2062 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) {
2063 *cp01 = i;
2064 return ci->scale_nsecs[i];
2065 }
2066 }
2067
2068 return -ERANGE;
2069}
2070
2071static int rtl_set_coalesce(struct net_device *dev,
2072 struct ethtool_coalesce *ec,
2073 struct kernel_ethtool_coalesce *kernel_coal,
2074 struct netlink_ext_ack *extack)
2075{
2076 struct rtl8169_private *tp = netdev_priv(dev);
2077 u32 tx_fr = ec->tx_max_coalesced_frames;
2078 u32 rx_fr = ec->rx_max_coalesced_frames;
2079 u32 coal_usec_max, units;
2080 u16 w = 0, cp01 = 0;
2081 int scale;
2082
2083 if (rtl_is_8125(tp))
2084 return -EOPNOTSUPP;
2085
2086 if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX)
2087 return -ERANGE;
2088
2089 coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs);
2090 scale = rtl_coalesce_choose_scale(tp, usec: coal_usec_max, cp01: &cp01);
2091 if (scale < 0)
2092 return scale;
2093
2094 /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it
2095 * not only when usecs=0 because of e.g. the following scenario:
2096 *
2097 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
2098 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
2099 * - then user does `ethtool -C eth0 rx-usecs 100`
2100 *
2101 * Since ethtool sends to kernel whole ethtool_coalesce settings,
2102 * if we want to ignore rx_frames then it has to be set to 0.
2103 */
2104 if (rx_fr == 1)
2105 rx_fr = 0;
2106 if (tx_fr == 1)
2107 tx_fr = 0;
2108
2109 /* HW requires time limit to be set if frame limit is set */
2110 if ((tx_fr && !ec->tx_coalesce_usecs) ||
2111 (rx_fr && !ec->rx_coalesce_usecs))
2112 return -EINVAL;
2113
2114 w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4));
2115 w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4));
2116
2117 units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale);
2118 w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units);
2119 units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale);
2120 w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units);
2121
2122 RTL_W16(tp, IntrMitigate, w);
2123
2124 /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */
2125 if (rtl_is_8168evl_up(tp)) {
2126 if (!rx_fr && !tx_fr)
2127 /* disable packet counter */
2128 tp->cp_cmd |= PktCntrDisable;
2129 else
2130 tp->cp_cmd &= ~PktCntrDisable;
2131 }
2132
2133 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
2134 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
2135 rtl_pci_commit(tp);
2136
2137 return 0;
2138}
2139
2140static void rtl_set_eee_txidle_timer(struct rtl8169_private *tp)
2141{
2142 unsigned int timer_val = READ_ONCE(tp->dev->mtu) + ETH_HLEN + 0x20;
2143
2144 switch (tp->mac_version) {
2145 case RTL_GIGA_MAC_VER_46:
2146 case RTL_GIGA_MAC_VER_48:
2147 tp->tx_lpi_timer = timer_val;
2148 r8168_mac_ocp_write(tp, reg: 0xe048, data: timer_val);
2149 break;
2150 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST:
2151 tp->tx_lpi_timer = timer_val;
2152 RTL_W16(tp, EEE_TXIDLE_TIMER_8125, timer_val);
2153 break;
2154 default:
2155 break;
2156 }
2157}
2158
2159static unsigned int r8169_get_tx_lpi_timer_us(struct rtl8169_private *tp)
2160{
2161 unsigned int speed = tp->phydev->speed;
2162 unsigned int timer = tp->tx_lpi_timer;
2163
2164 if (!timer || speed == SPEED_UNKNOWN)
2165 return 0;
2166
2167 /* tx_lpi_timer value is in bytes */
2168 return DIV_ROUND_CLOSEST(timer * BITS_PER_BYTE, speed);
2169}
2170
2171static int rtl8169_get_eee(struct net_device *dev, struct ethtool_keee *data)
2172{
2173 struct rtl8169_private *tp = netdev_priv(dev);
2174 int ret;
2175
2176 if (!rtl_supports_eee(tp))
2177 return -EOPNOTSUPP;
2178
2179 ret = phy_ethtool_get_eee(phydev: tp->phydev, data);
2180 if (ret)
2181 return ret;
2182
2183 data->tx_lpi_timer = r8169_get_tx_lpi_timer_us(tp);
2184
2185 return 0;
2186}
2187
2188static int rtl8169_set_eee(struct net_device *dev, struct ethtool_keee *data)
2189{
2190 struct rtl8169_private *tp = netdev_priv(dev);
2191
2192 if (!rtl_supports_eee(tp))
2193 return -EOPNOTSUPP;
2194
2195 return phy_ethtool_set_eee(phydev: tp->phydev, data);
2196}
2197
2198static void rtl8169_get_ringparam(struct net_device *dev,
2199 struct ethtool_ringparam *data,
2200 struct kernel_ethtool_ringparam *kernel_data,
2201 struct netlink_ext_ack *extack)
2202{
2203 data->rx_max_pending = NUM_RX_DESC;
2204 data->rx_pending = NUM_RX_DESC;
2205 data->tx_max_pending = NUM_TX_DESC;
2206 data->tx_pending = NUM_TX_DESC;
2207}
2208
2209static void rtl8169_get_pause_stats(struct net_device *dev,
2210 struct ethtool_pause_stats *pause_stats)
2211{
2212 struct rtl8169_private *tp = netdev_priv(dev);
2213
2214 if (!rtl_is_8125(tp))
2215 return;
2216
2217 rtl8169_update_counters(tp);
2218 pause_stats->tx_pause_frames = le32_to_cpu(tp->counters->tx_pause_on);
2219 pause_stats->rx_pause_frames = le32_to_cpu(tp->counters->rx_pause_on);
2220}
2221
2222static void rtl8169_get_pauseparam(struct net_device *dev,
2223 struct ethtool_pauseparam *data)
2224{
2225 struct rtl8169_private *tp = netdev_priv(dev);
2226 bool tx_pause, rx_pause;
2227
2228 phy_get_pause(phydev: tp->phydev, tx_pause: &tx_pause, rx_pause: &rx_pause);
2229
2230 data->autoneg = tp->phydev->autoneg;
2231 data->tx_pause = tx_pause ? 1 : 0;
2232 data->rx_pause = rx_pause ? 1 : 0;
2233}
2234
2235static int rtl8169_set_pauseparam(struct net_device *dev,
2236 struct ethtool_pauseparam *data)
2237{
2238 struct rtl8169_private *tp = netdev_priv(dev);
2239
2240 if (dev->mtu > ETH_DATA_LEN)
2241 return -EOPNOTSUPP;
2242
2243 phy_set_asym_pause(phydev: tp->phydev, rx: data->rx_pause, tx: data->tx_pause);
2244
2245 return 0;
2246}
2247
2248static void rtl8169_get_eth_mac_stats(struct net_device *dev,
2249 struct ethtool_eth_mac_stats *mac_stats)
2250{
2251 struct rtl8169_private *tp = netdev_priv(dev);
2252
2253 rtl8169_update_counters(tp);
2254
2255 mac_stats->FramesTransmittedOK =
2256 le64_to_cpu(tp->counters->tx_packets);
2257 mac_stats->SingleCollisionFrames =
2258 le32_to_cpu(tp->counters->tx_one_collision);
2259 mac_stats->MultipleCollisionFrames =
2260 le32_to_cpu(tp->counters->tx_multi_collision);
2261 mac_stats->FramesReceivedOK =
2262 le64_to_cpu(tp->counters->rx_packets);
2263 mac_stats->AlignmentErrors =
2264 le16_to_cpu(tp->counters->align_errors);
2265 mac_stats->FramesLostDueToIntMACXmitError =
2266 le64_to_cpu(tp->counters->tx_errors);
2267 mac_stats->BroadcastFramesReceivedOK =
2268 le64_to_cpu(tp->counters->rx_broadcast);
2269 mac_stats->MulticastFramesReceivedOK =
2270 le32_to_cpu(tp->counters->rx_multicast);
2271
2272 if (!rtl_is_8125(tp))
2273 return;
2274
2275 mac_stats->AlignmentErrors =
2276 le32_to_cpu(tp->counters->align_errors32);
2277 mac_stats->OctetsTransmittedOK =
2278 le64_to_cpu(tp->counters->tx_octets);
2279 mac_stats->LateCollisions =
2280 le32_to_cpu(tp->counters->tx_late_collision);
2281 mac_stats->FramesAbortedDueToXSColls =
2282 le32_to_cpu(tp->counters->tx_aborted32);
2283 mac_stats->OctetsReceivedOK =
2284 le64_to_cpu(tp->counters->rx_octets);
2285 mac_stats->FramesLostDueToIntMACRcvError =
2286 le32_to_cpu(tp->counters->rx_mac_error);
2287 mac_stats->MulticastFramesXmittedOK =
2288 le64_to_cpu(tp->counters->tx_multicast64);
2289 mac_stats->BroadcastFramesXmittedOK =
2290 le64_to_cpu(tp->counters->tx_broadcast64);
2291 mac_stats->MulticastFramesReceivedOK =
2292 le64_to_cpu(tp->counters->rx_multicast64);
2293 mac_stats->FrameTooLongErrors =
2294 le32_to_cpu(tp->counters->rx_frame_too_long);
2295}
2296
2297static void rtl8169_get_eth_ctrl_stats(struct net_device *dev,
2298 struct ethtool_eth_ctrl_stats *ctrl_stats)
2299{
2300 struct rtl8169_private *tp = netdev_priv(dev);
2301
2302 if (!rtl_is_8125(tp))
2303 return;
2304
2305 rtl8169_update_counters(tp);
2306
2307 ctrl_stats->UnsupportedOpcodesReceived =
2308 le32_to_cpu(tp->counters->rx_unknown_opcode);
2309}
2310
2311static const struct ethtool_ops rtl8169_ethtool_ops = {
2312 .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
2313 ETHTOOL_COALESCE_MAX_FRAMES,
2314 .get_drvinfo = rtl8169_get_drvinfo,
2315 .get_regs_len = rtl8169_get_regs_len,
2316 .get_link = ethtool_op_get_link,
2317 .get_coalesce = rtl_get_coalesce,
2318 .set_coalesce = rtl_set_coalesce,
2319 .get_regs = rtl8169_get_regs,
2320 .get_wol = rtl8169_get_wol,
2321 .set_wol = rtl8169_set_wol,
2322 .get_strings = rtl8169_get_strings,
2323 .get_sset_count = rtl8169_get_sset_count,
2324 .get_ethtool_stats = rtl8169_get_ethtool_stats,
2325 .get_ts_info = ethtool_op_get_ts_info,
2326 .nway_reset = phy_ethtool_nway_reset,
2327 .get_eee = rtl8169_get_eee,
2328 .set_eee = rtl8169_set_eee,
2329 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2330 .set_link_ksettings = phy_ethtool_set_link_ksettings,
2331 .get_ringparam = rtl8169_get_ringparam,
2332 .get_pause_stats = rtl8169_get_pause_stats,
2333 .get_pauseparam = rtl8169_get_pauseparam,
2334 .set_pauseparam = rtl8169_set_pauseparam,
2335 .get_eth_mac_stats = rtl8169_get_eth_mac_stats,
2336 .get_eth_ctrl_stats = rtl8169_get_eth_ctrl_stats,
2337};
2338
2339static const struct rtl_chip_info *rtl8169_get_chip_version(u16 xid, bool gmii)
2340{
2341 /* Chips combining a 1Gbps MAC with a 100Mbps PHY */
2342 static const struct rtl_chip_info rtl8106eus_info = {
2343 .mac_version = RTL_GIGA_MAC_VER_43,
2344 .name = "RTL8106eus",
2345 .fw_name = FIRMWARE_8106E_2,
2346 };
2347 static const struct rtl_chip_info rtl8107e_info = {
2348 .mac_version = RTL_GIGA_MAC_VER_48,
2349 .name = "RTL8107e",
2350 .fw_name = FIRMWARE_8107E_2,
2351 };
2352 const struct rtl_chip_info *p = rtl_chip_infos;
2353
2354 while ((xid & p->mask) != p->val)
2355 p++;
2356
2357 if (p->mac_version == RTL_GIGA_MAC_VER_42 && !gmii)
2358 return &rtl8106eus_info;
2359 if (p->mac_version == RTL_GIGA_MAC_VER_46 && !gmii)
2360 return &rtl8107e_info;
2361
2362 return p;
2363}
2364
2365static void rtl_release_firmware(struct rtl8169_private *tp)
2366{
2367 if (tp->rtl_fw) {
2368 rtl_fw_release_firmware(rtl_fw: tp->rtl_fw);
2369 kfree(objp: tp->rtl_fw);
2370 tp->rtl_fw = NULL;
2371 }
2372}
2373
2374void r8169_apply_firmware(struct rtl8169_private *tp)
2375{
2376 int val;
2377
2378 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */
2379 if (tp->rtl_fw) {
2380 rtl_fw_write_firmware(tp, rtl_fw: tp->rtl_fw);
2381 /* At least one firmware doesn't reset tp->ocp_base. */
2382 tp->ocp_base = OCP_STD_PHY_BASE;
2383
2384 /* PHY soft reset may still be in progress */
2385 phy_read_poll_timeout(tp->phydev, MII_BMCR, val,
2386 !(val & BMCR_RESET),
2387 50000, 600000, true);
2388 }
2389}
2390
2391static void rtl_rar_exgmac_set(struct rtl8169_private *tp, const u8 *addr)
2392{
2393 rtl_eri_write(tp, addr: 0xe0, ERIAR_MASK_1111, val: get_unaligned_le32(p: addr));
2394 rtl_eri_write(tp, addr: 0xe4, ERIAR_MASK_1111, val: get_unaligned_le16(p: addr + 4));
2395 rtl_eri_write(tp, addr: 0xf0, ERIAR_MASK_1111, val: get_unaligned_le16(p: addr) << 16);
2396 rtl_eri_write(tp, addr: 0xf4, ERIAR_MASK_1111, val: get_unaligned_le32(p: addr + 2));
2397}
2398
2399u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp)
2400{
2401 u16 data1, data2, ioffset;
2402
2403 r8168_mac_ocp_write(tp, reg: 0xdd02, data: 0x807d);
2404 data1 = r8168_mac_ocp_read(tp, reg: 0xdd02);
2405 data2 = r8168_mac_ocp_read(tp, reg: 0xdd00);
2406
2407 ioffset = (data2 >> 1) & 0x7ff8;
2408 ioffset |= data2 & 0x0007;
2409 if (data1 & BIT(7))
2410 ioffset |= BIT(15);
2411
2412 return ioffset;
2413}
2414
2415static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
2416{
2417 set_bit(nr: flag, addr: tp->wk.flags);
2418 if (!schedule_work(work: &tp->wk.work))
2419 clear_bit(nr: flag, addr: tp->wk.flags);
2420}
2421
2422static void rtl8169_init_phy(struct rtl8169_private *tp)
2423{
2424 r8169_hw_phy_config(tp, phydev: tp->phydev, ver: tp->mac_version);
2425
2426 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2427 pci_write_config_byte(dev: tp->pci_dev, PCI_LATENCY_TIMER, val: 0x40);
2428 pci_write_config_byte(dev: tp->pci_dev, PCI_CACHE_LINE_SIZE, val: 0x08);
2429 /* set undocumented MAC Reg C+CR Offset 0x82h */
2430 RTL_W8(tp, 0x82, 0x01);
2431 }
2432
2433 if (tp->mac_version == RTL_GIGA_MAC_VER_05 &&
2434 tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE &&
2435 tp->pci_dev->subsystem_device == 0xe000)
2436 phy_write_paged(phydev: tp->phydev, page: 0x0001, regnum: 0x10, val: 0xf01b);
2437
2438 /* We may have called phy_speed_down before */
2439 phy_speed_up(phydev: tp->phydev);
2440
2441 genphy_soft_reset(phydev: tp->phydev);
2442}
2443
2444static void rtl_rar_set(struct rtl8169_private *tp, const u8 *addr)
2445{
2446 rtl_unlock_config_regs(tp);
2447
2448 RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4));
2449 rtl_pci_commit(tp);
2450
2451 RTL_W32(tp, MAC0, get_unaligned_le32(addr));
2452 rtl_pci_commit(tp);
2453
2454 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
2455 rtl_rar_exgmac_set(tp, addr);
2456
2457 rtl_lock_config_regs(tp);
2458}
2459
2460static int rtl_set_mac_address(struct net_device *dev, void *p)
2461{
2462 struct rtl8169_private *tp = netdev_priv(dev);
2463 int ret;
2464
2465 ret = eth_mac_addr(dev, p);
2466 if (ret)
2467 return ret;
2468
2469 rtl_rar_set(tp, addr: dev->dev_addr);
2470
2471 return 0;
2472}
2473
2474static void rtl_init_rxcfg(struct rtl8169_private *tp)
2475{
2476 switch (tp->mac_version) {
2477 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
2478 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
2479 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
2480 break;
2481 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
2482 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
2483 case RTL_GIGA_MAC_VER_38:
2484 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
2485 break;
2486 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52:
2487 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
2488 break;
2489 case RTL_GIGA_MAC_VER_61:
2490 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST);
2491 break;
2492 case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_LAST:
2493 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST |
2494 RX_PAUSE_SLOT_ON);
2495 break;
2496 default:
2497 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
2498 break;
2499 }
2500}
2501
2502static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2503{
2504 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
2505}
2506
2507static void rtl_jumbo_config(struct rtl8169_private *tp)
2508{
2509 bool jumbo = tp->dev->mtu > ETH_DATA_LEN;
2510 int readrq = 4096;
2511
2512 if (jumbo && tp->mac_version >= RTL_GIGA_MAC_VER_17 &&
2513 tp->mac_version <= RTL_GIGA_MAC_VER_26)
2514 readrq = 512;
2515
2516 rtl_unlock_config_regs(tp);
2517 switch (tp->mac_version) {
2518 case RTL_GIGA_MAC_VER_17:
2519 r8169_mod_reg8_cond(tp, reg: Config4, BIT(0), cond: jumbo);
2520 break;
2521 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
2522 r8169_mod_reg8_cond(tp, reg: Config3, bits: Jumbo_En0, cond: jumbo);
2523 r8169_mod_reg8_cond(tp, reg: Config4, bits: Jumbo_En1, cond: jumbo);
2524 break;
2525 case RTL_GIGA_MAC_VER_28:
2526 r8169_mod_reg8_cond(tp, reg: Config3, bits: Jumbo_En0, cond: jumbo);
2527 break;
2528 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33:
2529 RTL_W8(tp, MaxTxPacketSize, jumbo ? 0x24 : 0x3f);
2530 r8169_mod_reg8_cond(tp, reg: Config3, bits: Jumbo_En0, cond: jumbo);
2531 r8169_mod_reg8_cond(tp, reg: Config4, BIT(0), cond: jumbo);
2532 break;
2533 default:
2534 break;
2535 }
2536 rtl_lock_config_regs(tp);
2537
2538 if (pci_is_pcie(dev: tp->pci_dev) && tp->supports_gmii)
2539 pcie_set_readrq(dev: tp->pci_dev, rq: readrq);
2540
2541 /* Chip doesn't support pause in jumbo mode */
2542 if (jumbo) {
2543 linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT,
2544 tp->phydev->advertising);
2545 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
2546 tp->phydev->advertising);
2547 phy_start_aneg(phydev: tp->phydev);
2548 }
2549}
2550
2551DECLARE_RTL_COND(rtl_chipcmd_cond)
2552{
2553 return RTL_R8(tp, ChipCmd) & CmdReset;
2554}
2555
2556static void rtl_hw_reset(struct rtl8169_private *tp)
2557{
2558 RTL_W8(tp, ChipCmd, CmdReset);
2559
2560 rtl_loop_wait_low(tp, c: &rtl_chipcmd_cond, d: 100, n: 100);
2561}
2562
2563static void rtl_request_firmware(struct rtl8169_private *tp)
2564{
2565 struct rtl_fw *rtl_fw;
2566
2567 /* firmware loaded already or no firmware available */
2568 if (tp->rtl_fw || !tp->fw_name)
2569 return;
2570
2571 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
2572 if (!rtl_fw)
2573 return;
2574
2575 rtl_fw->phy_write = rtl_writephy;
2576 rtl_fw->phy_read = rtl_readphy;
2577 rtl_fw->mac_mcu_write = mac_mcu_write;
2578 rtl_fw->mac_mcu_read = mac_mcu_read;
2579 rtl_fw->fw_name = tp->fw_name;
2580 rtl_fw->dev = tp_to_dev(tp);
2581
2582 if (rtl_fw_request_firmware(rtl_fw))
2583 kfree(objp: rtl_fw);
2584 else
2585 tp->rtl_fw = rtl_fw;
2586}
2587
2588static void rtl_rx_close(struct rtl8169_private *tp)
2589{
2590 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
2591}
2592
2593DECLARE_RTL_COND(rtl_npq_cond)
2594{
2595 return RTL_R8(tp, TxPoll) & NPQ;
2596}
2597
2598DECLARE_RTL_COND(rtl_txcfg_empty_cond)
2599{
2600 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
2601}
2602
2603DECLARE_RTL_COND(rtl_rxtx_empty_cond)
2604{
2605 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
2606}
2607
2608DECLARE_RTL_COND(rtl_rxtx_empty_cond_2)
2609{
2610 /* IntrMitigate has new functionality on RTL8125 */
2611 return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103;
2612}
2613
2614static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp)
2615{
2616 switch (tp->mac_version) {
2617 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52:
2618 rtl_loop_wait_high(tp, c: &rtl_txcfg_empty_cond, d: 100, n: 42);
2619 rtl_loop_wait_high(tp, c: &rtl_rxtx_empty_cond, d: 100, n: 42);
2620 break;
2621 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_61:
2622 rtl_loop_wait_high(tp, c: &rtl_rxtx_empty_cond, d: 100, n: 42);
2623 break;
2624 case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_LAST:
2625 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
2626 rtl_loop_wait_high(tp, c: &rtl_rxtx_empty_cond, d: 100, n: 42);
2627 rtl_loop_wait_high(tp, c: &rtl_rxtx_empty_cond_2, d: 100, n: 42);
2628 break;
2629 default:
2630 break;
2631 }
2632}
2633
2634static void rtl_disable_rxdvgate(struct rtl8169_private *tp)
2635{
2636 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
2637}
2638
2639static void rtl_enable_rxdvgate(struct rtl8169_private *tp)
2640{
2641 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
2642 fsleep(usecs: 2000);
2643 rtl_wait_txrx_fifo_empty(tp);
2644}
2645
2646static void rtl_wol_enable_rx(struct rtl8169_private *tp)
2647{
2648 if (tp->mac_version >= RTL_GIGA_MAC_VER_25)
2649 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
2650 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
2651
2652 if (tp->mac_version >= RTL_GIGA_MAC_VER_40)
2653 rtl_disable_rxdvgate(tp);
2654}
2655
2656static void rtl_prepare_power_down(struct rtl8169_private *tp)
2657{
2658 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
2659 tp->mac_version == RTL_GIGA_MAC_VER_33)
2660 rtl_ephy_write(tp, reg_addr: 0x19, value: 0xff64);
2661
2662 if (device_may_wakeup(dev: tp_to_dev(tp))) {
2663 phy_speed_down(phydev: tp->phydev, sync: false);
2664 rtl_wol_enable_rx(tp);
2665 }
2666}
2667
2668static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
2669{
2670 u32 val = TX_DMA_BURST << TxDMAShift |
2671 InterFrameGap << TxInterFrameGapShift;
2672
2673 if (rtl_is_8168evl_up(tp))
2674 val |= TXCFG_AUTO_FIFO;
2675
2676 RTL_W32(tp, TxConfig, val);
2677}
2678
2679static void rtl_set_rx_max_size(struct rtl8169_private *tp)
2680{
2681 /* Low hurts. Let's disable the filtering. */
2682 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
2683}
2684
2685static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
2686{
2687 /*
2688 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2689 * register to be written before TxDescAddrLow to work.
2690 * Switching from MMIO to I/O access fixes the issue as well.
2691 */
2692 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
2693 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
2694 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
2695 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
2696}
2697
2698static void rtl8169_set_magic_reg(struct rtl8169_private *tp)
2699{
2700 u32 val;
2701
2702 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
2703 val = 0x000fff00;
2704 else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
2705 val = 0x00ffff00;
2706 else
2707 return;
2708
2709 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
2710 val |= 0xff;
2711
2712 RTL_W32(tp, 0x7c, val);
2713}
2714
2715static void rtl_set_rx_mode(struct net_device *dev)
2716{
2717 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast;
2718 /* Multicast hash filter */
2719 u32 mc_filter[2] = { 0xffffffff, 0xffffffff };
2720 struct rtl8169_private *tp = netdev_priv(dev);
2721 u32 tmp;
2722
2723 if (dev->flags & IFF_PROMISC) {
2724 rx_mode |= AcceptAllPhys;
2725 } else if (!(dev->flags & IFF_MULTICAST)) {
2726 rx_mode &= ~AcceptMulticast;
2727 } else if (dev->flags & IFF_ALLMULTI ||
2728 tp->mac_version == RTL_GIGA_MAC_VER_35) {
2729 /* accept all multicasts */
2730 } else if (netdev_mc_empty(dev)) {
2731 rx_mode &= ~AcceptMulticast;
2732 } else {
2733 struct netdev_hw_addr *ha;
2734
2735 mc_filter[1] = mc_filter[0] = 0;
2736 netdev_for_each_mc_addr(ha, dev) {
2737 u32 bit_nr = eth_hw_addr_crc(ha) >> 26;
2738 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31);
2739 }
2740
2741 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
2742 tmp = mc_filter[0];
2743 mc_filter[0] = swab32(mc_filter[1]);
2744 mc_filter[1] = swab32(tmp);
2745 }
2746 }
2747
2748 RTL_W32(tp, MAR0 + 4, mc_filter[1]);
2749 RTL_W32(tp, MAR0 + 0, mc_filter[0]);
2750
2751 tmp = RTL_R32(tp, RxConfig);
2752 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode);
2753}
2754
2755DECLARE_RTL_COND(rtl_csiar_cond)
2756{
2757 return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
2758}
2759
2760static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
2761{
2762 u32 func = PCI_FUNC(tp->pci_dev->devfn);
2763
2764 RTL_W32(tp, CSIDR, value);
2765 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
2766 CSIAR_BYTE_ENABLE | func << 16);
2767
2768 rtl_loop_wait_low(tp, c: &rtl_csiar_cond, d: 10, n: 100);
2769}
2770
2771static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
2772{
2773 u32 func = PCI_FUNC(tp->pci_dev->devfn);
2774
2775 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
2776 CSIAR_BYTE_ENABLE);
2777
2778 return rtl_loop_wait_high(tp, c: &rtl_csiar_cond, d: 10, n: 100) ?
2779 RTL_R32(tp, CSIDR) : ~0;
2780}
2781
2782static void rtl_csi_mod(struct rtl8169_private *tp, int addr,
2783 u32 mask, u32 set)
2784{
2785 u32 val;
2786
2787 WARN(addr % 4, "Invalid CSI address %#x\n", addr);
2788
2789 netdev_notice_once(tp->dev,
2790 "No native access to PCI extended config space, falling back to CSI\n");
2791
2792 val = rtl_csi_read(tp, addr);
2793 rtl_csi_write(tp, addr, value: (val & ~mask) | set);
2794}
2795
2796static void rtl_disable_zrxdc_timeout(struct rtl8169_private *tp)
2797{
2798 struct pci_dev *pdev = tp->pci_dev;
2799 int rc;
2800 u8 val;
2801
2802#define RTL_GEN3_RELATED_OFF 0x0890
2803#define RTL_GEN3_ZRXDC_NONCOMPL 0x1
2804 if (pdev->cfg_size > RTL_GEN3_RELATED_OFF) {
2805 rc = pci_read_config_byte(dev: pdev, RTL_GEN3_RELATED_OFF, val: &val);
2806 if (rc == PCIBIOS_SUCCESSFUL) {
2807 val &= ~RTL_GEN3_ZRXDC_NONCOMPL;
2808 rc = pci_write_config_byte(dev: pdev, RTL_GEN3_RELATED_OFF,
2809 val);
2810 if (rc == PCIBIOS_SUCCESSFUL)
2811 return;
2812 }
2813 }
2814
2815 rtl_csi_mod(tp, RTL_GEN3_RELATED_OFF, RTL_GEN3_ZRXDC_NONCOMPL, set: 0);
2816}
2817
2818static void rtl_set_aspm_entry_latency(struct rtl8169_private *tp, u8 val)
2819{
2820 struct pci_dev *pdev = tp->pci_dev;
2821
2822 /* According to Realtek the value at config space address 0x070f
2823 * controls the L0s/L1 entrance latency. We try standard ECAM access
2824 * first and if it fails fall back to CSI.
2825 * bit 0..2: L0: 0 = 1us, 1 = 2us .. 6 = 7us, 7 = 7us (no typo)
2826 * bit 3..5: L1: 0 = 1us, 1 = 2us .. 6 = 64us, 7 = 64us
2827 */
2828 if (pdev->cfg_size > 0x070f &&
2829 pci_write_config_byte(dev: pdev, where: 0x070f, val) == PCIBIOS_SUCCESSFUL)
2830 return;
2831
2832 rtl_csi_mod(tp, addr: 0x070c, mask: 0xff000000, set: val << 24);
2833}
2834
2835static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
2836{
2837 /* L0 7us, L1 16us */
2838 rtl_set_aspm_entry_latency(tp, val: 0x27);
2839}
2840
2841struct ephy_info {
2842 unsigned int offset;
2843 u16 mask;
2844 u16 bits;
2845};
2846
2847static void __rtl_ephy_init(struct rtl8169_private *tp,
2848 const struct ephy_info *e, int len)
2849{
2850 u16 w;
2851
2852 while (len-- > 0) {
2853 w = (rtl_ephy_read(tp, reg_addr: e->offset) & ~e->mask) | e->bits;
2854 rtl_ephy_write(tp, reg_addr: e->offset, value: w);
2855 e++;
2856 }
2857}
2858
2859#define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
2860
2861static void rtl_disable_clock_request(struct rtl8169_private *tp)
2862{
2863 pcie_capability_clear_word(dev: tp->pci_dev, PCI_EXP_LNKCTL,
2864 PCI_EXP_LNKCTL_CLKREQ_EN);
2865}
2866
2867static void rtl_enable_clock_request(struct rtl8169_private *tp)
2868{
2869 pcie_capability_set_word(dev: tp->pci_dev, PCI_EXP_LNKCTL,
2870 PCI_EXP_LNKCTL_CLKREQ_EN);
2871}
2872
2873static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
2874{
2875 /* work around an issue when PCI reset occurs during L2/L3 state */
2876 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
2877}
2878
2879static void rtl_enable_exit_l1(struct rtl8169_private *tp)
2880{
2881 /* Bits control which events trigger ASPM L1 exit:
2882 * Bit 12: rxdv
2883 * Bit 11: ltr_msg
2884 * Bit 10: txdma_poll
2885 * Bit 9: xadm
2886 * Bit 8: pktavi
2887 * Bit 7: txpla
2888 */
2889 switch (tp->mac_version) {
2890 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
2891 rtl_eri_set_bits(tp, addr: 0xd4, p: 0x1f00);
2892 break;
2893 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_38:
2894 rtl_eri_set_bits(tp, addr: 0xd4, p: 0x0c00);
2895 break;
2896 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_LAST:
2897 r8168_mac_ocp_modify(tp, reg: 0xc0ac, mask: 0, set: 0x1f80);
2898 break;
2899 default:
2900 break;
2901 }
2902}
2903
2904static void rtl_disable_exit_l1(struct rtl8169_private *tp)
2905{
2906 switch (tp->mac_version) {
2907 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
2908 rtl_eri_clear_bits(tp, addr: 0xd4, m: 0x1f00);
2909 break;
2910 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_LAST:
2911 r8168_mac_ocp_modify(tp, reg: 0xc0ac, mask: 0x1f80, set: 0);
2912 break;
2913 default:
2914 break;
2915 }
2916}
2917
2918static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
2919{
2920 u8 val8;
2921
2922 if (tp->mac_version < RTL_GIGA_MAC_VER_32)
2923 return;
2924
2925 /* Don't enable ASPM in the chip if OS can't control ASPM */
2926 if (enable && tp->aspm_manageable) {
2927 /* On these chip versions ASPM can even harm
2928 * bus communication of other PCI devices.
2929 */
2930 if (tp->mac_version == RTL_GIGA_MAC_VER_42 ||
2931 tp->mac_version == RTL_GIGA_MAC_VER_43)
2932 return;
2933
2934 rtl_mod_config5(tp, clear: 0, set: ASPM_en);
2935 switch (tp->mac_version) {
2936 case RTL_GIGA_MAC_VER_70:
2937 case RTL_GIGA_MAC_VER_80:
2938 val8 = RTL_R8(tp, INT_CFG0_8125) | INT_CFG0_CLKREQEN;
2939 RTL_W8(tp, INT_CFG0_8125, val8);
2940 break;
2941 default:
2942 rtl_mod_config2(tp, clear: 0, set: ClkReqEn);
2943 break;
2944 }
2945
2946 switch (tp->mac_version) {
2947 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48:
2948 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST:
2949 /* reset ephy tx/rx disable timer */
2950 r8168_mac_ocp_modify(tp, reg: 0xe094, mask: 0xff00, set: 0);
2951 /* chip can trigger L1.2 */
2952 r8168_mac_ocp_modify(tp, reg: 0xe092, mask: 0x00ff, BIT(2));
2953 break;
2954 default:
2955 break;
2956 }
2957 } else {
2958 switch (tp->mac_version) {
2959 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48:
2960 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST:
2961 r8168_mac_ocp_modify(tp, reg: 0xe092, mask: 0x00ff, set: 0);
2962 break;
2963 default:
2964 break;
2965 }
2966
2967 switch (tp->mac_version) {
2968 case RTL_GIGA_MAC_VER_70:
2969 case RTL_GIGA_MAC_VER_80:
2970 val8 = RTL_R8(tp, INT_CFG0_8125) & ~INT_CFG0_CLKREQEN;
2971 RTL_W8(tp, INT_CFG0_8125, val8);
2972 break;
2973 default:
2974 rtl_mod_config2(tp, clear: ClkReqEn, set: 0);
2975 break;
2976 }
2977 rtl_mod_config5(tp, clear: ASPM_en, set: 0);
2978 }
2979}
2980
2981static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,
2982 u16 tx_stat, u16 rx_dyn, u16 tx_dyn)
2983{
2984 /* Usage of dynamic vs. static FIFO is controlled by bit
2985 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known.
2986 */
2987 rtl_eri_write(tp, addr: 0xc8, ERIAR_MASK_1111, val: (rx_stat << 16) | rx_dyn);
2988 rtl_eri_write(tp, addr: 0xe8, ERIAR_MASK_1111, val: (tx_stat << 16) | tx_dyn);
2989}
2990
2991static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,
2992 u8 low, u8 high)
2993{
2994 /* FIFO thresholds for pause flow control */
2995 rtl_eri_write(tp, addr: 0xcc, ERIAR_MASK_0001, val: low);
2996 rtl_eri_write(tp, addr: 0xd0, ERIAR_MASK_0001, val: high);
2997}
2998
2999static void rtl_hw_start_8168b(struct rtl8169_private *tp)
3000{
3001 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3002}
3003
3004static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
3005{
3006 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
3007
3008 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3009
3010 rtl_disable_clock_request(tp);
3011}
3012
3013static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
3014{
3015 static const struct ephy_info e_info_8168cp[] = {
3016 { 0x01, 0, 0x0001 },
3017 { 0x02, 0x0800, 0x1000 },
3018 { 0x03, 0, 0x0042 },
3019 { 0x06, 0x0080, 0x0000 },
3020 { 0x07, 0, 0x2000 }
3021 };
3022
3023 rtl_set_def_aspm_entry_latency(tp);
3024
3025 rtl_ephy_init(tp, e_info_8168cp);
3026
3027 __rtl_hw_start_8168cp(tp);
3028}
3029
3030static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
3031{
3032 rtl_set_def_aspm_entry_latency(tp);
3033
3034 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3035}
3036
3037static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
3038{
3039 rtl_set_def_aspm_entry_latency(tp);
3040
3041 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3042
3043 /* Magic. */
3044 RTL_W8(tp, DBG_REG, 0x20);
3045}
3046
3047static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
3048{
3049 static const struct ephy_info e_info_8168c_1[] = {
3050 { 0x02, 0x0800, 0x1000 },
3051 { 0x03, 0, 0x0002 },
3052 { 0x06, 0x0080, 0x0000 }
3053 };
3054
3055 rtl_set_def_aspm_entry_latency(tp);
3056
3057 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3058
3059 rtl_ephy_init(tp, e_info_8168c_1);
3060
3061 __rtl_hw_start_8168cp(tp);
3062}
3063
3064static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
3065{
3066 static const struct ephy_info e_info_8168c_2[] = {
3067 { 0x01, 0, 0x0001 },
3068 { 0x03, 0x0400, 0x0020 }
3069 };
3070
3071 rtl_set_def_aspm_entry_latency(tp);
3072
3073 rtl_ephy_init(tp, e_info_8168c_2);
3074
3075 __rtl_hw_start_8168cp(tp);
3076}
3077
3078static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
3079{
3080 rtl_set_def_aspm_entry_latency(tp);
3081
3082 __rtl_hw_start_8168cp(tp);
3083}
3084
3085static void rtl_hw_start_8168d(struct rtl8169_private *tp)
3086{
3087 rtl_set_def_aspm_entry_latency(tp);
3088
3089 rtl_disable_clock_request(tp);
3090}
3091
3092static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
3093{
3094 static const struct ephy_info e_info_8168d_4[] = {
3095 { 0x0b, 0x0000, 0x0048 },
3096 { 0x19, 0x0020, 0x0050 },
3097 { 0x0c, 0x0100, 0x0020 },
3098 { 0x10, 0x0004, 0x0000 },
3099 };
3100
3101 rtl_set_def_aspm_entry_latency(tp);
3102
3103 rtl_ephy_init(tp, e_info_8168d_4);
3104
3105 rtl_enable_clock_request(tp);
3106}
3107
3108static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
3109{
3110 static const struct ephy_info e_info_8168e_1[] = {
3111 { 0x00, 0x0200, 0x0100 },
3112 { 0x00, 0x0000, 0x0004 },
3113 { 0x06, 0x0002, 0x0001 },
3114 { 0x06, 0x0000, 0x0030 },
3115 { 0x07, 0x0000, 0x2000 },
3116 { 0x00, 0x0000, 0x0020 },
3117 { 0x03, 0x5800, 0x2000 },
3118 { 0x03, 0x0000, 0x0001 },
3119 { 0x01, 0x0800, 0x1000 },
3120 { 0x07, 0x0000, 0x4000 },
3121 { 0x1e, 0x0000, 0x2000 },
3122 { 0x19, 0xffff, 0xfe6c },
3123 { 0x0a, 0x0000, 0x0040 }
3124 };
3125
3126 rtl_set_def_aspm_entry_latency(tp);
3127
3128 rtl_ephy_init(tp, e_info_8168e_1);
3129
3130 rtl_disable_clock_request(tp);
3131
3132 /* Reset tx FIFO pointer */
3133 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
3134 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
3135
3136 rtl_mod_config5(tp, clear: Spi_en, set: 0);
3137}
3138
3139static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
3140{
3141 static const struct ephy_info e_info_8168e_2[] = {
3142 { 0x09, 0x0000, 0x0080 },
3143 { 0x19, 0x0000, 0x0224 },
3144 { 0x00, 0x0000, 0x0004 },
3145 { 0x0c, 0x3df0, 0x0200 },
3146 };
3147
3148 rtl_set_def_aspm_entry_latency(tp);
3149
3150 rtl_ephy_init(tp, e_info_8168e_2);
3151
3152 rtl_eri_write(tp, addr: 0xc0, ERIAR_MASK_0011, val: 0x0000);
3153 rtl_eri_write(tp, addr: 0xb8, ERIAR_MASK_1111, val: 0x0000);
3154 rtl_set_fifo_size(tp, rx_stat: 0x10, tx_stat: 0x10, rx_dyn: 0x02, tx_dyn: 0x06);
3155 rtl_eri_set_bits(tp, addr: 0x1d0, BIT(1));
3156 rtl_reset_packet_filter(tp);
3157 rtl_eri_set_bits(tp, addr: 0x1b0, BIT(4));
3158 rtl_eri_write(tp, addr: 0xcc, ERIAR_MASK_1111, val: 0x00000050);
3159 rtl_eri_write(tp, addr: 0xd0, ERIAR_MASK_1111, val: 0x07ff0060);
3160
3161 rtl_disable_clock_request(tp);
3162
3163 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
3164
3165 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
3166 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
3167 rtl_mod_config5(tp, clear: Spi_en, set: 0);
3168}
3169
3170static void rtl_hw_start_8168f(struct rtl8169_private *tp)
3171{
3172 rtl_set_def_aspm_entry_latency(tp);
3173
3174 rtl_eri_write(tp, addr: 0xc0, ERIAR_MASK_0011, val: 0x0000);
3175 rtl_eri_write(tp, addr: 0xb8, ERIAR_MASK_1111, val: 0x0000);
3176 rtl_set_fifo_size(tp, rx_stat: 0x10, tx_stat: 0x10, rx_dyn: 0x02, tx_dyn: 0x06);
3177 rtl_reset_packet_filter(tp);
3178 rtl_eri_set_bits(tp, addr: 0x1b0, BIT(4));
3179 rtl_eri_set_bits(tp, addr: 0x1d0, BIT(4) | BIT(1));
3180 rtl_eri_write(tp, addr: 0xcc, ERIAR_MASK_1111, val: 0x00000050);
3181 rtl_eri_write(tp, addr: 0xd0, ERIAR_MASK_1111, val: 0x00000060);
3182
3183 rtl_disable_clock_request(tp);
3184
3185 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
3186 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
3187 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
3188 rtl_mod_config5(tp, clear: Spi_en, set: 0);
3189}
3190
3191static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
3192{
3193 static const struct ephy_info e_info_8168f_1[] = {
3194 { 0x06, 0x00c0, 0x0020 },
3195 { 0x08, 0x0001, 0x0002 },
3196 { 0x09, 0x0000, 0x0080 },
3197 { 0x19, 0x0000, 0x0224 },
3198 { 0x00, 0x0000, 0x0008 },
3199 { 0x0c, 0x3df0, 0x0200 },
3200 };
3201
3202 rtl_hw_start_8168f(tp);
3203
3204 rtl_ephy_init(tp, e_info_8168f_1);
3205}
3206
3207static void rtl_hw_start_8411(struct rtl8169_private *tp)
3208{
3209 static const struct ephy_info e_info_8168f_1[] = {
3210 { 0x06, 0x00c0, 0x0020 },
3211 { 0x0f, 0xffff, 0x5200 },
3212 { 0x19, 0x0000, 0x0224 },
3213 { 0x00, 0x0000, 0x0008 },
3214 { 0x0c, 0x3df0, 0x0200 },
3215 };
3216
3217 rtl_hw_start_8168f(tp);
3218 rtl_pcie_state_l2l3_disable(tp);
3219
3220 rtl_ephy_init(tp, e_info_8168f_1);
3221}
3222
3223static void rtl_hw_start_8168g(struct rtl8169_private *tp)
3224{
3225 rtl_set_fifo_size(tp, rx_stat: 0x08, tx_stat: 0x10, rx_dyn: 0x02, tx_dyn: 0x06);
3226 rtl8168g_set_pause_thresholds(tp, low: 0x38, high: 0x48);
3227
3228 rtl_set_def_aspm_entry_latency(tp);
3229
3230 rtl_reset_packet_filter(tp);
3231 rtl_eri_write(tp, addr: 0x2f8, ERIAR_MASK_0011, val: 0x1d8f);
3232
3233 rtl_disable_rxdvgate(tp);
3234
3235 rtl_eri_write(tp, addr: 0xc0, ERIAR_MASK_0011, val: 0x0000);
3236 rtl_eri_write(tp, addr: 0xb8, ERIAR_MASK_0011, val: 0x0000);
3237
3238 rtl_w0w1_eri(tp, addr: 0x2fc, p: 0x01, m: 0x06);
3239 rtl_eri_clear_bits(tp, addr: 0x1b0, BIT(12));
3240
3241 rtl_pcie_state_l2l3_disable(tp);
3242}
3243
3244static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
3245{
3246 static const struct ephy_info e_info_8168g_1[] = {
3247 { 0x00, 0x0008, 0x0000 },
3248 { 0x0c, 0x3ff0, 0x0820 },
3249 { 0x1e, 0x0000, 0x0001 },
3250 { 0x19, 0x8000, 0x0000 }
3251 };
3252
3253 rtl_hw_start_8168g(tp);
3254 rtl_ephy_init(tp, e_info_8168g_1);
3255}
3256
3257static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
3258{
3259 static const struct ephy_info e_info_8168g_2[] = {
3260 { 0x00, 0x0008, 0x0000 },
3261 { 0x0c, 0x3ff0, 0x0820 },
3262 { 0x19, 0xffff, 0x7c00 },
3263 { 0x1e, 0xffff, 0x20eb },
3264 { 0x0d, 0xffff, 0x1666 },
3265 { 0x00, 0xffff, 0x10a3 },
3266 { 0x06, 0xffff, 0xf050 },
3267 { 0x04, 0x0000, 0x0010 },
3268 { 0x1d, 0x4000, 0x0000 },
3269 };
3270
3271 rtl_hw_start_8168g(tp);
3272 rtl_ephy_init(tp, e_info_8168g_2);
3273}
3274
3275static void rtl8411b_fix_phy_down(struct rtl8169_private *tp)
3276{
3277 static const u16 fix_data[] = {
3278/* 0xf800 */ 0xe008, 0xe00a, 0xe00c, 0xe00e, 0xe027, 0xe04f, 0xe05e, 0xe065,
3279/* 0xf810 */ 0xc602, 0xbe00, 0x0000, 0xc502, 0xbd00, 0x074c, 0xc302, 0xbb00,
3280/* 0xf820 */ 0x080a, 0x6420, 0x48c2, 0x8c20, 0xc516, 0x64a4, 0x49c0, 0xf009,
3281/* 0xf830 */ 0x74a2, 0x8ca5, 0x74a0, 0xc50e, 0x9ca2, 0x1c11, 0x9ca0, 0xe006,
3282/* 0xf840 */ 0x74f8, 0x48c4, 0x8cf8, 0xc404, 0xbc00, 0xc403, 0xbc00, 0x0bf2,
3283/* 0xf850 */ 0x0c0a, 0xe434, 0xd3c0, 0x49d9, 0xf01f, 0xc526, 0x64a5, 0x1400,
3284/* 0xf860 */ 0xf007, 0x0c01, 0x8ca5, 0x1c15, 0xc51b, 0x9ca0, 0xe013, 0xc519,
3285/* 0xf870 */ 0x74a0, 0x48c4, 0x8ca0, 0xc516, 0x74a4, 0x48c8, 0x48ca, 0x9ca4,
3286/* 0xf880 */ 0xc512, 0x1b00, 0x9ba0, 0x1b1c, 0x483f, 0x9ba2, 0x1b04, 0xc508,
3287/* 0xf890 */ 0x9ba0, 0xc505, 0xbd00, 0xc502, 0xbd00, 0x0300, 0x051e, 0xe434,
3288/* 0xf8a0 */ 0xe018, 0xe092, 0xde20, 0xd3c0, 0xc50f, 0x76a4, 0x49e3, 0xf007,
3289/* 0xf8b0 */ 0x49c0, 0xf103, 0xc607, 0xbe00, 0xc606, 0xbe00, 0xc602, 0xbe00,
3290/* 0xf8c0 */ 0x0c4c, 0x0c28, 0x0c2c, 0xdc00, 0xc707, 0x1d00, 0x8de2, 0x48c1,
3291/* 0xf8d0 */ 0xc502, 0xbd00, 0x00aa, 0xe0c0, 0xc502, 0xbd00, 0x0132
3292 };
3293 unsigned long flags;
3294 int i;
3295
3296 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags);
3297 for (i = 0; i < ARRAY_SIZE(fix_data); i++)
3298 __r8168_mac_ocp_write(tp, reg: 0xf800 + 2 * i, data: fix_data[i]);
3299 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags);
3300}
3301
3302static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
3303{
3304 static const struct ephy_info e_info_8411_2[] = {
3305 { 0x00, 0x0008, 0x0000 },
3306 { 0x0c, 0x37d0, 0x0820 },
3307 { 0x1e, 0x0000, 0x0001 },
3308 { 0x19, 0x8021, 0x0000 },
3309 { 0x1e, 0x0000, 0x2000 },
3310 { 0x0d, 0x0100, 0x0200 },
3311 { 0x00, 0x0000, 0x0080 },
3312 { 0x06, 0x0000, 0x0010 },
3313 { 0x04, 0x0000, 0x0010 },
3314 { 0x1d, 0x0000, 0x4000 },
3315 };
3316
3317 rtl_hw_start_8168g(tp);
3318
3319 rtl_ephy_init(tp, e_info_8411_2);
3320
3321 /* The following Realtek-provided magic fixes an issue with the RX unit
3322 * getting confused after the PHY having been powered-down.
3323 */
3324 r8168_mac_ocp_write(tp, reg: 0xFC28, data: 0x0000);
3325 r8168_mac_ocp_write(tp, reg: 0xFC2A, data: 0x0000);
3326 r8168_mac_ocp_write(tp, reg: 0xFC2C, data: 0x0000);
3327 r8168_mac_ocp_write(tp, reg: 0xFC2E, data: 0x0000);
3328 r8168_mac_ocp_write(tp, reg: 0xFC30, data: 0x0000);
3329 r8168_mac_ocp_write(tp, reg: 0xFC32, data: 0x0000);
3330 r8168_mac_ocp_write(tp, reg: 0xFC34, data: 0x0000);
3331 r8168_mac_ocp_write(tp, reg: 0xFC36, data: 0x0000);
3332 mdelay(3);
3333 r8168_mac_ocp_write(tp, reg: 0xFC26, data: 0x0000);
3334
3335 rtl8411b_fix_phy_down(tp);
3336
3337 r8168_mac_ocp_write(tp, reg: 0xFC26, data: 0x8000);
3338
3339 r8168_mac_ocp_write(tp, reg: 0xFC2A, data: 0x0743);
3340 r8168_mac_ocp_write(tp, reg: 0xFC2C, data: 0x0801);
3341 r8168_mac_ocp_write(tp, reg: 0xFC2E, data: 0x0BE9);
3342 r8168_mac_ocp_write(tp, reg: 0xFC30, data: 0x02FD);
3343 r8168_mac_ocp_write(tp, reg: 0xFC32, data: 0x0C25);
3344 r8168_mac_ocp_write(tp, reg: 0xFC34, data: 0x00A9);
3345 r8168_mac_ocp_write(tp, reg: 0xFC36, data: 0x012D);
3346}
3347
3348static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
3349{
3350 static const struct ephy_info e_info_8168h_1[] = {
3351 { 0x1e, 0x0800, 0x0001 },
3352 { 0x1d, 0x0000, 0x0800 },
3353 { 0x05, 0xffff, 0x2089 },
3354 { 0x06, 0xffff, 0x5881 },
3355 { 0x04, 0xffff, 0x854a },
3356 { 0x01, 0xffff, 0x068b }
3357 };
3358 int rg_saw_cnt;
3359
3360 rtl_ephy_init(tp, e_info_8168h_1);
3361
3362 rtl_set_fifo_size(tp, rx_stat: 0x08, tx_stat: 0x10, rx_dyn: 0x02, tx_dyn: 0x06);
3363 rtl8168g_set_pause_thresholds(tp, low: 0x38, high: 0x48);
3364
3365 rtl_set_def_aspm_entry_latency(tp);
3366
3367 rtl_reset_packet_filter(tp);
3368
3369 rtl_eri_set_bits(tp, addr: 0xdc, p: 0x001c);
3370
3371 rtl_eri_write(tp, addr: 0x5f0, ERIAR_MASK_0011, val: 0x4f87);
3372
3373 rtl_disable_rxdvgate(tp);
3374
3375 rtl_eri_write(tp, addr: 0xc0, ERIAR_MASK_0011, val: 0x0000);
3376 rtl_eri_write(tp, addr: 0xb8, ERIAR_MASK_0011, val: 0x0000);
3377
3378 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3379 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3380
3381 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3382
3383 rtl_eri_clear_bits(tp, addr: 0x1b0, BIT(12));
3384
3385 rtl_pcie_state_l2l3_disable(tp);
3386
3387 rg_saw_cnt = phy_read_paged(phydev: tp->phydev, page: 0x0c42, regnum: 0x13) & 0x3fff;
3388 if (rg_saw_cnt > 0) {
3389 u16 sw_cnt_1ms_ini;
3390
3391 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
3392 sw_cnt_1ms_ini &= 0x0fff;
3393 r8168_mac_ocp_modify(tp, reg: 0xd412, mask: 0x0fff, set: sw_cnt_1ms_ini);
3394 }
3395
3396 r8168_mac_ocp_modify(tp, reg: 0xe056, mask: 0x00f0, set: 0x0000);
3397 r8168_mac_ocp_modify(tp, reg: 0xe052, mask: 0x6000, set: 0x8008);
3398 r8168_mac_ocp_modify(tp, reg: 0xe0d6, mask: 0x01ff, set: 0x017f);
3399 r8168_mac_ocp_modify(tp, reg: 0xd420, mask: 0x0fff, set: 0x047f);
3400
3401 r8168_mac_ocp_write(tp, reg: 0xe63e, data: 0x0001);
3402 r8168_mac_ocp_write(tp, reg: 0xe63e, data: 0x0000);
3403 r8168_mac_ocp_write(tp, reg: 0xc094, data: 0x0000);
3404 r8168_mac_ocp_write(tp, reg: 0xc09e, data: 0x0000);
3405}
3406
3407static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
3408{
3409 rtl8168ep_stop_cmac(tp);
3410
3411 rtl_set_fifo_size(tp, rx_stat: 0x08, tx_stat: 0x10, rx_dyn: 0x02, tx_dyn: 0x06);
3412 rtl8168g_set_pause_thresholds(tp, low: 0x2f, high: 0x5f);
3413
3414 rtl_set_def_aspm_entry_latency(tp);
3415
3416 rtl_reset_packet_filter(tp);
3417
3418 rtl_eri_write(tp, addr: 0x5f0, ERIAR_MASK_0011, val: 0x4f87);
3419
3420 rtl_disable_rxdvgate(tp);
3421
3422 rtl_eri_write(tp, addr: 0xc0, ERIAR_MASK_0011, val: 0x0000);
3423 rtl_eri_write(tp, addr: 0xb8, ERIAR_MASK_0011, val: 0x0000);
3424
3425 rtl_w0w1_eri(tp, addr: 0x2fc, p: 0x01, m: 0x06);
3426
3427 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3428
3429 rtl_pcie_state_l2l3_disable(tp);
3430}
3431
3432static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
3433{
3434 static const struct ephy_info e_info_8168ep_3[] = {
3435 { 0x00, 0x0000, 0x0080 },
3436 { 0x0d, 0x0100, 0x0200 },
3437 { 0x19, 0x8021, 0x0000 },
3438 { 0x1e, 0x0000, 0x2000 },
3439 };
3440
3441 rtl_ephy_init(tp, e_info_8168ep_3);
3442
3443 rtl_hw_start_8168ep(tp);
3444
3445 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3446 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3447
3448 r8168_mac_ocp_modify(tp, reg: 0xd3e2, mask: 0x0fff, set: 0x0271);
3449 r8168_mac_ocp_modify(tp, reg: 0xd3e4, mask: 0x00ff, set: 0x0000);
3450 r8168_mac_ocp_modify(tp, reg: 0xe860, mask: 0x0000, set: 0x0080);
3451}
3452
3453static void rtl_hw_start_8117(struct rtl8169_private *tp)
3454{
3455 static const struct ephy_info e_info_8117[] = {
3456 { 0x19, 0x0040, 0x1100 },
3457 { 0x59, 0x0040, 0x1100 },
3458 };
3459 int rg_saw_cnt;
3460
3461 rtl8168ep_stop_cmac(tp);
3462 rtl_ephy_init(tp, e_info_8117);
3463
3464 rtl_set_fifo_size(tp, rx_stat: 0x08, tx_stat: 0x10, rx_dyn: 0x02, tx_dyn: 0x06);
3465 rtl8168g_set_pause_thresholds(tp, low: 0x2f, high: 0x5f);
3466
3467 rtl_set_def_aspm_entry_latency(tp);
3468
3469 rtl_reset_packet_filter(tp);
3470
3471 rtl_eri_set_bits(tp, addr: 0xd4, p: 0x0010);
3472
3473 rtl_eri_write(tp, addr: 0x5f0, ERIAR_MASK_0011, val: 0x4f87);
3474
3475 rtl_disable_rxdvgate(tp);
3476
3477 rtl_eri_write(tp, addr: 0xc0, ERIAR_MASK_0011, val: 0x0000);
3478 rtl_eri_write(tp, addr: 0xb8, ERIAR_MASK_0011, val: 0x0000);
3479
3480 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3481 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3482
3483 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3484
3485 rtl_eri_clear_bits(tp, addr: 0x1b0, BIT(12));
3486
3487 rtl_pcie_state_l2l3_disable(tp);
3488
3489 rg_saw_cnt = phy_read_paged(phydev: tp->phydev, page: 0x0c42, regnum: 0x13) & 0x3fff;
3490 if (rg_saw_cnt > 0) {
3491 u16 sw_cnt_1ms_ini;
3492
3493 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff;
3494 r8168_mac_ocp_modify(tp, reg: 0xd412, mask: 0x0fff, set: sw_cnt_1ms_ini);
3495 }
3496
3497 r8168_mac_ocp_modify(tp, reg: 0xe056, mask: 0x00f0, set: 0x0000);
3498 r8168_mac_ocp_write(tp, reg: 0xea80, data: 0x0003);
3499 r8168_mac_ocp_modify(tp, reg: 0xe052, mask: 0x0000, set: 0x0009);
3500 r8168_mac_ocp_modify(tp, reg: 0xd420, mask: 0x0fff, set: 0x047f);
3501
3502 r8168_mac_ocp_write(tp, reg: 0xe63e, data: 0x0001);
3503 r8168_mac_ocp_write(tp, reg: 0xe63e, data: 0x0000);
3504 r8168_mac_ocp_write(tp, reg: 0xc094, data: 0x0000);
3505 r8168_mac_ocp_write(tp, reg: 0xc09e, data: 0x0000);
3506
3507 /* firmware is for MAC only */
3508 r8169_apply_firmware(tp);
3509}
3510
3511static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
3512{
3513 static const struct ephy_info e_info_8102e_1[] = {
3514 { 0x01, 0, 0x6e65 },
3515 { 0x02, 0, 0x091f },
3516 { 0x03, 0, 0xc2f9 },
3517 { 0x06, 0, 0xafb5 },
3518 { 0x07, 0, 0x0e00 },
3519 { 0x19, 0, 0xec80 },
3520 { 0x01, 0, 0x2e65 },
3521 { 0x01, 0, 0x6e65 }
3522 };
3523 u8 cfg1;
3524
3525 rtl_set_def_aspm_entry_latency(tp);
3526
3527 RTL_W8(tp, DBG_REG, FIX_NAK_1);
3528
3529 RTL_W8(tp, Config1,
3530 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3531 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3532
3533 cfg1 = RTL_R8(tp, Config1);
3534 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3535 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
3536
3537 rtl_ephy_init(tp, e_info_8102e_1);
3538}
3539
3540static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
3541{
3542 rtl_set_def_aspm_entry_latency(tp);
3543
3544 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
3545 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3546}
3547
3548static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
3549{
3550 rtl_hw_start_8102e_2(tp);
3551
3552 rtl_ephy_write(tp, reg_addr: 0x03, value: 0xc2f9);
3553}
3554
3555static void rtl_hw_start_8401(struct rtl8169_private *tp)
3556{
3557 static const struct ephy_info e_info_8401[] = {
3558 { 0x01, 0xffff, 0x6fe5 },
3559 { 0x03, 0xffff, 0x0599 },
3560 { 0x06, 0xffff, 0xaf25 },
3561 { 0x07, 0xffff, 0x8e68 },
3562 };
3563
3564 rtl_ephy_init(tp, e_info_8401);
3565 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3566}
3567
3568static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
3569{
3570 static const struct ephy_info e_info_8105e_1[] = {
3571 { 0x07, 0, 0x4000 },
3572 { 0x19, 0, 0x0200 },
3573 { 0x19, 0, 0x0020 },
3574 { 0x1e, 0, 0x2000 },
3575 { 0x03, 0, 0x0001 },
3576 { 0x19, 0, 0x0100 },
3577 { 0x19, 0, 0x0004 },
3578 { 0x0a, 0, 0x0020 }
3579 };
3580
3581 /* Force LAN exit from ASPM if Rx/Tx are not idle */
3582 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3583
3584 /* Disable Early Tally Counter */
3585 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
3586
3587 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3588 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
3589
3590 rtl_ephy_init(tp, e_info_8105e_1);
3591
3592 rtl_pcie_state_l2l3_disable(tp);
3593}
3594
3595static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
3596{
3597 rtl_hw_start_8105e_1(tp);
3598 rtl_ephy_write(tp, reg_addr: 0x1e, value: rtl_ephy_read(tp, reg_addr: 0x1e) | 0x8000);
3599}
3600
3601static void rtl_hw_start_8402(struct rtl8169_private *tp)
3602{
3603 static const struct ephy_info e_info_8402[] = {
3604 { 0x19, 0xffff, 0xff64 },
3605 { 0x1e, 0, 0x4000 }
3606 };
3607
3608 rtl_set_def_aspm_entry_latency(tp);
3609
3610 /* Force LAN exit from ASPM if Rx/Tx are not idle */
3611 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3612
3613 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
3614
3615 rtl_ephy_init(tp, e_info_8402);
3616
3617 rtl_set_fifo_size(tp, rx_stat: 0x00, tx_stat: 0x00, rx_dyn: 0x02, tx_dyn: 0x06);
3618 rtl_reset_packet_filter(tp);
3619 rtl_eri_write(tp, addr: 0xc0, ERIAR_MASK_0011, val: 0x0000);
3620 rtl_eri_write(tp, addr: 0xb8, ERIAR_MASK_0011, val: 0x0000);
3621 rtl_w0w1_eri(tp, addr: 0x0d4, p: 0x0e00, m: 0xff00);
3622
3623 /* disable EEE */
3624 rtl_eri_write(tp, addr: 0x1b0, ERIAR_MASK_0011, val: 0x0000);
3625
3626 rtl_pcie_state_l2l3_disable(tp);
3627}
3628
3629static void rtl_hw_start_8106(struct rtl8169_private *tp)
3630{
3631 /* Force LAN exit from ASPM if Rx/Tx are not idle */
3632 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3633
3634 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
3635 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3636 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3637
3638 /* L0 7us, L1 32us - needed to avoid issues with link-up detection */
3639 rtl_set_aspm_entry_latency(tp, val: 0x2f);
3640
3641 rtl_eri_write(tp, addr: 0x1d0, ERIAR_MASK_0011, val: 0x0000);
3642
3643 /* disable EEE */
3644 rtl_eri_write(tp, addr: 0x1b0, ERIAR_MASK_0011, val: 0x0000);
3645
3646 rtl_pcie_state_l2l3_disable(tp);
3647}
3648
3649DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond)
3650{
3651 return r8168_mac_ocp_read(tp, reg: 0xe00e) & BIT(13);
3652}
3653
3654static void rtl_hw_start_8125_common(struct rtl8169_private *tp)
3655{
3656 rtl_pcie_state_l2l3_disable(tp);
3657
3658 RTL_W16(tp, 0x382, 0x221b);
3659 RTL_W32(tp, RSS_CTRL_8125, 0);
3660 RTL_W16(tp, Q_NUM_CTRL_8125, 0);
3661
3662 /* disable UPS */
3663 r8168_mac_ocp_modify(tp, reg: 0xd40a, mask: 0x0010, set: 0x0000);
3664
3665 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10);
3666
3667 r8168_mac_ocp_write(tp, reg: 0xc140, data: 0xffff);
3668 r8168_mac_ocp_write(tp, reg: 0xc142, data: 0xffff);
3669
3670 r8168_mac_ocp_modify(tp, reg: 0xd3e2, mask: 0x0fff, set: 0x03a9);
3671 r8168_mac_ocp_modify(tp, reg: 0xd3e4, mask: 0x00ff, set: 0x0000);
3672 r8168_mac_ocp_modify(tp, reg: 0xe860, mask: 0x0000, set: 0x0080);
3673
3674 /* disable new tx descriptor format */
3675 r8168_mac_ocp_modify(tp, reg: 0xeb58, mask: 0x0001, set: 0x0000);
3676
3677 if (tp->mac_version == RTL_GIGA_MAC_VER_70 ||
3678 tp->mac_version == RTL_GIGA_MAC_VER_80)
3679 RTL_W8(tp, 0xD8, RTL_R8(tp, 0xD8) & ~0x02);
3680
3681 if (tp->mac_version == RTL_GIGA_MAC_VER_80)
3682 r8168_mac_ocp_modify(tp, reg: 0xe614, mask: 0x0f00, set: 0x0f00);
3683 else if (tp->mac_version == RTL_GIGA_MAC_VER_70)
3684 r8168_mac_ocp_modify(tp, reg: 0xe614, mask: 0x0700, set: 0x0400);
3685 else if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3686 r8168_mac_ocp_modify(tp, reg: 0xe614, mask: 0x0700, set: 0x0200);
3687 else
3688 r8168_mac_ocp_modify(tp, reg: 0xe614, mask: 0x0700, set: 0x0300);
3689
3690 if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3691 r8168_mac_ocp_modify(tp, reg: 0xe63e, mask: 0x0c30, set: 0x0000);
3692 else
3693 r8168_mac_ocp_modify(tp, reg: 0xe63e, mask: 0x0c30, set: 0x0020);
3694
3695 r8168_mac_ocp_modify(tp, reg: 0xc0b4, mask: 0x0000, set: 0x000c);
3696 r8168_mac_ocp_modify(tp, reg: 0xeb6a, mask: 0x00ff, set: 0x0033);
3697 r8168_mac_ocp_modify(tp, reg: 0xeb50, mask: 0x03e0, set: 0x0040);
3698 r8168_mac_ocp_modify(tp, reg: 0xe056, mask: 0x00f0, set: 0x0000);
3699 r8168_mac_ocp_modify(tp, reg: 0xe040, mask: 0x1000, set: 0x0000);
3700 r8168_mac_ocp_modify(tp, reg: 0xea1c, mask: 0x0003, set: 0x0001);
3701 if (tp->mac_version == RTL_GIGA_MAC_VER_70 ||
3702 tp->mac_version == RTL_GIGA_MAC_VER_80)
3703 r8168_mac_ocp_modify(tp, reg: 0xea1c, mask: 0x0300, set: 0x0000);
3704 else
3705 r8168_mac_ocp_modify(tp, reg: 0xea1c, mask: 0x0004, set: 0x0000);
3706 r8168_mac_ocp_modify(tp, reg: 0xe0c0, mask: 0x4f0f, set: 0x4403);
3707 r8168_mac_ocp_modify(tp, reg: 0xe052, mask: 0x0080, set: 0x0068);
3708 r8168_mac_ocp_modify(tp, reg: 0xd430, mask: 0x0fff, set: 0x047f);
3709
3710 r8168_mac_ocp_modify(tp, reg: 0xea1c, mask: 0x0004, set: 0x0000);
3711 r8168_mac_ocp_modify(tp, reg: 0xeb54, mask: 0x0000, set: 0x0001);
3712 udelay(usec: 1);
3713 r8168_mac_ocp_modify(tp, reg: 0xeb54, mask: 0x0001, set: 0x0000);
3714 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030);
3715
3716 r8168_mac_ocp_write(tp, reg: 0xe098, data: 0xc302);
3717
3718 rtl_loop_wait_low(tp, c: &rtl_mac_ocp_e00e_cond, d: 1000, n: 10);
3719
3720 rtl_disable_rxdvgate(tp);
3721}
3722
3723static void rtl_hw_start_8125a_2(struct rtl8169_private *tp)
3724{
3725 static const struct ephy_info e_info_8125a_2[] = {
3726 { 0x04, 0xffff, 0xd000 },
3727 { 0x0a, 0xffff, 0x8653 },
3728 { 0x23, 0xffff, 0xab66 },
3729 { 0x20, 0xffff, 0x9455 },
3730 { 0x21, 0xffff, 0x99ff },
3731 { 0x29, 0xffff, 0xfe04 },
3732
3733 { 0x44, 0xffff, 0xd000 },
3734 { 0x4a, 0xffff, 0x8653 },
3735 { 0x63, 0xffff, 0xab66 },
3736 { 0x60, 0xffff, 0x9455 },
3737 { 0x61, 0xffff, 0x99ff },
3738 { 0x69, 0xffff, 0xfe04 },
3739 };
3740
3741 rtl_set_def_aspm_entry_latency(tp);
3742 rtl_ephy_init(tp, e_info_8125a_2);
3743 rtl_hw_start_8125_common(tp);
3744}
3745
3746static void rtl_hw_start_8125b(struct rtl8169_private *tp)
3747{
3748 static const struct ephy_info e_info_8125b[] = {
3749 { 0x0b, 0xffff, 0xa908 },
3750 { 0x1e, 0xffff, 0x20eb },
3751 { 0x4b, 0xffff, 0xa908 },
3752 { 0x5e, 0xffff, 0x20eb },
3753 { 0x22, 0x0030, 0x0020 },
3754 { 0x62, 0x0030, 0x0020 },
3755 };
3756
3757 rtl_set_def_aspm_entry_latency(tp);
3758 rtl_ephy_init(tp, e_info_8125b);
3759 rtl_hw_start_8125_common(tp);
3760}
3761
3762static void rtl_hw_start_8125d(struct rtl8169_private *tp)
3763{
3764 rtl_set_def_aspm_entry_latency(tp);
3765 rtl_hw_start_8125_common(tp);
3766}
3767
3768static void rtl_hw_start_8126a(struct rtl8169_private *tp)
3769{
3770 rtl_disable_zrxdc_timeout(tp);
3771 rtl_set_def_aspm_entry_latency(tp);
3772 rtl_hw_start_8125_common(tp);
3773}
3774
3775static void rtl_hw_start_8127a(struct rtl8169_private *tp)
3776{
3777 rtl_set_def_aspm_entry_latency(tp);
3778 rtl_hw_start_8125_common(tp);
3779}
3780
3781static void rtl_hw_config(struct rtl8169_private *tp)
3782{
3783 static const rtl_generic_fct hw_configs[] = {
3784 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1,
3785 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3,
3786 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2,
3787 [RTL_GIGA_MAC_VER_10] = NULL,
3788 [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401,
3789 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b,
3790 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1,
3791 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1,
3792 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2,
3793 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_2,
3794 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4,
3795 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2,
3796 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3,
3797 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d,
3798 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d,
3799 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4,
3800 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1,
3801 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2,
3802 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d,
3803 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1,
3804 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1,
3805 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2,
3806 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1,
3807 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1,
3808 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402,
3809 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411,
3810 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106,
3811 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1,
3812 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2,
3813 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2,
3814 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2,
3815 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1,
3816 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1,
3817 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3,
3818 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117,
3819 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2,
3820 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b,
3821 [RTL_GIGA_MAC_VER_64] = rtl_hw_start_8125d,
3822 [RTL_GIGA_MAC_VER_66] = rtl_hw_start_8125d,
3823 [RTL_GIGA_MAC_VER_70] = rtl_hw_start_8126a,
3824 [RTL_GIGA_MAC_VER_80] = rtl_hw_start_8127a,
3825 };
3826
3827 if (hw_configs[tp->mac_version])
3828 hw_configs[tp->mac_version](tp);
3829}
3830
3831static void rtl_hw_start_8125(struct rtl8169_private *tp)
3832{
3833 int i;
3834
3835 RTL_W8(tp, INT_CFG0_8125, 0x00);
3836
3837 /* disable interrupt coalescing */
3838 switch (tp->mac_version) {
3839 case RTL_GIGA_MAC_VER_61:
3840 case RTL_GIGA_MAC_VER_64:
3841 case RTL_GIGA_MAC_VER_66:
3842 case RTL_GIGA_MAC_VER_80:
3843 for (i = 0xa00; i < 0xb00; i += 4)
3844 RTL_W32(tp, i, 0);
3845 if (tp->mac_version == RTL_GIGA_MAC_VER_80)
3846 RTL_W16(tp, INT_CFG1_8125, 0x0000);
3847 break;
3848 case RTL_GIGA_MAC_VER_63:
3849 case RTL_GIGA_MAC_VER_70:
3850 for (i = 0xa00; i < 0xa80; i += 4)
3851 RTL_W32(tp, i, 0);
3852 RTL_W16(tp, INT_CFG1_8125, 0x0000);
3853 break;
3854 default:
3855 break;
3856 }
3857
3858 /* enable extended tally counter */
3859 r8168_mac_ocp_modify(tp, reg: 0xea84, mask: 0, BIT(1) | BIT(0));
3860
3861 rtl_hw_config(tp);
3862}
3863
3864static void rtl_hw_start_8168(struct rtl8169_private *tp)
3865{
3866 if (rtl_is_8168evl_up(tp))
3867 RTL_W8(tp, MaxTxPacketSize, EarlySize);
3868 else
3869 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
3870
3871 rtl_hw_config(tp);
3872
3873 /* disable interrupt coalescing */
3874 RTL_W16(tp, IntrMitigate, 0x0000);
3875}
3876
3877static void rtl_hw_start_8169(struct rtl8169_private *tp)
3878{
3879 RTL_W8(tp, EarlyTxThres, NoEarlyTx);
3880
3881 tp->cp_cmd |= PCIMulRW;
3882
3883 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3884 tp->mac_version == RTL_GIGA_MAC_VER_03)
3885 tp->cp_cmd |= EnAnaPLL;
3886
3887 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3888
3889 rtl8169_set_magic_reg(tp);
3890
3891 /* disable interrupt coalescing */
3892 RTL_W16(tp, IntrMitigate, 0x0000);
3893}
3894
3895static void rtl_hw_start(struct rtl8169_private *tp)
3896{
3897 rtl_unlock_config_regs(tp);
3898 /* disable aspm and clock request before ephy access */
3899 rtl_hw_aspm_clkreq_enable(tp, enable: false);
3900 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3901
3902 rtl_set_eee_txidle_timer(tp);
3903
3904 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3905 rtl_hw_start_8169(tp);
3906 else if (rtl_is_8125(tp))
3907 rtl_hw_start_8125(tp);
3908 else
3909 rtl_hw_start_8168(tp);
3910
3911 rtl_enable_exit_l1(tp);
3912 rtl_hw_aspm_clkreq_enable(tp, enable: true);
3913 rtl_set_rx_max_size(tp);
3914 rtl_set_rx_tx_desc_registers(tp);
3915 rtl_lock_config_regs(tp);
3916
3917 rtl_jumbo_config(tp);
3918
3919 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3920 rtl_pci_commit(tp);
3921
3922 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
3923 rtl_init_rxcfg(tp);
3924 rtl_set_tx_config_registers(tp);
3925 rtl_set_rx_config_features(tp, features: tp->dev->features);
3926 rtl_set_rx_mode(dev: tp->dev);
3927 rtl_irq_enable(tp);
3928}
3929
3930static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3931{
3932 struct rtl8169_private *tp = netdev_priv(dev);
3933
3934 WRITE_ONCE(dev->mtu, new_mtu);
3935 netdev_update_features(dev);
3936 rtl_jumbo_config(tp);
3937 rtl_set_eee_txidle_timer(tp);
3938
3939 return 0;
3940}
3941
3942static void rtl8169_mark_to_asic(struct RxDesc *desc)
3943{
3944 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3945
3946 desc->opts2 = 0;
3947 /* Force memory writes to complete before releasing descriptor */
3948 dma_wmb();
3949 WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE));
3950}
3951
3952static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
3953 struct RxDesc *desc)
3954{
3955 struct device *d = tp_to_dev(tp);
3956 int node = dev_to_node(dev: d);
3957 dma_addr_t mapping;
3958 struct page *data;
3959
3960 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE));
3961 if (!data)
3962 return NULL;
3963
3964 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
3965 if (unlikely(dma_mapping_error(d, mapping))) {
3966 netdev_err(dev: tp->dev, format: "Failed to map RX DMA!\n");
3967 __free_pages(page: data, order: get_order(R8169_RX_BUF_SIZE));
3968 return NULL;
3969 }
3970
3971 desc->addr = cpu_to_le64(mapping);
3972 rtl8169_mark_to_asic(desc);
3973
3974 return data;
3975}
3976
3977static void rtl8169_rx_clear(struct rtl8169_private *tp)
3978{
3979 int i;
3980
3981 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) {
3982 dma_unmap_page(tp_to_dev(tp),
3983 le64_to_cpu(tp->RxDescArray[i].addr),
3984 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
3985 __free_pages(page: tp->Rx_databuff[i], order: get_order(R8169_RX_BUF_SIZE));
3986 tp->Rx_databuff[i] = NULL;
3987 tp->RxDescArray[i].addr = 0;
3988 tp->RxDescArray[i].opts1 = 0;
3989 }
3990}
3991
3992static int rtl8169_rx_fill(struct rtl8169_private *tp)
3993{
3994 int i;
3995
3996 for (i = 0; i < NUM_RX_DESC; i++) {
3997 struct page *data;
3998
3999 data = rtl8169_alloc_rx_data(tp, desc: tp->RxDescArray + i);
4000 if (!data) {
4001 rtl8169_rx_clear(tp);
4002 return -ENOMEM;
4003 }
4004 tp->Rx_databuff[i] = data;
4005 }
4006
4007 /* mark as last descriptor in the ring */
4008 tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd);
4009
4010 return 0;
4011}
4012
4013static int rtl8169_init_ring(struct rtl8169_private *tp)
4014{
4015 rtl8169_init_ring_indexes(tp);
4016
4017 memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
4018 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
4019
4020 return rtl8169_rx_fill(tp);
4021}
4022
4023static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry)
4024{
4025 struct ring_info *tx_skb = tp->tx_skb + entry;
4026 struct TxDesc *desc = tp->TxDescArray + entry;
4027
4028 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len,
4029 DMA_TO_DEVICE);
4030 memset(desc, 0, sizeof(*desc));
4031 memset(tx_skb, 0, sizeof(*tx_skb));
4032}
4033
4034static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4035 unsigned int n)
4036{
4037 unsigned int i;
4038
4039 for (i = 0; i < n; i++) {
4040 unsigned int entry = (start + i) % NUM_TX_DESC;
4041 struct ring_info *tx_skb = tp->tx_skb + entry;
4042 unsigned int len = tx_skb->len;
4043
4044 if (len) {
4045 struct sk_buff *skb = tx_skb->skb;
4046
4047 rtl8169_unmap_tx_skb(tp, entry);
4048 if (skb)
4049 dev_consume_skb_any(skb);
4050 }
4051 }
4052}
4053
4054static void rtl8169_tx_clear(struct rtl8169_private *tp)
4055{
4056 rtl8169_tx_clear_range(tp, start: tp->dirty_tx, NUM_TX_DESC);
4057 netdev_reset_queue(dev_queue: tp->dev);
4058}
4059
4060static void rtl8169_cleanup(struct rtl8169_private *tp)
4061{
4062 napi_disable(n: &tp->napi);
4063
4064 /* Give a racing hard_start_xmit a few cycles to complete. */
4065 synchronize_net();
4066
4067 /* Disable interrupts */
4068 rtl8169_irq_mask_and_ack(tp);
4069
4070 rtl_rx_close(tp);
4071
4072 switch (tp->mac_version) {
4073 case RTL_GIGA_MAC_VER_28:
4074 case RTL_GIGA_MAC_VER_31:
4075 rtl_loop_wait_low(tp, c: &rtl_npq_cond, d: 20, n: 2000);
4076 break;
4077 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
4078 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4079 rtl_loop_wait_high(tp, c: &rtl_txcfg_empty_cond, d: 100, n: 666);
4080 break;
4081 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_LAST:
4082 rtl_enable_rxdvgate(tp);
4083 fsleep(usecs: 2000);
4084 break;
4085 default:
4086 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4087 fsleep(usecs: 100);
4088 break;
4089 }
4090
4091 rtl_hw_reset(tp);
4092
4093 rtl8169_tx_clear(tp);
4094 rtl8169_init_ring_indexes(tp);
4095}
4096
4097static void rtl_reset_work(struct rtl8169_private *tp)
4098{
4099 int i;
4100
4101 netif_stop_queue(dev: tp->dev);
4102
4103 rtl8169_cleanup(tp);
4104
4105 for (i = 0; i < NUM_RX_DESC; i++)
4106 rtl8169_mark_to_asic(desc: tp->RxDescArray + i);
4107
4108 napi_enable(n: &tp->napi);
4109 rtl_hw_start(tp);
4110}
4111
4112static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue)
4113{
4114 struct rtl8169_private *tp = netdev_priv(dev);
4115
4116 rtl_schedule_task(tp, flag: RTL_FLAG_TASK_TX_TIMEOUT);
4117}
4118
4119static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len,
4120 void *addr, unsigned int entry, bool desc_own)
4121{
4122 struct TxDesc *txd = tp->TxDescArray + entry;
4123 struct device *d = tp_to_dev(tp);
4124 dma_addr_t mapping;
4125 u32 opts1;
4126 int ret;
4127
4128 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
4129 ret = dma_mapping_error(dev: d, dma_addr: mapping);
4130 if (unlikely(ret)) {
4131 if (net_ratelimit())
4132 netdev_err(dev: tp->dev, format: "Failed to map TX data!\n");
4133 return ret;
4134 }
4135
4136 txd->addr = cpu_to_le64(mapping);
4137 txd->opts2 = cpu_to_le32(opts[1]);
4138
4139 opts1 = opts[0] | len;
4140 if (entry == NUM_TX_DESC - 1)
4141 opts1 |= RingEnd;
4142 if (desc_own)
4143 opts1 |= DescOwn;
4144 txd->opts1 = cpu_to_le32(opts1);
4145
4146 tp->tx_skb[entry].len = len;
4147
4148 return 0;
4149}
4150
4151static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4152 const u32 *opts, unsigned int entry)
4153{
4154 struct skb_shared_info *info = skb_shinfo(skb);
4155 unsigned int cur_frag;
4156
4157 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4158 const skb_frag_t *frag = info->frags + cur_frag;
4159 void *addr = skb_frag_address(frag);
4160 u32 len = skb_frag_size(frag);
4161
4162 entry = (entry + 1) % NUM_TX_DESC;
4163
4164 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true)))
4165 goto err_out;
4166 }
4167
4168 return 0;
4169
4170err_out:
4171 rtl8169_tx_clear_range(tp, start: tp->cur_tx + 1, n: cur_frag);
4172 return -EIO;
4173}
4174
4175static bool rtl_skb_is_udp(struct sk_buff *skb)
4176{
4177 int no = skb_network_offset(skb);
4178 struct ipv6hdr *i6h, _i6h;
4179 struct iphdr *ih, _ih;
4180
4181 switch (vlan_get_protocol(skb)) {
4182 case htons(ETH_P_IP):
4183 ih = skb_header_pointer(skb, offset: no, len: sizeof(_ih), buffer: &_ih);
4184 return ih && ih->protocol == IPPROTO_UDP;
4185 case htons(ETH_P_IPV6):
4186 i6h = skb_header_pointer(skb, offset: no, len: sizeof(_i6h), buffer: &_i6h);
4187 return i6h && i6h->nexthdr == IPPROTO_UDP;
4188 default:
4189 return false;
4190 }
4191}
4192
4193#define RTL_MIN_PATCH_LEN 47
4194
4195/* see rtl8125_get_patch_pad_len() in r8125 vendor driver */
4196static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp,
4197 struct sk_buff *skb)
4198{
4199 unsigned int padto = 0, len = skb->len;
4200
4201 if (len < 128 + RTL_MIN_PATCH_LEN && rtl_skb_is_udp(skb) &&
4202 skb_transport_header_was_set(skb)) {
4203 unsigned int trans_data_len = skb_tail_pointer(skb) -
4204 skb_transport_header(skb);
4205
4206 if (trans_data_len >= offsetof(struct udphdr, len) &&
4207 trans_data_len < RTL_MIN_PATCH_LEN) {
4208 u16 dest = ntohs(udp_hdr(skb)->dest);
4209
4210 /* dest is a standard PTP port */
4211 if (dest == 319 || dest == 320)
4212 padto = len + RTL_MIN_PATCH_LEN - trans_data_len;
4213 }
4214
4215 if (trans_data_len < sizeof(struct udphdr))
4216 padto = max_t(unsigned int, padto,
4217 len + sizeof(struct udphdr) - trans_data_len);
4218 }
4219
4220 return padto;
4221}
4222
4223static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp,
4224 struct sk_buff *skb)
4225{
4226 unsigned int padto = 0;
4227
4228 switch (tp->mac_version) {
4229 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63:
4230 padto = rtl8125_quirk_udp_padto(tp, skb);
4231 break;
4232 default:
4233 break;
4234 }
4235
4236 switch (tp->mac_version) {
4237 case RTL_GIGA_MAC_VER_34:
4238 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST:
4239 padto = max_t(unsigned int, padto, ETH_ZLEN);
4240 break;
4241 default:
4242 break;
4243 }
4244
4245 return padto;
4246}
4247
4248static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts)
4249{
4250 u32 mss = skb_shinfo(skb)->gso_size;
4251
4252 if (mss) {
4253 opts[0] |= TD_LSO;
4254 opts[0] |= mss << TD0_MSS_SHIFT;
4255 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4256 const struct iphdr *ip = ip_hdr(skb);
4257
4258 if (ip->protocol == IPPROTO_TCP)
4259 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
4260 else if (ip->protocol == IPPROTO_UDP)
4261 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
4262 else
4263 WARN_ON_ONCE(1);
4264 }
4265}
4266
4267static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
4268 struct sk_buff *skb, u32 *opts)
4269{
4270 struct skb_shared_info *shinfo = skb_shinfo(skb);
4271 u32 mss = shinfo->gso_size;
4272
4273 if (mss) {
4274 if (shinfo->gso_type & SKB_GSO_TCPV4) {
4275 opts[0] |= TD1_GTSENV4;
4276 } else if (shinfo->gso_type & SKB_GSO_TCPV6) {
4277 if (skb_cow_head(skb, headroom: 0))
4278 return false;
4279
4280 tcp_v6_gso_csum_prep(skb);
4281 opts[0] |= TD1_GTSENV6;
4282 } else {
4283 WARN_ON_ONCE(1);
4284 }
4285
4286 opts[0] |= skb_transport_offset(skb) << GTTCPHO_SHIFT;
4287 opts[1] |= mss << TD1_MSS_SHIFT;
4288 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4289 u8 ip_protocol;
4290
4291 switch (vlan_get_protocol(skb)) {
4292 case htons(ETH_P_IP):
4293 opts[1] |= TD1_IPv4_CS;
4294 ip_protocol = ip_hdr(skb)->protocol;
4295 break;
4296
4297 case htons(ETH_P_IPV6):
4298 opts[1] |= TD1_IPv6_CS;
4299 ip_protocol = ipv6_hdr(skb)->nexthdr;
4300 break;
4301
4302 default:
4303 ip_protocol = IPPROTO_RAW;
4304 break;
4305 }
4306
4307 if (ip_protocol == IPPROTO_TCP)
4308 opts[1] |= TD1_TCP_CS;
4309 else if (ip_protocol == IPPROTO_UDP)
4310 opts[1] |= TD1_UDP_CS;
4311 else
4312 WARN_ON_ONCE(1);
4313
4314 opts[1] |= skb_transport_offset(skb) << TCPHO_SHIFT;
4315 } else {
4316 unsigned int padto = rtl_quirk_packet_padto(tp, skb);
4317
4318 /* skb_padto would free the skb on error */
4319 return !__skb_put_padto(skb, len: padto, free_on_error: false);
4320 }
4321
4322 return true;
4323}
4324
4325static unsigned int rtl_tx_slots_avail(struct rtl8169_private *tp)
4326{
4327 return READ_ONCE(tp->dirty_tx) + NUM_TX_DESC - READ_ONCE(tp->cur_tx);
4328}
4329
4330/* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
4331static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
4332{
4333 switch (tp->mac_version) {
4334 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
4335 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4336 return false;
4337 default:
4338 return true;
4339 }
4340}
4341
4342static void rtl8169_doorbell(struct rtl8169_private *tp)
4343{
4344 if (rtl_is_8125(tp))
4345 RTL_W16(tp, TxPoll_8125, BIT(0));
4346 else
4347 RTL_W8(tp, TxPoll, NPQ);
4348}
4349
4350static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4351 struct net_device *dev)
4352{
4353 struct rtl8169_private *tp = netdev_priv(dev);
4354 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
4355 struct TxDesc *txd_first, *txd_last;
4356 bool stop_queue, door_bell;
4357 unsigned int frags;
4358 u32 opts[2];
4359
4360 if (unlikely(!rtl_tx_slots_avail(tp))) {
4361 if (net_ratelimit())
4362 netdev_err(dev, format: "BUG! Tx Ring full when queue awake!\n");
4363 netif_stop_queue(dev);
4364 return NETDEV_TX_BUSY;
4365 }
4366
4367 opts[1] = rtl8169_tx_vlan_tag(skb);
4368 opts[0] = 0;
4369
4370 if (!rtl_chip_supports_csum_v2(tp))
4371 rtl8169_tso_csum_v1(skb, opts);
4372 else if (!rtl8169_tso_csum_v2(tp, skb, opts))
4373 goto err_dma_0;
4374
4375 if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data,
4376 entry, false)))
4377 goto err_dma_0;
4378
4379 txd_first = tp->TxDescArray + entry;
4380
4381 frags = skb_shinfo(skb)->nr_frags;
4382 if (frags) {
4383 if (rtl8169_xmit_frags(tp, skb, opts, entry))
4384 goto err_dma_1;
4385 entry = (entry + frags) % NUM_TX_DESC;
4386 }
4387
4388 txd_last = tp->TxDescArray + entry;
4389 txd_last->opts1 |= cpu_to_le32(LastFrag);
4390 tp->tx_skb[entry].skb = skb;
4391
4392 skb_tx_timestamp(skb);
4393
4394 /* Force memory writes to complete before releasing descriptor */
4395 dma_wmb();
4396
4397 door_bell = __netdev_sent_queue(dev, bytes: skb->len, xmit_more: netdev_xmit_more());
4398
4399 txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag);
4400
4401 /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */
4402 smp_wmb();
4403
4404 WRITE_ONCE(tp->cur_tx, tp->cur_tx + frags + 1);
4405
4406 stop_queue = !netif_subqueue_maybe_stop(dev, 0, rtl_tx_slots_avail(tp),
4407 R8169_TX_STOP_THRS,
4408 R8169_TX_START_THRS);
4409 if (door_bell || stop_queue)
4410 rtl8169_doorbell(tp);
4411
4412 return NETDEV_TX_OK;
4413
4414err_dma_1:
4415 rtl8169_unmap_tx_skb(tp, entry);
4416err_dma_0:
4417 dev_kfree_skb_any(skb);
4418 dev->stats.tx_dropped++;
4419 return NETDEV_TX_OK;
4420}
4421
4422static unsigned int rtl_last_frag_len(struct sk_buff *skb)
4423{
4424 struct skb_shared_info *info = skb_shinfo(skb);
4425 unsigned int nr_frags = info->nr_frags;
4426
4427 if (!nr_frags)
4428 return UINT_MAX;
4429
4430 return skb_frag_size(frag: info->frags + nr_frags - 1);
4431}
4432
4433/* Workaround for hw issues with TSO on RTL8168evl */
4434static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb,
4435 netdev_features_t features)
4436{
4437 /* IPv4 header has options field */
4438 if (vlan_get_protocol(skb) == htons(ETH_P_IP) &&
4439 ip_hdrlen(skb) > sizeof(struct iphdr))
4440 features &= ~NETIF_F_ALL_TSO;
4441
4442 /* IPv4 TCP header has options field */
4443 else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 &&
4444 tcp_hdrlen(skb) > sizeof(struct tcphdr))
4445 features &= ~NETIF_F_ALL_TSO;
4446
4447 else if (rtl_last_frag_len(skb) <= 6)
4448 features &= ~NETIF_F_ALL_TSO;
4449
4450 return features;
4451}
4452
4453static netdev_features_t rtl8169_features_check(struct sk_buff *skb,
4454 struct net_device *dev,
4455 netdev_features_t features)
4456{
4457 struct rtl8169_private *tp = netdev_priv(dev);
4458
4459 if (skb_is_gso(skb)) {
4460 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4461 features = rtl8168evl_fix_tso(skb, features);
4462
4463 if (skb_transport_offset(skb) > GTTCPHO_MAX &&
4464 rtl_chip_supports_csum_v2(tp))
4465 features &= ~NETIF_F_ALL_TSO;
4466 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4467 /* work around hw bug on some chip versions */
4468 if (skb->len < ETH_ZLEN)
4469 features &= ~NETIF_F_CSUM_MASK;
4470
4471 if (rtl_quirk_packet_padto(tp, skb))
4472 features &= ~NETIF_F_CSUM_MASK;
4473
4474 if (skb_transport_offset(skb) > TCPHO_MAX &&
4475 rtl_chip_supports_csum_v2(tp))
4476 features &= ~NETIF_F_CSUM_MASK;
4477 }
4478
4479 return vlan_features_check(skb, features);
4480}
4481
4482static void rtl8169_pcierr_interrupt(struct net_device *dev)
4483{
4484 struct rtl8169_private *tp = netdev_priv(dev);
4485 struct pci_dev *pdev = tp->pci_dev;
4486 int pci_status_errs;
4487 u16 pci_cmd;
4488
4489 pci_read_config_word(dev: pdev, PCI_COMMAND, val: &pci_cmd);
4490
4491 pci_status_errs = pci_status_get_and_clear_errors(pdev);
4492
4493 if (net_ratelimit())
4494 netdev_err(dev, format: "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n",
4495 pci_cmd, pci_status_errs);
4496
4497 rtl_schedule_task(tp, flag: RTL_FLAG_TASK_RESET_PENDING);
4498}
4499
4500static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
4501 int budget)
4502{
4503 unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0;
4504 struct sk_buff *skb;
4505
4506 dirty_tx = tp->dirty_tx;
4507
4508 while (READ_ONCE(tp->cur_tx) != dirty_tx) {
4509 unsigned int entry = dirty_tx % NUM_TX_DESC;
4510 u32 status;
4511
4512 status = le32_to_cpu(READ_ONCE(tp->TxDescArray[entry].opts1));
4513 if (status & DescOwn)
4514 break;
4515
4516 skb = tp->tx_skb[entry].skb;
4517 rtl8169_unmap_tx_skb(tp, entry);
4518
4519 if (skb) {
4520 pkts_compl++;
4521 bytes_compl += skb->len;
4522 napi_consume_skb(skb, budget);
4523 }
4524 dirty_tx++;
4525 }
4526
4527 if (tp->dirty_tx != dirty_tx) {
4528 dev_sw_netstats_tx_add(dev, packets: pkts_compl, len: bytes_compl);
4529 WRITE_ONCE(tp->dirty_tx, dirty_tx);
4530
4531 netif_subqueue_completed_wake(dev, 0, pkts_compl, bytes_compl,
4532 rtl_tx_slots_avail(tp),
4533 R8169_TX_START_THRS);
4534 /*
4535 * 8168 hack: TxPoll requests are lost when the Tx packets are
4536 * too close. Let's kick an extra TxPoll request when a burst
4537 * of start_xmit activity is detected (if it is not detected,
4538 * it is slow enough). -- FR
4539 * If skb is NULL then we come here again once a tx irq is
4540 * triggered after the last fragment is marked transmitted.
4541 */
4542 if (READ_ONCE(tp->cur_tx) != dirty_tx && skb)
4543 rtl8169_doorbell(tp);
4544 }
4545}
4546
4547static inline int rtl8169_fragmented_frame(u32 status)
4548{
4549 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4550}
4551
4552static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
4553{
4554 u32 status = opts1 & (RxProtoMask | RxCSFailMask);
4555
4556 if (status == RxProtoTCP || status == RxProtoUDP)
4557 skb->ip_summed = CHECKSUM_UNNECESSARY;
4558 else
4559 skb_checksum_none_assert(skb);
4560}
4561
4562static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, int budget)
4563{
4564 struct device *d = tp_to_dev(tp);
4565 int count;
4566
4567 for (count = 0; count < budget; count++, tp->cur_rx++) {
4568 unsigned int pkt_size, entry = tp->cur_rx % NUM_RX_DESC;
4569 struct RxDesc *desc = tp->RxDescArray + entry;
4570 struct sk_buff *skb;
4571 const void *rx_buf;
4572 dma_addr_t addr;
4573 u32 status;
4574
4575 status = le32_to_cpu(READ_ONCE(desc->opts1));
4576 if (status & DescOwn)
4577 break;
4578
4579 /* This barrier is needed to keep us from reading
4580 * any other fields out of the Rx descriptor until
4581 * we know the status of DescOwn
4582 */
4583 dma_rmb();
4584
4585 if (unlikely(status & RxRES)) {
4586 if (net_ratelimit())
4587 netdev_warn(dev, format: "Rx ERROR. status = %08x\n",
4588 status);
4589 dev->stats.rx_errors++;
4590 if (status & (RxRWT | RxRUNT))
4591 dev->stats.rx_length_errors++;
4592 if (status & RxCRC)
4593 dev->stats.rx_crc_errors++;
4594
4595 if (!(dev->features & NETIF_F_RXALL))
4596 goto release_descriptor;
4597 else if (status & RxRWT || !(status & (RxRUNT | RxCRC)))
4598 goto release_descriptor;
4599 }
4600
4601 pkt_size = status & GENMASK(13, 0);
4602 if (likely(!(dev->features & NETIF_F_RXFCS)))
4603 pkt_size -= ETH_FCS_LEN;
4604
4605 /* The driver does not support incoming fragmented frames.
4606 * They are seen as a symptom of over-mtu sized frames.
4607 */
4608 if (unlikely(rtl8169_fragmented_frame(status))) {
4609 dev->stats.rx_dropped++;
4610 dev->stats.rx_length_errors++;
4611 goto release_descriptor;
4612 }
4613
4614 skb = napi_alloc_skb(napi: &tp->napi, length: pkt_size);
4615 if (unlikely(!skb)) {
4616 dev->stats.rx_dropped++;
4617 goto release_descriptor;
4618 }
4619
4620 addr = le64_to_cpu(desc->addr);
4621 rx_buf = page_address(tp->Rx_databuff[entry]);
4622
4623 dma_sync_single_for_cpu(dev: d, addr, size: pkt_size, dir: DMA_FROM_DEVICE);
4624 prefetch(rx_buf);
4625 skb_copy_to_linear_data(skb, from: rx_buf, len: pkt_size);
4626 skb->tail += pkt_size;
4627 skb->len = pkt_size;
4628 dma_sync_single_for_device(dev: d, addr, size: pkt_size, dir: DMA_FROM_DEVICE);
4629
4630 rtl8169_rx_csum(skb, opts1: status);
4631 skb->protocol = eth_type_trans(skb, dev);
4632
4633 rtl8169_rx_vlan_tag(desc, skb);
4634
4635 if (skb->pkt_type == PACKET_MULTICAST)
4636 dev->stats.multicast++;
4637
4638 napi_gro_receive(napi: &tp->napi, skb);
4639
4640 dev_sw_netstats_rx_add(dev, len: pkt_size);
4641release_descriptor:
4642 rtl8169_mark_to_asic(desc);
4643 }
4644
4645 return count;
4646}
4647
4648static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
4649{
4650 struct rtl8169_private *tp = dev_instance;
4651 u32 status = rtl_get_events(tp);
4652
4653 if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask))
4654 return IRQ_NONE;
4655
4656 /* At least RTL8168fp may unexpectedly set the SYSErr bit */
4657 if (unlikely(status & SYSErr &&
4658 tp->mac_version <= RTL_GIGA_MAC_VER_06)) {
4659 rtl8169_pcierr_interrupt(dev: tp->dev);
4660 goto out;
4661 }
4662
4663 if (status & LinkChg)
4664 phy_mac_interrupt(phydev: tp->phydev);
4665
4666 rtl_irq_disable(tp);
4667 napi_schedule(n: &tp->napi);
4668out:
4669 rtl_ack_events(tp, bits: status);
4670
4671 return IRQ_HANDLED;
4672}
4673
4674static void rtl_task(struct work_struct *work)
4675{
4676 struct rtl8169_private *tp =
4677 container_of(work, struct rtl8169_private, wk.work);
4678 int ret;
4679
4680 if (test_and_clear_bit(nr: RTL_FLAG_TASK_TX_TIMEOUT, addr: tp->wk.flags)) {
4681 /* if chip isn't accessible, reset bus to revive it */
4682 if (RTL_R32(tp, TxConfig) == ~0) {
4683 ret = pci_reset_bus(dev: tp->pci_dev);
4684 if (ret < 0) {
4685 netdev_err(dev: tp->dev, format: "Can't reset secondary PCI bus, detach NIC\n");
4686 netif_device_detach(dev: tp->dev);
4687 return;
4688 }
4689 }
4690
4691 /* ASPM compatibility issues are a typical reason for tx timeouts */
4692 ret = pci_disable_link_state(pdev: tp->pci_dev, PCIE_LINK_STATE_L1 |
4693 PCIE_LINK_STATE_L0S);
4694 if (!ret)
4695 netdev_warn_once(tp->dev, "ASPM disabled on Tx timeout\n");
4696 goto reset;
4697 }
4698
4699 if (test_and_clear_bit(nr: RTL_FLAG_TASK_RESET_PENDING, addr: tp->wk.flags)) {
4700reset:
4701 rtl_reset_work(tp);
4702 netif_wake_queue(dev: tp->dev);
4703 }
4704}
4705
4706static int rtl8169_poll(struct napi_struct *napi, int budget)
4707{
4708 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4709 struct net_device *dev = tp->dev;
4710 int work_done;
4711
4712 rtl_tx(dev, tp, budget);
4713
4714 work_done = rtl_rx(dev, tp, budget);
4715
4716 if (work_done < budget && napi_complete_done(n: napi, work_done))
4717 rtl_irq_enable(tp);
4718
4719 return work_done;
4720}
4721
4722static void rtl_enable_tx_lpi(struct rtl8169_private *tp, bool enable)
4723{
4724 if (!rtl_supports_eee(tp))
4725 return;
4726
4727 switch (tp->mac_version) {
4728 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_52:
4729 /* Adjust EEE LED frequency */
4730 if (tp->mac_version != RTL_GIGA_MAC_VER_38)
4731 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
4732 if (enable)
4733 rtl_eri_set_bits(tp, addr: 0x1b0, p: 0x0003);
4734 else
4735 rtl_eri_clear_bits(tp, addr: 0x1b0, m: 0x0003);
4736 break;
4737 case RTL_GIGA_MAC_VER_61:
4738 if (enable) {
4739 r8168_mac_ocp_modify(tp, reg: 0xe040, mask: 0, set: 0x0003);
4740 r8168_mac_ocp_modify(tp, reg: 0xeb62, mask: 0, set: 0x0006);
4741 } else {
4742 r8168_mac_ocp_modify(tp, reg: 0xe040, mask: 0x0003, set: 0);
4743 r8168_mac_ocp_modify(tp, reg: 0xeb62, mask: 0x0006, set: 0);
4744 }
4745 break;
4746 case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_LAST:
4747 if (enable)
4748 r8168_mac_ocp_modify(tp, reg: 0xe040, mask: 0, set: 0x0003);
4749 else
4750 r8168_mac_ocp_modify(tp, reg: 0xe040, mask: 0x0003, set: 0);
4751 break;
4752 default:
4753 break;
4754 }
4755}
4756
4757static void r8169_phylink_handler(struct net_device *ndev)
4758{
4759 struct rtl8169_private *tp = netdev_priv(dev: ndev);
4760 struct device *d = tp_to_dev(tp);
4761
4762 if (netif_carrier_ok(dev: ndev)) {
4763 rtl_link_chg_patch(tp);
4764 rtl_enable_tx_lpi(tp, enable: tp->phydev->enable_tx_lpi);
4765 pm_request_resume(dev: d);
4766 } else {
4767 pm_runtime_idle(dev: d);
4768 }
4769
4770 phy_print_status(phydev: tp->phydev);
4771}
4772
4773static int r8169_phy_connect(struct rtl8169_private *tp)
4774{
4775 struct phy_device *phydev = tp->phydev;
4776 phy_interface_t phy_mode;
4777 int ret;
4778
4779 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
4780 PHY_INTERFACE_MODE_MII;
4781
4782 ret = phy_connect_direct(dev: tp->dev, phydev, handler: r8169_phylink_handler,
4783 interface: phy_mode);
4784 if (ret)
4785 return ret;
4786
4787 if (!tp->supports_gmii)
4788 phy_set_max_speed(phydev, SPEED_100);
4789
4790 phy_attached_info(phydev);
4791
4792 return 0;
4793}
4794
4795static void rtl8169_down(struct rtl8169_private *tp)
4796{
4797 disable_work_sync(work: &tp->wk.work);
4798 /* Clear all task flags */
4799 bitmap_zero(dst: tp->wk.flags, nbits: RTL_FLAG_MAX);
4800
4801 phy_stop(phydev: tp->phydev);
4802
4803 rtl8169_update_counters(tp);
4804
4805 pci_clear_master(dev: tp->pci_dev);
4806 rtl_pci_commit(tp);
4807
4808 rtl8169_cleanup(tp);
4809 rtl_disable_exit_l1(tp);
4810 rtl_prepare_power_down(tp);
4811
4812 if (tp->dash_type != RTL_DASH_NONE && !tp->saved_wolopts)
4813 rtl8168_driver_stop(tp);
4814}
4815
4816static void rtl8169_up(struct rtl8169_private *tp)
4817{
4818 if (tp->dash_type != RTL_DASH_NONE)
4819 rtl8168_driver_start(tp);
4820
4821 pci_set_master(dev: tp->pci_dev);
4822 phy_init_hw(phydev: tp->phydev);
4823 phy_resume(phydev: tp->phydev);
4824 rtl8169_init_phy(tp);
4825 napi_enable(n: &tp->napi);
4826 enable_work(work: &tp->wk.work);
4827 rtl_reset_work(tp);
4828
4829 phy_start(phydev: tp->phydev);
4830}
4831
4832static int rtl8169_close(struct net_device *dev)
4833{
4834 struct rtl8169_private *tp = netdev_priv(dev);
4835 struct pci_dev *pdev = tp->pci_dev;
4836
4837 pm_runtime_get_sync(dev: &pdev->dev);
4838
4839 netif_stop_queue(dev);
4840 rtl8169_down(tp);
4841 rtl8169_rx_clear(tp);
4842
4843 free_irq(tp->irq, tp);
4844
4845 phy_disconnect(phydev: tp->phydev);
4846
4847 dma_free_coherent(dev: &pdev->dev, R8169_RX_RING_BYTES, cpu_addr: tp->RxDescArray,
4848 dma_handle: tp->RxPhyAddr);
4849 dma_free_coherent(dev: &pdev->dev, R8169_TX_RING_BYTES, cpu_addr: tp->TxDescArray,
4850 dma_handle: tp->TxPhyAddr);
4851 tp->TxDescArray = NULL;
4852 tp->RxDescArray = NULL;
4853
4854 pm_runtime_put_sync(dev: &pdev->dev);
4855
4856 return 0;
4857}
4858
4859#ifdef CONFIG_NET_POLL_CONTROLLER
4860static void rtl8169_netpoll(struct net_device *dev)
4861{
4862 struct rtl8169_private *tp = netdev_priv(dev);
4863
4864 rtl8169_interrupt(irq: tp->irq, dev_instance: tp);
4865}
4866#endif
4867
4868static int rtl_open(struct net_device *dev)
4869{
4870 struct rtl8169_private *tp = netdev_priv(dev);
4871 struct pci_dev *pdev = tp->pci_dev;
4872 unsigned long irqflags;
4873 int retval = -ENOMEM;
4874
4875 pm_runtime_get_sync(dev: &pdev->dev);
4876
4877 /*
4878 * Rx and Tx descriptors needs 256 bytes alignment.
4879 * dma_alloc_coherent provides more.
4880 */
4881 tp->TxDescArray = dma_alloc_coherent(dev: &pdev->dev, R8169_TX_RING_BYTES,
4882 dma_handle: &tp->TxPhyAddr, GFP_KERNEL);
4883 if (!tp->TxDescArray)
4884 goto out;
4885
4886 tp->RxDescArray = dma_alloc_coherent(dev: &pdev->dev, R8169_RX_RING_BYTES,
4887 dma_handle: &tp->RxPhyAddr, GFP_KERNEL);
4888 if (!tp->RxDescArray)
4889 goto err_free_tx_0;
4890
4891 retval = rtl8169_init_ring(tp);
4892 if (retval < 0)
4893 goto err_free_rx_1;
4894
4895 rtl_request_firmware(tp);
4896
4897 irqflags = pci_dev_msi_enabled(pci_dev: pdev) ? IRQF_NO_THREAD : IRQF_SHARED;
4898 retval = request_irq(irq: tp->irq, handler: rtl8169_interrupt, flags: irqflags, name: dev->name, dev: tp);
4899 if (retval < 0)
4900 goto err_release_fw_2;
4901
4902 retval = r8169_phy_connect(tp);
4903 if (retval)
4904 goto err_free_irq;
4905
4906 rtl8169_up(tp);
4907 rtl8169_init_counter_offsets(tp);
4908 netif_start_queue(dev);
4909out:
4910 pm_runtime_put_sync(dev: &pdev->dev);
4911
4912 return retval;
4913
4914err_free_irq:
4915 free_irq(tp->irq, tp);
4916err_release_fw_2:
4917 rtl_release_firmware(tp);
4918 rtl8169_rx_clear(tp);
4919err_free_rx_1:
4920 dma_free_coherent(dev: &pdev->dev, R8169_RX_RING_BYTES, cpu_addr: tp->RxDescArray,
4921 dma_handle: tp->RxPhyAddr);
4922 tp->RxDescArray = NULL;
4923err_free_tx_0:
4924 dma_free_coherent(dev: &pdev->dev, R8169_TX_RING_BYTES, cpu_addr: tp->TxDescArray,
4925 dma_handle: tp->TxPhyAddr);
4926 tp->TxDescArray = NULL;
4927 goto out;
4928}
4929
4930static void
4931rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
4932{
4933 struct rtl8169_private *tp = netdev_priv(dev);
4934 struct pci_dev *pdev = tp->pci_dev;
4935 struct rtl8169_counters *counters = tp->counters;
4936
4937 pm_runtime_get_noresume(dev: &pdev->dev);
4938
4939 netdev_stats_to_stats64(stats64: stats, netdev_stats: &dev->stats);
4940 dev_fetch_sw_netstats(s: stats, netstats: dev->tstats);
4941
4942 /*
4943 * Fetch additional counter values missing in stats collected by driver
4944 * from tally counters.
4945 */
4946 if (pm_runtime_active(dev: &pdev->dev))
4947 rtl8169_update_counters(tp);
4948
4949 /*
4950 * Subtract values fetched during initalization.
4951 * See rtl8169_init_counter_offsets for a description why we do that.
4952 */
4953 stats->tx_errors = le64_to_cpu(counters->tx_errors) -
4954 le64_to_cpu(tp->tc_offset.tx_errors);
4955 stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
4956 le32_to_cpu(tp->tc_offset.tx_multi_collision);
4957 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
4958 le16_to_cpu(tp->tc_offset.tx_aborted);
4959 stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) -
4960 le16_to_cpu(tp->tc_offset.rx_missed);
4961
4962 pm_runtime_put_noidle(dev: &pdev->dev);
4963}
4964
4965static void rtl8169_net_suspend(struct rtl8169_private *tp)
4966{
4967 netif_device_detach(dev: tp->dev);
4968
4969 if (netif_running(dev: tp->dev))
4970 rtl8169_down(tp);
4971}
4972
4973static int rtl8169_runtime_resume(struct device *dev)
4974{
4975 struct rtl8169_private *tp = dev_get_drvdata(dev);
4976
4977 rtl_rar_set(tp, addr: tp->dev->dev_addr);
4978 __rtl8169_set_wol(tp, wolopts: tp->saved_wolopts);
4979
4980 if (tp->TxDescArray)
4981 rtl8169_up(tp);
4982
4983 netif_device_attach(dev: tp->dev);
4984
4985 return 0;
4986}
4987
4988static int rtl8169_suspend(struct device *device)
4989{
4990 struct rtl8169_private *tp = dev_get_drvdata(dev: device);
4991
4992 rtnl_lock();
4993 rtl8169_net_suspend(tp);
4994 if (!device_may_wakeup(dev: tp_to_dev(tp)))
4995 clk_disable_unprepare(clk: tp->clk);
4996 rtnl_unlock();
4997
4998 return 0;
4999}
5000
5001static int rtl8169_resume(struct device *device)
5002{
5003 struct rtl8169_private *tp = dev_get_drvdata(dev: device);
5004
5005 if (!device_may_wakeup(dev: tp_to_dev(tp)))
5006 clk_prepare_enable(clk: tp->clk);
5007
5008 /* Some chip versions may truncate packets without this initialization */
5009 rtl_init_rxcfg(tp);
5010
5011 return rtl8169_runtime_resume(dev: device);
5012}
5013
5014static int rtl8169_runtime_suspend(struct device *device)
5015{
5016 struct rtl8169_private *tp = dev_get_drvdata(dev: device);
5017
5018 if (!tp->TxDescArray) {
5019 netif_device_detach(dev: tp->dev);
5020 return 0;
5021 }
5022
5023 rtnl_lock();
5024 __rtl8169_set_wol(tp, WAKE_PHY);
5025 rtl8169_net_suspend(tp);
5026 rtnl_unlock();
5027
5028 return 0;
5029}
5030
5031static int rtl8169_runtime_idle(struct device *device)
5032{
5033 struct rtl8169_private *tp = dev_get_drvdata(dev: device);
5034
5035 if (tp->dash_enabled)
5036 return -EBUSY;
5037
5038 if (!netif_running(dev: tp->dev) || !netif_carrier_ok(dev: tp->dev))
5039 pm_schedule_suspend(dev: device, delay: 10000);
5040
5041 return -EBUSY;
5042}
5043
5044static const struct dev_pm_ops rtl8169_pm_ops = {
5045 SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume)
5046 RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume,
5047 rtl8169_runtime_idle)
5048};
5049
5050static void rtl_shutdown(struct pci_dev *pdev)
5051{
5052 struct rtl8169_private *tp = pci_get_drvdata(pdev);
5053
5054 rtnl_lock();
5055 rtl8169_net_suspend(tp);
5056 rtnl_unlock();
5057
5058 /* Restore original MAC address */
5059 rtl_rar_set(tp, addr: tp->dev->perm_addr);
5060
5061 if (system_state == SYSTEM_POWER_OFF && !tp->dash_enabled)
5062 pci_prepare_to_sleep(dev: pdev);
5063}
5064
5065static void rtl_remove_one(struct pci_dev *pdev)
5066{
5067 struct rtl8169_private *tp = pci_get_drvdata(pdev);
5068
5069 if (pci_dev_run_wake(dev: pdev))
5070 pm_runtime_get_noresume(dev: &pdev->dev);
5071
5072 disable_work_sync(work: &tp->wk.work);
5073
5074 if (IS_ENABLED(CONFIG_R8169_LEDS))
5075 r8169_remove_leds(leds: tp->leds);
5076
5077 unregister_netdev(dev: tp->dev);
5078
5079 if (tp->dash_type != RTL_DASH_NONE)
5080 rtl8168_driver_stop(tp);
5081
5082 rtl_release_firmware(tp);
5083
5084 /* restore original MAC address */
5085 rtl_rar_set(tp, addr: tp->dev->perm_addr);
5086}
5087
5088static const struct net_device_ops rtl_netdev_ops = {
5089 .ndo_open = rtl_open,
5090 .ndo_stop = rtl8169_close,
5091 .ndo_get_stats64 = rtl8169_get_stats64,
5092 .ndo_start_xmit = rtl8169_start_xmit,
5093 .ndo_features_check = rtl8169_features_check,
5094 .ndo_tx_timeout = rtl8169_tx_timeout,
5095 .ndo_validate_addr = eth_validate_addr,
5096 .ndo_change_mtu = rtl8169_change_mtu,
5097 .ndo_fix_features = rtl8169_fix_features,
5098 .ndo_set_features = rtl8169_set_features,
5099 .ndo_set_mac_address = rtl_set_mac_address,
5100 .ndo_eth_ioctl = phy_do_ioctl_running,
5101 .ndo_set_rx_mode = rtl_set_rx_mode,
5102#ifdef CONFIG_NET_POLL_CONTROLLER
5103 .ndo_poll_controller = rtl8169_netpoll,
5104#endif
5105
5106};
5107
5108static void rtl_set_irq_mask(struct rtl8169_private *tp)
5109{
5110 tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg;
5111
5112 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
5113 tp->irq_mask |= SYSErr | RxFIFOOver;
5114}
5115
5116static int rtl_alloc_irq(struct rtl8169_private *tp)
5117{
5118 unsigned int flags;
5119
5120 switch (tp->mac_version) {
5121 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5122 rtl_unlock_config_regs(tp);
5123 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
5124 rtl_lock_config_regs(tp);
5125 fallthrough;
5126 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17:
5127 flags = PCI_IRQ_INTX;
5128 break;
5129 default:
5130 flags = PCI_IRQ_ALL_TYPES;
5131 break;
5132 }
5133
5134 return pci_alloc_irq_vectors(dev: tp->pci_dev, min_vecs: 1, max_vecs: 1, flags);
5135}
5136
5137static void rtl_read_mac_address(struct rtl8169_private *tp,
5138 u8 mac_addr[ETH_ALEN])
5139{
5140 /* Get MAC address */
5141 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) {
5142 u32 value;
5143
5144 value = rtl_eri_read(tp, addr: 0xe0);
5145 put_unaligned_le32(val: value, p: mac_addr);
5146 value = rtl_eri_read(tp, addr: 0xe4);
5147 put_unaligned_le16(val: value, p: mac_addr + 4);
5148 } else if (rtl_is_8125(tp)) {
5149 rtl_read_mac_from_reg(tp, mac: mac_addr, reg: MAC0_BKP);
5150 }
5151}
5152
5153DECLARE_RTL_COND(rtl_link_list_ready_cond)
5154{
5155 return RTL_R8(tp, MCU) & LINK_LIST_RDY;
5156}
5157
5158static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp)
5159{
5160 rtl_loop_wait_high(tp, c: &rtl_link_list_ready_cond, d: 100, n: 42);
5161}
5162
5163static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
5164{
5165 struct rtl8169_private *tp = mii_bus->priv;
5166
5167 if (phyaddr > 0)
5168 return -ENODEV;
5169
5170 return rtl_readphy(tp, location: phyreg);
5171}
5172
5173static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
5174 int phyreg, u16 val)
5175{
5176 struct rtl8169_private *tp = mii_bus->priv;
5177
5178 if (phyaddr > 0)
5179 return -ENODEV;
5180
5181 rtl_writephy(tp, location: phyreg, val);
5182
5183 return 0;
5184}
5185
5186static int r8169_mdio_read_reg_c45(struct mii_bus *mii_bus, int addr,
5187 int devnum, int regnum)
5188{
5189 struct rtl8169_private *tp = mii_bus->priv;
5190
5191 if (addr > 0)
5192 return -ENODEV;
5193
5194 if (devnum == MDIO_MMD_VEND2 && regnum > MDIO_STAT2)
5195 return r8168_phy_ocp_read(tp, reg: regnum);
5196
5197 return 0;
5198}
5199
5200static int r8169_mdio_write_reg_c45(struct mii_bus *mii_bus, int addr,
5201 int devnum, int regnum, u16 val)
5202{
5203 struct rtl8169_private *tp = mii_bus->priv;
5204
5205 if (addr > 0 || devnum != MDIO_MMD_VEND2 || regnum <= MDIO_STAT2)
5206 return -ENODEV;
5207
5208 r8168_phy_ocp_write(tp, reg: regnum, data: val);
5209
5210 return 0;
5211}
5212
5213static int r8169_mdio_register(struct rtl8169_private *tp)
5214{
5215 struct pci_dev *pdev = tp->pci_dev;
5216 struct mii_bus *new_bus;
5217 int ret;
5218
5219 /* On some boards with this chip version the BIOS is buggy and misses
5220 * to reset the PHY page selector. This results in the PHY ID read
5221 * accessing registers on a different page, returning a more or
5222 * less random value. Fix this by resetting the page selector first.
5223 */
5224 if (tp->mac_version == RTL_GIGA_MAC_VER_25 ||
5225 tp->mac_version == RTL_GIGA_MAC_VER_26)
5226 r8169_mdio_write(tp, reg: 0x1f, value: 0);
5227
5228 new_bus = devm_mdiobus_alloc(dev: &pdev->dev);
5229 if (!new_bus)
5230 return -ENOMEM;
5231
5232 new_bus->name = "r8169";
5233 new_bus->priv = tp;
5234 new_bus->parent = &pdev->dev;
5235 new_bus->irq[0] = PHY_MAC_INTERRUPT;
5236 new_bus->phy_mask = GENMASK(31, 1);
5237 snprintf(buf: new_bus->id, MII_BUS_ID_SIZE, fmt: "r8169-%x-%x",
5238 pci_domain_nr(bus: pdev->bus), pci_dev_id(dev: pdev));
5239
5240 new_bus->read = r8169_mdio_read_reg;
5241 new_bus->write = r8169_mdio_write_reg;
5242
5243 if (tp->mac_version >= RTL_GIGA_MAC_VER_40) {
5244 new_bus->read_c45 = r8169_mdio_read_reg_c45;
5245 new_bus->write_c45 = r8169_mdio_write_reg_c45;
5246 }
5247
5248 ret = devm_mdiobus_register(&pdev->dev, new_bus);
5249 if (ret)
5250 return ret;
5251
5252 tp->phydev = mdiobus_get_phy(bus: new_bus, addr: 0);
5253 if (!tp->phydev) {
5254 return -ENODEV;
5255 } else if (!tp->phydev->drv) {
5256 /* Most chip versions fail with the genphy driver.
5257 * Therefore ensure that the dedicated PHY driver is loaded.
5258 */
5259 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n",
5260 tp->phydev->phy_id);
5261 return -EUNATCH;
5262 }
5263
5264 tp->phydev->mac_managed_pm = true;
5265 if (rtl_supports_eee(tp))
5266 phy_support_eee(phydev: tp->phydev);
5267 phy_support_asym_pause(phydev: tp->phydev);
5268
5269 /* mimic behavior of r8125/r8126 vendor drivers */
5270 if (tp->mac_version == RTL_GIGA_MAC_VER_61)
5271 phy_disable_eee_mode(phydev: tp->phydev,
5272 link_mode: ETHTOOL_LINK_MODE_2500baseT_Full_BIT);
5273
5274 /* PHY will be woken up in rtl_open() */
5275 phy_suspend(phydev: tp->phydev);
5276
5277 return 0;
5278}
5279
5280static void rtl_hw_init_8168g(struct rtl8169_private *tp)
5281{
5282 rtl_enable_rxdvgate(tp);
5283
5284 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
5285 msleep(msecs: 1);
5286 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5287
5288 r8168_mac_ocp_modify(tp, reg: 0xe8de, BIT(14), set: 0);
5289 r8168g_wait_ll_share_fifo_ready(tp);
5290
5291 r8168_mac_ocp_modify(tp, reg: 0xe8de, mask: 0, BIT(15));
5292 r8168g_wait_ll_share_fifo_ready(tp);
5293}
5294
5295static void rtl_hw_init_8125(struct rtl8169_private *tp)
5296{
5297 rtl_enable_rxdvgate(tp);
5298
5299 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
5300 msleep(msecs: 1);
5301 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5302
5303 r8168_mac_ocp_modify(tp, reg: 0xe8de, BIT(14), set: 0);
5304 r8168g_wait_ll_share_fifo_ready(tp);
5305
5306 r8168_mac_ocp_write(tp, reg: 0xc0aa, data: 0x07d0);
5307 r8168_mac_ocp_write(tp, reg: 0xc0a6, data: 0x0150);
5308 r8168_mac_ocp_write(tp, reg: 0xc01e, data: 0x5555);
5309 r8168g_wait_ll_share_fifo_ready(tp);
5310}
5311
5312static void rtl_hw_initialize(struct rtl8169_private *tp)
5313{
5314 switch (tp->mac_version) {
5315 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_52:
5316 rtl8168ep_stop_cmac(tp);
5317 fallthrough;
5318 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
5319 rtl_hw_init_8168g(tp);
5320 break;
5321 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST:
5322 rtl_hw_init_8125(tp);
5323 break;
5324 default:
5325 break;
5326 }
5327}
5328
5329static int rtl_jumbo_max(struct rtl8169_private *tp)
5330{
5331 /* Non-GBit versions don't support jumbo frames */
5332 if (!tp->supports_gmii)
5333 return 0;
5334
5335 switch (tp->mac_version) {
5336 /* RTL8169 */
5337 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5338 return JUMBO_7K;
5339 /* RTL8168b */
5340 case RTL_GIGA_MAC_VER_17:
5341 return JUMBO_4K;
5342 /* RTL8168c */
5343 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
5344 return JUMBO_6K;
5345 /* RTL8125/8126 */
5346 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST:
5347 return JUMBO_16K;
5348 default:
5349 return JUMBO_9K;
5350 }
5351}
5352
5353static void rtl_init_mac_address(struct rtl8169_private *tp)
5354{
5355 u8 mac_addr[ETH_ALEN] __aligned(2) = {};
5356 struct net_device *dev = tp->dev;
5357 int rc;
5358
5359 rc = eth_platform_get_mac_address(dev: tp_to_dev(tp), mac_addr);
5360 if (!rc)
5361 goto done;
5362
5363 rtl_read_mac_address(tp, mac_addr);
5364 if (is_valid_ether_addr(addr: mac_addr))
5365 goto done;
5366
5367 rtl_read_mac_from_reg(tp, mac: mac_addr, reg: MAC0);
5368 if (is_valid_ether_addr(addr: mac_addr))
5369 goto done;
5370
5371 eth_random_addr(addr: mac_addr);
5372 dev->addr_assign_type = NET_ADDR_RANDOM;
5373 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n");
5374done:
5375 eth_hw_addr_set(dev, addr: mac_addr);
5376 rtl_rar_set(tp, addr: mac_addr);
5377}
5378
5379/* register is set if system vendor successfully tested ASPM 1.2 */
5380static bool rtl_aspm_is_safe(struct rtl8169_private *tp)
5381{
5382 if (tp->mac_version >= RTL_GIGA_MAC_VER_46 &&
5383 r8168_mac_ocp_read(tp, reg: 0xc0b2) & 0xf)
5384 return true;
5385
5386 return false;
5387}
5388
5389static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5390{
5391 const struct rtl_chip_info *chip;
5392 struct rtl8169_private *tp;
5393 int jumbo_max, region, rc;
5394 struct net_device *dev;
5395 u32 txconfig;
5396 u16 xid;
5397
5398 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
5399 if (!dev)
5400 return -ENOMEM;
5401
5402 SET_NETDEV_DEV(dev, &pdev->dev);
5403 dev->netdev_ops = &rtl_netdev_ops;
5404 tp = netdev_priv(dev);
5405 tp->dev = dev;
5406 tp->pci_dev = pdev;
5407 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1;
5408 tp->ocp_base = OCP_STD_PHY_BASE;
5409
5410 raw_spin_lock_init(&tp->mac_ocp_lock);
5411 mutex_init(&tp->led_lock);
5412
5413 /* Get the *optional* external "ether_clk" used on some boards */
5414 tp->clk = devm_clk_get_optional_enabled(dev: &pdev->dev, id: "ether_clk");
5415 if (IS_ERR(ptr: tp->clk))
5416 return dev_err_probe(dev: &pdev->dev, err: PTR_ERR(ptr: tp->clk), fmt: "failed to get ether_clk\n");
5417
5418 /* enable device (incl. PCI PM wakeup and hotplug setup) */
5419 rc = pcim_enable_device(pdev);
5420 if (rc < 0)
5421 return dev_err_probe(dev: &pdev->dev, err: rc, fmt: "enable failure\n");
5422
5423 if (pcim_set_mwi(dev: pdev) < 0)
5424 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
5425
5426 /* use first MMIO region */
5427 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
5428 if (region < 0)
5429 return dev_err_probe(dev: &pdev->dev, err: -ENODEV, fmt: "no MMIO resource found\n");
5430
5431 tp->mmio_addr = pcim_iomap_region(pdev, bar: region, KBUILD_MODNAME);
5432 if (IS_ERR(ptr: tp->mmio_addr))
5433 return dev_err_probe(dev: &pdev->dev, err: PTR_ERR(ptr: tp->mmio_addr),
5434 fmt: "cannot remap MMIO, aborting\n");
5435
5436 txconfig = RTL_R32(tp, TxConfig);
5437 if (txconfig == ~0U)
5438 return dev_err_probe(dev: &pdev->dev, err: -EIO, fmt: "PCI read failed\n");
5439
5440 xid = (txconfig >> 20) & 0xfcf;
5441
5442 /* Identify chip attached to board */
5443 chip = rtl8169_get_chip_version(xid, gmii: tp->supports_gmii);
5444 if (chip->mac_version == RTL_GIGA_MAC_NONE)
5445 return dev_err_probe(dev: &pdev->dev, err: -ENODEV,
5446 fmt: "unknown chip XID %03x, contact r8169 maintainers (see MAINTAINERS file)\n",
5447 xid);
5448 tp->mac_version = chip->mac_version;
5449 tp->fw_name = chip->fw_name;
5450
5451 /* Disable ASPM L1 as that cause random device stop working
5452 * problems as well as full system hangs for some PCIe devices users.
5453 */
5454 if (rtl_aspm_is_safe(tp)) {
5455 dev_info(&pdev->dev, "System vendor flags ASPM as safe\n");
5456 rc = 0;
5457 } else {
5458 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1);
5459 }
5460 tp->aspm_manageable = !rc;
5461
5462 /* Fiber mode on RTL8127AF isn't supported */
5463 if (rtl_is_8125(tp)) {
5464 u16 data = r8168_mac_ocp_read(tp, reg: 0xd006);
5465
5466 if ((data & 0xff) == 0x07)
5467 return dev_err_probe(dev: &pdev->dev, err: -ENODEV,
5468 fmt: "Fiber mode not supported\n");
5469 }
5470
5471 tp->dash_type = rtl_get_dash_type(tp);
5472 tp->dash_enabled = rtl_dash_is_enabled(tp);
5473
5474 tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK;
5475
5476 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
5477 !dma_set_mask_and_coherent(dev: &pdev->dev, DMA_BIT_MASK(64)))
5478 dev->features |= NETIF_F_HIGHDMA;
5479
5480 rtl_init_rxcfg(tp);
5481
5482 rtl8169_irq_mask_and_ack(tp);
5483
5484 rtl_hw_initialize(tp);
5485
5486 rtl_hw_reset(tp);
5487
5488 rc = rtl_alloc_irq(tp);
5489 if (rc < 0)
5490 return dev_err_probe(dev: &pdev->dev, err: rc, fmt: "Can't allocate interrupt\n");
5491
5492 tp->irq = pci_irq_vector(dev: pdev, nr: 0);
5493
5494 INIT_WORK(&tp->wk.work, rtl_task);
5495 disable_work(work: &tp->wk.work);
5496
5497 rtl_init_mac_address(tp);
5498
5499 dev->ethtool_ops = &rtl8169_ethtool_ops;
5500
5501 netif_napi_add(dev, napi: &tp->napi, poll: rtl8169_poll);
5502
5503 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
5504 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
5505 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
5506 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
5507
5508 /*
5509 * Pretend we are using VLANs; This bypasses a nasty bug where
5510 * Interrupts stop flowing on high load on 8110SCd controllers.
5511 */
5512 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
5513 /* Disallow toggling */
5514 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
5515
5516 if (rtl_chip_supports_csum_v2(tp))
5517 dev->hw_features |= NETIF_F_IPV6_CSUM;
5518
5519 dev->features |= dev->hw_features;
5520
5521 if (rtl_chip_supports_csum_v2(tp)) {
5522 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6;
5523 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V2);
5524 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V2);
5525 } else {
5526 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO;
5527 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V1);
5528 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V1);
5529 }
5530
5531 /* There has been a number of reports that using SG/TSO results in
5532 * tx timeouts. However for a lot of people SG/TSO works fine.
5533 * It's not fully clear which chip versions are affected. Vendor
5534 * drivers enable SG/TSO for certain chip versions per default,
5535 * let's mimic this here. On other chip versions users can
5536 * use ethtool to enable SG/TSO, use at own risk!
5537 */
5538 if (tp->mac_version >= RTL_GIGA_MAC_VER_46 &&
5539 tp->mac_version != RTL_GIGA_MAC_VER_61)
5540 dev->features |= dev->hw_features;
5541
5542 dev->hw_features |= NETIF_F_RXALL;
5543 dev->hw_features |= NETIF_F_RXFCS;
5544
5545 dev->pcpu_stat_type = NETDEV_PCPU_STAT_TSTATS;
5546
5547 netdev_sw_irq_coalesce_default_on(dev);
5548
5549 /* configure chip for default features */
5550 rtl8169_set_features(dev, features: dev->features);
5551
5552 if (!tp->dash_enabled) {
5553 rtl_set_d3_pll_down(tp, enable: true);
5554 } else {
5555 rtl_set_d3_pll_down(tp, enable: false);
5556 dev->ethtool->wol_enabled = 1;
5557 }
5558
5559 jumbo_max = rtl_jumbo_max(tp);
5560 if (jumbo_max)
5561 dev->max_mtu = jumbo_max;
5562
5563 rtl_set_irq_mask(tp);
5564
5565 tp->counters = dmam_alloc_coherent (dev: &pdev->dev, size: sizeof(*tp->counters),
5566 dma_handle: &tp->counters_phys_addr,
5567 GFP_KERNEL);
5568 if (!tp->counters)
5569 return -ENOMEM;
5570
5571 pci_set_drvdata(pdev, data: tp);
5572
5573 rc = r8169_mdio_register(tp);
5574 if (rc)
5575 return rc;
5576
5577 rc = register_netdev(dev);
5578 if (rc)
5579 return rc;
5580
5581 if (IS_ENABLED(CONFIG_R8169_LEDS)) {
5582 if (rtl_is_8125(tp))
5583 tp->leds = rtl8125_init_leds(ndev: dev);
5584 else if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5585 tp->leds = rtl8168_init_leds(ndev: dev);
5586 }
5587
5588 netdev_info(dev, format: "%s, %pM, XID %03x, IRQ %d\n",
5589 chip->name, dev->dev_addr, xid, tp->irq);
5590
5591 if (jumbo_max)
5592 netdev_info(dev, format: "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
5593 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
5594 "ok" : "ko");
5595
5596 if (tp->dash_type != RTL_DASH_NONE) {
5597 netdev_info(dev, format: "DASH %s\n",
5598 tp->dash_enabled ? "enabled" : "disabled");
5599 rtl8168_driver_start(tp);
5600 }
5601
5602 if (pci_dev_run_wake(dev: pdev))
5603 pm_runtime_put_sync(dev: &pdev->dev);
5604
5605 return 0;
5606}
5607
5608static struct pci_driver rtl8169_pci_driver = {
5609 .name = KBUILD_MODNAME,
5610 .id_table = rtl8169_pci_tbl,
5611 .probe = rtl_init_one,
5612 .remove = rtl_remove_one,
5613 .shutdown = rtl_shutdown,
5614 .driver.pm = pm_ptr(&rtl8169_pm_ops),
5615};
5616
5617module_pci_driver(rtl8169_pci_driver);
5618

source code of linux/drivers/net/ethernet/realtek/r8169_main.c