1	// SPDX-License-Identifier: GPL-2.0-only
2	/*
3	* Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
4	*/
5
6	#include <linux/signal.h>
7	#include <linux/slab.h>
8	#include <linux/module.h>
9	#include <linux/netdevice.h>
10	#include <linux/etherdevice.h>
11	#include <linux/mii.h>
12	#include <linux/ethtool.h>
13	#include <linux/phy.h>
14	#include <linux/usb.h>
15	#include <linux/crc32.h>
16	#include <linux/if_vlan.h>
17	#include <linux/uaccess.h>
18	#include <linux/list.h>
19	#include <linux/ip.h>
20	#include <linux/ipv6.h>
21	#include <net/ip6_checksum.h>
22	#include <uapi/linux/mdio.h>
23	#include <linux/mdio.h>
24	#include <linux/usb/cdc.h>
25	#include <linux/suspend.h>
26	#include <linux/atomic.h>
27	#include <linux/acpi.h>
28	#include <linux/firmware.h>
29	#include <crypto/hash.h>
30	#include <linux/usb/r8152.h>
31	#include <net/gso.h>
32
33	/* Information for net-next */
34	#define NETNEXT_VERSION "12"
35
36	/* Information for net */
37	#define NET_VERSION "13"
38
39	#define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION
40	#define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
41	#define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
42	#define MODULENAME "r8152"
43
44	#define R8152_PHY_ID 32
45
46	#define PLA_IDR 0xc000
47	#define PLA_RCR 0xc010
48	#define PLA_RCR1 0xc012
49	#define PLA_RMS 0xc016
50	#define PLA_RXFIFO_CTRL0 0xc0a0
51	#define PLA_RXFIFO_FULL 0xc0a2
52	#define PLA_RXFIFO_CTRL1 0xc0a4
53	#define PLA_RX_FIFO_FULL 0xc0a6
54	#define PLA_RXFIFO_CTRL2 0xc0a8
55	#define PLA_RX_FIFO_EMPTY 0xc0aa
56	#define PLA_DMY_REG0 0xc0b0
57	#define PLA_FMC 0xc0b4
58	#define PLA_CFG_WOL 0xc0b6
59	#define PLA_TEREDO_CFG 0xc0bc
60	#define PLA_TEREDO_WAKE_BASE 0xc0c4
61	#define PLA_MAR 0xcd00
62	#define PLA_BACKUP 0xd000
63	#define PLA_BDC_CR 0xd1a0
64	#define PLA_TEREDO_TIMER 0xd2cc
65	#define PLA_REALWOW_TIMER 0xd2e8
66	#define PLA_UPHY_TIMER 0xd388
67	#define PLA_SUSPEND_FLAG 0xd38a
68	#define PLA_INDICATE_FALG 0xd38c
69	#define PLA_MACDBG_PRE 0xd38c /* RTL_VER_04 only */
70	#define PLA_MACDBG_POST 0xd38e /* RTL_VER_04 only */
71	#define PLA_EXTRA_STATUS 0xd398
72	#define PLA_GPHY_CTRL 0xd3ae
73	#define PLA_POL_GPIO_CTRL 0xdc6a
74	#define PLA_EFUSE_DATA 0xdd00
75	#define PLA_EFUSE_CMD 0xdd02
76	#define PLA_LEDSEL 0xdd90
77	#define PLA_LED_FEATURE 0xdd92
78	#define PLA_PHYAR 0xde00
79	#define PLA_BOOT_CTRL 0xe004
80	#define PLA_LWAKE_CTRL_REG 0xe007
81	#define PLA_GPHY_INTR_IMR 0xe022
82	#define PLA_EEE_CR 0xe040
83	#define PLA_EEE_TXTWSYS 0xe04c
84	#define PLA_EEE_TXTWSYS_2P5G 0xe058
85	#define PLA_EEEP_CR 0xe080
86	#define PLA_MAC_PWR_CTRL 0xe0c0
87	#define PLA_MAC_PWR_CTRL2 0xe0ca
88	#define PLA_MAC_PWR_CTRL3 0xe0cc
89	#define PLA_MAC_PWR_CTRL4 0xe0ce
90	#define PLA_WDT6_CTRL 0xe428
91	#define PLA_TCR0 0xe610
92	#define PLA_TCR1 0xe612
93	#define PLA_MTPS 0xe615
94	#define PLA_TXFIFO_CTRL 0xe618
95	#define PLA_TXFIFO_FULL 0xe61a
96	#define PLA_RSTTALLY 0xe800
97	#define PLA_CR 0xe813
98	#define PLA_CRWECR 0xe81c
99	#define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
100	#define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
101	#define PLA_CONFIG5 0xe822
102	#define PLA_PHY_PWR 0xe84c
103	#define PLA_OOB_CTRL 0xe84f
104	#define PLA_CPCR 0xe854
105	#define PLA_MISC_0 0xe858
106	#define PLA_MISC_1 0xe85a
107	#define PLA_OCP_GPHY_BASE 0xe86c
108	#define PLA_TALLYCNT 0xe890
109	#define PLA_SFF_STS_7 0xe8de
110	#define PLA_PHYSTATUS 0xe908
111	#define PLA_CONFIG6 0xe90a /* CONFIG6 */
112	#define PLA_USB_CFG 0xe952
113	#define PLA_BP_BA 0xfc26
114	#define PLA_BP_0 0xfc28
115	#define PLA_BP_1 0xfc2a
116	#define PLA_BP_2 0xfc2c
117	#define PLA_BP_3 0xfc2e
118	#define PLA_BP_4 0xfc30
119	#define PLA_BP_5 0xfc32
120	#define PLA_BP_6 0xfc34
121	#define PLA_BP_7 0xfc36
122	#define PLA_BP_EN 0xfc38
123
124	#define USB_USB2PHY 0xb41e
125	#define USB_SSPHYLINK1 0xb426
126	#define USB_SSPHYLINK2 0xb428
127	#define USB_L1_CTRL 0xb45e
128	#define USB_U2P3_CTRL 0xb460
129	#define USB_CSR_DUMMY1 0xb464
130	#define USB_CSR_DUMMY2 0xb466
131	#define USB_DEV_STAT 0xb808
132	#define USB_CONNECT_TIMER 0xcbf8
133	#define USB_MSC_TIMER 0xcbfc
134	#define USB_BURST_SIZE 0xcfc0
135	#define USB_FW_FIX_EN0 0xcfca
136	#define USB_FW_FIX_EN1 0xcfcc
137	#define USB_LPM_CONFIG 0xcfd8
138	#define USB_ECM_OPTION 0xcfee
139	#define USB_CSTMR 0xcfef /* RTL8153A */
140	#define USB_MISC_2 0xcfff
141	#define USB_ECM_OP 0xd26b
142	#define USB_GPHY_CTRL 0xd284
143	#define USB_SPEED_OPTION 0xd32a
144	#define USB_FW_CTRL 0xd334 /* RTL8153B */
145	#define USB_FC_TIMER 0xd340
146	#define USB_USB_CTRL 0xd406
147	#define USB_PHY_CTRL 0xd408
148	#define USB_TX_AGG 0xd40a
149	#define USB_RX_BUF_TH 0xd40c
150	#define USB_USB_TIMER 0xd428
151	#define USB_RX_EARLY_TIMEOUT 0xd42c
152	#define USB_RX_EARLY_SIZE 0xd42e
153	#define USB_PM_CTRL_STATUS 0xd432 /* RTL8153A */
154	#define USB_RX_EXTRA_AGGR_TMR 0xd432 /* RTL8153B */
155	#define USB_TX_DMA 0xd434
156	#define USB_UPT_RXDMA_OWN 0xd437
157	#define USB_UPHY3_MDCMDIO 0xd480
158	#define USB_TOLERANCE 0xd490
159	#define USB_LPM_CTRL 0xd41a
160	#define USB_BMU_RESET 0xd4b0
161	#define USB_BMU_CONFIG 0xd4b4
162	#define USB_U1U2_TIMER 0xd4da
163	#define USB_FW_TASK 0xd4e8 /* RTL8153B */
164	#define USB_RX_AGGR_NUM 0xd4ee
165	#define USB_UPS_CTRL 0xd800
166	#define USB_POWER_CUT 0xd80a
167	#define USB_MISC_0 0xd81a
168	#define USB_MISC_1 0xd81f
169	#define USB_AFE_CTRL2 0xd824
170	#define USB_UPHY_XTAL 0xd826
171	#define USB_UPS_CFG 0xd842
172	#define USB_UPS_FLAGS 0xd848
173	#define USB_WDT1_CTRL 0xe404
174	#define USB_WDT11_CTRL 0xe43c
175	#define USB_BP_BA PLA_BP_BA
176	#define USB_BP_0 PLA_BP_0
177	#define USB_BP_1 PLA_BP_1
178	#define USB_BP_2 PLA_BP_2
179	#define USB_BP_3 PLA_BP_3
180	#define USB_BP_4 PLA_BP_4
181	#define USB_BP_5 PLA_BP_5
182	#define USB_BP_6 PLA_BP_6
183	#define USB_BP_7 PLA_BP_7
184	#define USB_BP_EN PLA_BP_EN /* RTL8153A */
185	#define USB_BP_8 0xfc38 /* RTL8153B */
186	#define USB_BP_9 0xfc3a
187	#define USB_BP_10 0xfc3c
188	#define USB_BP_11 0xfc3e
189	#define USB_BP_12 0xfc40
190	#define USB_BP_13 0xfc42
191	#define USB_BP_14 0xfc44
192	#define USB_BP_15 0xfc46
193	#define USB_BP2_EN 0xfc48
194
195	/* OCP Registers */
196	#define OCP_ALDPS_CONFIG 0x2010
197	#define OCP_EEE_CONFIG1 0x2080
198	#define OCP_EEE_CONFIG2 0x2092
199	#define OCP_EEE_CONFIG3 0x2094
200	#define OCP_BASE_MII 0xa400
201	#define OCP_EEE_AR 0xa41a
202	#define OCP_EEE_DATA 0xa41c
203	#define OCP_PHY_STATUS 0xa420
204	#define OCP_INTR_EN 0xa424
205	#define OCP_NCTL_CFG 0xa42c
206	#define OCP_POWER_CFG 0xa430
207	#define OCP_EEE_CFG 0xa432
208	#define OCP_SRAM_ADDR 0xa436
209	#define OCP_SRAM_DATA 0xa438
210	#define OCP_DOWN_SPEED 0xa442
211	#define OCP_EEE_ABLE 0xa5c4
212	#define OCP_EEE_ADV 0xa5d0
213	#define OCP_EEE_LPABLE 0xa5d2
214	#define OCP_10GBT_CTRL 0xa5d4
215	#define OCP_10GBT_STAT 0xa5d6
216	#define OCP_EEE_ADV2 0xa6d4
217	#define OCP_PHY_STATE 0xa708 /* nway state for 8153 */
218	#define OCP_PHY_PATCH_STAT 0xb800
219	#define OCP_PHY_PATCH_CMD 0xb820
220	#define OCP_PHY_LOCK 0xb82e
221	#define OCP_ADC_IOFFSET 0xbcfc
222	#define OCP_ADC_CFG 0xbc06
223	#define OCP_SYSCLK_CFG 0xc416
224
225	/* SRAM Register */
226	#define SRAM_GREEN_CFG 0x8011
227	#define SRAM_LPF_CFG 0x8012
228	#define SRAM_GPHY_FW_VER 0x801e
229	#define SRAM_10M_AMP1 0x8080
230	#define SRAM_10M_AMP2 0x8082
231	#define SRAM_IMPEDANCE 0x8084
232	#define SRAM_PHY_LOCK 0xb82e
233
234	/* PLA_RCR */
235	#define RCR_AAP 0x00000001
236	#define RCR_APM 0x00000002
237	#define RCR_AM 0x00000004
238	#define RCR_AB 0x00000008
239	#define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
240	#define SLOT_EN BIT(11)
241
242	/* PLA_RCR1 */
243	#define OUTER_VLAN BIT(7)
244	#define INNER_VLAN BIT(6)
245
246	/* PLA_RXFIFO_CTRL0 */
247	#define RXFIFO_THR1_NORMAL 0x00080002
248	#define RXFIFO_THR1_OOB 0x01800003
249
250	/* PLA_RXFIFO_FULL */
251	#define RXFIFO_FULL_MASK 0xfff
252
253	/* PLA_RXFIFO_CTRL1 */
254	#define RXFIFO_THR2_FULL 0x00000060
255	#define RXFIFO_THR2_HIGH 0x00000038
256	#define RXFIFO_THR2_OOB 0x0000004a
257	#define RXFIFO_THR2_NORMAL 0x00a0
258
259	/* PLA_RXFIFO_CTRL2 */
260	#define RXFIFO_THR3_FULL 0x00000078
261	#define RXFIFO_THR3_HIGH 0x00000048
262	#define RXFIFO_THR3_OOB 0x0000005a
263	#define RXFIFO_THR3_NORMAL 0x0110
264
265	/* PLA_TXFIFO_CTRL */
266	#define TXFIFO_THR_NORMAL 0x00400008
267	#define TXFIFO_THR_NORMAL2 0x01000008
268
269	/* PLA_DMY_REG0 */
270	#define ECM_ALDPS 0x0002
271
272	/* PLA_FMC */
273	#define FMC_FCR_MCU_EN 0x0001
274
275	/* PLA_EEEP_CR */
276	#define EEEP_CR_EEEP_TX 0x0002
277
278	/* PLA_WDT6_CTRL */
279	#define WDT6_SET_MODE 0x0010
280
281	/* PLA_TCR0 */
282	#define TCR0_TX_EMPTY 0x0800
283	#define TCR0_AUTO_FIFO 0x0080
284
285	/* PLA_TCR1 */
286	#define VERSION_MASK 0x7cf0
287	#define IFG_MASK (BIT(3) | BIT(9) | BIT(8))
288	#define IFG_144NS BIT(9)
289	#define IFG_96NS (BIT(9) | BIT(8))
290
291	/* PLA_MTPS */
292	#define MTPS_JUMBO (12 * 1024 / 64)
293	#define MTPS_DEFAULT (6 * 1024 / 64)
294
295	/* PLA_RSTTALLY */
296	#define TALLY_RESET 0x0001
297
298	/* PLA_CR */
299	#define CR_RST 0x10
300	#define CR_RE 0x08
301	#define CR_TE 0x04
302
303	/* PLA_CRWECR */
304	#define CRWECR_NORAML 0x00
305	#define CRWECR_CONFIG 0xc0
306
307	/* PLA_OOB_CTRL */
308	#define NOW_IS_OOB 0x80
309	#define TXFIFO_EMPTY 0x20
310	#define RXFIFO_EMPTY 0x10
311	#define LINK_LIST_READY 0x02
312	#define DIS_MCU_CLROOB 0x01
313	#define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
314
315	/* PLA_MISC_1 */
316	#define RXDY_GATED_EN 0x0008
317
318	/* PLA_SFF_STS_7 */
319	#define RE_INIT_LL 0x8000
320	#define MCU_BORW_EN 0x4000
321
322	/* PLA_CPCR */
323	#define FLOW_CTRL_EN BIT(0)
324	#define CPCR_RX_VLAN 0x0040
325
326	/* PLA_CFG_WOL */
327	#define MAGIC_EN 0x0001
328
329	/* PLA_TEREDO_CFG */
330	#define TEREDO_SEL 0x8000
331	#define TEREDO_WAKE_MASK 0x7f00
332	#define TEREDO_RS_EVENT_MASK 0x00fe
333	#define OOB_TEREDO_EN 0x0001
334
335	/* PLA_BDC_CR */
336	#define ALDPS_PROXY_MODE 0x0001
337
338	/* PLA_EFUSE_CMD */
339	#define EFUSE_READ_CMD BIT(15)
340	#define EFUSE_DATA_BIT16 BIT(7)
341
342	/* PLA_CONFIG34 */
343	#define LINK_ON_WAKE_EN 0x0010
344	#define LINK_OFF_WAKE_EN 0x0008
345
346	/* PLA_CONFIG6 */
347	#define LANWAKE_CLR_EN BIT(0)
348
349	/* PLA_USB_CFG */
350	#define EN_XG_LIP BIT(1)
351	#define EN_G_LIP BIT(2)
352
353	/* PLA_CONFIG5 */
354	#define BWF_EN 0x0040
355	#define MWF_EN 0x0020
356	#define UWF_EN 0x0010
357	#define LAN_WAKE_EN 0x0002
358
359	/* PLA_LED_FEATURE */
360	#define LED_MODE_MASK 0x0700
361
362	/* PLA_PHY_PWR */
363	#define TX_10M_IDLE_EN 0x0080
364	#define PFM_PWM_SWITCH 0x0040
365	#define TEST_IO_OFF BIT(4)
366
367	/* PLA_MAC_PWR_CTRL */
368	#define D3_CLK_GATED_EN 0x00004000
369	#define MCU_CLK_RATIO 0x07010f07
370	#define MCU_CLK_RATIO_MASK 0x0f0f0f0f
371	#define ALDPS_SPDWN_RATIO 0x0f87
372
373	/* PLA_MAC_PWR_CTRL2 */
374	#define EEE_SPDWN_RATIO 0x8007
375	#define MAC_CLK_SPDWN_EN BIT(15)
376	#define EEE_SPDWN_RATIO_MASK 0xff
377
378	/* PLA_MAC_PWR_CTRL3 */
379	#define PLA_MCU_SPDWN_EN BIT(14)
380	#define PKT_AVAIL_SPDWN_EN 0x0100
381	#define SUSPEND_SPDWN_EN 0x0004
382	#define U1U2_SPDWN_EN 0x0002
383	#define L1_SPDWN_EN 0x0001
384
385	/* PLA_MAC_PWR_CTRL4 */
386	#define PWRSAVE_SPDWN_EN 0x1000
387	#define RXDV_SPDWN_EN 0x0800
388	#define TX10MIDLE_EN 0x0100
389	#define IDLE_SPDWN_EN BIT(6)
390	#define TP100_SPDWN_EN 0x0020
391	#define TP500_SPDWN_EN 0x0010
392	#define TP1000_SPDWN_EN 0x0008
393	#define EEE_SPDWN_EN 0x0001
394
395	/* PLA_GPHY_INTR_IMR */
396	#define GPHY_STS_MSK 0x0001
397	#define SPEED_DOWN_MSK 0x0002
398	#define SPDWN_RXDV_MSK 0x0004
399	#define SPDWN_LINKCHG_MSK 0x0008
400
401	/* PLA_PHYAR */
402	#define PHYAR_FLAG 0x80000000
403
404	/* PLA_EEE_CR */
405	#define EEE_RX_EN 0x0001
406	#define EEE_TX_EN 0x0002
407
408	/* PLA_BOOT_CTRL */
409	#define AUTOLOAD_DONE 0x0002
410
411	/* PLA_LWAKE_CTRL_REG */
412	#define LANWAKE_PIN BIT(7)
413
414	/* PLA_SUSPEND_FLAG */
415	#define LINK_CHG_EVENT BIT(0)
416
417	/* PLA_INDICATE_FALG */
418	#define UPCOMING_RUNTIME_D3 BIT(0)
419
420	/* PLA_MACDBG_PRE and PLA_MACDBG_POST */
421	#define DEBUG_OE BIT(0)
422	#define DEBUG_LTSSM 0x0082
423
424	/* PLA_EXTRA_STATUS */
425	#define CUR_LINK_OK BIT(15)
426	#define U3P3_CHECK_EN BIT(7) /* RTL_VER_05 only */
427	#define LINK_CHANGE_FLAG BIT(8)
428	#define POLL_LINK_CHG BIT(0)
429
430	/* PLA_GPHY_CTRL */
431	#define GPHY_FLASH BIT(1)
432
433	/* PLA_POL_GPIO_CTRL */
434	#define DACK_DET_EN BIT(15)
435	#define POL_GPHY_PATCH BIT(4)
436
437	/* USB_USB2PHY */
438	#define USB2PHY_SUSPEND 0x0001
439	#define USB2PHY_L1 0x0002
440
441	/* USB_SSPHYLINK1 */
442	#define DELAY_PHY_PWR_CHG BIT(1)
443
444	/* USB_SSPHYLINK2 */
445	#define pwd_dn_scale_mask 0x3ffe
446	#define pwd_dn_scale(x) ((x) << 1)
447
448	/* USB_CSR_DUMMY1 */
449	#define DYNAMIC_BURST 0x0001
450
451	/* USB_CSR_DUMMY2 */
452	#define EP4_FULL_FC 0x0001
453
454	/* USB_DEV_STAT */
455	#define STAT_SPEED_MASK 0x0006
456	#define STAT_SPEED_HIGH 0x0000
457	#define STAT_SPEED_FULL 0x0002
458
459	/* USB_FW_FIX_EN0 */
460	#define FW_FIX_SUSPEND BIT(14)
461
462	/* USB_FW_FIX_EN1 */
463	#define FW_IP_RESET_EN BIT(9)
464
465	/* USB_LPM_CONFIG */
466	#define LPM_U1U2_EN BIT(0)
467
468	/* USB_TX_AGG */
469	#define TX_AGG_MAX_THRESHOLD 0x03
470
471	/* USB_RX_BUF_TH */
472	#define RX_THR_SUPPER 0x0c350180
473	#define RX_THR_HIGH 0x7a120180
474	#define RX_THR_SLOW 0xffff0180
475	#define RX_THR_B 0x00010001
476
477	/* USB_TX_DMA */
478	#define TEST_MODE_DISABLE 0x00000001
479	#define TX_SIZE_ADJUST1 0x00000100
480
481	/* USB_BMU_RESET */
482	#define BMU_RESET_EP_IN 0x01
483	#define BMU_RESET_EP_OUT 0x02
484
485	/* USB_BMU_CONFIG */
486	#define ACT_ODMA BIT(1)
487
488	/* USB_UPT_RXDMA_OWN */
489	#define OWN_UPDATE BIT(0)
490	#define OWN_CLEAR BIT(1)
491
492	/* USB_FW_TASK */
493	#define FC_PATCH_TASK BIT(1)
494
495	/* USB_RX_AGGR_NUM */
496	#define RX_AGGR_NUM_MASK 0x1ff
497
498	/* USB_UPS_CTRL */
499	#define POWER_CUT 0x0100
500
501	/* USB_PM_CTRL_STATUS */
502	#define RESUME_INDICATE 0x0001
503
504	/* USB_ECM_OPTION */
505	#define BYPASS_MAC_RESET BIT(5)
506
507	/* USB_CSTMR */
508	#define FORCE_SUPER BIT(0)
509
510	/* USB_MISC_2 */
511	#define UPS_FORCE_PWR_DOWN BIT(0)
512
513	/* USB_ECM_OP */
514	#define EN_ALL_SPEED BIT(0)
515
516	/* USB_GPHY_CTRL */
517	#define GPHY_PATCH_DONE BIT(2)
518	#define BYPASS_FLASH BIT(5)
519	#define BACKUP_RESTRORE BIT(6)
520
521	/* USB_SPEED_OPTION */
522	#define RG_PWRDN_EN BIT(8)
523	#define ALL_SPEED_OFF BIT(9)
524
525	/* USB_FW_CTRL */
526	#define FLOW_CTRL_PATCH_OPT BIT(1)
527	#define AUTO_SPEEDUP BIT(3)
528	#define FLOW_CTRL_PATCH_2 BIT(8)
529
530	/* USB_FC_TIMER */
531	#define CTRL_TIMER_EN BIT(15)
532
533	/* USB_USB_CTRL */
534	#define CDC_ECM_EN BIT(3)
535	#define RX_AGG_DISABLE 0x0010
536	#define RX_ZERO_EN 0x0080
537
538	/* USB_U2P3_CTRL */
539	#define U2P3_ENABLE 0x0001
540	#define RX_DETECT8 BIT(3)
541
542	/* USB_POWER_CUT */
543	#define PWR_EN 0x0001
544	#define PHASE2_EN 0x0008
545	#define UPS_EN BIT(4)
546	#define USP_PREWAKE BIT(5)
547
548	/* USB_MISC_0 */
549	#define PCUT_STATUS 0x0001
550
551	/* USB_RX_EARLY_TIMEOUT */
552	#define COALESCE_SUPER 85000U
553	#define COALESCE_HIGH 250000U
554	#define COALESCE_SLOW 524280U
555
556	/* USB_WDT1_CTRL */
557	#define WTD1_EN BIT(0)
558
559	/* USB_WDT11_CTRL */
560	#define TIMER11_EN 0x0001
561
562	/* USB_LPM_CTRL */
563	/* bit 4 ~ 5: fifo empty boundary */
564	#define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */
565	/* bit 2 ~ 3: LMP timer */
566	#define LPM_TIMER_MASK 0x0c
567	#define LPM_TIMER_500MS 0x04 /* 500 ms */
568	#define LPM_TIMER_500US 0x0c /* 500 us */
569	#define ROK_EXIT_LPM 0x02
570
571	/* USB_AFE_CTRL2 */
572	#define SEN_VAL_MASK 0xf800
573	#define SEN_VAL_NORMAL 0xa000
574	#define SEL_RXIDLE 0x0100
575
576	/* USB_UPHY_XTAL */
577	#define OOBS_POLLING BIT(8)
578
579	/* USB_UPS_CFG */
580	#define SAW_CNT_1MS_MASK 0x0fff
581	#define MID_REVERSE BIT(5) /* RTL8156A */
582
583	/* USB_UPS_FLAGS */
584	#define UPS_FLAGS_R_TUNE BIT(0)
585	#define UPS_FLAGS_EN_10M_CKDIV BIT(1)
586	#define UPS_FLAGS_250M_CKDIV BIT(2)
587	#define UPS_FLAGS_EN_ALDPS BIT(3)
588	#define UPS_FLAGS_CTAP_SHORT_DIS BIT(4)
589	#define UPS_FLAGS_SPEED_MASK (0xf << 16)
590	#define ups_flags_speed(x) ((x) << 16)
591	#define UPS_FLAGS_EN_EEE BIT(20)
592	#define UPS_FLAGS_EN_500M_EEE BIT(21)
593	#define UPS_FLAGS_EN_EEE_CKDIV BIT(22)
594	#define UPS_FLAGS_EEE_PLLOFF_100 BIT(23)
595	#define UPS_FLAGS_EEE_PLLOFF_GIGA BIT(24)
596	#define UPS_FLAGS_EEE_CMOD_LV_EN BIT(25)
597	#define UPS_FLAGS_EN_GREEN BIT(26)
598	#define UPS_FLAGS_EN_FLOW_CTR BIT(27)
599
600	enum spd_duplex {
601	NWAY_10M_HALF,
602	NWAY_10M_FULL,
603	NWAY_100M_HALF,
604	NWAY_100M_FULL,
605	NWAY_1000M_FULL,
606	FORCE_10M_HALF,
607	FORCE_10M_FULL,
608	FORCE_100M_HALF,
609	FORCE_100M_FULL,
610	FORCE_1000M_FULL,
611	NWAY_2500M_FULL,
612	};
613
614	/* OCP_ALDPS_CONFIG */
615	#define ENPWRSAVE 0x8000
616	#define ENPDNPS 0x0200
617	#define LINKENA 0x0100
618	#define DIS_SDSAVE 0x0010
619
620	/* OCP_PHY_STATUS */
621	#define PHY_STAT_MASK 0x0007
622	#define PHY_STAT_EXT_INIT 2
623	#define PHY_STAT_LAN_ON 3
624	#define PHY_STAT_PWRDN 5
625
626	/* OCP_INTR_EN */
627	#define INTR_SPEED_FORCE BIT(3)
628
629	/* OCP_NCTL_CFG */
630	#define PGA_RETURN_EN BIT(1)
631
632	/* OCP_POWER_CFG */
633	#define EEE_CLKDIV_EN 0x8000
634	#define EN_ALDPS 0x0004
635	#define EN_10M_PLLOFF 0x0001
636
637	/* OCP_EEE_CONFIG1 */
638	#define RG_TXLPI_MSK_HFDUP 0x8000
639	#define RG_MATCLR_EN 0x4000
640	#define EEE_10_CAP 0x2000
641	#define EEE_NWAY_EN 0x1000
642	#define TX_QUIET_EN 0x0200
643	#define RX_QUIET_EN 0x0100
644	#define sd_rise_time_mask 0x0070
645	#define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
646	#define RG_RXLPI_MSK_HFDUP 0x0008
647	#define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
648
649	/* OCP_EEE_CONFIG2 */
650	#define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
651	#define RG_DACQUIET_EN 0x0400
652	#define RG_LDVQUIET_EN 0x0200
653	#define RG_CKRSEL 0x0020
654	#define RG_EEEPRG_EN 0x0010
655
656	/* OCP_EEE_CONFIG3 */
657	#define fast_snr_mask 0xff80
658	#define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
659	#define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
660	#define MSK_PH 0x0006 /* bit 0 ~ 3 */
661
662	/* OCP_EEE_AR */
663	/* bit[15:14] function */
664	#define FUN_ADDR 0x0000
665	#define FUN_DATA 0x4000
666	/* bit[4:0] device addr */
667
668	/* OCP_EEE_CFG */
669	#define CTAP_SHORT_EN 0x0040
670	#define EEE10_EN 0x0010
671
672	/* OCP_DOWN_SPEED */
673	#define EN_EEE_CMODE BIT(14)
674	#define EN_EEE_1000 BIT(13)
675	#define EN_EEE_100 BIT(12)
676	#define EN_10M_CLKDIV BIT(11)
677	#define EN_10M_BGOFF 0x0080
678
679	/* OCP_10GBT_CTRL */
680	#define RTL_ADV2_5G_F_R BIT(5) /* Advertise 2.5GBASE-T fast-retrain */
681
682	/* OCP_PHY_STATE */
683	#define TXDIS_STATE 0x01
684	#define ABD_STATE 0x02
685
686	/* OCP_PHY_PATCH_STAT */
687	#define PATCH_READY BIT(6)
688
689	/* OCP_PHY_PATCH_CMD */
690	#define PATCH_REQUEST BIT(4)
691
692	/* OCP_PHY_LOCK */
693	#define PATCH_LOCK BIT(0)
694
695	/* OCP_ADC_CFG */
696	#define CKADSEL_L 0x0100
697	#define ADC_EN 0x0080
698	#define EN_EMI_L 0x0040
699
700	/* OCP_SYSCLK_CFG */
701	#define sysclk_div_expo(x) (min(x, 5) << 8)
702	#define clk_div_expo(x) (min(x, 5) << 4)
703
704	/* SRAM_GREEN_CFG */
705	#define GREEN_ETH_EN BIT(15)
706	#define R_TUNE_EN BIT(11)
707
708	/* SRAM_LPF_CFG */
709	#define LPF_AUTO_TUNE 0x8000
710
711	/* SRAM_10M_AMP1 */
712	#define GDAC_IB_UPALL 0x0008
713
714	/* SRAM_10M_AMP2 */
715	#define AMP_DN 0x0200
716
717	/* SRAM_IMPEDANCE */
718	#define RX_DRIVING_MASK 0x6000
719
720	/* SRAM_PHY_LOCK */
721	#define PHY_PATCH_LOCK 0x0001
722
723	/* MAC PASSTHRU */
724	#define AD_MASK 0xfee0
725	#define BND_MASK 0x0004
726	#define BD_MASK 0x0001
727	#define EFUSE 0xcfdb
728	#define PASS_THRU_MASK 0x1
729
730	#define BP4_SUPER_ONLY 0x1578 /* RTL_VER_04 only */
731
732	enum rtl_register_content {
733	_2500bps = BIT(10),
734	_1250bps = BIT(9),
735	_500bps = BIT(8),
736	_tx_flow = BIT(6),
737	_rx_flow = BIT(5),
738	_1000bps = 0x10,
739	_100bps = 0x08,
740	_10bps = 0x04,
741	LINK_STATUS = 0x02,
742	FULL_DUP = 0x01,
743	};
744
745	#define is_speed_2500(_speed) (((_speed) & (_2500bps | LINK_STATUS)) == (_2500bps | LINK_STATUS))
746	#define is_flow_control(_speed) (((_speed) & (_tx_flow | _rx_flow)) == (_tx_flow | _rx_flow))
747
748	#define RTL8152_MAX_TX 4
749	#define RTL8152_MAX_RX 10
750	#define INTBUFSIZE 2
751	#define TX_ALIGN 4
752	#define RX_ALIGN 8
753
754	#define RTL8152_RX_MAX_PENDING 4096
755	#define RTL8152_RXFG_HEADSZ 256
756
757	#define INTR_LINK 0x0004
758
759	#define RTL8152_RMS (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
760	#define RTL8153_RMS RTL8153_MAX_PACKET
761	#define RTL8152_TX_TIMEOUT (5 * HZ)
762	#define mtu_to_size(m) ((m) + VLAN_ETH_HLEN + ETH_FCS_LEN)
763	#define size_to_mtu(s) ((s) - VLAN_ETH_HLEN - ETH_FCS_LEN)
764	#define rx_reserved_size(x) (mtu_to_size(x) + sizeof(struct rx_desc) + RX_ALIGN)
765
766	/* rtl8152 flags */
767	enum rtl8152_flags {
768	RTL8152_INACCESSIBLE = 0,
769	RTL8152_SET_RX_MODE,
770	WORK_ENABLE,
771	RTL8152_LINK_CHG,
772	SELECTIVE_SUSPEND,
773	PHY_RESET,
774	SCHEDULE_TASKLET,
775	GREEN_ETHERNET,
776	RX_EPROTO,
777	IN_PRE_RESET,
778	PROBED_WITH_NO_ERRORS,
779	PROBE_SHOULD_RETRY,
780	};
781
782	#define DEVICE_ID_LENOVO_USB_C_TRAVEL_HUB 0x721e
783	#define DEVICE_ID_THINKPAD_ONELINK_PLUS_DOCK 0x3054
784	#define DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2 0x3082
785	#define DEVICE_ID_THINKPAD_USB_C_DONGLE 0x720c
786	#define DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2 0xa387
787	#define DEVICE_ID_THINKPAD_USB_C_DOCK_GEN3 0x3062
788
789	struct tally_counter {
790	__le64 tx_packets;
791	__le64 rx_packets;
792	__le64 tx_errors;
793	__le32 rx_errors;
794	__le16 rx_missed;
795	__le16 align_errors;
796	__le32 tx_one_collision;
797	__le32 tx_multi_collision;
798	__le64 rx_unicast;
799	__le64 rx_broadcast;
800	__le32 rx_multicast;
801	__le16 tx_aborted;
802	__le16 tx_underrun;
803	};
804
805	struct rx_desc {
806	__le32 opts1;
807	#define RX_LEN_MASK 0x7fff
808
809	__le32 opts2;
810	#define RD_UDP_CS BIT(23)
811	#define RD_TCP_CS BIT(22)
812	#define RD_IPV6_CS BIT(20)
813	#define RD_IPV4_CS BIT(19)
814
815	__le32 opts3;
816	#define IPF BIT(23) /* IP checksum fail */
817	#define UDPF BIT(22) /* UDP checksum fail */
818	#define TCPF BIT(21) /* TCP checksum fail */
819	#define RX_VLAN_TAG BIT(16)
820
821	__le32 opts4;
822	__le32 opts5;
823	__le32 opts6;
824	};
825
826	struct tx_desc {
827	__le32 opts1;
828	#define TX_FS BIT(31) /* First segment of a packet */
829	#define TX_LS BIT(30) /* Final segment of a packet */
830	#define GTSENDV4 BIT(28)
831	#define GTSENDV6 BIT(27)
832	#define GTTCPHO_SHIFT 18
833	#define GTTCPHO_MAX 0x7fU
834	#define TX_LEN_MAX 0x3ffffU
835
836	__le32 opts2;
837	#define UDP_CS BIT(31) /* Calculate UDP/IP checksum */
838	#define TCP_CS BIT(30) /* Calculate TCP/IP checksum */
839	#define IPV4_CS BIT(29) /* Calculate IPv4 checksum */
840	#define IPV6_CS BIT(28) /* Calculate IPv6 checksum */
841	#define MSS_SHIFT 17
842	#define MSS_MAX 0x7ffU
843	#define TCPHO_SHIFT 17
844	#define TCPHO_MAX 0x7ffU
845	#define TX_VLAN_TAG BIT(16)
846	};
847
848	struct r8152;
849
850	struct rx_agg {
851	struct list_head list, info_list;
852	struct urb *urb;
853	struct r8152 *context;
854	struct page *page;
855	void *buffer;
856	};
857
858	struct tx_agg {
859	struct list_head list;
860	struct urb *urb;
861	struct r8152 *context;
862	void *buffer;
863	void *head;
864	u32 skb_num;
865	u32 skb_len;
866	};
867
868	struct r8152 {
869	unsigned long flags;
870	struct usb_device *udev;
871	struct napi_struct napi;
872	struct usb_interface *intf;
873	struct net_device *netdev;
874	struct urb *intr_urb;
875	struct tx_agg tx_info[RTL8152_MAX_TX];
876	struct list_head rx_info, rx_used;
877	struct list_head rx_done, tx_free;
878	struct sk_buff_head tx_queue, rx_queue;
879	spinlock_t rx_lock, tx_lock;
880	struct delayed_work schedule, hw_phy_work;
881	struct mii_if_info mii;
882	struct mutex control; /* use for hw setting */
883	#ifdef CONFIG_PM_SLEEP
884	struct notifier_block pm_notifier;
885	#endif
886	struct tasklet_struct tx_tl;
887
888	struct rtl_ops {
889	void (*init)(struct r8152 *tp);
890	int (*enable)(struct r8152 *tp);
891	void (*disable)(struct r8152 *tp);
892	void (*up)(struct r8152 *tp);
893	void (*down)(struct r8152 *tp);
894	void (*unload)(struct r8152 *tp);
895	int (*eee_get)(struct r8152 *tp, struct ethtool_keee *eee);
896	int (*eee_set)(struct r8152 *tp, struct ethtool_keee *eee);
897	bool (*in_nway)(struct r8152 *tp);
898	void (*hw_phy_cfg)(struct r8152 *tp);
899	void (*autosuspend_en)(struct r8152 *tp, bool enable);
900	void (*change_mtu)(struct r8152 *tp);
901	} rtl_ops;
902
903	struct ups_info {
904	u32 r_tune:1;
905	u32 _10m_ckdiv:1;
906	u32 _250m_ckdiv:1;
907	u32 aldps:1;
908	u32 lite_mode:2;
909	u32 speed_duplex:4;
910	u32 eee:1;
911	u32 eee_lite:1;
912	u32 eee_ckdiv:1;
913	u32 eee_plloff_100:1;
914	u32 eee_plloff_giga:1;
915	u32 eee_cmod_lv:1;
916	u32 green:1;
917	u32 flow_control:1;
918	u32 ctap_short_off:1;
919	} ups_info;
920
921	#define RTL_VER_SIZE 32
922
923	struct rtl_fw {
924	const char *fw_name;
925	const struct firmware *fw;
926
927	char version[RTL_VER_SIZE];
928	int (*pre_fw)(struct r8152 *tp);
929	int (*post_fw)(struct r8152 *tp);
930
931	bool retry;
932	} rtl_fw;
933
934	atomic_t rx_count;
935
936	bool eee_en;
937	int intr_interval;
938	u32 saved_wolopts;
939	u32 msg_enable;
940	u32 tx_qlen;
941	u32 coalesce;
942	u32 advertising;
943	u32 rx_buf_sz;
944	u32 rx_copybreak;
945	u32 rx_pending;
946	u32 fc_pause_on, fc_pause_off;
947
948	unsigned int pipe_in, pipe_out, pipe_intr, pipe_ctrl_in, pipe_ctrl_out;
949
950	u32 support_2500full:1;
951	u32 lenovo_macpassthru:1;
952	u32 dell_tb_rx_agg_bug:1;
953	u16 ocp_base;
954	u16 speed;
955	u16 eee_adv;
956	u8 *intr_buff;
957	u8 version;
958	u8 duplex;
959	u8 autoneg;
960
961	unsigned int reg_access_reset_count;
962	};
963
964	/**
965	* struct fw_block - block type and total length
966	* @type: type of the current block, such as RTL_FW_END, RTL_FW_PLA,
967	* RTL_FW_USB and so on.
968	* @length: total length of the current block.
969	*/
970	struct fw_block {
971	__le32 type;
972	__le32 length;
973	} __packed;
974
975	/**
976	* struct fw_header - header of the firmware file
977	* @checksum: checksum of sha256 which is calculated from the whole file
978	* except the checksum field of the file. That is, calculate sha256
979	* from the version field to the end of the file.
980	* @version: version of this firmware.
981	* @blocks: the first firmware block of the file
982	*/
983	struct fw_header {
984	u8 checksum[32];
985	char version[RTL_VER_SIZE];
986	struct fw_block blocks[];
987	} __packed;
988
989	enum rtl8152_fw_flags {
990	FW_FLAGS_USB = 0,
991	FW_FLAGS_PLA,
992	FW_FLAGS_START,
993	FW_FLAGS_STOP,
994	FW_FLAGS_NC,
995	FW_FLAGS_NC1,
996	FW_FLAGS_NC2,
997	FW_FLAGS_UC2,
998	FW_FLAGS_UC,
999	FW_FLAGS_SPEED_UP,
1000	FW_FLAGS_VER,
1001	};
1002
1003	enum rtl8152_fw_fixup_cmd {
1004	FW_FIXUP_AND = 0,
1005	FW_FIXUP_OR,
1006	FW_FIXUP_NOT,
1007	FW_FIXUP_XOR,
1008	};
1009
1010	struct fw_phy_set {
1011	__le16 addr;
1012	__le16 data;
1013	} __packed;
1014
1015	struct fw_phy_speed_up {
1016	struct fw_block blk_hdr;
1017	__le16 fw_offset;
1018	__le16 version;
1019	__le16 fw_reg;
1020	__le16 reserved;
1021	char info[];
1022	} __packed;
1023
1024	struct fw_phy_ver {
1025	struct fw_block blk_hdr;
1026	struct fw_phy_set ver;
1027	__le32 reserved;
1028	} __packed;
1029
1030	struct fw_phy_fixup {
1031	struct fw_block blk_hdr;
1032	struct fw_phy_set setting;
1033	__le16 bit_cmd;
1034	__le16 reserved;
1035	} __packed;
1036
1037	struct fw_phy_union {
1038	struct fw_block blk_hdr;
1039	__le16 fw_offset;
1040	__le16 fw_reg;
1041	struct fw_phy_set pre_set[2];
1042	struct fw_phy_set bp[8];
1043	struct fw_phy_set bp_en;
1044	u8 pre_num;
1045	u8 bp_num;
1046	char info[];
1047	} __packed;
1048
1049	/**
1050	* struct fw_mac - a firmware block used by RTL_FW_PLA and RTL_FW_USB.
1051	* The layout of the firmware block is:
1052	* <struct fw_mac> + <info> + <firmware data>.
1053	* @blk_hdr: firmware descriptor (type, length)
1054	* @fw_offset: offset of the firmware binary data. The start address of
1055	* the data would be the address of struct fw_mac + @fw_offset.
1056	* @fw_reg: the register to load the firmware. Depends on chip.
1057	* @bp_ba_addr: the register to write break point base address. Depends on
1058	* chip.
1059	* @bp_ba_value: break point base address. Depends on chip.
1060	* @bp_en_addr: the register to write break point enabled mask. Depends
1061	* on chip.
1062	* @bp_en_value: break point enabled mask. Depends on the firmware.
1063	* @bp_start: the start register of break points. Depends on chip.
1064	* @bp_num: the break point number which needs to be set for this firmware.
1065	* Depends on the firmware.
1066	* @bp: break points. Depends on firmware.
1067	* @reserved: reserved space (unused)
1068	* @fw_ver_reg: the register to store the fw version.
1069	* @fw_ver_data: the firmware version of the current type.
1070	* @info: additional information for debugging, and is followed by the
1071	* binary data of firmware.
1072	*/
1073	struct fw_mac {
1074	struct fw_block blk_hdr;
1075	__le16 fw_offset;
1076	__le16 fw_reg;
1077	__le16 bp_ba_addr;
1078	__le16 bp_ba_value;
1079	__le16 bp_en_addr;
1080	__le16 bp_en_value;
1081	__le16 bp_start;
1082	__le16 bp_num;
1083	__le16 bp[16]; /* any value determined by firmware */
1084	__le32 reserved;
1085	__le16 fw_ver_reg;
1086	u8 fw_ver_data;
1087	char info[];
1088	} __packed;
1089
1090	/**
1091	* struct fw_phy_patch_key - a firmware block used by RTL_FW_PHY_START.
1092	* This is used to set patch key when loading the firmware of PHY.
1093	* @blk_hdr: firmware descriptor (type, length)
1094	* @key_reg: the register to write the patch key.
1095	* @key_data: patch key.
1096	* @reserved: reserved space (unused)
1097	*/
1098	struct fw_phy_patch_key {
1099	struct fw_block blk_hdr;
1100	__le16 key_reg;
1101	__le16 key_data;
1102	__le32 reserved;
1103	} __packed;
1104
1105	/**
1106	* struct fw_phy_nc - a firmware block used by RTL_FW_PHY_NC.
1107	* The layout of the firmware block is:
1108	* <struct fw_phy_nc> + <info> + <firmware data>.
1109	* @blk_hdr: firmware descriptor (type, length)
1110	* @fw_offset: offset of the firmware binary data. The start address of
1111	* the data would be the address of struct fw_phy_nc + @fw_offset.
1112	* @fw_reg: the register to load the firmware. Depends on chip.
1113	* @ba_reg: the register to write the base address. Depends on chip.
1114	* @ba_data: base address. Depends on chip.
1115	* @patch_en_addr: the register of enabling patch mode. Depends on chip.
1116	* @patch_en_value: patch mode enabled mask. Depends on the firmware.
1117	* @mode_reg: the regitster of switching the mode.
1118	* @mode_pre: the mode needing to be set before loading the firmware.
1119	* @mode_post: the mode to be set when finishing to load the firmware.
1120	* @reserved: reserved space (unused)
1121	* @bp_start: the start register of break points. Depends on chip.
1122	* @bp_num: the break point number which needs to be set for this firmware.
1123	* Depends on the firmware.
1124	* @bp: break points. Depends on firmware.
1125	* @info: additional information for debugging, and is followed by the
1126	* binary data of firmware.
1127	*/
1128	struct fw_phy_nc {
1129	struct fw_block blk_hdr;
1130	__le16 fw_offset;
1131	__le16 fw_reg;
1132	__le16 ba_reg;
1133	__le16 ba_data;
1134	__le16 patch_en_addr;
1135	__le16 patch_en_value;
1136	__le16 mode_reg;
1137	__le16 mode_pre;
1138	__le16 mode_post;
1139	__le16 reserved;
1140	__le16 bp_start;
1141	__le16 bp_num;
1142	__le16 bp[4];
1143	char info[];
1144	} __packed;
1145
1146	enum rtl_fw_type {
1147	RTL_FW_END = 0,
1148	RTL_FW_PLA,
1149	RTL_FW_USB,
1150	RTL_FW_PHY_START,
1151	RTL_FW_PHY_STOP,
1152	RTL_FW_PHY_NC,
1153	RTL_FW_PHY_FIXUP,
1154	RTL_FW_PHY_UNION_NC,
1155	RTL_FW_PHY_UNION_NC1,
1156	RTL_FW_PHY_UNION_NC2,
1157	RTL_FW_PHY_UNION_UC2,
1158	RTL_FW_PHY_UNION_UC,
1159	RTL_FW_PHY_UNION_MISC,
1160	RTL_FW_PHY_SPEED_UP,
1161	RTL_FW_PHY_VER,
1162	};
1163
1164	enum rtl_version {
1165	RTL_VER_UNKNOWN = 0,
1166	RTL_VER_01,
1167	RTL_VER_02,
1168	RTL_VER_03,
1169	RTL_VER_04,
1170	RTL_VER_05,
1171	RTL_VER_06,
1172	RTL_VER_07,
1173	RTL_VER_08,
1174	RTL_VER_09,
1175
1176	RTL_TEST_01,
1177	RTL_VER_10,
1178	RTL_VER_11,
1179	RTL_VER_12,
1180	RTL_VER_13,
1181	RTL_VER_14,
1182	RTL_VER_15,
1183
1184	RTL_VER_MAX
1185	};
1186
1187	enum tx_csum_stat {
1188	TX_CSUM_SUCCESS = 0,
1189	TX_CSUM_TSO,
1190	TX_CSUM_NONE
1191	};
1192
1193	#define RTL_ADVERTISED_10_HALF BIT(0)
1194	#define RTL_ADVERTISED_10_FULL BIT(1)
1195	#define RTL_ADVERTISED_100_HALF BIT(2)
1196	#define RTL_ADVERTISED_100_FULL BIT(3)
1197	#define RTL_ADVERTISED_1000_HALF BIT(4)
1198	#define RTL_ADVERTISED_1000_FULL BIT(5)
1199	#define RTL_ADVERTISED_2500_FULL BIT(6)
1200
1201	/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
1202	* The RTL chips use a 64 element hash table based on the Ethernet CRC.
1203	*/
1204	static const int multicast_filter_limit = 32;
1205	static unsigned int agg_buf_sz = 16384;
1206
1207	#define RTL_LIMITED_TSO_SIZE (size_to_mtu(agg_buf_sz) - sizeof(struct tx_desc))
1208
1209	/* If register access fails then we block access and issue a reset. If this
1210	* happens too many times in a row without a successful access then we stop
1211	* trying to reset and just leave access blocked.
1212	*/
1213	#define REGISTER_ACCESS_MAX_RESETS 3
1214
1215	static void rtl_set_inaccessible(struct r8152 *tp)
1216	{
1217	set_bit(nr: RTL8152_INACCESSIBLE, addr: &tp->flags);
1218	smp_mb__after_atomic();
1219	}
1220
1221	static void rtl_set_accessible(struct r8152 *tp)
1222	{
1223	clear_bit(nr: RTL8152_INACCESSIBLE, addr: &tp->flags);
1224	smp_mb__after_atomic();
1225	}
1226
1227	static
1228	int r8152_control_msg(struct r8152 *tp, unsigned int pipe, __u8 request,
1229	__u8 requesttype, __u16 value, __u16 index, void *data,
1230	__u16 size, const char *msg_tag)
1231	{
1232	struct usb_device *udev = tp->udev;
1233	int ret;
1234
1235	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
1236	return -ENODEV;
1237
1238	ret = usb_control_msg(dev: udev, pipe, request, requesttype,
1239	value, index, data, size,
1240	USB_CTRL_GET_TIMEOUT);
1241
1242	/* No need to issue a reset to report an error if the USB device got
1243	* unplugged; just return immediately.
1244	*/
1245	if (ret == -ENODEV)
1246	return ret;
1247
1248	/* If the write was successful then we're done */
1249	if (ret >= 0) {
1250	tp->reg_access_reset_count = 0;
1251	return ret;
1252	}
1253
1254	dev_err(&udev->dev,
1255	"Failed to %s %d bytes at %#06x/%#06x (%d)\n",
1256	msg_tag, size, value, index, ret);
1257
1258	/* Block all future register access until we reset. Much of the code
1259	* in the driver doesn't check for errors. Notably, many parts of the
1260	* driver do a read/modify/write of a register value without
1261	* confirming that the read succeeded. Writing back modified garbage
1262	* like this can fully wedge the adapter, requiring a power cycle.
1263	*/
1264	rtl_set_inaccessible(tp);
1265
1266	/* If probe hasn't yet finished, then we'll request a retry of the
1267	* whole probe routine if we get any control transfer errors. We
1268	* never have to clear this bit since we free/reallocate the whole "tp"
1269	* structure if we retry probe.
1270	*/
1271	if (!test_bit(PROBED_WITH_NO_ERRORS, &tp->flags)) {
1272	set_bit(nr: PROBE_SHOULD_RETRY, addr: &tp->flags);
1273	return ret;
1274	}
1275
1276	/* Failing to access registers in pre-reset is not surprising since we
1277	* wouldn't be resetting if things were behaving normally. The register
1278	* access we do in pre-reset isn't truly mandatory--we're just reusing
1279	* the disable() function and trying to be nice by powering the
1280	* adapter down before resetting it. Thus, if we're in pre-reset,
1281	* we'll return right away and not try to queue up yet another reset.
1282	* We know the post-reset is already coming.
1283	*/
1284	if (test_bit(IN_PRE_RESET, &tp->flags))
1285	return ret;
1286
1287	if (tp->reg_access_reset_count < REGISTER_ACCESS_MAX_RESETS) {
1288	usb_queue_reset_device(dev: tp->intf);
1289	tp->reg_access_reset_count++;
1290	} else if (tp->reg_access_reset_count == REGISTER_ACCESS_MAX_RESETS) {
1291	dev_err(&udev->dev,
1292	"Tried to reset %d times; giving up.\n",
1293	REGISTER_ACCESS_MAX_RESETS);
1294	}
1295
1296	return ret;
1297	}
1298
1299	static
1300	int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
1301	{
1302	int ret;
1303	void *tmp;
1304
1305	tmp = kmalloc(size, GFP_KERNEL);
1306	if (!tmp)
1307	return -ENOMEM;
1308
1309	ret = r8152_control_msg(tp, pipe: tp->pipe_ctrl_in,
1310	RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
1311	value, index, data: tmp, size, msg_tag: "read");
1312
1313	if (ret < 0)
1314	memset(data, 0xff, size);
1315	else
1316	memcpy(data, tmp, size);
1317
1318	kfree(objp: tmp);
1319
1320	return ret;
1321	}
1322
1323	static
1324	int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
1325	{
1326	int ret;
1327	void *tmp;
1328
1329	tmp = kmemdup(p: data, size, GFP_KERNEL);
1330	if (!tmp)
1331	return -ENOMEM;
1332
1333	ret = r8152_control_msg(tp, pipe: tp->pipe_ctrl_out,
1334	RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
1335	value, index, data: tmp, size, msg_tag: "write");
1336
1337	kfree(objp: tmp);
1338
1339	return ret;
1340	}
1341
1342	static void rtl_set_unplug(struct r8152 *tp)
1343	{
1344	if (tp->udev->state == USB_STATE_NOTATTACHED)
1345	rtl_set_inaccessible(tp);
1346	}
1347
1348	static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
1349	void *data, u16 type)
1350	{
1351	u16 limit = 64;
1352	int ret = 0;
1353
1354	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
1355	return -ENODEV;
1356
1357	/* both size and indix must be 4 bytes align */
1358	if ((size & 3) || !size || (index & 3) || !data)
1359	return -EPERM;
1360
1361	if ((u32)index + (u32)size > 0xffff)
1362	return -EPERM;
1363
1364	while (size) {
1365	if (size > limit) {
1366	ret = get_registers(tp, value: index, index: type, size: limit, data);
1367	if (ret < 0)
1368	break;
1369
1370	index += limit;
1371	data += limit;
1372	size -= limit;
1373	} else {
1374	ret = get_registers(tp, value: index, index: type, size, data);
1375	if (ret < 0)
1376	break;
1377
1378	index += size;
1379	data += size;
1380	size = 0;
1381	break;
1382	}
1383	}
1384
1385	if (ret == -ENODEV)
1386	rtl_set_unplug(tp);
1387
1388	return ret;
1389	}
1390
1391	static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
1392	u16 size, void *data, u16 type)
1393	{
1394	int ret;
1395	u16 byteen_start, byteen_end, byen;
1396	u16 limit = 512;
1397
1398	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
1399	return -ENODEV;
1400
1401	/* both size and indix must be 4 bytes align */
1402	if ((size & 3) || !size || (index & 3) || !data)
1403	return -EPERM;
1404
1405	if ((u32)index + (u32)size > 0xffff)
1406	return -EPERM;
1407
1408	byteen_start = byteen & BYTE_EN_START_MASK;
1409	byteen_end = byteen & BYTE_EN_END_MASK;
1410
1411	byen = byteen_start | (byteen_start << 4);
1412
1413	/* Split the first DWORD if the byte_en is not 0xff */
1414	if (byen != BYTE_EN_DWORD) {
1415	ret = set_registers(tp, value: index, index: type | byen, size: 4, data);
1416	if (ret < 0)
1417	goto error1;
1418
1419	index += 4;
1420	data += 4;
1421	size -= 4;
1422	}
1423
1424	if (size) {
1425	byen = byteen_end | (byteen_end >> 4);
1426
1427	/* Split the last DWORD if the byte_en is not 0xff */
1428	if (byen != BYTE_EN_DWORD)
1429	size -= 4;
1430
1431	while (size) {
1432	if (size > limit) {
1433	ret = set_registers(tp, value: index,
1434	index: type | BYTE_EN_DWORD,
1435	size: limit, data);
1436	if (ret < 0)
1437	goto error1;
1438
1439	index += limit;
1440	data += limit;
1441	size -= limit;
1442	} else {
1443	ret = set_registers(tp, value: index,
1444	index: type | BYTE_EN_DWORD,
1445	size, data);
1446	if (ret < 0)
1447	goto error1;
1448
1449	index += size;
1450	data += size;
1451	size = 0;
1452	break;
1453	}
1454	}
1455
1456	/* Set the last DWORD */
1457	if (byen != BYTE_EN_DWORD)
1458	ret = set_registers(tp, value: index, index: type | byen, size: 4, data);
1459	}
1460
1461	error1:
1462	if (ret == -ENODEV)
1463	rtl_set_unplug(tp);
1464
1465	return ret;
1466	}
1467
1468	static inline
1469	int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
1470	{
1471	return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
1472	}
1473
1474	static inline
1475	int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
1476	{
1477	return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
1478	}
1479
1480	static inline
1481	int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
1482	{
1483	return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
1484	}
1485
1486	static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
1487	{
1488	__le32 data;
1489
1490	generic_ocp_read(tp, index, size: sizeof(data), data: &data, type);
1491
1492	return __le32_to_cpu(data);
1493	}
1494
1495	static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
1496	{
1497	__le32 tmp = __cpu_to_le32(data);
1498
1499	generic_ocp_write(tp, index, BYTE_EN_DWORD, size: sizeof(tmp), data: &tmp, type);
1500	}
1501
1502	static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
1503	{
1504	u32 data;
1505	__le32 tmp;
1506	u16 byen = BYTE_EN_WORD;
1507	u8 shift = index & 2;
1508
1509	index &= ~3;
1510	byen <<= shift;
1511
1512	generic_ocp_read(tp, index, size: sizeof(tmp), data: &tmp, type: type | byen);
1513
1514	data = __le32_to_cpu(tmp);
1515	data >>= (shift * 8);
1516	data &= 0xffff;
1517
1518	return (u16)data;
1519	}
1520
1521	static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
1522	{
1523	u32 mask = 0xffff;
1524	__le32 tmp;
1525	u16 byen = BYTE_EN_WORD;
1526	u8 shift = index & 2;
1527
1528	data &= mask;
1529
1530	if (index & 2) {
1531	byen <<= shift;
1532	mask <<= (shift * 8);
1533	data <<= (shift * 8);
1534	index &= ~3;
1535	}
1536
1537	tmp = __cpu_to_le32(data);
1538
1539	generic_ocp_write(tp, index, byteen: byen, size: sizeof(tmp), data: &tmp, type);
1540	}
1541
1542	static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
1543	{
1544	u32 data;
1545	__le32 tmp;
1546	u8 shift = index & 3;
1547
1548	index &= ~3;
1549
1550	generic_ocp_read(tp, index, size: sizeof(tmp), data: &tmp, type);
1551
1552	data = __le32_to_cpu(tmp);
1553	data >>= (shift * 8);
1554	data &= 0xff;
1555
1556	return (u8)data;
1557	}
1558
1559	static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
1560	{
1561	u32 mask = 0xff;
1562	__le32 tmp;
1563	u16 byen = BYTE_EN_BYTE;
1564	u8 shift = index & 3;
1565
1566	data &= mask;
1567
1568	if (index & 3) {
1569	byen <<= shift;
1570	mask <<= (shift * 8);
1571	data <<= (shift * 8);
1572	index &= ~3;
1573	}
1574
1575	tmp = __cpu_to_le32(data);
1576
1577	generic_ocp_write(tp, index, byteen: byen, size: sizeof(tmp), data: &tmp, type);
1578	}
1579
1580	static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
1581	{
1582	u16 ocp_base, ocp_index;
1583
1584	ocp_base = addr & 0xf000;
1585	if (ocp_base != tp->ocp_base) {
1586	ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, data: ocp_base);
1587	tp->ocp_base = ocp_base;
1588	}
1589
1590	ocp_index = (addr & 0x0fff) | 0xb000;
1591	return ocp_read_word(tp, MCU_TYPE_PLA, index: ocp_index);
1592	}
1593
1594	static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
1595	{
1596	u16 ocp_base, ocp_index;
1597
1598	ocp_base = addr & 0xf000;
1599	if (ocp_base != tp->ocp_base) {
1600	ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, data: ocp_base);
1601	tp->ocp_base = ocp_base;
1602	}
1603
1604	ocp_index = (addr & 0x0fff) | 0xb000;
1605	ocp_write_word(tp, MCU_TYPE_PLA, index: ocp_index, data);
1606	}
1607
1608	static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
1609	{
1610	ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, data: value);
1611	}
1612
1613	static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
1614	{
1615	return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
1616	}
1617
1618	static void sram_write(struct r8152 *tp, u16 addr, u16 data)
1619	{
1620	ocp_reg_write(tp, OCP_SRAM_ADDR, data: addr);
1621	ocp_reg_write(tp, OCP_SRAM_DATA, data);
1622	}
1623
1624	static u16 sram_read(struct r8152 *tp, u16 addr)
1625	{
1626	ocp_reg_write(tp, OCP_SRAM_ADDR, data: addr);
1627	return ocp_reg_read(tp, OCP_SRAM_DATA);
1628	}
1629
1630	static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
1631	{
1632	struct r8152 *tp = netdev_priv(dev: netdev);
1633	int ret;
1634
1635	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
1636	return -ENODEV;
1637
1638	if (phy_id != R8152_PHY_ID)
1639	return -EINVAL;
1640
1641	ret = r8152_mdio_read(tp, reg_addr: reg);
1642
1643	return ret;
1644	}
1645
1646	static
1647	void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
1648	{
1649	struct r8152 *tp = netdev_priv(dev: netdev);
1650
1651	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
1652	return;
1653
1654	if (phy_id != R8152_PHY_ID)
1655	return;
1656
1657	r8152_mdio_write(tp, reg_addr: reg, value: val);
1658	}
1659
1660	static int
1661	r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
1662
1663	static int
1664	rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex,
1665	u32 advertising);
1666
1667	static int __rtl8152_set_mac_address(struct net_device *netdev, void *p,
1668	bool in_resume)
1669	{
1670	struct r8152 *tp = netdev_priv(dev: netdev);
1671	struct sockaddr *addr = p;
1672	int ret = -EADDRNOTAVAIL;
1673
1674	if (!is_valid_ether_addr(addr: addr->sa_data))
1675	goto out1;
1676
1677	if (!in_resume) {
1678	ret = usb_autopm_get_interface(intf: tp->intf);
1679	if (ret < 0)
1680	goto out1;
1681	}
1682
1683	mutex_lock(&tp->control);
1684
1685	eth_hw_addr_set(dev: netdev, addr: addr->sa_data);
1686
1687	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1688	pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, size: 8, data: addr->sa_data);
1689	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1690
1691	mutex_unlock(lock: &tp->control);
1692
1693	if (!in_resume)
1694	usb_autopm_put_interface(intf: tp->intf);
1695	out1:
1696	return ret;
1697	}
1698
1699	static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
1700	{
1701	return __rtl8152_set_mac_address(netdev, p, in_resume: false);
1702	}
1703
1704	/* Devices containing proper chips can support a persistent
1705	* host system provided MAC address.
1706	* Examples of this are Dell TB15 and Dell WD15 docks
1707	*/
1708	static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa)
1709	{
1710	acpi_status status;
1711	struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
1712	union acpi_object *obj;
1713	int ret = -EINVAL;
1714	u32 ocp_data;
1715	unsigned char buf[6];
1716	char *mac_obj_name;
1717	acpi_object_type mac_obj_type;
1718	int mac_strlen;
1719
1720	if (tp->lenovo_macpassthru) {
1721	mac_obj_name = "\\MACA";
1722	mac_obj_type = ACPI_TYPE_STRING;
1723	mac_strlen = 0x16;
1724	} else {
1725	/* test for -AD variant of RTL8153 */
1726	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
1727	if ((ocp_data & AD_MASK) == 0x1000) {
1728	/* test for MAC address pass-through bit */
1729	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE);
1730	if ((ocp_data & PASS_THRU_MASK) != 1) {
1731	netif_dbg(tp, probe, tp->netdev,
1732	"No efuse for RTL8153-AD MAC pass through\n");
1733	return -ENODEV;
1734	}
1735	} else {
1736	/* test for RTL8153-BND and RTL8153-BD */
1737	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
1738	if ((ocp_data & BND_MASK) == 0 && (ocp_data & BD_MASK) == 0) {
1739	netif_dbg(tp, probe, tp->netdev,
1740	"Invalid variant for MAC pass through\n");
1741	return -ENODEV;
1742	}
1743	}
1744
1745	mac_obj_name = "\\_SB.AMAC";
1746	mac_obj_type = ACPI_TYPE_BUFFER;
1747	mac_strlen = 0x17;
1748	}
1749
1750	/* returns _AUXMAC_#AABBCCDDEEFF# */
1751	status = acpi_evaluate_object(NULL, pathname: mac_obj_name, NULL, return_object_buffer: &buffer);
1752	obj = (union acpi_object *)buffer.pointer;
1753	if (!ACPI_SUCCESS(status))
1754	return -ENODEV;
1755	if (obj->type != mac_obj_type || obj->string.length != mac_strlen) {
1756	netif_warn(tp, probe, tp->netdev,
1757	"Invalid buffer for pass-thru MAC addr: (%d, %d)\n",
1758	obj->type, obj->string.length);
1759	goto amacout;
1760	}
1761
1762	if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 ||
1763	strncmp(obj->string.pointer + 0x15, "#", 1) != 0) {
1764	netif_warn(tp, probe, tp->netdev,
1765	"Invalid header when reading pass-thru MAC addr\n");
1766	goto amacout;
1767	}
1768	ret = hex2bin(dst: buf, src: obj->string.pointer + 9, count: 6);
1769	if (!(ret == 0 && is_valid_ether_addr(addr: buf))) {
1770	netif_warn(tp, probe, tp->netdev,
1771	"Invalid MAC for pass-thru MAC addr: %d, %pM\n",
1772	ret, buf);
1773	ret = -EINVAL;
1774	goto amacout;
1775	}
1776	memcpy(sa->sa_data, buf, 6);
1777	netif_info(tp, probe, tp->netdev,
1778	"Using pass-thru MAC addr %pM\n", sa->sa_data);
1779
1780	amacout:
1781	kfree(objp: obj);
1782	return ret;
1783	}
1784
1785	static int determine_ethernet_addr(struct r8152 *tp, struct sockaddr *sa)
1786	{
1787	struct net_device *dev = tp->netdev;
1788	int ret;
1789
1790	sa->sa_family = dev->type;
1791
1792	ret = eth_platform_get_mac_address(dev: &tp->udev->dev, mac_addr: sa->sa_data);
1793	if (ret < 0) {
1794	if (tp->version == RTL_VER_01) {
1795	ret = pla_ocp_read(tp, PLA_IDR, size: 8, data: sa->sa_data);
1796	} else {
1797	/* if device doesn't support MAC pass through this will
1798	* be expected to be non-zero
1799	*/
1800	ret = vendor_mac_passthru_addr_read(tp, sa);
1801	if (ret < 0)
1802	ret = pla_ocp_read(tp, PLA_BACKUP, size: 8,
1803	data: sa->sa_data);
1804	}
1805	}
1806
1807	if (ret < 0) {
1808	netif_err(tp, probe, dev, "Get ether addr fail\n");
1809	} else if (!is_valid_ether_addr(addr: sa->sa_data)) {
1810	netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1811	sa->sa_data);
1812	eth_hw_addr_random(dev);
1813	ether_addr_copy(dst: sa->sa_data, src: dev->dev_addr);
1814	netif_info(tp, probe, dev, "Random ether addr %pM\n",
1815	sa->sa_data);
1816	return 0;
1817	}
1818
1819	return ret;
1820	}
1821
1822	static int set_ethernet_addr(struct r8152 *tp, bool in_resume)
1823	{
1824	struct net_device *dev = tp->netdev;
1825	struct sockaddr sa;
1826	int ret;
1827
1828	ret = determine_ethernet_addr(tp, sa: &sa);
1829	if (ret < 0)
1830	return ret;
1831
1832	if (tp->version == RTL_VER_01)
1833	eth_hw_addr_set(dev, addr: sa.sa_data);
1834	else
1835	ret = __rtl8152_set_mac_address(netdev: dev, p: &sa, in_resume);
1836
1837	return ret;
1838	}
1839
1840	static void read_bulk_callback(struct urb *urb)
1841	{
1842	struct net_device *netdev;
1843	int status = urb->status;
1844	struct rx_agg *agg;
1845	struct r8152 *tp;
1846	unsigned long flags;
1847
1848	agg = urb->context;
1849	if (!agg)
1850	return;
1851
1852	tp = agg->context;
1853	if (!tp)
1854	return;
1855
1856	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
1857	return;
1858
1859	if (!test_bit(WORK_ENABLE, &tp->flags))
1860	return;
1861
1862	netdev = tp->netdev;
1863
1864	/* When link down, the driver would cancel all bulks. */
1865	/* This avoid the re-submitting bulk */
1866	if (!netif_carrier_ok(dev: netdev))
1867	return;
1868
1869	usb_mark_last_busy(udev: tp->udev);
1870
1871	switch (status) {
1872	case 0:
1873	if (urb->actual_length < ETH_ZLEN)
1874	break;
1875
1876	spin_lock_irqsave(&tp->rx_lock, flags);
1877	list_add_tail(new: &agg->list, head: &tp->rx_done);
1878	spin_unlock_irqrestore(lock: &tp->rx_lock, flags);
1879	napi_schedule(n: &tp->napi);
1880	return;
1881	case -ESHUTDOWN:
1882	rtl_set_unplug(tp);
1883	netif_device_detach(dev: tp->netdev);
1884	return;
1885	case -EPROTO:
1886	urb->actual_length = 0;
1887	spin_lock_irqsave(&tp->rx_lock, flags);
1888	list_add_tail(new: &agg->list, head: &tp->rx_done);
1889	spin_unlock_irqrestore(lock: &tp->rx_lock, flags);
1890	set_bit(nr: RX_EPROTO, addr: &tp->flags);
1891	schedule_delayed_work(dwork: &tp->schedule, delay: 1);
1892	return;
1893	case -ENOENT:
1894	return; /* the urb is in unlink state */
1895	case -ETIME:
1896	if (net_ratelimit())
1897	netdev_warn(dev: netdev, format: "maybe reset is needed?\n");
1898	break;
1899	default:
1900	if (net_ratelimit())
1901	netdev_warn(dev: netdev, format: "Rx status %d\n", status);
1902	break;
1903	}
1904
1905	r8152_submit_rx(tp, agg, GFP_ATOMIC);
1906	}
1907
1908	static void write_bulk_callback(struct urb *urb)
1909	{
1910	struct net_device_stats *stats;
1911	struct net_device *netdev;
1912	struct tx_agg *agg;
1913	struct r8152 *tp;
1914	unsigned long flags;
1915	int status = urb->status;
1916
1917	agg = urb->context;
1918	if (!agg)
1919	return;
1920
1921	tp = agg->context;
1922	if (!tp)
1923	return;
1924
1925	netdev = tp->netdev;
1926	stats = &netdev->stats;
1927	if (status) {
1928	if (net_ratelimit())
1929	netdev_warn(dev: netdev, format: "Tx status %d\n", status);
1930	stats->tx_errors += agg->skb_num;
1931	} else {
1932	stats->tx_packets += agg->skb_num;
1933	stats->tx_bytes += agg->skb_len;
1934	}
1935
1936	spin_lock_irqsave(&tp->tx_lock, flags);
1937	list_add_tail(new: &agg->list, head: &tp->tx_free);
1938	spin_unlock_irqrestore(lock: &tp->tx_lock, flags);
1939
1940	usb_autopm_put_interface_async(intf: tp->intf);
1941
1942	if (!netif_carrier_ok(dev: netdev))
1943	return;
1944
1945	if (!test_bit(WORK_ENABLE, &tp->flags))
1946	return;
1947
1948	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
1949	return;
1950
1951	if (!skb_queue_empty(list: &tp->tx_queue))
1952	tasklet_schedule(t: &tp->tx_tl);
1953	}
1954
1955	static void intr_callback(struct urb *urb)
1956	{
1957	struct r8152 *tp;
1958	__le16 *d;
1959	int status = urb->status;
1960	int res;
1961
1962	tp = urb->context;
1963	if (!tp)
1964	return;
1965
1966	if (!test_bit(WORK_ENABLE, &tp->flags))
1967	return;
1968
1969	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
1970	return;
1971
1972	switch (status) {
1973	case 0: /* success */
1974	break;
1975	case -ECONNRESET: /* unlink */
1976	case -ESHUTDOWN:
1977	netif_device_detach(dev: tp->netdev);
1978	fallthrough;
1979	case -ENOENT:
1980	case -EPROTO:
1981	netif_info(tp, intr, tp->netdev,
1982	"Stop submitting intr, status %d\n", status);
1983	return;
1984	case -EOVERFLOW:
1985	if (net_ratelimit())
1986	netif_info(tp, intr, tp->netdev,
1987	"intr status -EOVERFLOW\n");
1988	goto resubmit;
1989	/* -EPIPE: should clear the halt */
1990	default:
1991	netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1992	goto resubmit;
1993	}
1994
1995	d = urb->transfer_buffer;
1996	if (INTR_LINK & __le16_to_cpu(d[0])) {
1997	if (!netif_carrier_ok(dev: tp->netdev)) {
1998	set_bit(nr: RTL8152_LINK_CHG, addr: &tp->flags);
1999	schedule_delayed_work(dwork: &tp->schedule, delay: 0);
2000	}
2001	} else {
2002	if (netif_carrier_ok(dev: tp->netdev)) {
2003	netif_stop_queue(dev: tp->netdev);
2004	set_bit(nr: RTL8152_LINK_CHG, addr: &tp->flags);
2005	schedule_delayed_work(dwork: &tp->schedule, delay: 0);
2006	}
2007	}
2008
2009	resubmit:
2010	res = usb_submit_urb(urb, GFP_ATOMIC);
2011	if (res == -ENODEV) {
2012	rtl_set_unplug(tp);
2013	netif_device_detach(dev: tp->netdev);
2014	} else if (res) {
2015	netif_err(tp, intr, tp->netdev,
2016	"can't resubmit intr, status %d\n", res);
2017	}
2018	}
2019
2020	static inline void *rx_agg_align(void *data)
2021	{
2022	return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
2023	}
2024
2025	static inline void *tx_agg_align(void *data)
2026	{
2027	return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
2028	}
2029
2030	static void free_rx_agg(struct r8152 *tp, struct rx_agg *agg)
2031	{
2032	list_del(entry: &agg->info_list);
2033
2034	usb_free_urb(urb: agg->urb);
2035	put_page(page: agg->page);
2036	kfree(objp: agg);
2037
2038	atomic_dec(v: &tp->rx_count);
2039	}
2040
2041	static struct rx_agg *alloc_rx_agg(struct r8152 *tp, gfp_t mflags)
2042	{
2043	struct net_device *netdev = tp->netdev;
2044	int node = netdev->dev.parent ? dev_to_node(dev: netdev->dev.parent) : -1;
2045	unsigned int order = get_order(size: tp->rx_buf_sz);
2046	struct rx_agg *rx_agg;
2047	unsigned long flags;
2048
2049	rx_agg = kmalloc_node(size: sizeof(*rx_agg), flags: mflags, node);
2050	if (!rx_agg)
2051	return NULL;
2052
2053	rx_agg->page = alloc_pages(gfp: mflags | __GFP_COMP | __GFP_NOWARN, order);
2054	if (!rx_agg->page)
2055	goto free_rx;
2056
2057	rx_agg->buffer = page_address(rx_agg->page);
2058
2059	rx_agg->urb = usb_alloc_urb(iso_packets: 0, mem_flags: mflags);
2060	if (!rx_agg->urb)
2061	goto free_buf;
2062
2063	rx_agg->context = tp;
2064
2065	INIT_LIST_HEAD(list: &rx_agg->list);
2066	INIT_LIST_HEAD(list: &rx_agg->info_list);
2067	spin_lock_irqsave(&tp->rx_lock, flags);
2068	list_add_tail(new: &rx_agg->info_list, head: &tp->rx_info);
2069	spin_unlock_irqrestore(lock: &tp->rx_lock, flags);
2070
2071	atomic_inc(v: &tp->rx_count);
2072
2073	return rx_agg;
2074
2075	free_buf:
2076	__free_pages(page: rx_agg->page, order);
2077	free_rx:
2078	kfree(objp: rx_agg);
2079	return NULL;
2080	}
2081
2082	static void free_all_mem(struct r8152 *tp)
2083	{
2084	struct rx_agg *agg, *agg_next;
2085	unsigned long flags;
2086	int i;
2087
2088	spin_lock_irqsave(&tp->rx_lock, flags);
2089
2090	list_for_each_entry_safe(agg, agg_next, &tp->rx_info, info_list)
2091	free_rx_agg(tp, agg);
2092
2093	spin_unlock_irqrestore(lock: &tp->rx_lock, flags);
2094
2095	WARN_ON(atomic_read(&tp->rx_count));
2096
2097	for (i = 0; i < RTL8152_MAX_TX; i++) {
2098	usb_free_urb(urb: tp->tx_info[i].urb);
2099	tp->tx_info[i].urb = NULL;
2100
2101	kfree(objp: tp->tx_info[i].buffer);
2102	tp->tx_info[i].buffer = NULL;
2103	tp->tx_info[i].head = NULL;
2104	}
2105
2106	usb_free_urb(urb: tp->intr_urb);
2107	tp->intr_urb = NULL;
2108
2109	kfree(objp: tp->intr_buff);
2110	tp->intr_buff = NULL;
2111	}
2112
2113	static int alloc_all_mem(struct r8152 *tp)
2114	{
2115	struct net_device *netdev = tp->netdev;
2116	struct usb_interface *intf = tp->intf;
2117	struct usb_host_interface *alt = intf->cur_altsetting;
2118	struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
2119	int node, i;
2120
2121	node = netdev->dev.parent ? dev_to_node(dev: netdev->dev.parent) : -1;
2122
2123	spin_lock_init(&tp->rx_lock);
2124	spin_lock_init(&tp->tx_lock);
2125	INIT_LIST_HEAD(list: &tp->rx_info);
2126	INIT_LIST_HEAD(list: &tp->tx_free);
2127	INIT_LIST_HEAD(list: &tp->rx_done);
2128	skb_queue_head_init(list: &tp->tx_queue);
2129	skb_queue_head_init(list: &tp->rx_queue);
2130	atomic_set(v: &tp->rx_count, i: 0);
2131
2132	for (i = 0; i < RTL8152_MAX_RX; i++) {
2133	if (!alloc_rx_agg(tp, GFP_KERNEL))
2134	goto err1;
2135	}
2136
2137	for (i = 0; i < RTL8152_MAX_TX; i++) {
2138	struct urb *urb;
2139	u8 *buf;
2140
2141	buf = kmalloc_node(size: agg_buf_sz, GFP_KERNEL, node);
2142	if (!buf)
2143	goto err1;
2144
2145	if (buf != tx_agg_align(data: buf)) {
2146	kfree(objp: buf);
2147	buf = kmalloc_node(size: agg_buf_sz + TX_ALIGN, GFP_KERNEL,
2148	node);
2149	if (!buf)
2150	goto err1;
2151	}
2152
2153	urb = usb_alloc_urb(iso_packets: 0, GFP_KERNEL);
2154	if (!urb) {
2155	kfree(objp: buf);
2156	goto err1;
2157	}
2158
2159	INIT_LIST_HEAD(list: &tp->tx_info[i].list);
2160	tp->tx_info[i].context = tp;
2161	tp->tx_info[i].urb = urb;
2162	tp->tx_info[i].buffer = buf;
2163	tp->tx_info[i].head = tx_agg_align(data: buf);
2164
2165	list_add_tail(new: &tp->tx_info[i].list, head: &tp->tx_free);
2166	}
2167
2168	tp->intr_urb = usb_alloc_urb(iso_packets: 0, GFP_KERNEL);
2169	if (!tp->intr_urb)
2170	goto err1;
2171
2172	tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
2173	if (!tp->intr_buff)
2174	goto err1;
2175
2176	tp->intr_interval = (int)ep_intr->desc.bInterval;
2177	usb_fill_int_urb(urb: tp->intr_urb, dev: tp->udev, pipe: tp->pipe_intr,
2178	transfer_buffer: tp->intr_buff, INTBUFSIZE, complete_fn: intr_callback,
2179	context: tp, interval: tp->intr_interval);
2180
2181	return 0;
2182
2183	err1:
2184	free_all_mem(tp);
2185	return -ENOMEM;
2186	}
2187
2188	static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
2189	{
2190	struct tx_agg *agg = NULL;
2191	unsigned long flags;
2192
2193	if (list_empty(head: &tp->tx_free))
2194	return NULL;
2195
2196	spin_lock_irqsave(&tp->tx_lock, flags);
2197	if (!list_empty(head: &tp->tx_free)) {
2198	struct list_head *cursor;
2199
2200	cursor = tp->tx_free.next;
2201	list_del_init(entry: cursor);
2202	agg = list_entry(cursor, struct tx_agg, list);
2203	}
2204	spin_unlock_irqrestore(lock: &tp->tx_lock, flags);
2205
2206	return agg;
2207	}
2208
2209	/* r8152_csum_workaround()
2210	* The hw limits the value of the transport offset. When the offset is out of
2211	* range, calculate the checksum by sw.
2212	*/
2213	static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
2214	struct sk_buff_head *list)
2215	{
2216	if (skb_shinfo(skb)->gso_size) {
2217	netdev_features_t features = tp->netdev->features;
2218	struct sk_buff *segs, *seg, *next;
2219	struct sk_buff_head seg_list;
2220
2221	features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
2222	segs = skb_gso_segment(skb, features);
2223	if (IS_ERR(ptr: segs) || !segs)
2224	goto drop;
2225
2226	__skb_queue_head_init(list: &seg_list);
2227
2228	skb_list_walk_safe(segs, seg, next) {
2229	skb_mark_not_on_list(skb: seg);
2230	__skb_queue_tail(list: &seg_list, newsk: seg);
2231	}
2232
2233	skb_queue_splice(list: &seg_list, head: list);
2234	dev_kfree_skb(skb);
2235	} else if (skb->ip_summed == CHECKSUM_PARTIAL) {
2236	if (skb_checksum_help(skb) < 0)
2237	goto drop;
2238
2239	__skb_queue_head(list, newsk: skb);
2240	} else {
2241	struct net_device_stats *stats;
2242
2243	drop:
2244	stats = &tp->netdev->stats;
2245	stats->tx_dropped++;
2246	dev_kfree_skb(skb);
2247	}
2248	}
2249
2250	static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
2251	{
2252	if (skb_vlan_tag_present(skb)) {
2253	u32 opts2;
2254
2255	opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
2256	desc->opts2 |= cpu_to_le32(opts2);
2257	}
2258	}
2259
2260	static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
2261	{
2262	u32 opts2 = le32_to_cpu(desc->opts2);
2263
2264	if (opts2 & RX_VLAN_TAG)
2265	__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
2266	swab16(opts2 & 0xffff));
2267	}
2268
2269	static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
2270	struct sk_buff *skb, u32 len)
2271	{
2272	u32 mss = skb_shinfo(skb)->gso_size;
2273	u32 opts1, opts2 = 0;
2274	int ret = TX_CSUM_SUCCESS;
2275
2276	WARN_ON_ONCE(len > TX_LEN_MAX);
2277
2278	opts1 = len | TX_FS | TX_LS;
2279
2280	if (mss) {
2281	u32 transport_offset = (u32)skb_transport_offset(skb);
2282
2283	if (transport_offset > GTTCPHO_MAX) {
2284	netif_warn(tp, tx_err, tp->netdev,
2285	"Invalid transport offset 0x%x for TSO\n",
2286	transport_offset);
2287	ret = TX_CSUM_TSO;
2288	goto unavailable;
2289	}
2290
2291	switch (vlan_get_protocol(skb)) {
2292	case htons(ETH_P_IP):
2293	opts1 |= GTSENDV4;
2294	break;
2295
2296	case htons(ETH_P_IPV6):
2297	if (skb_cow_head(skb, headroom: 0)) {
2298	ret = TX_CSUM_TSO;
2299	goto unavailable;
2300	}
2301	tcp_v6_gso_csum_prep(skb);
2302	opts1 |= GTSENDV6;
2303	break;
2304
2305	default:
2306	WARN_ON_ONCE(1);
2307	break;
2308	}
2309
2310	opts1 |= transport_offset << GTTCPHO_SHIFT;
2311	opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
2312	} else if (skb->ip_summed == CHECKSUM_PARTIAL) {
2313	u32 transport_offset = (u32)skb_transport_offset(skb);
2314	u8 ip_protocol;
2315
2316	if (transport_offset > TCPHO_MAX) {
2317	netif_warn(tp, tx_err, tp->netdev,
2318	"Invalid transport offset 0x%x\n",
2319	transport_offset);
2320	ret = TX_CSUM_NONE;
2321	goto unavailable;
2322	}
2323
2324	switch (vlan_get_protocol(skb)) {
2325	case htons(ETH_P_IP):
2326	opts2 |= IPV4_CS;
2327	ip_protocol = ip_hdr(skb)->protocol;
2328	break;
2329
2330	case htons(ETH_P_IPV6):
2331	opts2 |= IPV6_CS;
2332	ip_protocol = ipv6_hdr(skb)->nexthdr;
2333	break;
2334
2335	default:
2336	ip_protocol = IPPROTO_RAW;
2337	break;
2338	}
2339
2340	if (ip_protocol == IPPROTO_TCP)
2341	opts2 |= TCP_CS;
2342	else if (ip_protocol == IPPROTO_UDP)
2343	opts2 |= UDP_CS;
2344	else
2345	WARN_ON_ONCE(1);
2346
2347	opts2 |= transport_offset << TCPHO_SHIFT;
2348	}
2349
2350	desc->opts2 = cpu_to_le32(opts2);
2351	desc->opts1 = cpu_to_le32(opts1);
2352
2353	unavailable:
2354	return ret;
2355	}
2356
2357	static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
2358	{
2359	struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2360	int remain, ret;
2361	u8 *tx_data;
2362
2363	__skb_queue_head_init(list: &skb_head);
2364	spin_lock(lock: &tx_queue->lock);
2365	skb_queue_splice_init(list: tx_queue, head: &skb_head);
2366	spin_unlock(lock: &tx_queue->lock);
2367
2368	tx_data = agg->head;
2369	agg->skb_num = 0;
2370	agg->skb_len = 0;
2371	remain = agg_buf_sz;
2372
2373	while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
2374	struct tx_desc *tx_desc;
2375	struct sk_buff *skb;
2376	unsigned int len;
2377
2378	skb = __skb_dequeue(list: &skb_head);
2379	if (!skb)
2380	break;
2381
2382	len = skb->len + sizeof(*tx_desc);
2383
2384	if (len > remain) {
2385	__skb_queue_head(list: &skb_head, newsk: skb);
2386	break;
2387	}
2388
2389	tx_data = tx_agg_align(data: tx_data);
2390	tx_desc = (struct tx_desc *)tx_data;
2391
2392	if (r8152_tx_csum(tp, desc: tx_desc, skb, len: skb->len)) {
2393	r8152_csum_workaround(tp, skb, list: &skb_head);
2394	continue;
2395	}
2396
2397	rtl_tx_vlan_tag(desc: tx_desc, skb);
2398
2399	tx_data += sizeof(*tx_desc);
2400
2401	len = skb->len;
2402	if (skb_copy_bits(skb, offset: 0, to: tx_data, len) < 0) {
2403	struct net_device_stats *stats = &tp->netdev->stats;
2404
2405	stats->tx_dropped++;
2406	dev_kfree_skb_any(skb);
2407	tx_data -= sizeof(*tx_desc);
2408	continue;
2409	}
2410
2411	tx_data += len;
2412	agg->skb_len += len;
2413	agg->skb_num += skb_shinfo(skb)->gso_segs ?: 1;
2414
2415	dev_kfree_skb_any(skb);
2416
2417	remain = agg_buf_sz - (int)(tx_agg_align(data: tx_data) - agg->head);
2418
2419	if (tp->dell_tb_rx_agg_bug)
2420	break;
2421	}
2422
2423	if (!skb_queue_empty(list: &skb_head)) {
2424	spin_lock(lock: &tx_queue->lock);
2425	skb_queue_splice(list: &skb_head, head: tx_queue);
2426	spin_unlock(lock: &tx_queue->lock);
2427	}
2428
2429	netif_tx_lock(dev: tp->netdev);
2430
2431	if (netif_queue_stopped(dev: tp->netdev) &&
2432	skb_queue_len(list_: &tp->tx_queue) < tp->tx_qlen)
2433	netif_wake_queue(dev: tp->netdev);
2434
2435	netif_tx_unlock(dev: tp->netdev);
2436
2437	ret = usb_autopm_get_interface_async(intf: tp->intf);
2438	if (ret < 0)
2439	goto out_tx_fill;
2440
2441	usb_fill_bulk_urb(urb: agg->urb, dev: tp->udev, pipe: tp->pipe_out,
2442	transfer_buffer: agg->head, buffer_length: (int)(tx_data - (u8 *)agg->head),
2443	complete_fn: (usb_complete_t)write_bulk_callback, context: agg);
2444
2445	ret = usb_submit_urb(urb: agg->urb, GFP_ATOMIC);
2446	if (ret < 0)
2447	usb_autopm_put_interface_async(intf: tp->intf);
2448
2449	out_tx_fill:
2450	return ret;
2451	}
2452
2453	static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
2454	{
2455	u8 checksum = CHECKSUM_NONE;
2456	u32 opts2, opts3;
2457
2458	if (!(tp->netdev->features & NETIF_F_RXCSUM))
2459	goto return_result;
2460
2461	opts2 = le32_to_cpu(rx_desc->opts2);
2462	opts3 = le32_to_cpu(rx_desc->opts3);
2463
2464	if (opts2 & RD_IPV4_CS) {
2465	if (opts3 & IPF)
2466	checksum = CHECKSUM_NONE;
2467	else if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
2468	checksum = CHECKSUM_UNNECESSARY;
2469	else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
2470	checksum = CHECKSUM_UNNECESSARY;
2471	} else if (opts2 & RD_IPV6_CS) {
2472	if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
2473	checksum = CHECKSUM_UNNECESSARY;
2474	else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
2475	checksum = CHECKSUM_UNNECESSARY;
2476	}
2477
2478	return_result:
2479	return checksum;
2480	}
2481
2482	static inline bool rx_count_exceed(struct r8152 *tp)
2483	{
2484	return atomic_read(v: &tp->rx_count) > RTL8152_MAX_RX;
2485	}
2486
2487	static inline int agg_offset(struct rx_agg *agg, void *addr)
2488	{
2489	return (int)(addr - agg->buffer);
2490	}
2491
2492	static struct rx_agg *rtl_get_free_rx(struct r8152 *tp, gfp_t mflags)
2493	{
2494	struct rx_agg *agg, *agg_next, *agg_free = NULL;
2495	unsigned long flags;
2496
2497	spin_lock_irqsave(&tp->rx_lock, flags);
2498
2499	list_for_each_entry_safe(agg, agg_next, &tp->rx_used, list) {
2500	if (page_count(page: agg->page) == 1) {
2501	if (!agg_free) {
2502	list_del_init(entry: &agg->list);
2503	agg_free = agg;
2504	continue;
2505	}
2506	if (rx_count_exceed(tp)) {
2507	list_del_init(entry: &agg->list);
2508	free_rx_agg(tp, agg);
2509	}
2510	break;
2511	}
2512	}
2513
2514	spin_unlock_irqrestore(lock: &tp->rx_lock, flags);
2515
2516	if (!agg_free && atomic_read(v: &tp->rx_count) < tp->rx_pending)
2517	agg_free = alloc_rx_agg(tp, mflags);
2518
2519	return agg_free;
2520	}
2521
2522	static int rx_bottom(struct r8152 *tp, int budget)
2523	{
2524	unsigned long flags;
2525	struct list_head *cursor, *next, rx_queue;
2526	int ret = 0, work_done = 0;
2527	struct napi_struct *napi = &tp->napi;
2528
2529	if (!skb_queue_empty(list: &tp->rx_queue)) {
2530	while (work_done < budget) {
2531	struct sk_buff *skb = __skb_dequeue(list: &tp->rx_queue);
2532	struct net_device *netdev = tp->netdev;
2533	struct net_device_stats *stats = &netdev->stats;
2534	unsigned int pkt_len;
2535
2536	if (!skb)
2537	break;
2538
2539	pkt_len = skb->len;
2540	napi_gro_receive(napi, skb);
2541	work_done++;
2542	stats->rx_packets++;
2543	stats->rx_bytes += pkt_len;
2544	}
2545	}
2546
2547	if (list_empty(head: &tp->rx_done) || work_done >= budget)
2548	goto out1;
2549
2550	clear_bit(nr: RX_EPROTO, addr: &tp->flags);
2551	INIT_LIST_HEAD(list: &rx_queue);
2552	spin_lock_irqsave(&tp->rx_lock, flags);
2553	list_splice_init(list: &tp->rx_done, head: &rx_queue);
2554	spin_unlock_irqrestore(lock: &tp->rx_lock, flags);
2555
2556	list_for_each_safe(cursor, next, &rx_queue) {
2557	struct rx_desc *rx_desc;
2558	struct rx_agg *agg, *agg_free;
2559	int len_used = 0;
2560	struct urb *urb;
2561	u8 *rx_data;
2562
2563	/* A bulk transfer of USB may contain may packets, so the
2564	* total packets may more than the budget. Deal with all
2565	* packets in current bulk transfer, and stop to handle the
2566	* next bulk transfer until next schedule, if budget is
2567	* exhausted.
2568	*/
2569	if (work_done >= budget)
2570	break;
2571
2572	list_del_init(entry: cursor);
2573
2574	agg = list_entry(cursor, struct rx_agg, list);
2575	urb = agg->urb;
2576	if (urb->status != 0 || urb->actual_length < ETH_ZLEN)
2577	goto submit;
2578
2579	agg_free = rtl_get_free_rx(tp, GFP_ATOMIC);
2580
2581	rx_desc = agg->buffer;
2582	rx_data = agg->buffer;
2583	len_used += sizeof(struct rx_desc);
2584
2585	while (urb->actual_length > len_used) {
2586	struct net_device *netdev = tp->netdev;
2587	struct net_device_stats *stats = &netdev->stats;
2588	unsigned int pkt_len, rx_frag_head_sz, len;
2589	struct sk_buff *skb;
2590	bool use_frags;
2591
2592	WARN_ON_ONCE(skb_queue_len(&tp->rx_queue) >= 1000);
2593
2594	pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
2595	if (pkt_len < ETH_ZLEN)
2596	break;
2597
2598	len_used += pkt_len;
2599	if (urb->actual_length < len_used)
2600	break;
2601
2602	pkt_len -= ETH_FCS_LEN;
2603	len = pkt_len;
2604	rx_data += sizeof(struct rx_desc);
2605
2606	if (!agg_free || tp->rx_copybreak > len)
2607	use_frags = false;
2608	else
2609	use_frags = true;
2610
2611	if (use_frags) {
2612	/* If the budget is exhausted, the packet
2613	* would be queued in the driver. That is,
2614	* napi_gro_frags() wouldn't be called, so
2615	* we couldn't use napi_get_frags().
2616	*/
2617	if (work_done >= budget) {
2618	rx_frag_head_sz = tp->rx_copybreak;
2619	skb = napi_alloc_skb(napi,
2620	length: rx_frag_head_sz);
2621	} else {
2622	rx_frag_head_sz = 0;
2623	skb = napi_get_frags(napi);
2624	}
2625	} else {
2626	rx_frag_head_sz = 0;
2627	skb = napi_alloc_skb(napi, length: len);
2628	}
2629
2630	if (!skb) {
2631	stats->rx_dropped++;
2632	goto find_next_rx;
2633	}
2634
2635	skb->ip_summed = r8152_rx_csum(tp, rx_desc);
2636	rtl_rx_vlan_tag(desc: rx_desc, skb);
2637
2638	if (use_frags) {
2639	if (rx_frag_head_sz) {
2640	memcpy(skb->data, rx_data,
2641	rx_frag_head_sz);
2642	skb_put(skb, len: rx_frag_head_sz);
2643	len -= rx_frag_head_sz;
2644	rx_data += rx_frag_head_sz;
2645	skb->protocol = eth_type_trans(skb,
2646	dev: netdev);
2647	}
2648
2649	skb_add_rx_frag(skb, i: 0, page: agg->page,
2650	off: agg_offset(agg, addr: rx_data),
2651	size: len, SKB_DATA_ALIGN(len));
2652	get_page(page: agg->page);
2653	} else {
2654	memcpy(skb->data, rx_data, len);
2655	skb_put(skb, len);
2656	skb->protocol = eth_type_trans(skb, dev: netdev);
2657	}
2658
2659	if (work_done < budget) {
2660	if (use_frags)
2661	napi_gro_frags(napi);
2662	else
2663	napi_gro_receive(napi, skb);
2664
2665	work_done++;
2666	stats->rx_packets++;
2667	stats->rx_bytes += pkt_len;
2668	} else {
2669	__skb_queue_tail(list: &tp->rx_queue, newsk: skb);
2670	}
2671
2672	find_next_rx:
2673	rx_data = rx_agg_align(data: rx_data + len + ETH_FCS_LEN);
2674	rx_desc = (struct rx_desc *)rx_data;
2675	len_used = agg_offset(agg, addr: rx_data);
2676	len_used += sizeof(struct rx_desc);
2677	}
2678
2679	WARN_ON(!agg_free && page_count(agg->page) > 1);
2680
2681	if (agg_free) {
2682	spin_lock_irqsave(&tp->rx_lock, flags);
2683	if (page_count(page: agg->page) == 1) {
2684	list_add(new: &agg_free->list, head: &tp->rx_used);
2685	} else {
2686	list_add_tail(new: &agg->list, head: &tp->rx_used);
2687	agg = agg_free;
2688	urb = agg->urb;
2689	}
2690	spin_unlock_irqrestore(lock: &tp->rx_lock, flags);
2691	}
2692
2693	submit:
2694	if (!ret) {
2695	ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
2696	} else {
2697	urb->actual_length = 0;
2698	list_add_tail(new: &agg->list, head: next);
2699	}
2700	}
2701
2702	/* Splice the remained list back to rx_done for next schedule */
2703	if (!list_empty(head: &rx_queue)) {
2704	spin_lock_irqsave(&tp->rx_lock, flags);
2705	list_splice(list: &rx_queue, head: &tp->rx_done);
2706	spin_unlock_irqrestore(lock: &tp->rx_lock, flags);
2707	}
2708
2709	out1:
2710	return work_done;
2711	}
2712
2713	static void tx_bottom(struct r8152 *tp)
2714	{
2715	int res;
2716
2717	do {
2718	struct net_device *netdev = tp->netdev;
2719	struct tx_agg *agg;
2720
2721	if (skb_queue_empty(list: &tp->tx_queue))
2722	break;
2723
2724	agg = r8152_get_tx_agg(tp);
2725	if (!agg)
2726	break;
2727
2728	res = r8152_tx_agg_fill(tp, agg);
2729	if (!res)
2730	continue;
2731
2732	if (res == -ENODEV) {
2733	rtl_set_unplug(tp);
2734	netif_device_detach(dev: netdev);
2735	} else {
2736	struct net_device_stats *stats = &netdev->stats;
2737	unsigned long flags;
2738
2739	netif_warn(tp, tx_err, netdev,
2740	"failed tx_urb %d\n", res);
2741	stats->tx_dropped += agg->skb_num;
2742
2743	spin_lock_irqsave(&tp->tx_lock, flags);
2744	list_add_tail(new: &agg->list, head: &tp->tx_free);
2745	spin_unlock_irqrestore(lock: &tp->tx_lock, flags);
2746	}
2747	} while (res == 0);
2748	}
2749
2750	static void bottom_half(struct tasklet_struct *t)
2751	{
2752	struct r8152 *tp = from_tasklet(tp, t, tx_tl);
2753
2754	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
2755	return;
2756
2757	if (!test_bit(WORK_ENABLE, &tp->flags))
2758	return;
2759
2760	/* When link down, the driver would cancel all bulks. */
2761	/* This avoid the re-submitting bulk */
2762	if (!netif_carrier_ok(dev: tp->netdev))
2763	return;
2764
2765	clear_bit(nr: SCHEDULE_TASKLET, addr: &tp->flags);
2766
2767	tx_bottom(tp);
2768	}
2769
2770	static int r8152_poll(struct napi_struct *napi, int budget)
2771	{
2772	struct r8152 *tp = container_of(napi, struct r8152, napi);
2773	int work_done;
2774
2775	if (!budget)
2776	return 0;
2777
2778	work_done = rx_bottom(tp, budget);
2779
2780	if (work_done < budget) {
2781	if (!napi_complete_done(n: napi, work_done))
2782	goto out;
2783	if (!list_empty(head: &tp->rx_done))
2784	napi_schedule(n: napi);
2785	}
2786
2787	out:
2788	return work_done;
2789	}
2790
2791	static
2792	int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
2793	{
2794	int ret;
2795
2796	/* The rx would be stopped, so skip submitting */
2797	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags) ||
2798	!test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(dev: tp->netdev))
2799	return 0;
2800
2801	usb_fill_bulk_urb(urb: agg->urb, dev: tp->udev, pipe: tp->pipe_in,
2802	transfer_buffer: agg->buffer, buffer_length: tp->rx_buf_sz,
2803	complete_fn: (usb_complete_t)read_bulk_callback, context: agg);
2804
2805	ret = usb_submit_urb(urb: agg->urb, mem_flags);
2806	if (ret == -ENODEV) {
2807	rtl_set_unplug(tp);
2808	netif_device_detach(dev: tp->netdev);
2809	} else if (ret) {
2810	struct urb *urb = agg->urb;
2811	unsigned long flags;
2812
2813	urb->actual_length = 0;
2814	spin_lock_irqsave(&tp->rx_lock, flags);
2815	list_add_tail(new: &agg->list, head: &tp->rx_done);
2816	spin_unlock_irqrestore(lock: &tp->rx_lock, flags);
2817
2818	netif_err(tp, rx_err, tp->netdev,
2819	"Couldn't submit rx[%p], ret = %d\n", agg, ret);
2820
2821	napi_schedule(n: &tp->napi);
2822	}
2823
2824	return ret;
2825	}
2826
2827	static void rtl_drop_queued_tx(struct r8152 *tp)
2828	{
2829	struct net_device_stats *stats = &tp->netdev->stats;
2830	struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2831	struct sk_buff *skb;
2832
2833	if (skb_queue_empty(list: tx_queue))
2834	return;
2835
2836	__skb_queue_head_init(list: &skb_head);
2837	spin_lock_bh(lock: &tx_queue->lock);
2838	skb_queue_splice_init(list: tx_queue, head: &skb_head);
2839	spin_unlock_bh(lock: &tx_queue->lock);
2840
2841	while ((skb = __skb_dequeue(list: &skb_head))) {
2842	dev_kfree_skb(skb);
2843	stats->tx_dropped++;
2844	}
2845	}
2846
2847	static void rtl8152_tx_timeout(struct net_device *netdev, unsigned int txqueue)
2848	{
2849	struct r8152 *tp = netdev_priv(dev: netdev);
2850
2851	netif_warn(tp, tx_err, netdev, "Tx timeout\n");
2852
2853	usb_queue_reset_device(dev: tp->intf);
2854	}
2855
2856	static void rtl8152_set_rx_mode(struct net_device *netdev)
2857	{
2858	struct r8152 *tp = netdev_priv(dev: netdev);
2859
2860	if (netif_carrier_ok(dev: netdev)) {
2861	set_bit(nr: RTL8152_SET_RX_MODE, addr: &tp->flags);
2862	schedule_delayed_work(dwork: &tp->schedule, delay: 0);
2863	}
2864	}
2865
2866	static void _rtl8152_set_rx_mode(struct net_device *netdev)
2867	{
2868	struct r8152 *tp = netdev_priv(dev: netdev);
2869	u32 mc_filter[2]; /* Multicast hash filter */
2870	__le32 tmp[2];
2871	u32 ocp_data;
2872
2873	netif_stop_queue(dev: netdev);
2874	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2875	ocp_data &= ~RCR_ACPT_ALL;
2876	ocp_data |= RCR_AB | RCR_APM;
2877
2878	if (netdev->flags & IFF_PROMISC) {
2879	/* Unconditionally log net taps. */
2880	netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
2881	ocp_data |= RCR_AM | RCR_AAP;
2882	mc_filter[1] = 0xffffffff;
2883	mc_filter[0] = 0xffffffff;
2884	} else if ((netdev->flags & IFF_MULTICAST &&
2885	netdev_mc_count(netdev) > multicast_filter_limit) ||
2886	(netdev->flags & IFF_ALLMULTI)) {
2887	/* Too many to filter perfectly -- accept all multicasts. */
2888	ocp_data |= RCR_AM;
2889	mc_filter[1] = 0xffffffff;
2890	mc_filter[0] = 0xffffffff;
2891	} else {
2892	mc_filter[1] = 0;
2893	mc_filter[0] = 0;
2894
2895	if (netdev->flags & IFF_MULTICAST) {
2896	struct netdev_hw_addr *ha;
2897
2898	netdev_for_each_mc_addr(ha, netdev) {
2899	int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
2900
2901	mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2902	ocp_data |= RCR_AM;
2903	}
2904	}
2905	}
2906
2907	tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
2908	tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
2909
2910	pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, size: sizeof(tmp), data: tmp);
2911	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, data: ocp_data);
2912	netif_wake_queue(dev: netdev);
2913	}
2914
2915	static netdev_features_t
2916	rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
2917	netdev_features_t features)
2918	{
2919	u32 mss = skb_shinfo(skb)->gso_size;
2920	int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
2921
2922	if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) &&
2923	skb_transport_offset(skb) > max_offset)
2924	features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2925	else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
2926	features &= ~NETIF_F_GSO_MASK;
2927
2928	return features;
2929	}
2930
2931	static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
2932	struct net_device *netdev)
2933	{
2934	struct r8152 *tp = netdev_priv(dev: netdev);
2935
2936	skb_tx_timestamp(skb);
2937
2938	skb_queue_tail(list: &tp->tx_queue, newsk: skb);
2939
2940	if (!list_empty(head: &tp->tx_free)) {
2941	if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
2942	set_bit(nr: SCHEDULE_TASKLET, addr: &tp->flags);
2943	schedule_delayed_work(dwork: &tp->schedule, delay: 0);
2944	} else {
2945	usb_mark_last_busy(udev: tp->udev);
2946	tasklet_schedule(t: &tp->tx_tl);
2947	}
2948	} else if (skb_queue_len(list_: &tp->tx_queue) > tp->tx_qlen) {
2949	netif_stop_queue(dev: netdev);
2950	}
2951
2952	return NETDEV_TX_OK;
2953	}
2954
2955	static void r8152b_reset_packet_filter(struct r8152 *tp)
2956	{
2957	u32 ocp_data;
2958
2959	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
2960	ocp_data &= ~FMC_FCR_MCU_EN;
2961	ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, data: ocp_data);
2962	ocp_data |= FMC_FCR_MCU_EN;
2963	ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, data: ocp_data);
2964	}
2965
2966	static void rtl8152_nic_reset(struct r8152 *tp)
2967	{
2968	u32 ocp_data;
2969	int i;
2970
2971	switch (tp->version) {
2972	case RTL_TEST_01:
2973	case RTL_VER_10:
2974	case RTL_VER_11:
2975	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2976	ocp_data &= ~CR_TE;
2977	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, data: ocp_data);
2978
2979	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_RESET);
2980	ocp_data &= ~BMU_RESET_EP_IN;
2981	ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_RESET, data: ocp_data);
2982
2983	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2984	ocp_data |= CDC_ECM_EN;
2985	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, data: ocp_data);
2986
2987	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2988	ocp_data &= ~CR_RE;
2989	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, data: ocp_data);
2990
2991	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_RESET);
2992	ocp_data |= BMU_RESET_EP_IN;
2993	ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_RESET, data: ocp_data);
2994
2995	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2996	ocp_data &= ~CDC_ECM_EN;
2997	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, data: ocp_data);
2998	break;
2999
3000	default:
3001	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
3002
3003	for (i = 0; i < 1000; i++) {
3004	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
3005	break;
3006	if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
3007	break;
3008	usleep_range(min: 100, max: 400);
3009	}
3010	break;
3011	}
3012	}
3013
3014	static void set_tx_qlen(struct r8152 *tp)
3015	{
3016	tp->tx_qlen = agg_buf_sz / (mtu_to_size(tp->netdev->mtu) + sizeof(struct tx_desc));
3017	}
3018
3019	static inline u16 rtl8152_get_speed(struct r8152 *tp)
3020	{
3021	return ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
3022	}
3023
3024	static void rtl_eee_plus_en(struct r8152 *tp, bool enable)
3025	{
3026	u32 ocp_data;
3027
3028	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
3029	if (enable)
3030	ocp_data |= EEEP_CR_EEEP_TX;
3031	else
3032	ocp_data &= ~EEEP_CR_EEEP_TX;
3033	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, data: ocp_data);
3034	}
3035
3036	static void rtl_set_eee_plus(struct r8152 *tp)
3037	{
3038	if (rtl8152_get_speed(tp) & _10bps)
3039	rtl_eee_plus_en(tp, enable: true);
3040	else
3041	rtl_eee_plus_en(tp, enable: false);
3042	}
3043
3044	static void rxdy_gated_en(struct r8152 *tp, bool enable)
3045	{
3046	u32 ocp_data;
3047
3048	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
3049	if (enable)
3050	ocp_data |= RXDY_GATED_EN;
3051	else
3052	ocp_data &= ~RXDY_GATED_EN;
3053	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, data: ocp_data);
3054	}
3055
3056	static int rtl_start_rx(struct r8152 *tp)
3057	{
3058	struct rx_agg *agg, *agg_next;
3059	struct list_head tmp_list;
3060	unsigned long flags;
3061	int ret = 0, i = 0;
3062
3063	INIT_LIST_HEAD(list: &tmp_list);
3064
3065	spin_lock_irqsave(&tp->rx_lock, flags);
3066
3067	INIT_LIST_HEAD(list: &tp->rx_done);
3068	INIT_LIST_HEAD(list: &tp->rx_used);
3069
3070	list_splice_init(list: &tp->rx_info, head: &tmp_list);
3071
3072	spin_unlock_irqrestore(lock: &tp->rx_lock, flags);
3073
3074	list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {
3075	INIT_LIST_HEAD(list: &agg->list);
3076
3077	/* Only RTL8152_MAX_RX rx_agg need to be submitted. */
3078	if (++i > RTL8152_MAX_RX) {
3079	spin_lock_irqsave(&tp->rx_lock, flags);
3080	list_add_tail(new: &agg->list, head: &tp->rx_used);
3081	spin_unlock_irqrestore(lock: &tp->rx_lock, flags);
3082	} else if (unlikely(ret < 0)) {
3083	spin_lock_irqsave(&tp->rx_lock, flags);
3084	list_add_tail(new: &agg->list, head: &tp->rx_done);
3085	spin_unlock_irqrestore(lock: &tp->rx_lock, flags);
3086	} else {
3087	ret = r8152_submit_rx(tp, agg, GFP_KERNEL);
3088	}
3089	}
3090
3091	spin_lock_irqsave(&tp->rx_lock, flags);
3092	WARN_ON(!list_empty(&tp->rx_info));
3093	list_splice(list: &tmp_list, head: &tp->rx_info);
3094	spin_unlock_irqrestore(lock: &tp->rx_lock, flags);
3095
3096	return ret;
3097	}
3098
3099	static int rtl_stop_rx(struct r8152 *tp)
3100	{
3101	struct rx_agg *agg, *agg_next;
3102	struct list_head tmp_list;
3103	unsigned long flags;
3104
3105	INIT_LIST_HEAD(list: &tmp_list);
3106
3107	/* The usb_kill_urb() couldn't be used in atomic.
3108	* Therefore, move the list of rx_info to a tmp one.
3109	* Then, list_for_each_entry_safe could be used without
3110	* spin lock.
3111	*/
3112
3113	spin_lock_irqsave(&tp->rx_lock, flags);
3114	list_splice_init(list: &tp->rx_info, head: &tmp_list);
3115	spin_unlock_irqrestore(lock: &tp->rx_lock, flags);
3116
3117	list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {
3118	/* At least RTL8152_MAX_RX rx_agg have the page_count being
3119	* equal to 1, so the other ones could be freed safely.
3120	*/
3121	if (page_count(page: agg->page) > 1)
3122	free_rx_agg(tp, agg);
3123	else
3124	usb_kill_urb(urb: agg->urb);
3125	}
3126
3127	/* Move back the list of temp to the rx_info */
3128	spin_lock_irqsave(&tp->rx_lock, flags);
3129	WARN_ON(!list_empty(&tp->rx_info));
3130	list_splice(list: &tmp_list, head: &tp->rx_info);
3131	spin_unlock_irqrestore(lock: &tp->rx_lock, flags);
3132
3133	while (!skb_queue_empty(list: &tp->rx_queue))
3134	dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
3135
3136	return 0;
3137	}
3138
3139	static void rtl_set_ifg(struct r8152 *tp, u16 speed)
3140	{
3141	u32 ocp_data;
3142
3143	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
3144	ocp_data &= ~IFG_MASK;
3145	if ((speed & (_10bps | _100bps)) && !(speed & FULL_DUP)) {
3146	ocp_data |= IFG_144NS;
3147	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR1, data: ocp_data);
3148
3149	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
3150	ocp_data &= ~TX10MIDLE_EN;
3151	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, data: ocp_data);
3152	} else {
3153	ocp_data |= IFG_96NS;
3154	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR1, data: ocp_data);
3155
3156	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
3157	ocp_data |= TX10MIDLE_EN;
3158	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, data: ocp_data);
3159	}
3160	}
3161
3162	static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp)
3163	{
3164	ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN,
3165	OWN_UPDATE | OWN_CLEAR);
3166	}
3167
3168	static int rtl_enable(struct r8152 *tp)
3169	{
3170	u32 ocp_data;
3171
3172	r8152b_reset_packet_filter(tp);
3173
3174	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
3175	ocp_data |= CR_RE | CR_TE;
3176	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, data: ocp_data);
3177
3178	switch (tp->version) {
3179	case RTL_VER_01:
3180	case RTL_VER_02:
3181	case RTL_VER_03:
3182	case RTL_VER_04:
3183	case RTL_VER_05:
3184	case RTL_VER_06:
3185	case RTL_VER_07:
3186	break;
3187	default:
3188	r8153b_rx_agg_chg_indicate(tp);
3189	break;
3190	}
3191
3192	rxdy_gated_en(tp, enable: false);
3193
3194	return 0;
3195	}
3196
3197	static int rtl8152_enable(struct r8152 *tp)
3198	{
3199	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
3200	return -ENODEV;
3201
3202	set_tx_qlen(tp);
3203	rtl_set_eee_plus(tp);
3204
3205	return rtl_enable(tp);
3206	}
3207
3208	static void r8153_set_rx_early_timeout(struct r8152 *tp)
3209	{
3210	u32 ocp_data = tp->coalesce / 8;
3211
3212	switch (tp->version) {
3213	case RTL_VER_03:
3214	case RTL_VER_04:
3215	case RTL_VER_05:
3216	case RTL_VER_06:
3217	ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
3218	data: ocp_data);
3219	break;
3220
3221	case RTL_VER_08:
3222	case RTL_VER_09:
3223	case RTL_VER_14:
3224	/* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout
3225	* primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns.
3226	*/
3227	ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
3228	data: 128 / 8);
3229	ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
3230	data: ocp_data);
3231	break;
3232
3233	case RTL_VER_10:
3234	case RTL_VER_11:
3235	case RTL_VER_12:
3236	case RTL_VER_13:
3237	case RTL_VER_15:
3238	ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
3239	data: 640 / 8);
3240	ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
3241	data: ocp_data);
3242	break;
3243
3244	default:
3245	break;
3246	}
3247	}
3248
3249	static void r8153_set_rx_early_size(struct r8152 *tp)
3250	{
3251	u32 ocp_data = tp->rx_buf_sz - rx_reserved_size(tp->netdev->mtu);
3252
3253	switch (tp->version) {
3254	case RTL_VER_03:
3255	case RTL_VER_04:
3256	case RTL_VER_05:
3257	case RTL_VER_06:
3258	ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
3259	data: ocp_data / 4);
3260	break;
3261	case RTL_VER_08:
3262	case RTL_VER_09:
3263	case RTL_VER_14:
3264	ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
3265	data: ocp_data / 8);
3266	break;
3267	case RTL_TEST_01:
3268	case RTL_VER_10:
3269	case RTL_VER_11:
3270	case RTL_VER_12:
3271	case RTL_VER_13:
3272	case RTL_VER_15:
3273	ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
3274	data: ocp_data / 8);
3275	break;
3276	default:
3277	WARN_ON_ONCE(1);
3278	break;
3279	}
3280	}
3281
3282	static int rtl8153_enable(struct r8152 *tp)
3283	{
3284	u32 ocp_data;
3285
3286	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
3287	return -ENODEV;
3288
3289	set_tx_qlen(tp);
3290	rtl_set_eee_plus(tp);
3291	r8153_set_rx_early_timeout(tp);
3292	r8153_set_rx_early_size(tp);
3293
3294	rtl_set_ifg(tp, speed: rtl8152_get_speed(tp));
3295
3296	switch (tp->version) {
3297	case RTL_VER_09:
3298	case RTL_VER_14:
3299	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
3300	ocp_data &= ~FC_PATCH_TASK;
3301	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, data: ocp_data);
3302	usleep_range(min: 1000, max: 2000);
3303	ocp_data |= FC_PATCH_TASK;
3304	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, data: ocp_data);
3305	break;
3306	default:
3307	break;
3308	}
3309
3310	return rtl_enable(tp);
3311	}
3312
3313	static void rtl_disable(struct r8152 *tp)
3314	{
3315	u32 ocp_data;
3316	int i;
3317
3318	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) {
3319	rtl_drop_queued_tx(tp);
3320	return;
3321	}
3322
3323	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3324	ocp_data &= ~RCR_ACPT_ALL;
3325	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, data: ocp_data);
3326
3327	rtl_drop_queued_tx(tp);
3328
3329	for (i = 0; i < RTL8152_MAX_TX; i++)
3330	usb_kill_urb(urb: tp->tx_info[i].urb);
3331
3332	rxdy_gated_en(tp, enable: true);
3333
3334	for (i = 0; i < 1000; i++) {
3335	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
3336	break;
3337	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3338	if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
3339	break;
3340	usleep_range(min: 1000, max: 2000);
3341	}
3342
3343	for (i = 0; i < 1000; i++) {
3344	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
3345	break;
3346	if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
3347	break;
3348	usleep_range(min: 1000, max: 2000);
3349	}
3350
3351	rtl_stop_rx(tp);
3352
3353	rtl8152_nic_reset(tp);
3354	}
3355
3356	static void r8152_power_cut_en(struct r8152 *tp, bool enable)
3357	{
3358	u32 ocp_data;
3359
3360	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
3361	if (enable)
3362	ocp_data |= POWER_CUT;
3363	else
3364	ocp_data &= ~POWER_CUT;
3365	ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, data: ocp_data);
3366
3367	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
3368	ocp_data &= ~RESUME_INDICATE;
3369	ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, data: ocp_data);
3370	}
3371
3372	static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
3373	{
3374	u32 ocp_data;
3375
3376	switch (tp->version) {
3377	case RTL_VER_01:
3378	case RTL_VER_02:
3379	case RTL_VER_03:
3380	case RTL_VER_04:
3381	case RTL_VER_05:
3382	case RTL_VER_06:
3383	case RTL_VER_07:
3384	case RTL_VER_08:
3385	case RTL_VER_09:
3386	case RTL_VER_14:
3387	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
3388	if (enable)
3389	ocp_data |= CPCR_RX_VLAN;
3390	else
3391	ocp_data &= ~CPCR_RX_VLAN;
3392	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, data: ocp_data);
3393	break;
3394
3395	case RTL_TEST_01:
3396	case RTL_VER_10:
3397	case RTL_VER_11:
3398	case RTL_VER_12:
3399	case RTL_VER_13:
3400	case RTL_VER_15:
3401	default:
3402	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RCR1);
3403	if (enable)
3404	ocp_data |= OUTER_VLAN | INNER_VLAN;
3405	else
3406	ocp_data &= ~(OUTER_VLAN | INNER_VLAN);
3407	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RCR1, data: ocp_data);
3408	break;
3409	}
3410	}
3411
3412	static int rtl8152_set_features(struct net_device *dev,
3413	netdev_features_t features)
3414	{
3415	netdev_features_t changed = features ^ dev->features;
3416	struct r8152 *tp = netdev_priv(dev);
3417	int ret;
3418
3419	ret = usb_autopm_get_interface(intf: tp->intf);
3420	if (ret < 0)
3421	goto out;
3422
3423	mutex_lock(&tp->control);
3424
3425	if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
3426	if (features & NETIF_F_HW_VLAN_CTAG_RX)
3427	rtl_rx_vlan_en(tp, enable: true);
3428	else
3429	rtl_rx_vlan_en(tp, enable: false);
3430	}
3431
3432	mutex_unlock(lock: &tp->control);
3433
3434	usb_autopm_put_interface(intf: tp->intf);
3435
3436	out:
3437	return ret;
3438	}
3439
3440	#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
3441
3442	static u32 __rtl_get_wol(struct r8152 *tp)
3443	{
3444	u32 ocp_data;
3445	u32 wolopts = 0;
3446
3447	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3448	if (ocp_data & LINK_ON_WAKE_EN)
3449	wolopts |= WAKE_PHY;
3450
3451	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
3452	if (ocp_data & UWF_EN)
3453	wolopts |= WAKE_UCAST;
3454	if (ocp_data & BWF_EN)
3455	wolopts |= WAKE_BCAST;
3456	if (ocp_data & MWF_EN)
3457	wolopts |= WAKE_MCAST;
3458
3459	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
3460	if (ocp_data & MAGIC_EN)
3461	wolopts |= WAKE_MAGIC;
3462
3463	return wolopts;
3464	}
3465
3466	static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
3467	{
3468	u32 ocp_data;
3469
3470	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3471
3472	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3473	ocp_data &= ~LINK_ON_WAKE_EN;
3474	if (wolopts & WAKE_PHY)
3475	ocp_data |= LINK_ON_WAKE_EN;
3476	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, data: ocp_data);
3477
3478	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
3479	ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN);
3480	if (wolopts & WAKE_UCAST)
3481	ocp_data |= UWF_EN;
3482	if (wolopts & WAKE_BCAST)
3483	ocp_data |= BWF_EN;
3484	if (wolopts & WAKE_MCAST)
3485	ocp_data |= MWF_EN;
3486	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, data: ocp_data);
3487
3488	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3489
3490	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
3491	ocp_data &= ~MAGIC_EN;
3492	if (wolopts & WAKE_MAGIC)
3493	ocp_data |= MAGIC_EN;
3494	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, data: ocp_data);
3495
3496	if (wolopts & WAKE_ANY)
3497	device_set_wakeup_enable(dev: &tp->udev->dev, enable: true);
3498	else
3499	device_set_wakeup_enable(dev: &tp->udev->dev, enable: false);
3500	}
3501
3502	static void r8153_mac_clk_speed_down(struct r8152 *tp, bool enable)
3503	{
3504	u32 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
3505
3506	/* MAC clock speed down */
3507	if (enable)
3508	ocp_data |= MAC_CLK_SPDWN_EN;
3509	else
3510	ocp_data &= ~MAC_CLK_SPDWN_EN;
3511
3512	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, data: ocp_data);
3513	}
3514
3515	static void r8156_mac_clk_spd(struct r8152 *tp, bool enable)
3516	{
3517	u32 ocp_data;
3518
3519	/* MAC clock speed down */
3520	if (enable) {
3521	/* aldps_spdwn_ratio, tp10_spdwn_ratio */
3522	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL,
3523	data: 0x0403);
3524
3525	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
3526	ocp_data &= ~EEE_SPDWN_RATIO_MASK;
3527	ocp_data |= MAC_CLK_SPDWN_EN | 0x03; /* eee_spdwn_ratio */
3528	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, data: ocp_data);
3529	} else {
3530	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
3531	ocp_data &= ~MAC_CLK_SPDWN_EN;
3532	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, data: ocp_data);
3533	}
3534	}
3535
3536	static void r8153_u1u2en(struct r8152 *tp, bool enable)
3537	{
3538	u8 u1u2[8];
3539
3540	if (enable)
3541	memset(u1u2, 0xff, sizeof(u1u2));
3542	else
3543	memset(u1u2, 0x00, sizeof(u1u2));
3544
3545	usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, size: sizeof(u1u2), data: u1u2);
3546	}
3547
3548	static void r8153b_u1u2en(struct r8152 *tp, bool enable)
3549	{
3550	u32 ocp_data;
3551
3552	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG);
3553	if (enable)
3554	ocp_data |= LPM_U1U2_EN;
3555	else
3556	ocp_data &= ~LPM_U1U2_EN;
3557
3558	ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, data: ocp_data);
3559	}
3560
3561	static void r8153_u2p3en(struct r8152 *tp, bool enable)
3562	{
3563	u32 ocp_data;
3564
3565	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
3566	if (enable)
3567	ocp_data |= U2P3_ENABLE;
3568	else
3569	ocp_data &= ~U2P3_ENABLE;
3570	ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, data: ocp_data);
3571	}
3572
3573	static void r8153b_ups_flags(struct r8152 *tp)
3574	{
3575	u32 ups_flags = 0;
3576
3577	if (tp->ups_info.green)
3578	ups_flags |= UPS_FLAGS_EN_GREEN;
3579
3580	if (tp->ups_info.aldps)
3581	ups_flags |= UPS_FLAGS_EN_ALDPS;
3582
3583	if (tp->ups_info.eee)
3584	ups_flags |= UPS_FLAGS_EN_EEE;
3585
3586	if (tp->ups_info.flow_control)
3587	ups_flags |= UPS_FLAGS_EN_FLOW_CTR;
3588
3589	if (tp->ups_info.eee_ckdiv)
3590	ups_flags |= UPS_FLAGS_EN_EEE_CKDIV;
3591
3592	if (tp->ups_info.eee_cmod_lv)
3593	ups_flags |= UPS_FLAGS_EEE_CMOD_LV_EN;
3594
3595	if (tp->ups_info.r_tune)
3596	ups_flags |= UPS_FLAGS_R_TUNE;
3597
3598	if (tp->ups_info._10m_ckdiv)
3599	ups_flags |= UPS_FLAGS_EN_10M_CKDIV;
3600
3601	if (tp->ups_info.eee_plloff_100)
3602	ups_flags |= UPS_FLAGS_EEE_PLLOFF_100;
3603
3604	if (tp->ups_info.eee_plloff_giga)
3605	ups_flags |= UPS_FLAGS_EEE_PLLOFF_GIGA;
3606
3607	if (tp->ups_info._250m_ckdiv)
3608	ups_flags |= UPS_FLAGS_250M_CKDIV;
3609
3610	if (tp->ups_info.ctap_short_off)
3611	ups_flags |= UPS_FLAGS_CTAP_SHORT_DIS;
3612
3613	switch (tp->ups_info.speed_duplex) {
3614	case NWAY_10M_HALF:
3615	ups_flags |= ups_flags_speed(1);
3616	break;
3617	case NWAY_10M_FULL:
3618	ups_flags |= ups_flags_speed(2);
3619	break;
3620	case NWAY_100M_HALF:
3621	ups_flags |= ups_flags_speed(3);
3622	break;
3623	case NWAY_100M_FULL:
3624	ups_flags |= ups_flags_speed(4);
3625	break;
3626	case NWAY_1000M_FULL:
3627	ups_flags |= ups_flags_speed(5);
3628	break;
3629	case FORCE_10M_HALF:
3630	ups_flags |= ups_flags_speed(6);
3631	break;
3632	case FORCE_10M_FULL:
3633	ups_flags |= ups_flags_speed(7);
3634	break;
3635	case FORCE_100M_HALF:
3636	ups_flags |= ups_flags_speed(8);
3637	break;
3638	case FORCE_100M_FULL:
3639	ups_flags |= ups_flags_speed(9);
3640	break;
3641	default:
3642	break;
3643	}
3644
3645	ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, data: ups_flags);
3646	}
3647
3648	static void r8156_ups_flags(struct r8152 *tp)
3649	{
3650	u32 ups_flags = 0;
3651
3652	if (tp->ups_info.green)
3653	ups_flags |= UPS_FLAGS_EN_GREEN;
3654
3655	if (tp->ups_info.aldps)
3656	ups_flags |= UPS_FLAGS_EN_ALDPS;
3657
3658	if (tp->ups_info.eee)
3659	ups_flags |= UPS_FLAGS_EN_EEE;
3660
3661	if (tp->ups_info.flow_control)
3662	ups_flags |= UPS_FLAGS_EN_FLOW_CTR;
3663
3664	if (tp->ups_info.eee_ckdiv)
3665	ups_flags |= UPS_FLAGS_EN_EEE_CKDIV;
3666
3667	if (tp->ups_info._10m_ckdiv)
3668	ups_flags |= UPS_FLAGS_EN_10M_CKDIV;
3669
3670	if (tp->ups_info.eee_plloff_100)
3671	ups_flags |= UPS_FLAGS_EEE_PLLOFF_100;
3672
3673	if (tp->ups_info.eee_plloff_giga)
3674	ups_flags |= UPS_FLAGS_EEE_PLLOFF_GIGA;
3675
3676	if (tp->ups_info._250m_ckdiv)
3677	ups_flags |= UPS_FLAGS_250M_CKDIV;
3678
3679	switch (tp->ups_info.speed_duplex) {
3680	case FORCE_10M_HALF:
3681	ups_flags |= ups_flags_speed(0);
3682	break;
3683	case FORCE_10M_FULL:
3684	ups_flags |= ups_flags_speed(1);
3685	break;
3686	case FORCE_100M_HALF:
3687	ups_flags |= ups_flags_speed(2);
3688	break;
3689	case FORCE_100M_FULL:
3690	ups_flags |= ups_flags_speed(3);
3691	break;
3692	case NWAY_10M_HALF:
3693	ups_flags |= ups_flags_speed(4);
3694	break;
3695	case NWAY_10M_FULL:
3696	ups_flags |= ups_flags_speed(5);
3697	break;
3698	case NWAY_100M_HALF:
3699	ups_flags |= ups_flags_speed(6);
3700	break;
3701	case NWAY_100M_FULL:
3702	ups_flags |= ups_flags_speed(7);
3703	break;
3704	case NWAY_1000M_FULL:
3705	ups_flags |= ups_flags_speed(8);
3706	break;
3707	case NWAY_2500M_FULL:
3708	ups_flags |= ups_flags_speed(9);
3709	break;
3710	default:
3711	break;
3712	}
3713
3714	switch (tp->ups_info.lite_mode) {
3715	case 1:
3716	ups_flags |= 0 << 5;
3717	break;
3718	case 2:
3719	ups_flags |= 2 << 5;
3720	break;
3721	case 0:
3722	default:
3723	ups_flags |= 1 << 5;
3724	break;
3725	}
3726
3727	ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, data: ups_flags);
3728	}
3729
3730	static void rtl_green_en(struct r8152 *tp, bool enable)
3731	{
3732	u16 data;
3733
3734	data = sram_read(tp, SRAM_GREEN_CFG);
3735	if (enable)
3736	data |= GREEN_ETH_EN;
3737	else
3738	data &= ~GREEN_ETH_EN;
3739	sram_write(tp, SRAM_GREEN_CFG, data);
3740
3741	tp->ups_info.green = enable;
3742	}
3743
3744	static void r8153b_green_en(struct r8152 *tp, bool enable)
3745	{
3746	if (enable) {
3747	sram_write(tp, addr: 0x8045, data: 0); /* 10M abiq&ldvbias */
3748	sram_write(tp, addr: 0x804d, data: 0x1222); /* 100M short abiq&ldvbias */
3749	sram_write(tp, addr: 0x805d, data: 0x0022); /* 1000M short abiq&ldvbias */
3750	} else {
3751	sram_write(tp, addr: 0x8045, data: 0x2444); /* 10M abiq&ldvbias */
3752	sram_write(tp, addr: 0x804d, data: 0x2444); /* 100M short abiq&ldvbias */
3753	sram_write(tp, addr: 0x805d, data: 0x2444); /* 1000M short abiq&ldvbias */
3754	}
3755
3756	rtl_green_en(tp, enable: true);
3757	}
3758
3759	static u16 r8153_phy_status(struct r8152 *tp, u16 desired)
3760	{
3761	u16 data;
3762	int i;
3763
3764	for (i = 0; i < 500; i++) {
3765	data = ocp_reg_read(tp, OCP_PHY_STATUS);
3766	data &= PHY_STAT_MASK;
3767	if (desired) {
3768	if (data == desired)
3769	break;
3770	} else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN ||
3771	data == PHY_STAT_EXT_INIT) {
3772	break;
3773	}
3774
3775	msleep(msecs: 20);
3776	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
3777	break;
3778	}
3779
3780	return data;
3781	}
3782
3783	static void r8153b_ups_en(struct r8152 *tp, bool enable)
3784	{
3785	u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
3786
3787	if (enable) {
3788	r8153b_ups_flags(tp);
3789
3790	ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
3791	ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, data: ocp_data);
3792
3793	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3794	ocp_data |= UPS_FORCE_PWR_DOWN;
3795	ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, data: ocp_data);
3796	} else {
3797	ocp_data &= ~(UPS_EN | USP_PREWAKE);
3798	ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, data: ocp_data);
3799
3800	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3801	ocp_data &= ~UPS_FORCE_PWR_DOWN;
3802	ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, data: ocp_data);
3803
3804	if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {
3805	int i;
3806
3807	for (i = 0; i < 500; i++) {
3808	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
3809	return;
3810	if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
3811	AUTOLOAD_DONE)
3812	break;
3813	msleep(msecs: 20);
3814	}
3815
3816	tp->rtl_ops.hw_phy_cfg(tp);
3817
3818	rtl8152_set_speed(tp, autoneg: tp->autoneg, speed: tp->speed,
3819	duplex: tp->duplex, advertising: tp->advertising);
3820	}
3821	}
3822	}
3823
3824	static void r8153c_ups_en(struct r8152 *tp, bool enable)
3825	{
3826	u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
3827
3828	if (enable) {
3829	r8153b_ups_flags(tp);
3830
3831	ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
3832	ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, data: ocp_data);
3833
3834	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3835	ocp_data |= UPS_FORCE_PWR_DOWN;
3836	ocp_data &= ~BIT(7);
3837	ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, data: ocp_data);
3838	} else {
3839	ocp_data &= ~(UPS_EN | USP_PREWAKE);
3840	ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, data: ocp_data);
3841
3842	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3843	ocp_data &= ~UPS_FORCE_PWR_DOWN;
3844	ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, data: ocp_data);
3845
3846	if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {
3847	int i;
3848
3849	for (i = 0; i < 500; i++) {
3850	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
3851	return;
3852	if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
3853	AUTOLOAD_DONE)
3854	break;
3855	msleep(msecs: 20);
3856	}
3857
3858	tp->rtl_ops.hw_phy_cfg(tp);
3859
3860	rtl8152_set_speed(tp, autoneg: tp->autoneg, speed: tp->speed,
3861	duplex: tp->duplex, advertising: tp->advertising);
3862	}
3863
3864	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3865
3866	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3867	ocp_data |= BIT(8);
3868	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, data: ocp_data);
3869
3870	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3871	}
3872	}
3873
3874	static void r8156_ups_en(struct r8152 *tp, bool enable)
3875	{
3876	u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
3877
3878	if (enable) {
3879	r8156_ups_flags(tp);
3880
3881	ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
3882	ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, data: ocp_data);
3883
3884	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3885	ocp_data |= UPS_FORCE_PWR_DOWN;
3886	ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, data: ocp_data);
3887
3888	switch (tp->version) {
3889	case RTL_VER_13:
3890	case RTL_VER_15:
3891	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPHY_XTAL);
3892	ocp_data &= ~OOBS_POLLING;
3893	ocp_write_byte(tp, MCU_TYPE_USB, USB_UPHY_XTAL, data: ocp_data);
3894	break;
3895	default:
3896	break;
3897	}
3898	} else {
3899	ocp_data &= ~(UPS_EN | USP_PREWAKE);
3900	ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, data: ocp_data);
3901
3902	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3903	ocp_data &= ~UPS_FORCE_PWR_DOWN;
3904	ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, data: ocp_data);
3905
3906	if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {
3907	tp->rtl_ops.hw_phy_cfg(tp);
3908
3909	rtl8152_set_speed(tp, autoneg: tp->autoneg, speed: tp->speed,
3910	duplex: tp->duplex, advertising: tp->advertising);
3911	}
3912	}
3913	}
3914
3915	static void r8153_power_cut_en(struct r8152 *tp, bool enable)
3916	{
3917	u32 ocp_data;
3918
3919	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
3920	if (enable)
3921	ocp_data |= PWR_EN | PHASE2_EN;
3922	else
3923	ocp_data &= ~(PWR_EN | PHASE2_EN);
3924	ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, data: ocp_data);
3925
3926	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3927	ocp_data &= ~PCUT_STATUS;
3928	ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, data: ocp_data);
3929	}
3930
3931	static void r8153b_power_cut_en(struct r8152 *tp, bool enable)
3932	{
3933	u32 ocp_data;
3934
3935	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
3936	if (enable)
3937	ocp_data |= PWR_EN | PHASE2_EN;
3938	else
3939	ocp_data &= ~PWR_EN;
3940	ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, data: ocp_data);
3941
3942	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3943	ocp_data &= ~PCUT_STATUS;
3944	ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, data: ocp_data);
3945	}
3946
3947	static void r8153_queue_wake(struct r8152 *tp, bool enable)
3948	{
3949	u32 ocp_data;
3950
3951	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG);
3952	if (enable)
3953	ocp_data |= UPCOMING_RUNTIME_D3;
3954	else
3955	ocp_data &= ~UPCOMING_RUNTIME_D3;
3956	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG, data: ocp_data);
3957
3958	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG);
3959	ocp_data &= ~LINK_CHG_EVENT;
3960	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG, data: ocp_data);
3961
3962	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
3963	ocp_data &= ~LINK_CHANGE_FLAG;
3964	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, data: ocp_data);
3965	}
3966
3967	static bool rtl_can_wakeup(struct r8152 *tp)
3968	{
3969	struct usb_device *udev = tp->udev;
3970
3971	return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP);
3972	}
3973
3974	static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
3975	{
3976	if (enable) {
3977	u32 ocp_data;
3978
3979	__rtl_set_wol(tp, WAKE_ANY);
3980
3981	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3982
3983	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3984	ocp_data |= LINK_OFF_WAKE_EN;
3985	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, data: ocp_data);
3986
3987	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3988	} else {
3989	u32 ocp_data;
3990
3991	__rtl_set_wol(tp, wolopts: tp->saved_wolopts);
3992
3993	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3994
3995	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3996	ocp_data &= ~LINK_OFF_WAKE_EN;
3997	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, data: ocp_data);
3998
3999	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
4000	}
4001	}
4002
4003	static void rtl8153_runtime_enable(struct r8152 *tp, bool enable)
4004	{
4005	if (enable) {
4006	r8153_u1u2en(tp, enable: false);
4007	r8153_u2p3en(tp, enable: false);
4008	rtl_runtime_suspend_enable(tp, enable: true);
4009	} else {
4010	rtl_runtime_suspend_enable(tp, enable: false);
4011
4012	switch (tp->version) {
4013	case RTL_VER_03:
4014	case RTL_VER_04:
4015	break;
4016	case RTL_VER_05:
4017	case RTL_VER_06:
4018	default:
4019	r8153_u2p3en(tp, enable: true);
4020	break;
4021	}
4022
4023	r8153_u1u2en(tp, enable: true);
4024	}
4025	}
4026
4027	static void rtl8153b_runtime_enable(struct r8152 *tp, bool enable)
4028	{
4029	if (enable) {
4030	r8153_queue_wake(tp, enable: true);
4031	r8153b_u1u2en(tp, enable: false);
4032	r8153_u2p3en(tp, enable: false);
4033	rtl_runtime_suspend_enable(tp, enable: true);
4034	r8153b_ups_en(tp, enable: true);
4035	} else {
4036	r8153b_ups_en(tp, enable: false);
4037	r8153_queue_wake(tp, enable: false);
4038	rtl_runtime_suspend_enable(tp, enable: false);
4039	if (tp->udev->speed >= USB_SPEED_SUPER)
4040	r8153b_u1u2en(tp, enable: true);
4041	}
4042	}
4043
4044	static void rtl8153c_runtime_enable(struct r8152 *tp, bool enable)
4045	{
4046	if (enable) {
4047	r8153_queue_wake(tp, enable: true);
4048	r8153b_u1u2en(tp, enable: false);
4049	r8153_u2p3en(tp, enable: false);
4050	rtl_runtime_suspend_enable(tp, enable: true);
4051	r8153c_ups_en(tp, enable: true);
4052	} else {
4053	r8153c_ups_en(tp, enable: false);
4054	r8153_queue_wake(tp, enable: false);
4055	rtl_runtime_suspend_enable(tp, enable: false);
4056	r8153b_u1u2en(tp, enable: true);
4057	}
4058	}
4059
4060	static void rtl8156_runtime_enable(struct r8152 *tp, bool enable)
4061	{
4062	if (enable) {
4063	r8153_queue_wake(tp, enable: true);
4064	r8153b_u1u2en(tp, enable: false);
4065	r8153_u2p3en(tp, enable: false);
4066	rtl_runtime_suspend_enable(tp, enable: true);
4067	} else {
4068	r8153_queue_wake(tp, enable: false);
4069	rtl_runtime_suspend_enable(tp, enable: false);
4070	r8153_u2p3en(tp, enable: true);
4071	if (tp->udev->speed >= USB_SPEED_SUPER)
4072	r8153b_u1u2en(tp, enable: true);
4073	}
4074	}
4075
4076	static void r8153_teredo_off(struct r8152 *tp)
4077	{
4078	u32 ocp_data;
4079
4080	switch (tp->version) {
4081	case RTL_VER_01:
4082	case RTL_VER_02:
4083	case RTL_VER_03:
4084	case RTL_VER_04:
4085	case RTL_VER_05:
4086	case RTL_VER_06:
4087	case RTL_VER_07:
4088	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
4089	ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK |
4090	OOB_TEREDO_EN);
4091	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, data: ocp_data);
4092	break;
4093
4094	case RTL_VER_08:
4095	case RTL_VER_09:
4096	case RTL_TEST_01:
4097	case RTL_VER_10:
4098	case RTL_VER_11:
4099	case RTL_VER_12:
4100	case RTL_VER_13:
4101	case RTL_VER_14:
4102	case RTL_VER_15:
4103	default:
4104	/* The bit 0 ~ 7 are relative with teredo settings. They are
4105	* W1C (write 1 to clear), so set all 1 to disable it.
4106	*/
4107	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, data: 0xff);
4108	break;
4109	}
4110
4111	ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
4112	ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, data: 0);
4113	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, data: 0);
4114	}
4115
4116	static void rtl_reset_bmu(struct r8152 *tp)
4117	{
4118	u32 ocp_data;
4119
4120	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET);
4121	ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT);
4122	ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, data: ocp_data);
4123	ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT;
4124	ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, data: ocp_data);
4125	}
4126
4127	/* Clear the bp to stop the firmware before loading a new one */
4128	static void rtl_clear_bp(struct r8152 *tp, u16 type)
4129	{
4130	u16 bp[16] = {0};
4131	u16 bp_num;
4132
4133	switch (tp->version) {
4134	case RTL_VER_08:
4135	case RTL_VER_09:
4136	case RTL_VER_10:
4137	case RTL_VER_11:
4138	case RTL_VER_12:
4139	case RTL_VER_13:
4140	case RTL_VER_15:
4141	if (type == MCU_TYPE_USB) {
4142	ocp_write_word(tp, MCU_TYPE_USB, USB_BP2_EN, data: 0);
4143	bp_num = 16;
4144	break;
4145	}
4146	fallthrough;
4147	case RTL_VER_03:
4148	case RTL_VER_04:
4149	case RTL_VER_05:
4150	case RTL_VER_06:
4151	ocp_write_byte(tp, type, PLA_BP_EN, data: 0);
4152	fallthrough;
4153	case RTL_VER_01:
4154	case RTL_VER_02:
4155	case RTL_VER_07:
4156	bp_num = 8;
4157	break;
4158	case RTL_VER_14:
4159	default:
4160	ocp_write_word(tp, type, USB_BP2_EN, data: 0);
4161	bp_num = 16;
4162	break;
4163	}
4164
4165	generic_ocp_write(tp, PLA_BP_0, BYTE_EN_DWORD, size: bp_num << 1, data: bp, type);
4166
4167	/* wait 3 ms to make sure the firmware is stopped */
4168	usleep_range(min: 3000, max: 6000);
4169	ocp_write_word(tp, type, PLA_BP_BA, data: 0);
4170	}
4171
4172	static inline void rtl_reset_ocp_base(struct r8152 *tp)
4173	{
4174	tp->ocp_base = -1;
4175	}
4176
4177	static int rtl_phy_patch_request(struct r8152 *tp, bool request, bool wait)
4178	{
4179	u16 data, check;
4180	int i;
4181
4182	data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD);
4183	if (request) {
4184	data |= PATCH_REQUEST;
4185	check = 0;
4186	} else {
4187	data &= ~PATCH_REQUEST;
4188	check = PATCH_READY;
4189	}
4190	ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data);
4191
4192	for (i = 0; wait && i < 5000; i++) {
4193	u32 ocp_data;
4194
4195	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
4196	return -ENODEV;
4197
4198	usleep_range(min: 1000, max: 2000);
4199	ocp_data = ocp_reg_read(tp, OCP_PHY_PATCH_STAT);
4200	if ((ocp_data & PATCH_READY) ^ check)
4201	break;
4202	}
4203
4204	if (request && wait &&
4205	!(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) {
4206	dev_err(&tp->intf->dev, "PHY patch request fail\n");
4207	rtl_phy_patch_request(tp, request: false, wait: false);
4208	return -ETIME;
4209	} else {
4210	return 0;
4211	}
4212	}
4213
4214	static void rtl_patch_key_set(struct r8152 *tp, u16 key_addr, u16 patch_key)
4215	{
4216	if (patch_key && key_addr) {
4217	sram_write(tp, addr: key_addr, data: patch_key);
4218	sram_write(tp, SRAM_PHY_LOCK, PHY_PATCH_LOCK);
4219	} else if (key_addr) {
4220	u16 data;
4221
4222	sram_write(tp, addr: 0x0000, data: 0x0000);
4223
4224	data = ocp_reg_read(tp, OCP_PHY_LOCK);
4225	data &= ~PATCH_LOCK;
4226	ocp_reg_write(tp, OCP_PHY_LOCK, data);
4227
4228	sram_write(tp, addr: key_addr, data: 0x0000);
4229	} else {
4230	WARN_ON_ONCE(1);
4231	}
4232	}
4233
4234	static int
4235	rtl_pre_ram_code(struct r8152 *tp, u16 key_addr, u16 patch_key, bool wait)
4236	{
4237	if (rtl_phy_patch_request(tp, request: true, wait))
4238	return -ETIME;
4239
4240	rtl_patch_key_set(tp, key_addr, patch_key);
4241
4242	return 0;
4243	}
4244
4245	static int rtl_post_ram_code(struct r8152 *tp, u16 key_addr, bool wait)
4246	{
4247	rtl_patch_key_set(tp, key_addr, patch_key: 0);
4248
4249	rtl_phy_patch_request(tp, request: false, wait);
4250
4251	return 0;
4252	}
4253
4254	static bool rtl8152_is_fw_phy_speed_up_ok(struct r8152 *tp, struct fw_phy_speed_up *phy)
4255	{
4256	u16 fw_offset;
4257	u32 length;
4258	bool rc = false;
4259
4260	switch (tp->version) {
4261	case RTL_VER_01:
4262	case RTL_VER_02:
4263	case RTL_VER_03:
4264	case RTL_VER_04:
4265	case RTL_VER_05:
4266	case RTL_VER_06:
4267	case RTL_VER_07:
4268	case RTL_VER_08:
4269	case RTL_VER_09:
4270	case RTL_VER_10:
4271	case RTL_VER_11:
4272	case RTL_VER_12:
4273	case RTL_VER_14:
4274	goto out;
4275	case RTL_VER_13:
4276	case RTL_VER_15:
4277	default:
4278	break;
4279	}
4280
4281	fw_offset = __le16_to_cpu(phy->fw_offset);
4282	length = __le32_to_cpu(phy->blk_hdr.length);
4283	if (fw_offset < sizeof(*phy) || length <= fw_offset) {
4284	dev_err(&tp->intf->dev, "invalid fw_offset\n");
4285	goto out;
4286	}
4287
4288	length -= fw_offset;
4289	if (length & 3) {
4290	dev_err(&tp->intf->dev, "invalid block length\n");
4291	goto out;
4292	}
4293
4294	if (__le16_to_cpu(phy->fw_reg) != 0x9A00) {
4295	dev_err(&tp->intf->dev, "invalid register to load firmware\n");
4296	goto out;
4297	}
4298
4299	rc = true;
4300	out:
4301	return rc;
4302	}
4303
4304	static bool rtl8152_is_fw_phy_ver_ok(struct r8152 *tp, struct fw_phy_ver *ver)
4305	{
4306	bool rc = false;
4307
4308	switch (tp->version) {
4309	case RTL_VER_10:
4310	case RTL_VER_11:
4311	case RTL_VER_12:
4312	case RTL_VER_13:
4313	case RTL_VER_15:
4314	break;
4315	default:
4316	goto out;
4317	}
4318
4319	if (__le32_to_cpu(ver->blk_hdr.length) != sizeof(*ver)) {
4320	dev_err(&tp->intf->dev, "invalid block length\n");
4321	goto out;
4322	}
4323
4324	if (__le16_to_cpu(ver->ver.addr) != SRAM_GPHY_FW_VER) {
4325	dev_err(&tp->intf->dev, "invalid phy ver addr\n");
4326	goto out;
4327	}
4328
4329	rc = true;
4330	out:
4331	return rc;
4332	}
4333
4334	static bool rtl8152_is_fw_phy_fixup_ok(struct r8152 *tp, struct fw_phy_fixup *fix)
4335	{
4336	bool rc = false;
4337
4338	switch (tp->version) {
4339	case RTL_VER_10:
4340	case RTL_VER_11:
4341	case RTL_VER_12:
4342	case RTL_VER_13:
4343	case RTL_VER_15:
4344	break;
4345	default:
4346	goto out;
4347	}
4348
4349	if (__le32_to_cpu(fix->blk_hdr.length) != sizeof(*fix)) {
4350	dev_err(&tp->intf->dev, "invalid block length\n");
4351	goto out;
4352	}
4353
4354	if (__le16_to_cpu(fix->setting.addr) != OCP_PHY_PATCH_CMD ||
4355	__le16_to_cpu(fix->setting.data) != BIT(7)) {
4356	dev_err(&tp->intf->dev, "invalid phy fixup\n");
4357	goto out;
4358	}
4359
4360	rc = true;
4361	out:
4362	return rc;
4363	}
4364
4365	static bool rtl8152_is_fw_phy_union_ok(struct r8152 *tp, struct fw_phy_union *phy)
4366	{
4367	u16 fw_offset;
4368	u32 length;
4369	bool rc = false;
4370
4371	switch (tp->version) {
4372	case RTL_VER_10:
4373	case RTL_VER_11:
4374	case RTL_VER_12:
4375	case RTL_VER_13:
4376	case RTL_VER_15:
4377	break;
4378	default:
4379	goto out;
4380	}
4381
4382	fw_offset = __le16_to_cpu(phy->fw_offset);
4383	length = __le32_to_cpu(phy->blk_hdr.length);
4384	if (fw_offset < sizeof(*phy) || length <= fw_offset) {
4385	dev_err(&tp->intf->dev, "invalid fw_offset\n");
4386	goto out;
4387	}
4388
4389	length -= fw_offset;
4390	if (length & 1) {
4391	dev_err(&tp->intf->dev, "invalid block length\n");
4392	goto out;
4393	}
4394
4395	if (phy->pre_num > 2) {
4396	dev_err(&tp->intf->dev, "invalid pre_num %d\n", phy->pre_num);
4397	goto out;
4398	}
4399
4400	if (phy->bp_num > 8) {
4401	dev_err(&tp->intf->dev, "invalid bp_num %d\n", phy->bp_num);
4402	goto out;
4403	}
4404
4405	rc = true;
4406	out:
4407	return rc;
4408	}
4409
4410	static bool rtl8152_is_fw_phy_nc_ok(struct r8152 *tp, struct fw_phy_nc *phy)
4411	{
4412	u32 length;
4413	u16 fw_offset, fw_reg, ba_reg, patch_en_addr, mode_reg, bp_start;
4414	bool rc = false;
4415
4416	switch (tp->version) {
4417	case RTL_VER_04:
4418	case RTL_VER_05:
4419	case RTL_VER_06:
4420	fw_reg = 0xa014;
4421	ba_reg = 0xa012;
4422	patch_en_addr = 0xa01a;
4423	mode_reg = 0xb820;
4424	bp_start = 0xa000;
4425	break;
4426	default:
4427	goto out;
4428	}
4429
4430	fw_offset = __le16_to_cpu(phy->fw_offset);
4431	if (fw_offset < sizeof(*phy)) {
4432	dev_err(&tp->intf->dev, "fw_offset too small\n");
4433	goto out;
4434	}
4435
4436	length = __le32_to_cpu(phy->blk_hdr.length);
4437	if (length < fw_offset) {
4438	dev_err(&tp->intf->dev, "invalid fw_offset\n");
4439	goto out;
4440	}
4441
4442	length -= __le16_to_cpu(phy->fw_offset);
4443	if (!length || (length & 1)) {
4444	dev_err(&tp->intf->dev, "invalid block length\n");
4445	goto out;
4446	}
4447
4448	if (__le16_to_cpu(phy->fw_reg) != fw_reg) {
4449	dev_err(&tp->intf->dev, "invalid register to load firmware\n");
4450	goto out;
4451	}
4452
4453	if (__le16_to_cpu(phy->ba_reg) != ba_reg) {
4454	dev_err(&tp->intf->dev, "invalid base address register\n");
4455	goto out;
4456	}
4457
4458	if (__le16_to_cpu(phy->patch_en_addr) != patch_en_addr) {
4459	dev_err(&tp->intf->dev,
4460	"invalid patch mode enabled register\n");
4461	goto out;
4462	}
4463
4464	if (__le16_to_cpu(phy->mode_reg) != mode_reg) {
4465	dev_err(&tp->intf->dev,
4466	"invalid register to switch the mode\n");
4467	goto out;
4468	}
4469
4470	if (__le16_to_cpu(phy->bp_start) != bp_start) {
4471	dev_err(&tp->intf->dev,
4472	"invalid start register of break point\n");
4473	goto out;
4474	}
4475
4476	if (__le16_to_cpu(phy->bp_num) > 4) {
4477	dev_err(&tp->intf->dev, "invalid break point number\n");
4478	goto out;
4479	}
4480
4481	rc = true;
4482	out:
4483	return rc;
4484	}
4485
4486	static bool rtl8152_is_fw_mac_ok(struct r8152 *tp, struct fw_mac *mac)
4487	{
4488	u16 fw_reg, bp_ba_addr, bp_en_addr, bp_start, fw_offset;
4489	bool rc = false;
4490	u32 length, type;
4491	int i, max_bp;
4492
4493	type = __le32_to_cpu(mac->blk_hdr.type);
4494	if (type == RTL_FW_PLA) {
4495	switch (tp->version) {
4496	case RTL_VER_01:
4497	case RTL_VER_02:
4498	case RTL_VER_07:
4499	fw_reg = 0xf800;
4500	bp_ba_addr = PLA_BP_BA;
4501	bp_en_addr = 0;
4502	bp_start = PLA_BP_0;
4503	max_bp = 8;
4504	break;
4505	case RTL_VER_03:
4506	case RTL_VER_04:
4507	case RTL_VER_05:
4508	case RTL_VER_06:
4509	case RTL_VER_08:
4510	case RTL_VER_09:
4511	case RTL_VER_11:
4512	case RTL_VER_12:
4513	case RTL_VER_13:
4514	case RTL_VER_15:
4515	fw_reg = 0xf800;
4516	bp_ba_addr = PLA_BP_BA;
4517	bp_en_addr = PLA_BP_EN;
4518	bp_start = PLA_BP_0;
4519	max_bp = 8;
4520	break;
4521	case RTL_VER_14:
4522	fw_reg = 0xf800;
4523	bp_ba_addr = PLA_BP_BA;
4524	bp_en_addr = USB_BP2_EN;
4525	bp_start = PLA_BP_0;
4526	max_bp = 16;
4527	break;
4528	default:
4529	goto out;
4530	}
4531	} else if (type == RTL_FW_USB) {
4532	switch (tp->version) {
4533	case RTL_VER_03:
4534	case RTL_VER_04:
4535	case RTL_VER_05:
4536	case RTL_VER_06:
4537	fw_reg = 0xf800;
4538	bp_ba_addr = USB_BP_BA;
4539	bp_en_addr = USB_BP_EN;
4540	bp_start = USB_BP_0;
4541	max_bp = 8;
4542	break;
4543	case RTL_VER_08:
4544	case RTL_VER_09:
4545	case RTL_VER_11:
4546	case RTL_VER_12:
4547	case RTL_VER_13:
4548	case RTL_VER_14:
4549	case RTL_VER_15:
4550	fw_reg = 0xe600;
4551	bp_ba_addr = USB_BP_BA;
4552	bp_en_addr = USB_BP2_EN;
4553	bp_start = USB_BP_0;
4554	max_bp = 16;
4555	break;
4556	case RTL_VER_01:
4557	case RTL_VER_02:
4558	case RTL_VER_07:
4559	default:
4560	goto out;
4561	}
4562	} else {
4563	goto out;
4564	}
4565
4566	fw_offset = __le16_to_cpu(mac->fw_offset);
4567	if (fw_offset < sizeof(*mac)) {
4568	dev_err(&tp->intf->dev, "fw_offset too small\n");
4569	goto out;
4570	}
4571
4572	length = __le32_to_cpu(mac->blk_hdr.length);
4573	if (length < fw_offset) {
4574	dev_err(&tp->intf->dev, "invalid fw_offset\n");
4575	goto out;
4576	}
4577
4578	length -= fw_offset;
4579	if (length < 4 || (length & 3)) {
4580	dev_err(&tp->intf->dev, "invalid block length\n");
4581	goto out;
4582	}
4583
4584	if (__le16_to_cpu(mac->fw_reg) != fw_reg) {
4585	dev_err(&tp->intf->dev, "invalid register to load firmware\n");
4586	goto out;
4587	}
4588
4589	if (__le16_to_cpu(mac->bp_ba_addr) != bp_ba_addr) {
4590	dev_err(&tp->intf->dev, "invalid base address register\n");
4591	goto out;
4592	}
4593
4594	if (__le16_to_cpu(mac->bp_en_addr) != bp_en_addr) {
4595	dev_err(&tp->intf->dev, "invalid enabled mask register\n");
4596	goto out;
4597	}
4598
4599	if (__le16_to_cpu(mac->bp_start) != bp_start) {
4600	dev_err(&tp->intf->dev,
4601	"invalid start register of break point\n");
4602	goto out;
4603	}
4604
4605	if (__le16_to_cpu(mac->bp_num) > max_bp) {
4606	dev_err(&tp->intf->dev, "invalid break point number\n");
4607	goto out;
4608	}
4609
4610	for (i = __le16_to_cpu(mac->bp_num); i < max_bp; i++) {
4611	if (mac->bp[i]) {
4612	dev_err(&tp->intf->dev, "unused bp%u is not zero\n", i);
4613	goto out;
4614	}
4615	}
4616
4617	rc = true;
4618	out:
4619	return rc;
4620	}
4621
4622	/* Verify the checksum for the firmware file. It is calculated from the version
4623	* field to the end of the file. Compare the result with the checksum field to
4624	* make sure the file is correct.
4625	*/
4626	static long rtl8152_fw_verify_checksum(struct r8152 *tp,
4627	struct fw_header *fw_hdr, size_t size)
4628	{
4629	unsigned char checksum[sizeof(fw_hdr->checksum)];
4630	struct crypto_shash *alg;
4631	struct shash_desc *sdesc;
4632	size_t len;
4633	long rc;
4634
4635	alg = crypto_alloc_shash(alg_name: "sha256", type: 0, mask: 0);
4636	if (IS_ERR(ptr: alg)) {
4637	rc = PTR_ERR(ptr: alg);
4638	goto out;
4639	}
4640
4641	if (crypto_shash_digestsize(tfm: alg) != sizeof(fw_hdr->checksum)) {
4642	rc = -EFAULT;
4643	dev_err(&tp->intf->dev, "digestsize incorrect (%u)\n",
4644	crypto_shash_digestsize(alg));
4645	goto free_shash;
4646	}
4647
4648	len = sizeof(*sdesc) + crypto_shash_descsize(tfm: alg);
4649	sdesc = kmalloc(size: len, GFP_KERNEL);
4650	if (!sdesc) {
4651	rc = -ENOMEM;
4652	goto free_shash;
4653	}
4654	sdesc->tfm = alg;
4655
4656	len = size - sizeof(fw_hdr->checksum);
4657	rc = crypto_shash_digest(desc: sdesc, data: fw_hdr->version, len, out: checksum);
4658	kfree(objp: sdesc);
4659	if (rc)
4660	goto free_shash;
4661
4662	if (memcmp(p: fw_hdr->checksum, q: checksum, size: sizeof(fw_hdr->checksum))) {
4663	dev_err(&tp->intf->dev, "checksum fail\n");
4664	rc = -EFAULT;
4665	}
4666
4667	free_shash:
4668	crypto_free_shash(tfm: alg);
4669	out:
4670	return rc;
4671	}
4672
4673	static long rtl8152_check_firmware(struct r8152 *tp, struct rtl_fw *rtl_fw)
4674	{
4675	const struct firmware *fw = rtl_fw->fw;
4676	struct fw_header *fw_hdr = (struct fw_header *)fw->data;
4677	unsigned long fw_flags = 0;
4678	long ret = -EFAULT;
4679	int i;
4680
4681	if (fw->size < sizeof(*fw_hdr)) {
4682	dev_err(&tp->intf->dev, "file too small\n");
4683	goto fail;
4684	}
4685
4686	ret = rtl8152_fw_verify_checksum(tp, fw_hdr, size: fw->size);
4687	if (ret)
4688	goto fail;
4689
4690	ret = -EFAULT;
4691
4692	for (i = sizeof(*fw_hdr); i < fw->size;) {
4693	struct fw_block *block = (struct fw_block *)&fw->data[i];
4694	u32 type;
4695
4696	if ((i + sizeof(*block)) > fw->size)
4697	goto fail;
4698
4699	type = __le32_to_cpu(block->type);
4700	switch (type) {
4701	case RTL_FW_END:
4702	if (__le32_to_cpu(block->length) != sizeof(*block))
4703	goto fail;
4704	goto fw_end;
4705	case RTL_FW_PLA:
4706	if (test_bit(FW_FLAGS_PLA, &fw_flags)) {
4707	dev_err(&tp->intf->dev,
4708	"multiple PLA firmware encountered");
4709	goto fail;
4710	}
4711
4712	if (!rtl8152_is_fw_mac_ok(tp, mac: (struct fw_mac *)block)) {
4713	dev_err(&tp->intf->dev,
4714	"check PLA firmware failed\n");
4715	goto fail;
4716	}
4717	__set_bit(FW_FLAGS_PLA, &fw_flags);
4718	break;
4719	case RTL_FW_USB:
4720	if (test_bit(FW_FLAGS_USB, &fw_flags)) {
4721	dev_err(&tp->intf->dev,
4722	"multiple USB firmware encountered");
4723	goto fail;
4724	}
4725
4726	if (!rtl8152_is_fw_mac_ok(tp, mac: (struct fw_mac *)block)) {
4727	dev_err(&tp->intf->dev,
4728	"check USB firmware failed\n");
4729	goto fail;
4730	}
4731	__set_bit(FW_FLAGS_USB, &fw_flags);
4732	break;
4733	case RTL_FW_PHY_START:
4734	if (test_bit(FW_FLAGS_START, &fw_flags) ||
4735	test_bit(FW_FLAGS_NC, &fw_flags) ||
4736	test_bit(FW_FLAGS_NC1, &fw_flags) ||
4737	test_bit(FW_FLAGS_NC2, &fw_flags) ||
4738	test_bit(FW_FLAGS_UC2, &fw_flags) ||
4739	test_bit(FW_FLAGS_UC, &fw_flags) ||
4740	test_bit(FW_FLAGS_STOP, &fw_flags)) {
4741	dev_err(&tp->intf->dev,
4742	"check PHY_START fail\n");
4743	goto fail;
4744	}
4745
4746	if (__le32_to_cpu(block->length) != sizeof(struct fw_phy_patch_key)) {
4747	dev_err(&tp->intf->dev,
4748	"Invalid length for PHY_START\n");
4749	goto fail;
4750	}
4751	__set_bit(FW_FLAGS_START, &fw_flags);
4752	break;
4753	case RTL_FW_PHY_STOP:
4754	if (test_bit(FW_FLAGS_STOP, &fw_flags) ||
4755	!test_bit(FW_FLAGS_START, &fw_flags)) {
4756	dev_err(&tp->intf->dev,
4757	"Check PHY_STOP fail\n");
4758	goto fail;
4759	}
4760
4761	if (__le32_to_cpu(block->length) != sizeof(*block)) {
4762	dev_err(&tp->intf->dev,
4763	"Invalid length for PHY_STOP\n");
4764	goto fail;
4765	}
4766	__set_bit(FW_FLAGS_STOP, &fw_flags);
4767	break;
4768	case RTL_FW_PHY_NC:
4769	if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4770	test_bit(FW_FLAGS_STOP, &fw_flags)) {
4771	dev_err(&tp->intf->dev,
4772	"check PHY_NC fail\n");
4773	goto fail;
4774	}
4775
4776	if (test_bit(FW_FLAGS_NC, &fw_flags)) {
4777	dev_err(&tp->intf->dev,
4778	"multiple PHY NC encountered\n");
4779	goto fail;
4780	}
4781
4782	if (!rtl8152_is_fw_phy_nc_ok(tp, phy: (struct fw_phy_nc *)block)) {
4783	dev_err(&tp->intf->dev,
4784	"check PHY NC firmware failed\n");
4785	goto fail;
4786	}
4787	__set_bit(FW_FLAGS_NC, &fw_flags);
4788	break;
4789	case RTL_FW_PHY_UNION_NC:
4790	if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4791	test_bit(FW_FLAGS_NC1, &fw_flags) ||
4792	test_bit(FW_FLAGS_NC2, &fw_flags) ||
4793	test_bit(FW_FLAGS_UC2, &fw_flags) ||
4794	test_bit(FW_FLAGS_UC, &fw_flags) ||
4795	test_bit(FW_FLAGS_STOP, &fw_flags)) {
4796	dev_err(&tp->intf->dev, "PHY_UNION_NC out of order\n");
4797	goto fail;
4798	}
4799
4800	if (test_bit(FW_FLAGS_NC, &fw_flags)) {
4801	dev_err(&tp->intf->dev, "multiple PHY_UNION_NC encountered\n");
4802	goto fail;
4803	}
4804
4805	if (!rtl8152_is_fw_phy_union_ok(tp, phy: (struct fw_phy_union *)block)) {
4806	dev_err(&tp->intf->dev, "check PHY_UNION_NC failed\n");
4807	goto fail;
4808	}
4809	__set_bit(FW_FLAGS_NC, &fw_flags);
4810	break;
4811	case RTL_FW_PHY_UNION_NC1:
4812	if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4813	test_bit(FW_FLAGS_NC2, &fw_flags) ||
4814	test_bit(FW_FLAGS_UC2, &fw_flags) ||
4815	test_bit(FW_FLAGS_UC, &fw_flags) ||
4816	test_bit(FW_FLAGS_STOP, &fw_flags)) {
4817	dev_err(&tp->intf->dev, "PHY_UNION_NC1 out of order\n");
4818	goto fail;
4819	}
4820
4821	if (test_bit(FW_FLAGS_NC1, &fw_flags)) {
4822	dev_err(&tp->intf->dev, "multiple PHY NC1 encountered\n");
4823	goto fail;
4824	}
4825
4826	if (!rtl8152_is_fw_phy_union_ok(tp, phy: (struct fw_phy_union *)block)) {
4827	dev_err(&tp->intf->dev, "check PHY_UNION_NC1 failed\n");
4828	goto fail;
4829	}
4830	__set_bit(FW_FLAGS_NC1, &fw_flags);
4831	break;
4832	case RTL_FW_PHY_UNION_NC2:
4833	if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4834	test_bit(FW_FLAGS_UC2, &fw_flags) ||
4835	test_bit(FW_FLAGS_UC, &fw_flags) ||
4836	test_bit(FW_FLAGS_STOP, &fw_flags)) {
4837	dev_err(&tp->intf->dev, "PHY_UNION_NC2 out of order\n");
4838	goto fail;
4839	}
4840
4841	if (test_bit(FW_FLAGS_NC2, &fw_flags)) {
4842	dev_err(&tp->intf->dev, "multiple PHY NC2 encountered\n");
4843	goto fail;
4844	}
4845
4846	if (!rtl8152_is_fw_phy_union_ok(tp, phy: (struct fw_phy_union *)block)) {
4847	dev_err(&tp->intf->dev, "check PHY_UNION_NC2 failed\n");
4848	goto fail;
4849	}
4850	__set_bit(FW_FLAGS_NC2, &fw_flags);
4851	break;
4852	case RTL_FW_PHY_UNION_UC2:
4853	if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4854	test_bit(FW_FLAGS_UC, &fw_flags) ||
4855	test_bit(FW_FLAGS_STOP, &fw_flags)) {
4856	dev_err(&tp->intf->dev, "PHY_UNION_UC2 out of order\n");
4857	goto fail;
4858	}
4859
4860	if (test_bit(FW_FLAGS_UC2, &fw_flags)) {
4861	dev_err(&tp->intf->dev, "multiple PHY UC2 encountered\n");
4862	goto fail;
4863	}
4864
4865	if (!rtl8152_is_fw_phy_union_ok(tp, phy: (struct fw_phy_union *)block)) {
4866	dev_err(&tp->intf->dev, "check PHY_UNION_UC2 failed\n");
4867	goto fail;
4868	}
4869	__set_bit(FW_FLAGS_UC2, &fw_flags);
4870	break;
4871	case RTL_FW_PHY_UNION_UC:
4872	if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4873	test_bit(FW_FLAGS_STOP, &fw_flags)) {
4874	dev_err(&tp->intf->dev, "PHY_UNION_UC out of order\n");
4875	goto fail;
4876	}
4877
4878	if (test_bit(FW_FLAGS_UC, &fw_flags)) {
4879	dev_err(&tp->intf->dev, "multiple PHY UC encountered\n");
4880	goto fail;
4881	}
4882
4883	if (!rtl8152_is_fw_phy_union_ok(tp, phy: (struct fw_phy_union *)block)) {
4884	dev_err(&tp->intf->dev, "check PHY_UNION_UC failed\n");
4885	goto fail;
4886	}
4887	__set_bit(FW_FLAGS_UC, &fw_flags);
4888	break;
4889	case RTL_FW_PHY_UNION_MISC:
4890	if (!rtl8152_is_fw_phy_union_ok(tp, phy: (struct fw_phy_union *)block)) {
4891	dev_err(&tp->intf->dev, "check RTL_FW_PHY_UNION_MISC failed\n");
4892	goto fail;
4893	}
4894	break;
4895	case RTL_FW_PHY_FIXUP:
4896	if (!rtl8152_is_fw_phy_fixup_ok(tp, fix: (struct fw_phy_fixup *)block)) {
4897	dev_err(&tp->intf->dev, "check PHY fixup failed\n");
4898	goto fail;
4899	}
4900	break;
4901	case RTL_FW_PHY_SPEED_UP:
4902	if (test_bit(FW_FLAGS_SPEED_UP, &fw_flags)) {
4903	dev_err(&tp->intf->dev, "multiple PHY firmware encountered");
4904	goto fail;
4905	}
4906
4907	if (!rtl8152_is_fw_phy_speed_up_ok(tp, phy: (struct fw_phy_speed_up *)block)) {
4908	dev_err(&tp->intf->dev, "check PHY speed up failed\n");
4909	goto fail;
4910	}
4911	__set_bit(FW_FLAGS_SPEED_UP, &fw_flags);
4912	break;
4913	case RTL_FW_PHY_VER:
4914	if (test_bit(FW_FLAGS_START, &fw_flags) ||
4915	test_bit(FW_FLAGS_NC, &fw_flags) ||
4916	test_bit(FW_FLAGS_NC1, &fw_flags) ||
4917	test_bit(FW_FLAGS_NC2, &fw_flags) ||
4918	test_bit(FW_FLAGS_UC2, &fw_flags) ||
4919	test_bit(FW_FLAGS_UC, &fw_flags) ||
4920	test_bit(FW_FLAGS_STOP, &fw_flags)) {
4921	dev_err(&tp->intf->dev, "Invalid order to set PHY version\n");
4922	goto fail;
4923	}
4924
4925	if (test_bit(FW_FLAGS_VER, &fw_flags)) {
4926	dev_err(&tp->intf->dev, "multiple PHY version encountered");
4927	goto fail;
4928	}
4929
4930	if (!rtl8152_is_fw_phy_ver_ok(tp, ver: (struct fw_phy_ver *)block)) {
4931	dev_err(&tp->intf->dev, "check PHY version failed\n");
4932	goto fail;
4933	}
4934	__set_bit(FW_FLAGS_VER, &fw_flags);
4935	break;
4936	default:
4937	dev_warn(&tp->intf->dev, "Unknown type %u is found\n",
4938	type);
4939	break;
4940	}
4941
4942	/* next block */
4943	i += ALIGN(__le32_to_cpu(block->length), 8);
4944	}
4945
4946	fw_end:
4947	if (test_bit(FW_FLAGS_START, &fw_flags) && !test_bit(FW_FLAGS_STOP, &fw_flags)) {
4948	dev_err(&tp->intf->dev, "without PHY_STOP\n");
4949	goto fail;
4950	}
4951
4952	return 0;
4953	fail:
4954	return ret;
4955	}
4956
4957	static void rtl_ram_code_speed_up(struct r8152 *tp, struct fw_phy_speed_up *phy, bool wait)
4958	{
4959	u32 len;
4960	u8 *data;
4961
4962	rtl_reset_ocp_base(tp);
4963
4964	if (sram_read(tp, SRAM_GPHY_FW_VER) >= __le16_to_cpu(phy->version)) {
4965	dev_dbg(&tp->intf->dev, "PHY firmware has been the newest\n");
4966	return;
4967	}
4968
4969	len = __le32_to_cpu(phy->blk_hdr.length);
4970	len -= __le16_to_cpu(phy->fw_offset);
4971	data = (u8 *)phy + __le16_to_cpu(phy->fw_offset);
4972
4973	if (rtl_phy_patch_request(tp, request: true, wait))
4974	return;
4975
4976	while (len) {
4977	u32 ocp_data, size;
4978	int i;
4979
4980	if (len < 2048)
4981	size = len;
4982	else
4983	size = 2048;
4984
4985	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL);
4986	ocp_data |= GPHY_PATCH_DONE | BACKUP_RESTRORE;
4987	ocp_write_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL, data: ocp_data);
4988
4989	generic_ocp_write(tp, __le16_to_cpu(phy->fw_reg), byteen: 0xff, size, data, MCU_TYPE_USB);
4990
4991	data += size;
4992	len -= size;
4993
4994	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL);
4995	ocp_data |= POL_GPHY_PATCH;
4996	ocp_write_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL, data: ocp_data);
4997
4998	for (i = 0; i < 1000; i++) {
4999	if (!(ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL) & POL_GPHY_PATCH))
5000	break;
5001	}
5002
5003	if (i == 1000) {
5004	dev_err(&tp->intf->dev, "ram code speedup mode timeout\n");
5005	break;
5006	}
5007	}
5008
5009	rtl_reset_ocp_base(tp);
5010
5011	rtl_phy_patch_request(tp, request: false, wait);
5012
5013	if (sram_read(tp, SRAM_GPHY_FW_VER) == __le16_to_cpu(phy->version))
5014	dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info);
5015	else
5016	dev_err(&tp->intf->dev, "ram code speedup mode fail\n");
5017	}
5018
5019	static int rtl8152_fw_phy_ver(struct r8152 *tp, struct fw_phy_ver *phy_ver)
5020	{
5021	u16 ver_addr, ver;
5022
5023	ver_addr = __le16_to_cpu(phy_ver->ver.addr);
5024	ver = __le16_to_cpu(phy_ver->ver.data);
5025
5026	rtl_reset_ocp_base(tp);
5027
5028	if (sram_read(tp, addr: ver_addr) >= ver) {
5029	dev_dbg(&tp->intf->dev, "PHY firmware has been the newest\n");
5030	return 0;
5031	}
5032
5033	sram_write(tp, addr: ver_addr, data: ver);
5034
5035	dev_dbg(&tp->intf->dev, "PHY firmware version %x\n", ver);
5036
5037	return ver;
5038	}
5039
5040	static void rtl8152_fw_phy_fixup(struct r8152 *tp, struct fw_phy_fixup *fix)
5041	{
5042	u16 addr, data;
5043
5044	rtl_reset_ocp_base(tp);
5045
5046	addr = __le16_to_cpu(fix->setting.addr);
5047	data = ocp_reg_read(tp, addr);
5048
5049	switch (__le16_to_cpu(fix->bit_cmd)) {
5050	case FW_FIXUP_AND:
5051	data &= __le16_to_cpu(fix->setting.data);
5052	break;
5053	case FW_FIXUP_OR:
5054	data |= __le16_to_cpu(fix->setting.data);
5055	break;
5056	case FW_FIXUP_NOT:
5057	data &= ~__le16_to_cpu(fix->setting.data);
5058	break;
5059	case FW_FIXUP_XOR:
5060	data ^= __le16_to_cpu(fix->setting.data);
5061	break;
5062	default:
5063	return;
5064	}
5065
5066	ocp_reg_write(tp, addr, data);
5067
5068	dev_dbg(&tp->intf->dev, "applied ocp %x %x\n", addr, data);
5069	}
5070
5071	static void rtl8152_fw_phy_union_apply(struct r8152 *tp, struct fw_phy_union *phy)
5072	{
5073	__le16 *data;
5074	u32 length;
5075	int i, num;
5076
5077	rtl_reset_ocp_base(tp);
5078
5079	num = phy->pre_num;
5080	for (i = 0; i < num; i++)
5081	sram_write(tp, __le16_to_cpu(phy->pre_set[i].addr),
5082	__le16_to_cpu(phy->pre_set[i].data));
5083
5084	length = __le32_to_cpu(phy->blk_hdr.length);
5085	length -= __le16_to_cpu(phy->fw_offset);
5086	num = length / 2;
5087	data = (__le16 *)((u8 *)phy + __le16_to_cpu(phy->fw_offset));
5088
5089	ocp_reg_write(tp, OCP_SRAM_ADDR, __le16_to_cpu(phy->fw_reg));
5090	for (i = 0; i < num; i++)
5091	ocp_reg_write(tp, OCP_SRAM_DATA, __le16_to_cpu(data[i]));
5092
5093	num = phy->bp_num;
5094	for (i = 0; i < num; i++)
5095	sram_write(tp, __le16_to_cpu(phy->bp[i].addr), __le16_to_cpu(phy->bp[i].data));
5096
5097	if (phy->bp_num && phy->bp_en.addr)
5098	sram_write(tp, __le16_to_cpu(phy->bp_en.addr), __le16_to_cpu(phy->bp_en.data));
5099
5100	dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info);
5101	}
5102
5103	static void rtl8152_fw_phy_nc_apply(struct r8152 *tp, struct fw_phy_nc *phy)
5104	{
5105	u16 mode_reg, bp_index;
5106	u32 length, i, num;
5107	__le16 *data;
5108
5109	rtl_reset_ocp_base(tp);
5110
5111	mode_reg = __le16_to_cpu(phy->mode_reg);
5112	sram_write(tp, addr: mode_reg, __le16_to_cpu(phy->mode_pre));
5113	sram_write(tp, __le16_to_cpu(phy->ba_reg),
5114	__le16_to_cpu(phy->ba_data));
5115
5116	length = __le32_to_cpu(phy->blk_hdr.length);
5117	length -= __le16_to_cpu(phy->fw_offset);
5118	num = length / 2;
5119	data = (__le16 *)((u8 *)phy + __le16_to_cpu(phy->fw_offset));
5120
5121	ocp_reg_write(tp, OCP_SRAM_ADDR, __le16_to_cpu(phy->fw_reg));
5122	for (i = 0; i < num; i++)
5123	ocp_reg_write(tp, OCP_SRAM_DATA, __le16_to_cpu(data[i]));
5124
5125	sram_write(tp, __le16_to_cpu(phy->patch_en_addr),
5126	__le16_to_cpu(phy->patch_en_value));
5127
5128	bp_index = __le16_to_cpu(phy->bp_start);
5129	num = __le16_to_cpu(phy->bp_num);
5130	for (i = 0; i < num; i++) {
5131	sram_write(tp, addr: bp_index, __le16_to_cpu(phy->bp[i]));
5132	bp_index += 2;
5133	}
5134
5135	sram_write(tp, addr: mode_reg, __le16_to_cpu(phy->mode_post));
5136
5137	dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info);
5138	}
5139
5140	static void rtl8152_fw_mac_apply(struct r8152 *tp, struct fw_mac *mac)
5141	{
5142	u16 bp_en_addr, type, fw_ver_reg;
5143	u32 length;
5144	u8 *data;
5145
5146	switch (__le32_to_cpu(mac->blk_hdr.type)) {
5147	case RTL_FW_PLA:
5148	type = MCU_TYPE_PLA;
5149	break;
5150	case RTL_FW_USB:
5151	type = MCU_TYPE_USB;
5152	break;
5153	default:
5154	return;
5155	}
5156
5157	fw_ver_reg = __le16_to_cpu(mac->fw_ver_reg);
5158	if (fw_ver_reg && ocp_read_byte(tp, MCU_TYPE_USB, index: fw_ver_reg) >= mac->fw_ver_data) {
5159	dev_dbg(&tp->intf->dev, "%s firmware has been the newest\n", type ? "PLA" : "USB");
5160	return;
5161	}
5162
5163	rtl_clear_bp(tp, type);
5164
5165	/* Enable backup/restore of MACDBG. This is required after clearing PLA
5166	* break points and before applying the PLA firmware.
5167	*/
5168	if (tp->version == RTL_VER_04 && type == MCU_TYPE_PLA &&
5169	!(ocp_read_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST) & DEBUG_OE)) {
5170	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_PRE, DEBUG_LTSSM);
5171	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST, DEBUG_LTSSM);
5172	}
5173
5174	length = __le32_to_cpu(mac->blk_hdr.length);
5175	length -= __le16_to_cpu(mac->fw_offset);
5176
5177	data = (u8 *)mac;
5178	data += __le16_to_cpu(mac->fw_offset);
5179
5180	generic_ocp_write(tp, __le16_to_cpu(mac->fw_reg), byteen: 0xff, size: length, data,
5181	type);
5182
5183	ocp_write_word(tp, type, __le16_to_cpu(mac->bp_ba_addr),
5184	__le16_to_cpu(mac->bp_ba_value));
5185
5186	generic_ocp_write(tp, __le16_to_cpu(mac->bp_start), BYTE_EN_DWORD,
5187	__le16_to_cpu(mac->bp_num) << 1, data: mac->bp, type);
5188
5189	bp_en_addr = __le16_to_cpu(mac->bp_en_addr);
5190	if (bp_en_addr)
5191	ocp_write_word(tp, type, index: bp_en_addr,
5192	__le16_to_cpu(mac->bp_en_value));
5193
5194	if (fw_ver_reg)
5195	ocp_write_byte(tp, MCU_TYPE_USB, index: fw_ver_reg,
5196	data: mac->fw_ver_data);
5197
5198	dev_dbg(&tp->intf->dev, "successfully applied %s\n", mac->info);
5199	}
5200
5201	static void rtl8152_apply_firmware(struct r8152 *tp, bool power_cut)
5202	{
5203	struct rtl_fw *rtl_fw = &tp->rtl_fw;
5204	const struct firmware *fw;
5205	struct fw_header *fw_hdr;
5206	struct fw_phy_patch_key *key;
5207	u16 key_addr = 0;
5208	int i, patch_phy = 1;
5209
5210	if (IS_ERR_OR_NULL(ptr: rtl_fw->fw))
5211	return;
5212
5213	fw = rtl_fw->fw;
5214	fw_hdr = (struct fw_header *)fw->data;
5215
5216	if (rtl_fw->pre_fw)
5217	rtl_fw->pre_fw(tp);
5218
5219	for (i = offsetof(struct fw_header, blocks); i < fw->size;) {
5220	struct fw_block *block = (struct fw_block *)&fw->data[i];
5221
5222	switch (__le32_to_cpu(block->type)) {
5223	case RTL_FW_END:
5224	goto post_fw;
5225	case RTL_FW_PLA:
5226	case RTL_FW_USB:
5227	rtl8152_fw_mac_apply(tp, mac: (struct fw_mac *)block);
5228	break;
5229	case RTL_FW_PHY_START:
5230	if (!patch_phy)
5231	break;
5232	key = (struct fw_phy_patch_key *)block;
5233	key_addr = __le16_to_cpu(key->key_reg);
5234	rtl_pre_ram_code(tp, key_addr, __le16_to_cpu(key->key_data), wait: !power_cut);
5235	break;
5236	case RTL_FW_PHY_STOP:
5237	if (!patch_phy)
5238	break;
5239	WARN_ON(!key_addr);
5240	rtl_post_ram_code(tp, key_addr, wait: !power_cut);
5241	break;
5242	case RTL_FW_PHY_NC:
5243	rtl8152_fw_phy_nc_apply(tp, phy: (struct fw_phy_nc *)block);
5244	break;
5245	case RTL_FW_PHY_VER:
5246	patch_phy = rtl8152_fw_phy_ver(tp, phy_ver: (struct fw_phy_ver *)block);
5247	break;
5248	case RTL_FW_PHY_UNION_NC:
5249	case RTL_FW_PHY_UNION_NC1:
5250	case RTL_FW_PHY_UNION_NC2:
5251	case RTL_FW_PHY_UNION_UC2:
5252	case RTL_FW_PHY_UNION_UC:
5253	case RTL_FW_PHY_UNION_MISC:
5254	if (patch_phy)
5255	rtl8152_fw_phy_union_apply(tp, phy: (struct fw_phy_union *)block);
5256	break;
5257	case RTL_FW_PHY_FIXUP:
5258	if (patch_phy)
5259	rtl8152_fw_phy_fixup(tp, fix: (struct fw_phy_fixup *)block);
5260	break;
5261	case RTL_FW_PHY_SPEED_UP:
5262	rtl_ram_code_speed_up(tp, phy: (struct fw_phy_speed_up *)block, wait: !power_cut);
5263	break;
5264	default:
5265	break;
5266	}
5267
5268	i += ALIGN(__le32_to_cpu(block->length), 8);
5269	}
5270
5271	post_fw:
5272	if (rtl_fw->post_fw)
5273	rtl_fw->post_fw(tp);
5274
5275	rtl_reset_ocp_base(tp);
5276	strscpy(rtl_fw->version, fw_hdr->version, RTL_VER_SIZE);
5277	dev_info(&tp->intf->dev, "load %s successfully\n", rtl_fw->version);
5278	}
5279
5280	static void rtl8152_release_firmware(struct r8152 *tp)
5281	{
5282	struct rtl_fw *rtl_fw = &tp->rtl_fw;
5283
5284	if (!IS_ERR_OR_NULL(ptr: rtl_fw->fw)) {
5285	release_firmware(fw: rtl_fw->fw);
5286	rtl_fw->fw = NULL;
5287	}
5288	}
5289
5290	static int rtl8152_request_firmware(struct r8152 *tp)
5291	{
5292	struct rtl_fw *rtl_fw = &tp->rtl_fw;
5293	long rc;
5294
5295	if (rtl_fw->fw || !rtl_fw->fw_name) {
5296	dev_info(&tp->intf->dev, "skip request firmware\n");
5297	rc = 0;
5298	goto result;
5299	}
5300
5301	rc = request_firmware(fw: &rtl_fw->fw, name: rtl_fw->fw_name, device: &tp->intf->dev);
5302	if (rc < 0)
5303	goto result;
5304
5305	rc = rtl8152_check_firmware(tp, rtl_fw);
5306	if (rc < 0)
5307	release_firmware(fw: rtl_fw->fw);
5308
5309	result:
5310	if (rc) {
5311	rtl_fw->fw = ERR_PTR(error: rc);
5312
5313	dev_warn(&tp->intf->dev,
5314	"unable to load firmware patch %s (%ld)\n",
5315	rtl_fw->fw_name, rc);
5316	}
5317
5318	return rc;
5319	}
5320
5321	static void r8152_aldps_en(struct r8152 *tp, bool enable)
5322	{
5323	if (enable) {
5324	ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
5325	LINKENA | DIS_SDSAVE);
5326	} else {
5327	ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA |
5328	DIS_SDSAVE);
5329	msleep(msecs: 20);
5330	}
5331	}
5332
5333	static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
5334	{
5335	ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
5336	ocp_reg_write(tp, OCP_EEE_DATA, data: reg);
5337	ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
5338	}
5339
5340	static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
5341	{
5342	u16 data;
5343
5344	r8152_mmd_indirect(tp, dev, reg);
5345	data = ocp_reg_read(tp, OCP_EEE_DATA);
5346	ocp_reg_write(tp, OCP_EEE_AR, data: 0x0000);
5347
5348	return data;
5349	}
5350
5351	static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
5352	{
5353	r8152_mmd_indirect(tp, dev, reg);
5354	ocp_reg_write(tp, OCP_EEE_DATA, data);
5355	ocp_reg_write(tp, OCP_EEE_AR, data: 0x0000);
5356	}
5357
5358	static void r8152_eee_en(struct r8152 *tp, bool enable)
5359	{
5360	u16 config1, config2, config3;
5361	u32 ocp_data;
5362
5363	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
5364	config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
5365	config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
5366	config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
5367
5368	if (enable) {
5369	ocp_data |= EEE_RX_EN | EEE_TX_EN;
5370	config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
5371	config1 |= sd_rise_time(1);
5372	config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
5373	config3 |= fast_snr(42);
5374	} else {
5375	ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
5376	config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
5377	RX_QUIET_EN);
5378	config1 |= sd_rise_time(7);
5379	config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
5380	config3 |= fast_snr(511);
5381	}
5382
5383	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, data: ocp_data);
5384	ocp_reg_write(tp, OCP_EEE_CONFIG1, data: config1);
5385	ocp_reg_write(tp, OCP_EEE_CONFIG2, data: config2);
5386	ocp_reg_write(tp, OCP_EEE_CONFIG3, data: config3);
5387	}
5388
5389	static void r8153_eee_en(struct r8152 *tp, bool enable)
5390	{
5391	u32 ocp_data;
5392	u16 config;
5393
5394	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
5395	config = ocp_reg_read(tp, OCP_EEE_CFG);
5396
5397	if (enable) {
5398	ocp_data |= EEE_RX_EN | EEE_TX_EN;
5399	config |= EEE10_EN;
5400	} else {
5401	ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
5402	config &= ~EEE10_EN;
5403	}
5404
5405	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, data: ocp_data);
5406	ocp_reg_write(tp, OCP_EEE_CFG, data: config);
5407
5408	tp->ups_info.eee = enable;
5409	}
5410
5411	static void r8156_eee_en(struct r8152 *tp, bool enable)
5412	{
5413	u16 config;
5414
5415	r8153_eee_en(tp, enable);
5416
5417	config = ocp_reg_read(tp, OCP_EEE_ADV2);
5418
5419	if (enable)
5420	config |= MDIO_EEE_2_5GT;
5421	else
5422	config &= ~MDIO_EEE_2_5GT;
5423
5424	ocp_reg_write(tp, OCP_EEE_ADV2, data: config);
5425	}
5426
5427	static void rtl_eee_enable(struct r8152 *tp, bool enable)
5428	{
5429	switch (tp->version) {
5430	case RTL_VER_01:
5431	case RTL_VER_02:
5432	case RTL_VER_07:
5433	if (enable) {
5434	r8152_eee_en(tp, enable: true);
5435	r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV,
5436	data: tp->eee_adv);
5437	} else {
5438	r8152_eee_en(tp, enable: false);
5439	r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, data: 0);
5440	}
5441	break;
5442	case RTL_VER_03:
5443	case RTL_VER_04:
5444	case RTL_VER_05:
5445	case RTL_VER_06:
5446	case RTL_VER_08:
5447	case RTL_VER_09:
5448	case RTL_VER_14:
5449	if (enable) {
5450	r8153_eee_en(tp, enable: true);
5451	ocp_reg_write(tp, OCP_EEE_ADV, data: tp->eee_adv);
5452	} else {
5453	r8153_eee_en(tp, enable: false);
5454	ocp_reg_write(tp, OCP_EEE_ADV, data: 0);
5455	}
5456	break;
5457	case RTL_VER_10:
5458	case RTL_VER_11:
5459	case RTL_VER_12:
5460	case RTL_VER_13:
5461	case RTL_VER_15:
5462	if (enable) {
5463	r8156_eee_en(tp, enable: true);
5464	ocp_reg_write(tp, OCP_EEE_ADV, data: tp->eee_adv);
5465	} else {
5466	r8156_eee_en(tp, enable: false);
5467	ocp_reg_write(tp, OCP_EEE_ADV, data: 0);
5468	}
5469	break;
5470	default:
5471	break;
5472	}
5473	}
5474
5475	static void r8152b_enable_fc(struct r8152 *tp)
5476	{
5477	u16 anar;
5478
5479	anar = r8152_mdio_read(tp, MII_ADVERTISE);
5480	anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
5481	r8152_mdio_write(tp, MII_ADVERTISE, value: anar);
5482
5483	tp->ups_info.flow_control = true;
5484	}
5485
5486	static void rtl8152_disable(struct r8152 *tp)
5487	{
5488	r8152_aldps_en(tp, enable: false);
5489	rtl_disable(tp);
5490	r8152_aldps_en(tp, enable: true);
5491	}
5492
5493	static void r8152b_hw_phy_cfg(struct r8152 *tp)
5494	{
5495	rtl8152_apply_firmware(tp, power_cut: false);
5496	rtl_eee_enable(tp, enable: tp->eee_en);
5497	r8152_aldps_en(tp, enable: true);
5498	r8152b_enable_fc(tp);
5499
5500	set_bit(nr: PHY_RESET, addr: &tp->flags);
5501	}
5502
5503	static void wait_oob_link_list_ready(struct r8152 *tp)
5504	{
5505	u32 ocp_data;
5506	int i;
5507
5508	for (i = 0; i < 1000; i++) {
5509	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
5510	break;
5511	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5512	if (ocp_data & LINK_LIST_READY)
5513	break;
5514	usleep_range(min: 1000, max: 2000);
5515	}
5516	}
5517
5518	static void r8156b_wait_loading_flash(struct r8152 *tp)
5519	{
5520	if ((ocp_read_word(tp, MCU_TYPE_PLA, PLA_GPHY_CTRL) & GPHY_FLASH) &&
5521	!(ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL) & BYPASS_FLASH)) {
5522	int i;
5523
5524	for (i = 0; i < 100; i++) {
5525	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
5526	break;
5527	if (ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL) & GPHY_PATCH_DONE)
5528	break;
5529	usleep_range(min: 1000, max: 2000);
5530	}
5531	}
5532	}
5533
5534	static void r8152b_exit_oob(struct r8152 *tp)
5535	{
5536	u32 ocp_data;
5537
5538	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
5539	ocp_data &= ~RCR_ACPT_ALL;
5540	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, data: ocp_data);
5541
5542	rxdy_gated_en(tp, enable: true);
5543	r8153_teredo_off(tp);
5544	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
5545	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, data: 0x00);
5546
5547	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5548	ocp_data &= ~NOW_IS_OOB;
5549	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, data: ocp_data);
5550
5551	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5552	ocp_data &= ~MCU_BORW_EN;
5553	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, data: ocp_data);
5554
5555	wait_oob_link_list_ready(tp);
5556
5557	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5558	ocp_data |= RE_INIT_LL;
5559	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, data: ocp_data);
5560
5561	wait_oob_link_list_ready(tp);
5562
5563	rtl8152_nic_reset(tp);
5564
5565	/* rx share fifo credit full threshold */
5566	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
5567
5568	if (tp->udev->speed == USB_SPEED_FULL ||
5569	tp->udev->speed == USB_SPEED_LOW) {
5570	/* rx share fifo credit near full threshold */
5571	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
5572	RXFIFO_THR2_FULL);
5573	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
5574	RXFIFO_THR3_FULL);
5575	} else {
5576	/* rx share fifo credit near full threshold */
5577	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
5578	RXFIFO_THR2_HIGH);
5579	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
5580	RXFIFO_THR3_HIGH);
5581	}
5582
5583	/* TX share fifo free credit full threshold */
5584	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
5585
5586	ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
5587	ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
5588	ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
5589	TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
5590
5591	rtl_rx_vlan_en(tp, enable: tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
5592
5593	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
5594
5595	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
5596	ocp_data |= TCR0_AUTO_FIFO;
5597	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, data: ocp_data);
5598	}
5599
5600	static void r8152b_enter_oob(struct r8152 *tp)
5601	{
5602	u32 ocp_data;
5603
5604	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5605	ocp_data &= ~NOW_IS_OOB;
5606	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, data: ocp_data);
5607
5608	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
5609	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
5610	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
5611
5612	rtl_disable(tp);
5613
5614	wait_oob_link_list_ready(tp);
5615
5616	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5617	ocp_data |= RE_INIT_LL;
5618	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, data: ocp_data);
5619
5620	wait_oob_link_list_ready(tp);
5621
5622	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
5623
5624	rtl_rx_vlan_en(tp, enable: true);
5625
5626	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
5627	ocp_data |= ALDPS_PROXY_MODE;
5628	ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, data: ocp_data);
5629
5630	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5631	ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
5632	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, data: ocp_data);
5633
5634	rxdy_gated_en(tp, enable: false);
5635
5636	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
5637	ocp_data |= RCR_APM | RCR_AM | RCR_AB;
5638	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, data: ocp_data);
5639	}
5640
5641	static int r8153_pre_firmware_1(struct r8152 *tp)
5642	{
5643	int i;
5644
5645	/* Wait till the WTD timer is ready. It would take at most 104 ms. */
5646	for (i = 0; i < 104; i++) {
5647	u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_WDT1_CTRL);
5648
5649	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
5650	return -ENODEV;
5651	if (!(ocp_data & WTD1_EN))
5652	break;
5653	usleep_range(min: 1000, max: 2000);
5654	}
5655
5656	return 0;
5657	}
5658
5659	static int r8153_post_firmware_1(struct r8152 *tp)
5660	{
5661	/* set USB_BP_4 to support USB_SPEED_SUPER only */
5662	if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER)
5663	ocp_write_word(tp, MCU_TYPE_USB, USB_BP_4, BP4_SUPER_ONLY);
5664
5665	/* reset UPHY timer to 36 ms */
5666	ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, data: 36000 / 16);
5667
5668	return 0;
5669	}
5670
5671	static int r8153_pre_firmware_2(struct r8152 *tp)
5672	{
5673	u32 ocp_data;
5674
5675	r8153_pre_firmware_1(tp);
5676
5677	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0);
5678	ocp_data &= ~FW_FIX_SUSPEND;
5679	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, data: ocp_data);
5680
5681	return 0;
5682	}
5683
5684	static int r8153_post_firmware_2(struct r8152 *tp)
5685	{
5686	u32 ocp_data;
5687
5688	/* enable bp0 if support USB_SPEED_SUPER only */
5689	if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER) {
5690	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN);
5691	ocp_data |= BIT(0);
5692	ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, data: ocp_data);
5693	}
5694
5695	/* reset UPHY timer to 36 ms */
5696	ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, data: 36000 / 16);
5697
5698	/* enable U3P3 check, set the counter to 4 */
5699	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, U3P3_CHECK_EN | 4);
5700
5701	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0);
5702	ocp_data |= FW_FIX_SUSPEND;
5703	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, data: ocp_data);
5704
5705	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
5706	ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
5707	ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, data: ocp_data);
5708
5709	return 0;
5710	}
5711
5712	static int r8153_post_firmware_3(struct r8152 *tp)
5713	{
5714	u32 ocp_data;
5715
5716	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
5717	ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
5718	ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, data: ocp_data);
5719
5720	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
5721	ocp_data |= FW_IP_RESET_EN;
5722	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, data: ocp_data);
5723
5724	return 0;
5725	}
5726
5727	static int r8153b_pre_firmware_1(struct r8152 *tp)
5728	{
5729	/* enable fc timer and set timer to 1 second. */
5730	ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER,
5731	CTRL_TIMER_EN | (1000 / 8));
5732
5733	return 0;
5734	}
5735
5736	static int r8153b_post_firmware_1(struct r8152 *tp)
5737	{
5738	u32 ocp_data;
5739
5740	/* enable bp0 for RTL8153-BND */
5741	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
5742	if (ocp_data & BND_MASK) {
5743	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN);
5744	ocp_data |= BIT(0);
5745	ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, data: ocp_data);
5746	}
5747
5748	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
5749	ocp_data |= FLOW_CTRL_PATCH_OPT;
5750	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, data: ocp_data);
5751
5752	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
5753	ocp_data |= FC_PATCH_TASK;
5754	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, data: ocp_data);
5755
5756	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
5757	ocp_data |= FW_IP_RESET_EN;
5758	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, data: ocp_data);
5759
5760	return 0;
5761	}
5762
5763	static int r8153c_post_firmware_1(struct r8152 *tp)
5764	{
5765	u32 ocp_data;
5766
5767	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
5768	ocp_data |= FLOW_CTRL_PATCH_2;
5769	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, data: ocp_data);
5770
5771	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
5772	ocp_data |= FC_PATCH_TASK;
5773	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, data: ocp_data);
5774
5775	return 0;
5776	}
5777
5778	static int r8156a_post_firmware_1(struct r8152 *tp)
5779	{
5780	u32 ocp_data;
5781
5782	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
5783	ocp_data |= FW_IP_RESET_EN;
5784	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, data: ocp_data);
5785
5786	/* Modify U3PHY parameter for compatibility issue */
5787	ocp_write_dword(tp, MCU_TYPE_USB, USB_UPHY3_MDCMDIO, data: 0x4026840e);
5788	ocp_write_dword(tp, MCU_TYPE_USB, USB_UPHY3_MDCMDIO, data: 0x4001acc9);
5789
5790	return 0;
5791	}
5792
5793	static void r8153_aldps_en(struct r8152 *tp, bool enable)
5794	{
5795	u16 data;
5796
5797	data = ocp_reg_read(tp, OCP_POWER_CFG);
5798	if (enable) {
5799	data |= EN_ALDPS;
5800	ocp_reg_write(tp, OCP_POWER_CFG, data);
5801	} else {
5802	int i;
5803
5804	data &= ~EN_ALDPS;
5805	ocp_reg_write(tp, OCP_POWER_CFG, data);
5806	for (i = 0; i < 20; i++) {
5807	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
5808	return;
5809	usleep_range(min: 1000, max: 2000);
5810	if (ocp_read_word(tp, MCU_TYPE_PLA, index: 0xe000) & 0x0100)
5811	break;
5812	}
5813	}
5814
5815	tp->ups_info.aldps = enable;
5816	}
5817
5818	static void r8153_hw_phy_cfg(struct r8152 *tp)
5819	{
5820	u32 ocp_data;
5821	u16 data;
5822
5823	/* disable ALDPS before updating the PHY parameters */
5824	r8153_aldps_en(tp, enable: false);
5825
5826	/* disable EEE before updating the PHY parameters */
5827	rtl_eee_enable(tp, enable: false);
5828
5829	rtl8152_apply_firmware(tp, power_cut: false);
5830
5831	if (tp->version == RTL_VER_03) {
5832	data = ocp_reg_read(tp, OCP_EEE_CFG);
5833	data &= ~CTAP_SHORT_EN;
5834	ocp_reg_write(tp, OCP_EEE_CFG, data);
5835	}
5836
5837	data = ocp_reg_read(tp, OCP_POWER_CFG);
5838	data |= EEE_CLKDIV_EN;
5839	ocp_reg_write(tp, OCP_POWER_CFG, data);
5840
5841	data = ocp_reg_read(tp, OCP_DOWN_SPEED);
5842	data |= EN_10M_BGOFF;
5843	ocp_reg_write(tp, OCP_DOWN_SPEED, data);
5844	data = ocp_reg_read(tp, OCP_POWER_CFG);
5845	data |= EN_10M_PLLOFF;
5846	ocp_reg_write(tp, OCP_POWER_CFG, data);
5847	sram_write(tp, SRAM_IMPEDANCE, data: 0x0b13);
5848
5849	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
5850	ocp_data |= PFM_PWM_SWITCH;
5851	ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, data: ocp_data);
5852
5853	/* Enable LPF corner auto tune */
5854	sram_write(tp, SRAM_LPF_CFG, data: 0xf70f);
5855
5856	/* Adjust 10M Amplitude */
5857	sram_write(tp, SRAM_10M_AMP1, data: 0x00af);
5858	sram_write(tp, SRAM_10M_AMP2, data: 0x0208);
5859
5860	if (tp->eee_en)
5861	rtl_eee_enable(tp, enable: true);
5862
5863	r8153_aldps_en(tp, enable: true);
5864	r8152b_enable_fc(tp);
5865
5866	switch (tp->version) {
5867	case RTL_VER_03:
5868	case RTL_VER_04:
5869	break;
5870	case RTL_VER_05:
5871	case RTL_VER_06:
5872	default:
5873	r8153_u2p3en(tp, enable: true);
5874	break;
5875	}
5876
5877	set_bit(nr: PHY_RESET, addr: &tp->flags);
5878	}
5879
5880	static u32 r8152_efuse_read(struct r8152 *tp, u8 addr)
5881	{
5882	u32 ocp_data;
5883
5884	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr);
5885	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD);
5886	ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9; /* data of bit16 */
5887	ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA);
5888
5889	return ocp_data;
5890	}
5891
5892	static void r8153b_hw_phy_cfg(struct r8152 *tp)
5893	{
5894	u32 ocp_data;
5895	u16 data;
5896
5897	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
5898	if (ocp_data & PCUT_STATUS) {
5899	ocp_data &= ~PCUT_STATUS;
5900	ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, data: ocp_data);
5901	}
5902
5903	/* disable ALDPS before updating the PHY parameters */
5904	r8153_aldps_en(tp, enable: false);
5905
5906	/* disable EEE before updating the PHY parameters */
5907	rtl_eee_enable(tp, enable: false);
5908
5909	/* U1/U2/L1 idle timer. 500 us */
5910	ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, data: 500);
5911
5912	data = r8153_phy_status(tp, desired: 0);
5913
5914	switch (data) {
5915	case PHY_STAT_PWRDN:
5916	case PHY_STAT_EXT_INIT:
5917	rtl8152_apply_firmware(tp, power_cut: true);
5918
5919	data = r8152_mdio_read(tp, MII_BMCR);
5920	data &= ~BMCR_PDOWN;
5921	r8152_mdio_write(tp, MII_BMCR, value: data);
5922	break;
5923	case PHY_STAT_LAN_ON:
5924	default:
5925	rtl8152_apply_firmware(tp, power_cut: false);
5926	break;
5927	}
5928
5929	r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
5930
5931	data = sram_read(tp, SRAM_GREEN_CFG);
5932	data |= R_TUNE_EN;
5933	sram_write(tp, SRAM_GREEN_CFG, data);
5934	data = ocp_reg_read(tp, OCP_NCTL_CFG);
5935	data |= PGA_RETURN_EN;
5936	ocp_reg_write(tp, OCP_NCTL_CFG, data);
5937
5938	/* ADC Bias Calibration:
5939	* read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake
5940	* bit (bit3) to rebuild the real 16-bit data. Write the data to the
5941	* ADC ioffset.
5942	*/
5943	ocp_data = r8152_efuse_read(tp, addr: 0x7d);
5944	data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7));
5945	if (data != 0xffff)
5946	ocp_reg_write(tp, OCP_ADC_IOFFSET, data);
5947
5948	/* ups mode tx-link-pulse timing adjustment:
5949	* rg_saw_cnt = OCP reg 0xC426 Bit[13:0]
5950	* swr_cnt_1ms_ini = 16000000 / rg_saw_cnt
5951	*/
5952	ocp_data = ocp_reg_read(tp, addr: 0xc426);
5953	ocp_data &= 0x3fff;
5954	if (ocp_data) {
5955	u32 swr_cnt_1ms_ini;
5956
5957	swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK;
5958	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG);
5959	ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini;
5960	ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, data: ocp_data);
5961	}
5962
5963	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
5964	ocp_data |= PFM_PWM_SWITCH;
5965	ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, data: ocp_data);
5966
5967	/* Advnace EEE */
5968	if (!rtl_phy_patch_request(tp, request: true, wait: true)) {
5969	data = ocp_reg_read(tp, OCP_POWER_CFG);
5970	data |= EEE_CLKDIV_EN;
5971	ocp_reg_write(tp, OCP_POWER_CFG, data);
5972	tp->ups_info.eee_ckdiv = true;
5973
5974	data = ocp_reg_read(tp, OCP_DOWN_SPEED);
5975	data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV;
5976	ocp_reg_write(tp, OCP_DOWN_SPEED, data);
5977	tp->ups_info.eee_cmod_lv = true;
5978	tp->ups_info._10m_ckdiv = true;
5979	tp->ups_info.eee_plloff_giga = true;
5980
5981	ocp_reg_write(tp, OCP_SYSCLK_CFG, data: 0);
5982	ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5));
5983	tp->ups_info._250m_ckdiv = true;
5984
5985	rtl_phy_patch_request(tp, request: false, wait: true);
5986	}
5987
5988	if (tp->eee_en)
5989	rtl_eee_enable(tp, enable: true);
5990
5991	r8153_aldps_en(tp, enable: true);
5992	r8152b_enable_fc(tp);
5993
5994	set_bit(nr: PHY_RESET, addr: &tp->flags);
5995	}
5996
5997	static void r8153c_hw_phy_cfg(struct r8152 *tp)
5998	{
5999	r8153b_hw_phy_cfg(tp);
6000
6001	tp->ups_info.r_tune = true;
6002	}
6003
6004	static void rtl8153_change_mtu(struct r8152 *tp)
6005	{
6006	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, mtu_to_size(tp->netdev->mtu));
6007	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
6008	}
6009
6010	static void r8153_first_init(struct r8152 *tp)
6011	{
6012	u32 ocp_data;
6013
6014	rxdy_gated_en(tp, enable: true);
6015	r8153_teredo_off(tp);
6016
6017	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
6018	ocp_data &= ~RCR_ACPT_ALL;
6019	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, data: ocp_data);
6020
6021	rtl8152_nic_reset(tp);
6022	rtl_reset_bmu(tp);
6023
6024	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6025	ocp_data &= ~NOW_IS_OOB;
6026	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, data: ocp_data);
6027
6028	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6029	ocp_data &= ~MCU_BORW_EN;
6030	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, data: ocp_data);
6031
6032	wait_oob_link_list_ready(tp);
6033
6034	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6035	ocp_data |= RE_INIT_LL;
6036	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, data: ocp_data);
6037
6038	wait_oob_link_list_ready(tp);
6039
6040	rtl_rx_vlan_en(tp, enable: tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
6041
6042	rtl8153_change_mtu(tp);
6043
6044	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
6045	ocp_data |= TCR0_AUTO_FIFO;
6046	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, data: ocp_data);
6047
6048	rtl8152_nic_reset(tp);
6049
6050	/* rx share fifo credit full threshold */
6051	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
6052	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
6053	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
6054	/* TX share fifo free credit full threshold */
6055	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
6056	}
6057
6058	static void r8153_enter_oob(struct r8152 *tp)
6059	{
6060	u32 ocp_data;
6061
6062	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6063	ocp_data &= ~NOW_IS_OOB;
6064	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, data: ocp_data);
6065
6066	/* RX FIFO settings for OOB */
6067	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
6068	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
6069	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
6070
6071	rtl_disable(tp);
6072	rtl_reset_bmu(tp);
6073
6074	wait_oob_link_list_ready(tp);
6075
6076	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6077	ocp_data |= RE_INIT_LL;
6078	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, data: ocp_data);
6079
6080	wait_oob_link_list_ready(tp);
6081
6082	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, data: 1522);
6083	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_DEFAULT);
6084
6085	switch (tp->version) {
6086	case RTL_VER_03:
6087	case RTL_VER_04:
6088	case RTL_VER_05:
6089	case RTL_VER_06:
6090	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
6091	ocp_data &= ~TEREDO_WAKE_MASK;
6092	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, data: ocp_data);
6093	break;
6094
6095	case RTL_VER_08:
6096	case RTL_VER_09:
6097	case RTL_VER_14:
6098	/* Clear teredo wake event. bit[15:8] is the teredo wakeup
6099	* type. Set it to zero. bits[7:0] are the W1C bits about
6100	* the events. Set them to all 1 to clear them.
6101	*/
6102	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, data: 0x00ff);
6103	break;
6104
6105	default:
6106	break;
6107	}
6108
6109	rtl_rx_vlan_en(tp, enable: true);
6110
6111	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
6112	ocp_data |= ALDPS_PROXY_MODE;
6113	ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, data: ocp_data);
6114
6115	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6116	ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
6117	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, data: ocp_data);
6118
6119	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6120	ocp_data |= MCU_BORW_EN;
6121	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, data: ocp_data);
6122
6123	rxdy_gated_en(tp, enable: false);
6124
6125	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
6126	ocp_data |= RCR_APM | RCR_AM | RCR_AB;
6127	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, data: ocp_data);
6128	}
6129
6130	static void rtl8153_disable(struct r8152 *tp)
6131	{
6132	r8153_aldps_en(tp, enable: false);
6133	rtl_disable(tp);
6134	rtl_reset_bmu(tp);
6135	r8153_aldps_en(tp, enable: true);
6136	}
6137
6138	static u32 fc_pause_on_auto(struct r8152 *tp)
6139	{
6140	return (ALIGN(mtu_to_size(tp->netdev->mtu), 1024) + 6 * 1024);
6141	}
6142
6143	static u32 fc_pause_off_auto(struct r8152 *tp)
6144	{
6145	return (ALIGN(mtu_to_size(tp->netdev->mtu), 1024) + 14 * 1024);
6146	}
6147
6148	static void r8156_fc_parameter(struct r8152 *tp)
6149	{
6150	u32 pause_on = tp->fc_pause_on ? tp->fc_pause_on : fc_pause_on_auto(tp);
6151	u32 pause_off = tp->fc_pause_off ? tp->fc_pause_off : fc_pause_off_auto(tp);
6152
6153	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_FULL, data: pause_on / 16);
6154	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, data: pause_off / 16);
6155	}
6156
6157	static int rtl8156_enable(struct r8152 *tp)
6158	{
6159	u32 ocp_data;
6160	u16 speed;
6161
6162	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
6163	return -ENODEV;
6164
6165	r8156_fc_parameter(tp);
6166	set_tx_qlen(tp);
6167	rtl_set_eee_plus(tp);
6168	r8153_set_rx_early_timeout(tp);
6169	r8153_set_rx_early_size(tp);
6170
6171	speed = rtl8152_get_speed(tp);
6172	rtl_set_ifg(tp, speed);
6173
6174	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
6175	if (speed & _2500bps)
6176	ocp_data &= ~IDLE_SPDWN_EN;
6177	else
6178	ocp_data |= IDLE_SPDWN_EN;
6179	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, data: ocp_data);
6180
6181	if (speed & _1000bps)
6182	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, data: 0x11);
6183	else if (speed & _500bps)
6184	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, data: 0x3d);
6185
6186	if (tp->udev->speed == USB_SPEED_HIGH) {
6187	/* USB 0xb45e[3:0] l1_nyet_hird */
6188	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_L1_CTRL);
6189	ocp_data &= ~0xf;
6190	if (is_flow_control(speed))
6191	ocp_data |= 0xf;
6192	else
6193	ocp_data |= 0x1;
6194	ocp_write_word(tp, MCU_TYPE_USB, USB_L1_CTRL, data: ocp_data);
6195	}
6196
6197	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
6198	ocp_data &= ~FC_PATCH_TASK;
6199	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, data: ocp_data);
6200	usleep_range(min: 1000, max: 2000);
6201	ocp_data |= FC_PATCH_TASK;
6202	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, data: ocp_data);
6203
6204	return rtl_enable(tp);
6205	}
6206
6207	static void rtl8156_disable(struct r8152 *tp)
6208	{
6209	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_FULL, data: 0);
6210	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, data: 0);
6211
6212	rtl8153_disable(tp);
6213	}
6214
6215	static int rtl8156b_enable(struct r8152 *tp)
6216	{
6217	u32 ocp_data;
6218	u16 speed;
6219
6220	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
6221	return -ENODEV;
6222
6223	set_tx_qlen(tp);
6224	rtl_set_eee_plus(tp);
6225
6226	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM);
6227	ocp_data &= ~RX_AGGR_NUM_MASK;
6228	ocp_write_word(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM, data: ocp_data);
6229
6230	r8153_set_rx_early_timeout(tp);
6231	r8153_set_rx_early_size(tp);
6232
6233	speed = rtl8152_get_speed(tp);
6234	rtl_set_ifg(tp, speed);
6235
6236	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
6237	if (speed & _2500bps)
6238	ocp_data &= ~IDLE_SPDWN_EN;
6239	else
6240	ocp_data |= IDLE_SPDWN_EN;
6241	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, data: ocp_data);
6242
6243	if (tp->udev->speed == USB_SPEED_HIGH) {
6244	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_L1_CTRL);
6245	ocp_data &= ~0xf;
6246	if (is_flow_control(speed))
6247	ocp_data |= 0xf;
6248	else
6249	ocp_data |= 0x1;
6250	ocp_write_word(tp, MCU_TYPE_USB, USB_L1_CTRL, data: ocp_data);
6251	}
6252
6253	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
6254	ocp_data &= ~FC_PATCH_TASK;
6255	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, data: ocp_data);
6256	usleep_range(min: 1000, max: 2000);
6257	ocp_data |= FC_PATCH_TASK;
6258	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, data: ocp_data);
6259
6260	return rtl_enable(tp);
6261	}
6262
6263	static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex,
6264	u32 advertising)
6265	{
6266	u16 bmcr;
6267	int ret = 0;
6268
6269	if (autoneg == AUTONEG_DISABLE) {
6270	if (duplex != DUPLEX_HALF && duplex != DUPLEX_FULL)
6271	return -EINVAL;
6272
6273	switch (speed) {
6274	case SPEED_10:
6275	bmcr = BMCR_SPEED10;
6276	if (duplex == DUPLEX_FULL) {
6277	bmcr |= BMCR_FULLDPLX;
6278	tp->ups_info.speed_duplex = FORCE_10M_FULL;
6279	} else {
6280	tp->ups_info.speed_duplex = FORCE_10M_HALF;
6281	}
6282	break;
6283	case SPEED_100:
6284	bmcr = BMCR_SPEED100;
6285	if (duplex == DUPLEX_FULL) {
6286	bmcr |= BMCR_FULLDPLX;
6287	tp->ups_info.speed_duplex = FORCE_100M_FULL;
6288	} else {
6289	tp->ups_info.speed_duplex = FORCE_100M_HALF;
6290	}
6291	break;
6292	case SPEED_1000:
6293	if (tp->mii.supports_gmii) {
6294	bmcr = BMCR_SPEED1000 | BMCR_FULLDPLX;
6295	tp->ups_info.speed_duplex = NWAY_1000M_FULL;
6296	break;
6297	}
6298	fallthrough;
6299	default:
6300	ret = -EINVAL;
6301	goto out;
6302	}
6303
6304	if (duplex == DUPLEX_FULL)
6305	tp->mii.full_duplex = 1;
6306	else
6307	tp->mii.full_duplex = 0;
6308
6309	tp->mii.force_media = 1;
6310	} else {
6311	u16 orig, new1;
6312	u32 support;
6313
6314	support = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
6315	RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
6316
6317	if (tp->mii.supports_gmii) {
6318	support |= RTL_ADVERTISED_1000_FULL;
6319
6320	if (tp->support_2500full)
6321	support |= RTL_ADVERTISED_2500_FULL;
6322	}
6323
6324	if (!(advertising & support))
6325	return -EINVAL;
6326
6327	orig = r8152_mdio_read(tp, MII_ADVERTISE);
6328	new1 = orig & ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
6329	ADVERTISE_100HALF | ADVERTISE_100FULL);
6330	if (advertising & RTL_ADVERTISED_10_HALF) {
6331	new1 |= ADVERTISE_10HALF;
6332	tp->ups_info.speed_duplex = NWAY_10M_HALF;
6333	}
6334	if (advertising & RTL_ADVERTISED_10_FULL) {
6335	new1 |= ADVERTISE_10FULL;
6336	tp->ups_info.speed_duplex = NWAY_10M_FULL;
6337	}
6338
6339	if (advertising & RTL_ADVERTISED_100_HALF) {
6340	new1 |= ADVERTISE_100HALF;
6341	tp->ups_info.speed_duplex = NWAY_100M_HALF;
6342	}
6343	if (advertising & RTL_ADVERTISED_100_FULL) {
6344	new1 |= ADVERTISE_100FULL;
6345	tp->ups_info.speed_duplex = NWAY_100M_FULL;
6346	}
6347
6348	if (orig != new1) {
6349	r8152_mdio_write(tp, MII_ADVERTISE, value: new1);
6350	tp->mii.advertising = new1;
6351	}
6352
6353	if (tp->mii.supports_gmii) {
6354	orig = r8152_mdio_read(tp, MII_CTRL1000);
6355	new1 = orig & ~(ADVERTISE_1000FULL |
6356	ADVERTISE_1000HALF);
6357
6358	if (advertising & RTL_ADVERTISED_1000_FULL) {
6359	new1 |= ADVERTISE_1000FULL;
6360	tp->ups_info.speed_duplex = NWAY_1000M_FULL;
6361	}
6362
6363	if (orig != new1)
6364	r8152_mdio_write(tp, MII_CTRL1000, value: new1);
6365	}
6366
6367	if (tp->support_2500full) {
6368	orig = ocp_reg_read(tp, OCP_10GBT_CTRL);
6369	new1 = orig & ~MDIO_AN_10GBT_CTRL_ADV2_5G;
6370
6371	if (advertising & RTL_ADVERTISED_2500_FULL) {
6372	new1 |= MDIO_AN_10GBT_CTRL_ADV2_5G;
6373	tp->ups_info.speed_duplex = NWAY_2500M_FULL;
6374	}
6375
6376	if (orig != new1)
6377	ocp_reg_write(tp, OCP_10GBT_CTRL, data: new1);
6378	}
6379
6380	bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
6381
6382	tp->mii.force_media = 0;
6383	}
6384
6385	if (test_and_clear_bit(nr: PHY_RESET, addr: &tp->flags))
6386	bmcr |= BMCR_RESET;
6387
6388	r8152_mdio_write(tp, MII_BMCR, value: bmcr);
6389
6390	if (bmcr & BMCR_RESET) {
6391	int i;
6392
6393	for (i = 0; i < 50; i++) {
6394	msleep(msecs: 20);
6395	if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
6396	break;
6397	}
6398	}
6399
6400	out:
6401	return ret;
6402	}
6403
6404	static void rtl8152_up(struct r8152 *tp)
6405	{
6406	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
6407	return;
6408
6409	r8152_aldps_en(tp, enable: false);
6410	r8152b_exit_oob(tp);
6411	r8152_aldps_en(tp, enable: true);
6412	}
6413
6414	static void rtl8152_down(struct r8152 *tp)
6415	{
6416	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) {
6417	rtl_drop_queued_tx(tp);
6418	return;
6419	}
6420
6421	r8152_power_cut_en(tp, enable: false);
6422	r8152_aldps_en(tp, enable: false);
6423	r8152b_enter_oob(tp);
6424	r8152_aldps_en(tp, enable: true);
6425	}
6426
6427	static void rtl8153_up(struct r8152 *tp)
6428	{
6429	u32 ocp_data;
6430
6431	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
6432	return;
6433
6434	r8153_u1u2en(tp, enable: false);
6435	r8153_u2p3en(tp, enable: false);
6436	r8153_aldps_en(tp, enable: false);
6437	r8153_first_init(tp);
6438
6439	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
6440	ocp_data |= LANWAKE_CLR_EN;
6441	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, data: ocp_data);
6442
6443	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG);
6444	ocp_data &= ~LANWAKE_PIN;
6445	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, data: ocp_data);
6446
6447	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1);
6448	ocp_data &= ~DELAY_PHY_PWR_CHG;
6449	ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1, data: ocp_data);
6450
6451	r8153_aldps_en(tp, enable: true);
6452
6453	switch (tp->version) {
6454	case RTL_VER_03:
6455	case RTL_VER_04:
6456	break;
6457	case RTL_VER_05:
6458	case RTL_VER_06:
6459	default:
6460	r8153_u2p3en(tp, enable: true);
6461	break;
6462	}
6463
6464	r8153_u1u2en(tp, enable: true);
6465	}
6466
6467	static void rtl8153_down(struct r8152 *tp)
6468	{
6469	u32 ocp_data;
6470
6471	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) {
6472	rtl_drop_queued_tx(tp);
6473	return;
6474	}
6475
6476	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
6477	ocp_data &= ~LANWAKE_CLR_EN;
6478	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, data: ocp_data);
6479
6480	r8153_u1u2en(tp, enable: false);
6481	r8153_u2p3en(tp, enable: false);
6482	r8153_power_cut_en(tp, enable: false);
6483	r8153_aldps_en(tp, enable: false);
6484	r8153_enter_oob(tp);
6485	r8153_aldps_en(tp, enable: true);
6486	}
6487
6488	static void rtl8153b_up(struct r8152 *tp)
6489	{
6490	u32 ocp_data;
6491
6492	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
6493	return;
6494
6495	r8153b_u1u2en(tp, enable: false);
6496	r8153_u2p3en(tp, enable: false);
6497	r8153_aldps_en(tp, enable: false);
6498
6499	r8153_first_init(tp);
6500	ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);
6501
6502	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6503	ocp_data &= ~PLA_MCU_SPDWN_EN;
6504	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, data: ocp_data);
6505
6506	r8153_aldps_en(tp, enable: true);
6507
6508	if (tp->udev->speed >= USB_SPEED_SUPER)
6509	r8153b_u1u2en(tp, enable: true);
6510	}
6511
6512	static void rtl8153b_down(struct r8152 *tp)
6513	{
6514	u32 ocp_data;
6515
6516	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) {
6517	rtl_drop_queued_tx(tp);
6518	return;
6519	}
6520
6521	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6522	ocp_data |= PLA_MCU_SPDWN_EN;
6523	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, data: ocp_data);
6524
6525	r8153b_u1u2en(tp, enable: false);
6526	r8153_u2p3en(tp, enable: false);
6527	r8153b_power_cut_en(tp, enable: false);
6528	r8153_aldps_en(tp, enable: false);
6529	r8153_enter_oob(tp);
6530	r8153_aldps_en(tp, enable: true);
6531	}
6532
6533	static void rtl8153c_change_mtu(struct r8152 *tp)
6534	{
6535	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, mtu_to_size(tp->netdev->mtu));
6536	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, data: 10 * 1024 / 64);
6537
6538	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, data: 512 / 64);
6539
6540	/* Adjust the tx fifo free credit full threshold, otherwise
6541	* the fifo would be too small to send a jumbo frame packet.
6542	*/
6543	if (tp->netdev->mtu < 8000)
6544	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL, data: 2048 / 8);
6545	else
6546	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL, data: 900 / 8);
6547	}
6548
6549	static void rtl8153c_up(struct r8152 *tp)
6550	{
6551	u32 ocp_data;
6552
6553	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
6554	return;
6555
6556	r8153b_u1u2en(tp, enable: false);
6557	r8153_u2p3en(tp, enable: false);
6558	r8153_aldps_en(tp, enable: false);
6559
6560	rxdy_gated_en(tp, enable: true);
6561	r8153_teredo_off(tp);
6562
6563	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
6564	ocp_data &= ~RCR_ACPT_ALL;
6565	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, data: ocp_data);
6566
6567	rtl8152_nic_reset(tp);
6568	rtl_reset_bmu(tp);
6569
6570	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6571	ocp_data &= ~NOW_IS_OOB;
6572	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, data: ocp_data);
6573
6574	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6575	ocp_data &= ~MCU_BORW_EN;
6576	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, data: ocp_data);
6577
6578	wait_oob_link_list_ready(tp);
6579
6580	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6581	ocp_data |= RE_INIT_LL;
6582	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, data: ocp_data);
6583
6584	wait_oob_link_list_ready(tp);
6585
6586	rtl_rx_vlan_en(tp, enable: tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
6587
6588	rtl8153c_change_mtu(tp);
6589
6590	rtl8152_nic_reset(tp);
6591
6592	/* rx share fifo credit full threshold */
6593	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, data: 0x02);
6594	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, data: 0x08);
6595	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
6596	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
6597
6598	ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);
6599
6600	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
6601
6602	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
6603	ocp_data |= BIT(8);
6604	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, data: ocp_data);
6605
6606	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
6607
6608	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6609	ocp_data &= ~PLA_MCU_SPDWN_EN;
6610	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, data: ocp_data);
6611
6612	r8153_aldps_en(tp, enable: true);
6613	r8153b_u1u2en(tp, enable: true);
6614	}
6615
6616	static void rtl8156_change_mtu(struct r8152 *tp)
6617	{
6618	u32 rx_max_size = mtu_to_size(tp->netdev->mtu);
6619
6620	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, data: rx_max_size);
6621	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
6622	r8156_fc_parameter(tp);
6623
6624	/* TX share fifo free credit full threshold */
6625	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, data: 512 / 64);
6626	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL,
6627	ALIGN(rx_max_size + sizeof(struct tx_desc), 1024) / 16);
6628	}
6629
6630	static void rtl8156_up(struct r8152 *tp)
6631	{
6632	u32 ocp_data;
6633
6634	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
6635	return;
6636
6637	r8153b_u1u2en(tp, enable: false);
6638	r8153_u2p3en(tp, enable: false);
6639	r8153_aldps_en(tp, enable: false);
6640
6641	rxdy_gated_en(tp, enable: true);
6642	r8153_teredo_off(tp);
6643
6644	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
6645	ocp_data &= ~RCR_ACPT_ALL;
6646	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, data: ocp_data);
6647
6648	rtl8152_nic_reset(tp);
6649	rtl_reset_bmu(tp);
6650
6651	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6652	ocp_data &= ~NOW_IS_OOB;
6653	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, data: ocp_data);
6654
6655	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6656	ocp_data &= ~MCU_BORW_EN;
6657	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, data: ocp_data);
6658
6659	rtl_rx_vlan_en(tp, enable: tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
6660
6661	rtl8156_change_mtu(tp);
6662
6663	switch (tp->version) {
6664	case RTL_TEST_01:
6665	case RTL_VER_10:
6666	case RTL_VER_11:
6667	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_CONFIG);
6668	ocp_data |= ACT_ODMA;
6669	ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_CONFIG, data: ocp_data);
6670	break;
6671	default:
6672	break;
6673	}
6674
6675	/* share FIFO settings */
6676	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL);
6677	ocp_data &= ~RXFIFO_FULL_MASK;
6678	ocp_data |= 0x08;
6679	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, data: ocp_data);
6680
6681	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6682	ocp_data &= ~PLA_MCU_SPDWN_EN;
6683	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, data: ocp_data);
6684
6685	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION);
6686	ocp_data &= ~(RG_PWRDN_EN | ALL_SPEED_OFF);
6687	ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, data: ocp_data);
6688
6689	ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, data: 0x00600400);
6690
6691	if (tp->saved_wolopts != __rtl_get_wol(tp)) {
6692	netif_warn(tp, ifup, tp->netdev, "wol setting is changed\n");
6693	__rtl_set_wol(tp, wolopts: tp->saved_wolopts);
6694	}
6695
6696	r8153_aldps_en(tp, enable: true);
6697	r8153_u2p3en(tp, enable: true);
6698
6699	if (tp->udev->speed >= USB_SPEED_SUPER)
6700	r8153b_u1u2en(tp, enable: true);
6701	}
6702
6703	static void rtl8156_down(struct r8152 *tp)
6704	{
6705	u32 ocp_data;
6706
6707	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) {
6708	rtl_drop_queued_tx(tp);
6709	return;
6710	}
6711
6712	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6713	ocp_data |= PLA_MCU_SPDWN_EN;
6714	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, data: ocp_data);
6715
6716	r8153b_u1u2en(tp, enable: false);
6717	r8153_u2p3en(tp, enable: false);
6718	r8153b_power_cut_en(tp, enable: false);
6719	r8153_aldps_en(tp, enable: false);
6720
6721	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6722	ocp_data &= ~NOW_IS_OOB;
6723	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, data: ocp_data);
6724
6725	/* RX FIFO settings for OOB */
6726	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, data: 64 / 16);
6727	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_FULL, data: 1024 / 16);
6728	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, data: 4096 / 16);
6729
6730	rtl_disable(tp);
6731	rtl_reset_bmu(tp);
6732
6733	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, data: 1522);
6734	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_DEFAULT);
6735
6736	/* Clear teredo wake event. bit[15:8] is the teredo wakeup
6737	* type. Set it to zero. bits[7:0] are the W1C bits about
6738	* the events. Set them to all 1 to clear them.
6739	*/
6740	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, data: 0x00ff);
6741
6742	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6743	ocp_data |= NOW_IS_OOB;
6744	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, data: ocp_data);
6745
6746	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6747	ocp_data |= MCU_BORW_EN;
6748	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, data: ocp_data);
6749
6750	rtl_rx_vlan_en(tp, enable: true);
6751	rxdy_gated_en(tp, enable: false);
6752
6753	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
6754	ocp_data |= RCR_APM | RCR_AM | RCR_AB;
6755	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, data: ocp_data);
6756
6757	r8153_aldps_en(tp, enable: true);
6758	}
6759
6760	static bool rtl8152_in_nway(struct r8152 *tp)
6761	{
6762	u16 nway_state;
6763
6764	ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, data: 0x2000);
6765	tp->ocp_base = 0x2000;
6766	ocp_write_byte(tp, MCU_TYPE_PLA, index: 0xb014, data: 0x4c); /* phy state */
6767	nway_state = ocp_read_word(tp, MCU_TYPE_PLA, index: 0xb01a);
6768
6769	/* bit 15: TXDIS_STATE, bit 14: ABD_STATE */
6770	if (nway_state & 0xc000)
6771	return false;
6772	else
6773	return true;
6774	}
6775
6776	static bool rtl8153_in_nway(struct r8152 *tp)
6777	{
6778	u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff;
6779
6780	if (phy_state == TXDIS_STATE || phy_state == ABD_STATE)
6781	return false;
6782	else
6783	return true;
6784	}
6785
6786	static void r8156_mdio_force_mode(struct r8152 *tp)
6787	{
6788	u16 data;
6789
6790	/* Select force mode through 0xa5b4 bit 15
6791	* 0: MDIO force mode
6792	* 1: MMD force mode
6793	*/
6794	data = ocp_reg_read(tp, addr: 0xa5b4);
6795	if (data & BIT(15)) {
6796	data &= ~BIT(15);
6797	ocp_reg_write(tp, addr: 0xa5b4, data);
6798	}
6799	}
6800
6801	static void set_carrier(struct r8152 *tp)
6802	{
6803	struct net_device *netdev = tp->netdev;
6804	struct napi_struct *napi = &tp->napi;
6805	u16 speed;
6806
6807	speed = rtl8152_get_speed(tp);
6808
6809	if (speed & LINK_STATUS) {
6810	if (!netif_carrier_ok(dev: netdev)) {
6811	tp->rtl_ops.enable(tp);
6812	netif_stop_queue(dev: netdev);
6813	napi_disable(n: napi);
6814	netif_carrier_on(dev: netdev);
6815	rtl_start_rx(tp);
6816	clear_bit(nr: RTL8152_SET_RX_MODE, addr: &tp->flags);
6817	_rtl8152_set_rx_mode(netdev);
6818	napi_enable(n: napi);
6819	netif_wake_queue(dev: netdev);
6820	netif_info(tp, link, netdev, "carrier on\n");
6821	} else if (netif_queue_stopped(dev: netdev) &&
6822	skb_queue_len(list_: &tp->tx_queue) < tp->tx_qlen) {
6823	netif_wake_queue(dev: netdev);
6824	}
6825	} else {
6826	if (netif_carrier_ok(dev: netdev)) {
6827	netif_carrier_off(dev: netdev);
6828	tasklet_disable(t: &tp->tx_tl);
6829	napi_disable(n: napi);
6830	tp->rtl_ops.disable(tp);
6831	napi_enable(n: napi);
6832	tasklet_enable(t: &tp->tx_tl);
6833	netif_info(tp, link, netdev, "carrier off\n");
6834	}
6835	}
6836	}
6837
6838	static void rtl_work_func_t(struct work_struct *work)
6839	{
6840	struct r8152 *tp = container_of(work, struct r8152, schedule.work);
6841
6842	/* If the device is unplugged or !netif_running(), the workqueue
6843	* doesn't need to wake the device, and could return directly.
6844	*/
6845	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags) || !netif_running(dev: tp->netdev))
6846	return;
6847
6848	if (usb_autopm_get_interface(intf: tp->intf) < 0)
6849	return;
6850
6851	if (!test_bit(WORK_ENABLE, &tp->flags))
6852	goto out1;
6853
6854	if (!mutex_trylock(lock: &tp->control)) {
6855	schedule_delayed_work(dwork: &tp->schedule, delay: 0);
6856	goto out1;
6857	}
6858
6859	if (test_and_clear_bit(nr: RTL8152_LINK_CHG, addr: &tp->flags))
6860	set_carrier(tp);
6861
6862	if (test_and_clear_bit(nr: RTL8152_SET_RX_MODE, addr: &tp->flags))
6863	_rtl8152_set_rx_mode(netdev: tp->netdev);
6864
6865	/* don't schedule tasket before linking */
6866	if (test_and_clear_bit(nr: SCHEDULE_TASKLET, addr: &tp->flags) &&
6867	netif_carrier_ok(dev: tp->netdev))
6868	tasklet_schedule(t: &tp->tx_tl);
6869
6870	if (test_and_clear_bit(nr: RX_EPROTO, addr: &tp->flags) &&
6871	!list_empty(head: &tp->rx_done))
6872	napi_schedule(n: &tp->napi);
6873
6874	mutex_unlock(lock: &tp->control);
6875
6876	out1:
6877	usb_autopm_put_interface(intf: tp->intf);
6878	}
6879
6880	static void rtl_hw_phy_work_func_t(struct work_struct *work)
6881	{
6882	struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work);
6883
6884	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
6885	return;
6886
6887	if (usb_autopm_get_interface(intf: tp->intf) < 0)
6888	return;
6889
6890	mutex_lock(&tp->control);
6891
6892	if (rtl8152_request_firmware(tp) == -ENODEV && tp->rtl_fw.retry) {
6893	tp->rtl_fw.retry = false;
6894	tp->rtl_fw.fw = NULL;
6895
6896	/* Delay execution in case request_firmware() is not ready yet.
6897	*/
6898	queue_delayed_work(wq: system_long_wq, dwork: &tp->hw_phy_work, HZ * 10);
6899	goto ignore_once;
6900	}
6901
6902	tp->rtl_ops.hw_phy_cfg(tp);
6903
6904	rtl8152_set_speed(tp, autoneg: tp->autoneg, speed: tp->speed, duplex: tp->duplex,
6905	advertising: tp->advertising);
6906
6907	ignore_once:
6908	mutex_unlock(lock: &tp->control);
6909
6910	usb_autopm_put_interface(intf: tp->intf);
6911	}
6912
6913	#ifdef CONFIG_PM_SLEEP
6914	static int rtl_notifier(struct notifier_block *nb, unsigned long action,
6915	void *data)
6916	{
6917	struct r8152 *tp = container_of(nb, struct r8152, pm_notifier);
6918
6919	switch (action) {
6920	case PM_HIBERNATION_PREPARE:
6921	case PM_SUSPEND_PREPARE:
6922	usb_autopm_get_interface(intf: tp->intf);
6923	break;
6924
6925	case PM_POST_HIBERNATION:
6926	case PM_POST_SUSPEND:
6927	usb_autopm_put_interface(intf: tp->intf);
6928	break;
6929
6930	case PM_POST_RESTORE:
6931	case PM_RESTORE_PREPARE:
6932	default:
6933	break;
6934	}
6935
6936	return NOTIFY_DONE;
6937	}
6938	#endif
6939
6940	static int rtl8152_open(struct net_device *netdev)
6941	{
6942	struct r8152 *tp = netdev_priv(dev: netdev);
6943	int res = 0;
6944
6945	if (work_busy(work: &tp->hw_phy_work.work) & WORK_BUSY_PENDING) {
6946	cancel_delayed_work_sync(dwork: &tp->hw_phy_work);
6947	rtl_hw_phy_work_func_t(work: &tp->hw_phy_work.work);
6948	}
6949
6950	res = alloc_all_mem(tp);
6951	if (res)
6952	goto out;
6953
6954	res = usb_autopm_get_interface(intf: tp->intf);
6955	if (res < 0)
6956	goto out_free;
6957
6958	mutex_lock(&tp->control);
6959
6960	tp->rtl_ops.up(tp);
6961
6962	netif_carrier_off(dev: netdev);
6963	netif_start_queue(dev: netdev);
6964	set_bit(nr: WORK_ENABLE, addr: &tp->flags);
6965
6966	res = usb_submit_urb(urb: tp->intr_urb, GFP_KERNEL);
6967	if (res) {
6968	if (res == -ENODEV)
6969	netif_device_detach(dev: tp->netdev);
6970	netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
6971	res);
6972	goto out_unlock;
6973	}
6974	napi_enable(n: &tp->napi);
6975	tasklet_enable(t: &tp->tx_tl);
6976
6977	mutex_unlock(lock: &tp->control);
6978
6979	usb_autopm_put_interface(intf: tp->intf);
6980	#ifdef CONFIG_PM_SLEEP
6981	tp->pm_notifier.notifier_call = rtl_notifier;
6982	register_pm_notifier(nb: &tp->pm_notifier);
6983	#endif
6984	return 0;
6985
6986	out_unlock:
6987	mutex_unlock(lock: &tp->control);
6988	usb_autopm_put_interface(intf: tp->intf);
6989	out_free:
6990	free_all_mem(tp);
6991	out:
6992	return res;
6993	}
6994
6995	static int rtl8152_close(struct net_device *netdev)
6996	{
6997	struct r8152 *tp = netdev_priv(dev: netdev);
6998	int res = 0;
6999
7000	#ifdef CONFIG_PM_SLEEP
7001	unregister_pm_notifier(nb: &tp->pm_notifier);
7002	#endif
7003	tasklet_disable(t: &tp->tx_tl);
7004	clear_bit(nr: WORK_ENABLE, addr: &tp->flags);
7005	usb_kill_urb(urb: tp->intr_urb);
7006	cancel_delayed_work_sync(dwork: &tp->schedule);
7007	napi_disable(n: &tp->napi);
7008	netif_stop_queue(dev: netdev);
7009
7010	res = usb_autopm_get_interface(intf: tp->intf);
7011	if (res < 0 || test_bit(RTL8152_INACCESSIBLE, &tp->flags)) {
7012	rtl_drop_queued_tx(tp);
7013	rtl_stop_rx(tp);
7014	} else {
7015	mutex_lock(&tp->control);
7016
7017	tp->rtl_ops.down(tp);
7018
7019	mutex_unlock(lock: &tp->control);
7020	}
7021
7022	if (!res)
7023	usb_autopm_put_interface(intf: tp->intf);
7024
7025	free_all_mem(tp);
7026
7027	return res;
7028	}
7029
7030	static void rtl_tally_reset(struct r8152 *tp)
7031	{
7032	u32 ocp_data;
7033
7034	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
7035	ocp_data |= TALLY_RESET;
7036	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, data: ocp_data);
7037	}
7038
7039	static void r8152b_init(struct r8152 *tp)
7040	{
7041	u32 ocp_data;
7042	u16 data;
7043
7044	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
7045	return;
7046
7047	data = r8152_mdio_read(tp, MII_BMCR);
7048	if (data & BMCR_PDOWN) {
7049	data &= ~BMCR_PDOWN;
7050	r8152_mdio_write(tp, MII_BMCR, value: data);
7051	}
7052
7053	r8152_aldps_en(tp, enable: false);
7054
7055	if (tp->version == RTL_VER_01) {
7056	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
7057	ocp_data &= ~LED_MODE_MASK;
7058	ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, data: ocp_data);
7059	}
7060
7061	r8152_power_cut_en(tp, enable: false);
7062
7063	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
7064	ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
7065	ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, data: ocp_data);
7066	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
7067	ocp_data &= ~MCU_CLK_RATIO_MASK;
7068	ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
7069	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, data: ocp_data);
7070	ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
7071	SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
7072	ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, data: ocp_data);
7073
7074	rtl_tally_reset(tp);
7075
7076	/* enable rx aggregation */
7077	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
7078	ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
7079	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, data: ocp_data);
7080	}
7081
7082	static void r8153_init(struct r8152 *tp)
7083	{
7084	u32 ocp_data;
7085	u16 data;
7086	int i;
7087
7088	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
7089	return;
7090
7091	r8153_u1u2en(tp, enable: false);
7092
7093	for (i = 0; i < 500; i++) {
7094	if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
7095	AUTOLOAD_DONE)
7096	break;
7097
7098	msleep(msecs: 20);
7099	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
7100	break;
7101	}
7102
7103	data = r8153_phy_status(tp, desired: 0);
7104
7105	if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
7106	tp->version == RTL_VER_05)
7107	ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
7108
7109	data = r8152_mdio_read(tp, MII_BMCR);
7110	if (data & BMCR_PDOWN) {
7111	data &= ~BMCR_PDOWN;
7112	r8152_mdio_write(tp, MII_BMCR, value: data);
7113	}
7114
7115	data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7116
7117	r8153_u2p3en(tp, enable: false);
7118
7119	if (tp->version == RTL_VER_04) {
7120	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
7121	ocp_data &= ~pwd_dn_scale_mask;
7122	ocp_data |= pwd_dn_scale(96);
7123	ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, data: ocp_data);
7124
7125	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
7126	ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
7127	ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, data: ocp_data);
7128	} else if (tp->version == RTL_VER_05) {
7129	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
7130	ocp_data &= ~ECM_ALDPS;
7131	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, data: ocp_data);
7132
7133	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
7134	if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
7135	ocp_data &= ~DYNAMIC_BURST;
7136	else
7137	ocp_data |= DYNAMIC_BURST;
7138	ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, data: ocp_data);
7139	} else if (tp->version == RTL_VER_06) {
7140	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
7141	if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
7142	ocp_data &= ~DYNAMIC_BURST;
7143	else
7144	ocp_data |= DYNAMIC_BURST;
7145	ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, data: ocp_data);
7146
7147	r8153_queue_wake(tp, enable: false);
7148
7149	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
7150	if (rtl8152_get_speed(tp) & LINK_STATUS)
7151	ocp_data |= CUR_LINK_OK;
7152	else
7153	ocp_data &= ~CUR_LINK_OK;
7154	ocp_data |= POLL_LINK_CHG;
7155	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, data: ocp_data);
7156	}
7157
7158	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
7159	ocp_data |= EP4_FULL_FC;
7160	ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, data: ocp_data);
7161
7162	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
7163	ocp_data &= ~TIMER11_EN;
7164	ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, data: ocp_data);
7165
7166	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
7167	ocp_data &= ~LED_MODE_MASK;
7168	ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, data: ocp_data);
7169
7170	ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
7171	if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER)
7172	ocp_data |= LPM_TIMER_500MS;
7173	else
7174	ocp_data |= LPM_TIMER_500US;
7175	ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, data: ocp_data);
7176
7177	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
7178	ocp_data &= ~SEN_VAL_MASK;
7179	ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
7180	ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, data: ocp_data);
7181
7182	ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, data: 0x0001);
7183
7184	r8153_power_cut_en(tp, enable: false);
7185	rtl_runtime_suspend_enable(tp, enable: false);
7186	r8153_mac_clk_speed_down(tp, enable: false);
7187	r8153_u1u2en(tp, enable: true);
7188	usb_enable_lpm(udev: tp->udev);
7189
7190	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
7191	ocp_data |= LANWAKE_CLR_EN;
7192	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, data: ocp_data);
7193
7194	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG);
7195	ocp_data &= ~LANWAKE_PIN;
7196	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, data: ocp_data);
7197
7198	/* rx aggregation */
7199	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
7200	ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
7201	if (tp->dell_tb_rx_agg_bug)
7202	ocp_data |= RX_AGG_DISABLE;
7203
7204	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, data: ocp_data);
7205
7206	rtl_tally_reset(tp);
7207
7208	switch (tp->udev->speed) {
7209	case USB_SPEED_SUPER:
7210	case USB_SPEED_SUPER_PLUS:
7211	tp->coalesce = COALESCE_SUPER;
7212	break;
7213	case USB_SPEED_HIGH:
7214	tp->coalesce = COALESCE_HIGH;
7215	break;
7216	default:
7217	tp->coalesce = COALESCE_SLOW;
7218	break;
7219	}
7220	}
7221
7222	static void r8153b_init(struct r8152 *tp)
7223	{
7224	u32 ocp_data;
7225	u16 data;
7226	int i;
7227
7228	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
7229	return;
7230
7231	r8153b_u1u2en(tp, enable: false);
7232
7233	for (i = 0; i < 500; i++) {
7234	if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
7235	AUTOLOAD_DONE)
7236	break;
7237
7238	msleep(msecs: 20);
7239	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
7240	break;
7241	}
7242
7243	data = r8153_phy_status(tp, desired: 0);
7244
7245	data = r8152_mdio_read(tp, MII_BMCR);
7246	if (data & BMCR_PDOWN) {
7247	data &= ~BMCR_PDOWN;
7248	r8152_mdio_write(tp, MII_BMCR, value: data);
7249	}
7250
7251	data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7252
7253	r8153_u2p3en(tp, enable: false);
7254
7255	/* MSC timer = 0xfff * 8ms = 32760 ms */
7256	ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, data: 0x0fff);
7257
7258	r8153b_power_cut_en(tp, enable: false);
7259	r8153b_ups_en(tp, enable: false);
7260	r8153_queue_wake(tp, enable: false);
7261	rtl_runtime_suspend_enable(tp, enable: false);
7262
7263	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
7264	if (rtl8152_get_speed(tp) & LINK_STATUS)
7265	ocp_data |= CUR_LINK_OK;
7266	else
7267	ocp_data &= ~CUR_LINK_OK;
7268	ocp_data |= POLL_LINK_CHG;
7269	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, data: ocp_data);
7270
7271	if (tp->udev->speed >= USB_SPEED_SUPER)
7272	r8153b_u1u2en(tp, enable: true);
7273
7274	usb_enable_lpm(udev: tp->udev);
7275
7276	/* MAC clock speed down */
7277	r8153_mac_clk_speed_down(tp, enable: true);
7278
7279	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
7280	ocp_data &= ~PLA_MCU_SPDWN_EN;
7281	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, data: ocp_data);
7282
7283	if (tp->version == RTL_VER_09) {
7284	/* Disable Test IO for 32QFN */
7285	if (ocp_read_byte(tp, MCU_TYPE_PLA, index: 0xdc00) & BIT(5)) {
7286	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
7287	ocp_data |= TEST_IO_OFF;
7288	ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, data: ocp_data);
7289	}
7290	}
7291
7292	set_bit(nr: GREEN_ETHERNET, addr: &tp->flags);
7293
7294	/* rx aggregation */
7295	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
7296	ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
7297	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, data: ocp_data);
7298
7299	rtl_tally_reset(tp);
7300
7301	tp->coalesce = 15000; /* 15 us */
7302	}
7303
7304	static void r8153c_init(struct r8152 *tp)
7305	{
7306	u32 ocp_data;
7307	u16 data;
7308	int i;
7309
7310	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
7311	return;
7312
7313	r8153b_u1u2en(tp, enable: false);
7314
7315	/* Disable spi_en */
7316	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
7317	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
7318	ocp_data &= ~BIT(3);
7319	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, data: ocp_data);
7320	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, index: 0xcbf0);
7321	ocp_data |= BIT(1);
7322	ocp_write_word(tp, MCU_TYPE_USB, index: 0xcbf0, data: ocp_data);
7323
7324	for (i = 0; i < 500; i++) {
7325	if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
7326	AUTOLOAD_DONE)
7327	break;
7328
7329	msleep(msecs: 20);
7330	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
7331	return;
7332	}
7333
7334	data = r8153_phy_status(tp, desired: 0);
7335
7336	data = r8152_mdio_read(tp, MII_BMCR);
7337	if (data & BMCR_PDOWN) {
7338	data &= ~BMCR_PDOWN;
7339	r8152_mdio_write(tp, MII_BMCR, value: data);
7340	}
7341
7342	data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7343
7344	r8153_u2p3en(tp, enable: false);
7345
7346	/* MSC timer = 0xfff * 8ms = 32760 ms */
7347	ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, data: 0x0fff);
7348
7349	r8153b_power_cut_en(tp, enable: false);
7350	r8153c_ups_en(tp, enable: false);
7351	r8153_queue_wake(tp, enable: false);
7352	rtl_runtime_suspend_enable(tp, enable: false);
7353
7354	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
7355	if (rtl8152_get_speed(tp) & LINK_STATUS)
7356	ocp_data |= CUR_LINK_OK;
7357	else
7358	ocp_data &= ~CUR_LINK_OK;
7359
7360	ocp_data |= POLL_LINK_CHG;
7361	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, data: ocp_data);
7362
7363	r8153b_u1u2en(tp, enable: true);
7364
7365	usb_enable_lpm(udev: tp->udev);
7366
7367	/* MAC clock speed down */
7368	r8153_mac_clk_speed_down(tp, enable: true);
7369
7370	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
7371	ocp_data &= ~BIT(7);
7372	ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, data: ocp_data);
7373
7374	set_bit(nr: GREEN_ETHERNET, addr: &tp->flags);
7375
7376	/* rx aggregation */
7377	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
7378	ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
7379	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, data: ocp_data);
7380
7381	rtl_tally_reset(tp);
7382
7383	tp->coalesce = 15000; /* 15 us */
7384	}
7385
7386	static void r8156_hw_phy_cfg(struct r8152 *tp)
7387	{
7388	u32 ocp_data;
7389	u16 data;
7390
7391	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
7392	if (ocp_data & PCUT_STATUS) {
7393	ocp_data &= ~PCUT_STATUS;
7394	ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, data: ocp_data);
7395	}
7396
7397	data = r8153_phy_status(tp, desired: 0);
7398	switch (data) {
7399	case PHY_STAT_EXT_INIT:
7400	rtl8152_apply_firmware(tp, power_cut: true);
7401
7402	data = ocp_reg_read(tp, addr: 0xa468);
7403	data &= ~(BIT(3) | BIT(1));
7404	ocp_reg_write(tp, addr: 0xa468, data);
7405	break;
7406	case PHY_STAT_LAN_ON:
7407	case PHY_STAT_PWRDN:
7408	default:
7409	rtl8152_apply_firmware(tp, power_cut: false);
7410	break;
7411	}
7412
7413	/* disable ALDPS before updating the PHY parameters */
7414	r8153_aldps_en(tp, enable: false);
7415
7416	/* disable EEE before updating the PHY parameters */
7417	rtl_eee_enable(tp, enable: false);
7418
7419	data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7420	WARN_ON_ONCE(data != PHY_STAT_LAN_ON);
7421
7422	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
7423	ocp_data |= PFM_PWM_SWITCH;
7424	ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, data: ocp_data);
7425
7426	switch (tp->version) {
7427	case RTL_VER_10:
7428	data = ocp_reg_read(tp, addr: 0xad40);
7429	data &= ~0x3ff;
7430	data |= BIT(7) | BIT(2);
7431	ocp_reg_write(tp, addr: 0xad40, data);
7432
7433	data = ocp_reg_read(tp, addr: 0xad4e);
7434	data |= BIT(4);
7435	ocp_reg_write(tp, addr: 0xad4e, data);
7436	data = ocp_reg_read(tp, addr: 0xad16);
7437	data &= ~0x3ff;
7438	data |= 0x6;
7439	ocp_reg_write(tp, addr: 0xad16, data);
7440	data = ocp_reg_read(tp, addr: 0xad32);
7441	data &= ~0x3f;
7442	data |= 6;
7443	ocp_reg_write(tp, addr: 0xad32, data);
7444	data = ocp_reg_read(tp, addr: 0xac08);
7445	data &= ~(BIT(12) | BIT(8));
7446	ocp_reg_write(tp, addr: 0xac08, data);
7447	data = ocp_reg_read(tp, addr: 0xac8a);
7448	data |= BIT(12) | BIT(13) | BIT(14);
7449	data &= ~BIT(15);
7450	ocp_reg_write(tp, addr: 0xac8a, data);
7451	data = ocp_reg_read(tp, addr: 0xad18);
7452	data |= BIT(10);
7453	ocp_reg_write(tp, addr: 0xad18, data);
7454	data = ocp_reg_read(tp, addr: 0xad1a);
7455	data |= 0x3ff;
7456	ocp_reg_write(tp, addr: 0xad1a, data);
7457	data = ocp_reg_read(tp, addr: 0xad1c);
7458	data |= 0x3ff;
7459	ocp_reg_write(tp, addr: 0xad1c, data);
7460
7461	data = sram_read(tp, addr: 0x80ea);
7462	data &= ~0xff00;
7463	data |= 0xc400;
7464	sram_write(tp, addr: 0x80ea, data);
7465	data = sram_read(tp, addr: 0x80eb);
7466	data &= ~0x0700;
7467	data |= 0x0300;
7468	sram_write(tp, addr: 0x80eb, data);
7469	data = sram_read(tp, addr: 0x80f8);
7470	data &= ~0xff00;
7471	data |= 0x1c00;
7472	sram_write(tp, addr: 0x80f8, data);
7473	data = sram_read(tp, addr: 0x80f1);
7474	data &= ~0xff00;
7475	data |= 0x3000;
7476	sram_write(tp, addr: 0x80f1, data);
7477
7478	data = sram_read(tp, addr: 0x80fe);
7479	data &= ~0xff00;
7480	data |= 0xa500;
7481	sram_write(tp, addr: 0x80fe, data);
7482	data = sram_read(tp, addr: 0x8102);
7483	data &= ~0xff00;
7484	data |= 0x5000;
7485	sram_write(tp, addr: 0x8102, data);
7486	data = sram_read(tp, addr: 0x8015);
7487	data &= ~0xff00;
7488	data |= 0x3300;
7489	sram_write(tp, addr: 0x8015, data);
7490	data = sram_read(tp, addr: 0x8100);
7491	data &= ~0xff00;
7492	data |= 0x7000;
7493	sram_write(tp, addr: 0x8100, data);
7494	data = sram_read(tp, addr: 0x8014);
7495	data &= ~0xff00;
7496	data |= 0xf000;
7497	sram_write(tp, addr: 0x8014, data);
7498	data = sram_read(tp, addr: 0x8016);
7499	data &= ~0xff00;
7500	data |= 0x6500;
7501	sram_write(tp, addr: 0x8016, data);
7502	data = sram_read(tp, addr: 0x80dc);
7503	data &= ~0xff00;
7504	data |= 0xed00;
7505	sram_write(tp, addr: 0x80dc, data);
7506	data = sram_read(tp, addr: 0x80df);
7507	data |= BIT(8);
7508	sram_write(tp, addr: 0x80df, data);
7509	data = sram_read(tp, addr: 0x80e1);
7510	data &= ~BIT(8);
7511	sram_write(tp, addr: 0x80e1, data);
7512
7513	data = ocp_reg_read(tp, addr: 0xbf06);
7514	data &= ~0x003f;
7515	data |= 0x0038;
7516	ocp_reg_write(tp, addr: 0xbf06, data);
7517
7518	sram_write(tp, addr: 0x819f, data: 0xddb6);
7519
7520	ocp_reg_write(tp, addr: 0xbc34, data: 0x5555);
7521	data = ocp_reg_read(tp, addr: 0xbf0a);
7522	data &= ~0x0e00;
7523	data |= 0x0a00;
7524	ocp_reg_write(tp, addr: 0xbf0a, data);
7525
7526	data = ocp_reg_read(tp, addr: 0xbd2c);
7527	data &= ~BIT(13);
7528	ocp_reg_write(tp, addr: 0xbd2c, data);
7529	break;
7530	case RTL_VER_11:
7531	data = ocp_reg_read(tp, addr: 0xad16);
7532	data |= 0x3ff;
7533	ocp_reg_write(tp, addr: 0xad16, data);
7534	data = ocp_reg_read(tp, addr: 0xad32);
7535	data &= ~0x3f;
7536	data |= 6;
7537	ocp_reg_write(tp, addr: 0xad32, data);
7538	data = ocp_reg_read(tp, addr: 0xac08);
7539	data &= ~(BIT(12) | BIT(8));
7540	ocp_reg_write(tp, addr: 0xac08, data);
7541	data = ocp_reg_read(tp, addr: 0xacc0);
7542	data &= ~0x3;
7543	data |= BIT(1);
7544	ocp_reg_write(tp, addr: 0xacc0, data);
7545	data = ocp_reg_read(tp, addr: 0xad40);
7546	data &= ~0xe7;
7547	data |= BIT(6) | BIT(2);
7548	ocp_reg_write(tp, addr: 0xad40, data);
7549	data = ocp_reg_read(tp, addr: 0xac14);
7550	data &= ~BIT(7);
7551	ocp_reg_write(tp, addr: 0xac14, data);
7552	data = ocp_reg_read(tp, addr: 0xac80);
7553	data &= ~(BIT(8) | BIT(9));
7554	ocp_reg_write(tp, addr: 0xac80, data);
7555	data = ocp_reg_read(tp, addr: 0xac5e);
7556	data &= ~0x7;
7557	data |= BIT(1);
7558	ocp_reg_write(tp, addr: 0xac5e, data);
7559	ocp_reg_write(tp, addr: 0xad4c, data: 0x00a8);
7560	ocp_reg_write(tp, addr: 0xac5c, data: 0x01ff);
7561	data = ocp_reg_read(tp, addr: 0xac8a);
7562	data &= ~0xf0;
7563	data |= BIT(4) | BIT(5);
7564	ocp_reg_write(tp, addr: 0xac8a, data);
7565	ocp_reg_write(tp, addr: 0xb87c, data: 0x8157);
7566	data = ocp_reg_read(tp, addr: 0xb87e);
7567	data &= ~0xff00;
7568	data |= 0x0500;
7569	ocp_reg_write(tp, addr: 0xb87e, data);
7570	ocp_reg_write(tp, addr: 0xb87c, data: 0x8159);
7571	data = ocp_reg_read(tp, addr: 0xb87e);
7572	data &= ~0xff00;
7573	data |= 0x0700;
7574	ocp_reg_write(tp, addr: 0xb87e, data);
7575
7576	/* AAGC */
7577	ocp_reg_write(tp, addr: 0xb87c, data: 0x80a2);
7578	ocp_reg_write(tp, addr: 0xb87e, data: 0x0153);
7579	ocp_reg_write(tp, addr: 0xb87c, data: 0x809c);
7580	ocp_reg_write(tp, addr: 0xb87e, data: 0x0153);
7581
7582	/* EEE parameter */
7583	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS_2P5G, data: 0x0056);
7584
7585	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_USB_CFG);
7586	ocp_data |= EN_XG_LIP | EN_G_LIP;
7587	ocp_write_word(tp, MCU_TYPE_PLA, PLA_USB_CFG, data: ocp_data);
7588
7589	sram_write(tp, addr: 0x8257, data: 0x020f); /* XG PLL */
7590	sram_write(tp, addr: 0x80ea, data: 0x7843); /* GIGA Master */
7591
7592	if (rtl_phy_patch_request(tp, request: true, wait: true))
7593	return;
7594
7595	/* Advance EEE */
7596	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
7597	ocp_data |= EEE_SPDWN_EN;
7598	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, data: ocp_data);
7599
7600	data = ocp_reg_read(tp, OCP_DOWN_SPEED);
7601	data &= ~(EN_EEE_100 | EN_EEE_1000);
7602	data |= EN_10M_CLKDIV;
7603	ocp_reg_write(tp, OCP_DOWN_SPEED, data);
7604	tp->ups_info._10m_ckdiv = true;
7605	tp->ups_info.eee_plloff_100 = false;
7606	tp->ups_info.eee_plloff_giga = false;
7607
7608	data = ocp_reg_read(tp, OCP_POWER_CFG);
7609	data &= ~EEE_CLKDIV_EN;
7610	ocp_reg_write(tp, OCP_POWER_CFG, data);
7611	tp->ups_info.eee_ckdiv = false;
7612
7613	ocp_reg_write(tp, OCP_SYSCLK_CFG, data: 0);
7614	ocp_reg_write(tp, OCP_SYSCLK_CFG, sysclk_div_expo(5));
7615	tp->ups_info._250m_ckdiv = false;
7616
7617	rtl_phy_patch_request(tp, request: false, wait: true);
7618
7619	/* enable ADC Ibias Cal */
7620	data = ocp_reg_read(tp, addr: 0xd068);
7621	data |= BIT(13);
7622	ocp_reg_write(tp, addr: 0xd068, data);
7623
7624	/* enable Thermal Sensor */
7625	data = sram_read(tp, addr: 0x81a2);
7626	data &= ~BIT(8);
7627	sram_write(tp, addr: 0x81a2, data);
7628	data = ocp_reg_read(tp, addr: 0xb54c);
7629	data &= ~0xff00;
7630	data |= 0xdb00;
7631	ocp_reg_write(tp, addr: 0xb54c, data);
7632
7633	/* Nway 2.5G Lite */
7634	data = ocp_reg_read(tp, addr: 0xa454);
7635	data &= ~BIT(0);
7636	ocp_reg_write(tp, addr: 0xa454, data);
7637
7638	/* CS DSP solution */
7639	data = ocp_reg_read(tp, OCP_10GBT_CTRL);
7640	data |= RTL_ADV2_5G_F_R;
7641	ocp_reg_write(tp, OCP_10GBT_CTRL, data);
7642	data = ocp_reg_read(tp, addr: 0xad4e);
7643	data &= ~BIT(4);
7644	ocp_reg_write(tp, addr: 0xad4e, data);
7645	data = ocp_reg_read(tp, addr: 0xa86a);
7646	data &= ~BIT(0);
7647	ocp_reg_write(tp, addr: 0xa86a, data);
7648
7649	/* MDI SWAP */
7650	if ((ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG) & MID_REVERSE) &&
7651	(ocp_reg_read(tp, addr: 0xd068) & BIT(1))) {
7652	u16 swap_a, swap_b;
7653
7654	data = ocp_reg_read(tp, addr: 0xd068);
7655	data &= ~0x1f;
7656	data |= 0x1; /* p0 */
7657	ocp_reg_write(tp, addr: 0xd068, data);
7658	swap_a = ocp_reg_read(tp, addr: 0xd06a);
7659	data &= ~0x18;
7660	data |= 0x18; /* p3 */
7661	ocp_reg_write(tp, addr: 0xd068, data);
7662	swap_b = ocp_reg_read(tp, addr: 0xd06a);
7663	data &= ~0x18; /* p0 */
7664	ocp_reg_write(tp, addr: 0xd068, data);
7665	ocp_reg_write(tp, addr: 0xd06a,
7666	data: (swap_a & ~0x7ff) | (swap_b & 0x7ff));
7667	data |= 0x18; /* p3 */
7668	ocp_reg_write(tp, addr: 0xd068, data);
7669	ocp_reg_write(tp, addr: 0xd06a,
7670	data: (swap_b & ~0x7ff) | (swap_a & 0x7ff));
7671	data &= ~0x18;
7672	data |= 0x08; /* p1 */
7673	ocp_reg_write(tp, addr: 0xd068, data);
7674	swap_a = ocp_reg_read(tp, addr: 0xd06a);
7675	data &= ~0x18;
7676	data |= 0x10; /* p2 */
7677	ocp_reg_write(tp, addr: 0xd068, data);
7678	swap_b = ocp_reg_read(tp, addr: 0xd06a);
7679	data &= ~0x18;
7680	data |= 0x08; /* p1 */
7681	ocp_reg_write(tp, addr: 0xd068, data);
7682	ocp_reg_write(tp, addr: 0xd06a,
7683	data: (swap_a & ~0x7ff) | (swap_b & 0x7ff));
7684	data &= ~0x18;
7685	data |= 0x10; /* p2 */
7686	ocp_reg_write(tp, addr: 0xd068, data);
7687	ocp_reg_write(tp, addr: 0xd06a,
7688	data: (swap_b & ~0x7ff) | (swap_a & 0x7ff));
7689	swap_a = ocp_reg_read(tp, addr: 0xbd5a);
7690	swap_b = ocp_reg_read(tp, addr: 0xbd5c);
7691	ocp_reg_write(tp, addr: 0xbd5a, data: (swap_a & ~0x1f1f) |
7692	((swap_b & 0x1f) << 8) |
7693	((swap_b >> 8) & 0x1f));
7694	ocp_reg_write(tp, addr: 0xbd5c, data: (swap_b & ~0x1f1f) |
7695	((swap_a & 0x1f) << 8) |
7696	((swap_a >> 8) & 0x1f));
7697	swap_a = ocp_reg_read(tp, addr: 0xbc18);
7698	swap_b = ocp_reg_read(tp, addr: 0xbc1a);
7699	ocp_reg_write(tp, addr: 0xbc18, data: (swap_a & ~0x1f1f) |
7700	((swap_b & 0x1f) << 8) |
7701	((swap_b >> 8) & 0x1f));
7702	ocp_reg_write(tp, addr: 0xbc1a, data: (swap_b & ~0x1f1f) |
7703	((swap_a & 0x1f) << 8) |
7704	((swap_a >> 8) & 0x1f));
7705	}
7706
7707	/* Notify the MAC when the speed is changed to force mode. */
7708	data = ocp_reg_read(tp, OCP_INTR_EN);
7709	data |= INTR_SPEED_FORCE;
7710	ocp_reg_write(tp, OCP_INTR_EN, data);
7711	break;
7712	default:
7713	break;
7714	}
7715
7716	rtl_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
7717
7718	data = ocp_reg_read(tp, addr: 0xa428);
7719	data &= ~BIT(9);
7720	ocp_reg_write(tp, addr: 0xa428, data);
7721	data = ocp_reg_read(tp, addr: 0xa5ea);
7722	data &= ~BIT(0);
7723	ocp_reg_write(tp, addr: 0xa5ea, data);
7724	tp->ups_info.lite_mode = 0;
7725
7726	if (tp->eee_en)
7727	rtl_eee_enable(tp, enable: true);
7728
7729	r8153_aldps_en(tp, enable: true);
7730	r8152b_enable_fc(tp);
7731	r8153_u2p3en(tp, enable: true);
7732
7733	set_bit(nr: PHY_RESET, addr: &tp->flags);
7734	}
7735
7736	static void r8156b_hw_phy_cfg(struct r8152 *tp)
7737	{
7738	u32 ocp_data;
7739	u16 data;
7740
7741	switch (tp->version) {
7742	case RTL_VER_12:
7743	ocp_reg_write(tp, addr: 0xbf86, data: 0x9000);
7744	data = ocp_reg_read(tp, addr: 0xc402);
7745	data |= BIT(10);
7746	ocp_reg_write(tp, addr: 0xc402, data);
7747	data &= ~BIT(10);
7748	ocp_reg_write(tp, addr: 0xc402, data);
7749	ocp_reg_write(tp, addr: 0xbd86, data: 0x1010);
7750	ocp_reg_write(tp, addr: 0xbd88, data: 0x1010);
7751	data = ocp_reg_read(tp, addr: 0xbd4e);
7752	data &= ~(BIT(10) | BIT(11));
7753	data |= BIT(11);
7754	ocp_reg_write(tp, addr: 0xbd4e, data);
7755	data = ocp_reg_read(tp, addr: 0xbf46);
7756	data &= ~0xf00;
7757	data |= 0x700;
7758	ocp_reg_write(tp, addr: 0xbf46, data);
7759	break;
7760	case RTL_VER_13:
7761	case RTL_VER_15:
7762	r8156b_wait_loading_flash(tp);
7763	break;
7764	default:
7765	break;
7766	}
7767
7768	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
7769	if (ocp_data & PCUT_STATUS) {
7770	ocp_data &= ~PCUT_STATUS;
7771	ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, data: ocp_data);
7772	}
7773
7774	data = r8153_phy_status(tp, desired: 0);
7775	switch (data) {
7776	case PHY_STAT_EXT_INIT:
7777	rtl8152_apply_firmware(tp, power_cut: true);
7778
7779	data = ocp_reg_read(tp, addr: 0xa466);
7780	data &= ~BIT(0);
7781	ocp_reg_write(tp, addr: 0xa466, data);
7782
7783	data = ocp_reg_read(tp, addr: 0xa468);
7784	data &= ~(BIT(3) | BIT(1));
7785	ocp_reg_write(tp, addr: 0xa468, data);
7786	break;
7787	case PHY_STAT_LAN_ON:
7788	case PHY_STAT_PWRDN:
7789	default:
7790	rtl8152_apply_firmware(tp, power_cut: false);
7791	break;
7792	}
7793
7794	data = r8152_mdio_read(tp, MII_BMCR);
7795	if (data & BMCR_PDOWN) {
7796	data &= ~BMCR_PDOWN;
7797	r8152_mdio_write(tp, MII_BMCR, value: data);
7798	}
7799
7800	/* disable ALDPS before updating the PHY parameters */
7801	r8153_aldps_en(tp, enable: false);
7802
7803	/* disable EEE before updating the PHY parameters */
7804	rtl_eee_enable(tp, enable: false);
7805
7806	data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7807	WARN_ON_ONCE(data != PHY_STAT_LAN_ON);
7808
7809	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
7810	ocp_data |= PFM_PWM_SWITCH;
7811	ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, data: ocp_data);
7812
7813	switch (tp->version) {
7814	case RTL_VER_12:
7815	data = ocp_reg_read(tp, addr: 0xbc08);
7816	data |= BIT(3) | BIT(2);
7817	ocp_reg_write(tp, addr: 0xbc08, data);
7818
7819	data = sram_read(tp, addr: 0x8fff);
7820	data &= ~0xff00;
7821	data |= 0x0400;
7822	sram_write(tp, addr: 0x8fff, data);
7823
7824	data = ocp_reg_read(tp, addr: 0xacda);
7825	data |= 0xff00;
7826	ocp_reg_write(tp, addr: 0xacda, data);
7827	data = ocp_reg_read(tp, addr: 0xacde);
7828	data |= 0xf000;
7829	ocp_reg_write(tp, addr: 0xacde, data);
7830	ocp_reg_write(tp, addr: 0xac8c, data: 0x0ffc);
7831	ocp_reg_write(tp, addr: 0xac46, data: 0xb7b4);
7832	ocp_reg_write(tp, addr: 0xac50, data: 0x0fbc);
7833	ocp_reg_write(tp, addr: 0xac3c, data: 0x9240);
7834	ocp_reg_write(tp, addr: 0xac4e, data: 0x0db4);
7835	ocp_reg_write(tp, addr: 0xacc6, data: 0x0707);
7836	ocp_reg_write(tp, addr: 0xacc8, data: 0xa0d3);
7837	ocp_reg_write(tp, addr: 0xad08, data: 0x0007);
7838
7839	ocp_reg_write(tp, addr: 0xb87c, data: 0x8560);
7840	ocp_reg_write(tp, addr: 0xb87e, data: 0x19cc);
7841	ocp_reg_write(tp, addr: 0xb87c, data: 0x8562);
7842	ocp_reg_write(tp, addr: 0xb87e, data: 0x19cc);
7843	ocp_reg_write(tp, addr: 0xb87c, data: 0x8564);
7844	ocp_reg_write(tp, addr: 0xb87e, data: 0x19cc);
7845	ocp_reg_write(tp, addr: 0xb87c, data: 0x8566);
7846	ocp_reg_write(tp, addr: 0xb87e, data: 0x147d);
7847	ocp_reg_write(tp, addr: 0xb87c, data: 0x8568);
7848	ocp_reg_write(tp, addr: 0xb87e, data: 0x147d);
7849	ocp_reg_write(tp, addr: 0xb87c, data: 0x856a);
7850	ocp_reg_write(tp, addr: 0xb87e, data: 0x147d);
7851	ocp_reg_write(tp, addr: 0xb87c, data: 0x8ffe);
7852	ocp_reg_write(tp, addr: 0xb87e, data: 0x0907);
7853	ocp_reg_write(tp, addr: 0xb87c, data: 0x80d6);
7854	ocp_reg_write(tp, addr: 0xb87e, data: 0x2801);
7855	ocp_reg_write(tp, addr: 0xb87c, data: 0x80f2);
7856	ocp_reg_write(tp, addr: 0xb87e, data: 0x2801);
7857	ocp_reg_write(tp, addr: 0xb87c, data: 0x80f4);
7858	ocp_reg_write(tp, addr: 0xb87e, data: 0x6077);
7859	ocp_reg_write(tp, addr: 0xb506, data: 0x01e7);
7860
7861	ocp_reg_write(tp, addr: 0xb87c, data: 0x8013);
7862	ocp_reg_write(tp, addr: 0xb87e, data: 0x0700);
7863	ocp_reg_write(tp, addr: 0xb87c, data: 0x8fb9);
7864	ocp_reg_write(tp, addr: 0xb87e, data: 0x2801);
7865	ocp_reg_write(tp, addr: 0xb87c, data: 0x8fba);
7866	ocp_reg_write(tp, addr: 0xb87e, data: 0x0100);
7867	ocp_reg_write(tp, addr: 0xb87c, data: 0x8fbc);
7868	ocp_reg_write(tp, addr: 0xb87e, data: 0x1900);
7869	ocp_reg_write(tp, addr: 0xb87c, data: 0x8fbe);
7870	ocp_reg_write(tp, addr: 0xb87e, data: 0xe100);
7871	ocp_reg_write(tp, addr: 0xb87c, data: 0x8fc0);
7872	ocp_reg_write(tp, addr: 0xb87e, data: 0x0800);
7873	ocp_reg_write(tp, addr: 0xb87c, data: 0x8fc2);
7874	ocp_reg_write(tp, addr: 0xb87e, data: 0xe500);
7875	ocp_reg_write(tp, addr: 0xb87c, data: 0x8fc4);
7876	ocp_reg_write(tp, addr: 0xb87e, data: 0x0f00);
7877	ocp_reg_write(tp, addr: 0xb87c, data: 0x8fc6);
7878	ocp_reg_write(tp, addr: 0xb87e, data: 0xf100);
7879	ocp_reg_write(tp, addr: 0xb87c, data: 0x8fc8);
7880	ocp_reg_write(tp, addr: 0xb87e, data: 0x0400);
7881	ocp_reg_write(tp, addr: 0xb87c, data: 0x8fca);
7882	ocp_reg_write(tp, addr: 0xb87e, data: 0xf300);
7883	ocp_reg_write(tp, addr: 0xb87c, data: 0x8fcc);
7884	ocp_reg_write(tp, addr: 0xb87e, data: 0xfd00);
7885	ocp_reg_write(tp, addr: 0xb87c, data: 0x8fce);
7886	ocp_reg_write(tp, addr: 0xb87e, data: 0xff00);
7887	ocp_reg_write(tp, addr: 0xb87c, data: 0x8fd0);
7888	ocp_reg_write(tp, addr: 0xb87e, data: 0xfb00);
7889	ocp_reg_write(tp, addr: 0xb87c, data: 0x8fd2);
7890	ocp_reg_write(tp, addr: 0xb87e, data: 0x0100);
7891	ocp_reg_write(tp, addr: 0xb87c, data: 0x8fd4);
7892	ocp_reg_write(tp, addr: 0xb87e, data: 0xf400);
7893	ocp_reg_write(tp, addr: 0xb87c, data: 0x8fd6);
7894	ocp_reg_write(tp, addr: 0xb87e, data: 0xff00);
7895	ocp_reg_write(tp, addr: 0xb87c, data: 0x8fd8);
7896	ocp_reg_write(tp, addr: 0xb87e, data: 0xf600);
7897
7898	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_USB_CFG);
7899	ocp_data |= EN_XG_LIP | EN_G_LIP;
7900	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_USB_CFG, data: ocp_data);
7901	ocp_reg_write(tp, addr: 0xb87c, data: 0x813d);
7902	ocp_reg_write(tp, addr: 0xb87e, data: 0x390e);
7903	ocp_reg_write(tp, addr: 0xb87c, data: 0x814f);
7904	ocp_reg_write(tp, addr: 0xb87e, data: 0x790e);
7905	ocp_reg_write(tp, addr: 0xb87c, data: 0x80b0);
7906	ocp_reg_write(tp, addr: 0xb87e, data: 0x0f31);
7907	data = ocp_reg_read(tp, addr: 0xbf4c);
7908	data |= BIT(1);
7909	ocp_reg_write(tp, addr: 0xbf4c, data);
7910	data = ocp_reg_read(tp, addr: 0xbcca);
7911	data |= BIT(9) | BIT(8);
7912	ocp_reg_write(tp, addr: 0xbcca, data);
7913	ocp_reg_write(tp, addr: 0xb87c, data: 0x8141);
7914	ocp_reg_write(tp, addr: 0xb87e, data: 0x320e);
7915	ocp_reg_write(tp, addr: 0xb87c, data: 0x8153);
7916	ocp_reg_write(tp, addr: 0xb87e, data: 0x720e);
7917	ocp_reg_write(tp, addr: 0xb87c, data: 0x8529);
7918	ocp_reg_write(tp, addr: 0xb87e, data: 0x050e);
7919	data = ocp_reg_read(tp, OCP_EEE_CFG);
7920	data &= ~CTAP_SHORT_EN;
7921	ocp_reg_write(tp, OCP_EEE_CFG, data);
7922
7923	sram_write(tp, addr: 0x816c, data: 0xc4a0);
7924	sram_write(tp, addr: 0x8170, data: 0xc4a0);
7925	sram_write(tp, addr: 0x8174, data: 0x04a0);
7926	sram_write(tp, addr: 0x8178, data: 0x04a0);
7927	sram_write(tp, addr: 0x817c, data: 0x0719);
7928	sram_write(tp, addr: 0x8ff4, data: 0x0400);
7929	sram_write(tp, addr: 0x8ff1, data: 0x0404);
7930
7931	ocp_reg_write(tp, addr: 0xbf4a, data: 0x001b);
7932	ocp_reg_write(tp, addr: 0xb87c, data: 0x8033);
7933	ocp_reg_write(tp, addr: 0xb87e, data: 0x7c13);
7934	ocp_reg_write(tp, addr: 0xb87c, data: 0x8037);
7935	ocp_reg_write(tp, addr: 0xb87e, data: 0x7c13);
7936	ocp_reg_write(tp, addr: 0xb87c, data: 0x803b);
7937	ocp_reg_write(tp, addr: 0xb87e, data: 0xfc32);
7938	ocp_reg_write(tp, addr: 0xb87c, data: 0x803f);
7939	ocp_reg_write(tp, addr: 0xb87e, data: 0x7c13);
7940	ocp_reg_write(tp, addr: 0xb87c, data: 0x8043);
7941	ocp_reg_write(tp, addr: 0xb87e, data: 0x7c13);
7942	ocp_reg_write(tp, addr: 0xb87c, data: 0x8047);
7943	ocp_reg_write(tp, addr: 0xb87e, data: 0x7c13);
7944
7945	ocp_reg_write(tp, addr: 0xb87c, data: 0x8145);
7946	ocp_reg_write(tp, addr: 0xb87e, data: 0x370e);
7947	ocp_reg_write(tp, addr: 0xb87c, data: 0x8157);
7948	ocp_reg_write(tp, addr: 0xb87e, data: 0x770e);
7949	ocp_reg_write(tp, addr: 0xb87c, data: 0x8169);
7950	ocp_reg_write(tp, addr: 0xb87e, data: 0x0d0a);
7951	ocp_reg_write(tp, addr: 0xb87c, data: 0x817b);
7952	ocp_reg_write(tp, addr: 0xb87e, data: 0x1d0a);
7953
7954	data = sram_read(tp, addr: 0x8217);
7955	data &= ~0xff00;
7956	data |= 0x5000;
7957	sram_write(tp, addr: 0x8217, data);
7958	data = sram_read(tp, addr: 0x821a);
7959	data &= ~0xff00;
7960	data |= 0x5000;
7961	sram_write(tp, addr: 0x821a, data);
7962	sram_write(tp, addr: 0x80da, data: 0x0403);
7963	data = sram_read(tp, addr: 0x80dc);
7964	data &= ~0xff00;
7965	data |= 0x1000;
7966	sram_write(tp, addr: 0x80dc, data);
7967	sram_write(tp, addr: 0x80b3, data: 0x0384);
7968	sram_write(tp, addr: 0x80b7, data: 0x2007);
7969	data = sram_read(tp, addr: 0x80ba);
7970	data &= ~0xff00;
7971	data |= 0x6c00;
7972	sram_write(tp, addr: 0x80ba, data);
7973	sram_write(tp, addr: 0x80b5, data: 0xf009);
7974	data = sram_read(tp, addr: 0x80bd);
7975	data &= ~0xff00;
7976	data |= 0x9f00;
7977	sram_write(tp, addr: 0x80bd, data);
7978	sram_write(tp, addr: 0x80c7, data: 0xf083);
7979	sram_write(tp, addr: 0x80dd, data: 0x03f0);
7980	data = sram_read(tp, addr: 0x80df);
7981	data &= ~0xff00;
7982	data |= 0x1000;
7983	sram_write(tp, addr: 0x80df, data);
7984	sram_write(tp, addr: 0x80cb, data: 0x2007);
7985	data = sram_read(tp, addr: 0x80ce);
7986	data &= ~0xff00;
7987	data |= 0x6c00;
7988	sram_write(tp, addr: 0x80ce, data);
7989	sram_write(tp, addr: 0x80c9, data: 0x8009);
7990	data = sram_read(tp, addr: 0x80d1);
7991	data &= ~0xff00;
7992	data |= 0x8000;
7993	sram_write(tp, addr: 0x80d1, data);
7994	sram_write(tp, addr: 0x80a3, data: 0x200a);
7995	sram_write(tp, addr: 0x80a5, data: 0xf0ad);
7996	sram_write(tp, addr: 0x809f, data: 0x6073);
7997	sram_write(tp, addr: 0x80a1, data: 0x000b);
7998	data = sram_read(tp, addr: 0x80a9);
7999	data &= ~0xff00;
8000	data |= 0xc000;
8001	sram_write(tp, addr: 0x80a9, data);
8002
8003	if (rtl_phy_patch_request(tp, request: true, wait: true))
8004	return;
8005
8006	data = ocp_reg_read(tp, addr: 0xb896);
8007	data &= ~BIT(0);
8008	ocp_reg_write(tp, addr: 0xb896, data);
8009	data = ocp_reg_read(tp, addr: 0xb892);
8010	data &= ~0xff00;
8011	ocp_reg_write(tp, addr: 0xb892, data);
8012	ocp_reg_write(tp, addr: 0xb88e, data: 0xc23e);
8013	ocp_reg_write(tp, addr: 0xb890, data: 0x0000);
8014	ocp_reg_write(tp, addr: 0xb88e, data: 0xc240);
8015	ocp_reg_write(tp, addr: 0xb890, data: 0x0103);
8016	ocp_reg_write(tp, addr: 0xb88e, data: 0xc242);
8017	ocp_reg_write(tp, addr: 0xb890, data: 0x0507);
8018	ocp_reg_write(tp, addr: 0xb88e, data: 0xc244);
8019	ocp_reg_write(tp, addr: 0xb890, data: 0x090b);
8020	ocp_reg_write(tp, addr: 0xb88e, data: 0xc246);
8021	ocp_reg_write(tp, addr: 0xb890, data: 0x0c0e);
8022	ocp_reg_write(tp, addr: 0xb88e, data: 0xc248);
8023	ocp_reg_write(tp, addr: 0xb890, data: 0x1012);
8024	ocp_reg_write(tp, addr: 0xb88e, data: 0xc24a);
8025	ocp_reg_write(tp, addr: 0xb890, data: 0x1416);
8026	data = ocp_reg_read(tp, addr: 0xb896);
8027	data |= BIT(0);
8028	ocp_reg_write(tp, addr: 0xb896, data);
8029
8030	rtl_phy_patch_request(tp, request: false, wait: true);
8031
8032	data = ocp_reg_read(tp, addr: 0xa86a);
8033	data |= BIT(0);
8034	ocp_reg_write(tp, addr: 0xa86a, data);
8035	data = ocp_reg_read(tp, addr: 0xa6f0);
8036	data |= BIT(0);
8037	ocp_reg_write(tp, addr: 0xa6f0, data);
8038
8039	ocp_reg_write(tp, addr: 0xbfa0, data: 0xd70d);
8040	ocp_reg_write(tp, addr: 0xbfa2, data: 0x4100);
8041	ocp_reg_write(tp, addr: 0xbfa4, data: 0xe868);
8042	ocp_reg_write(tp, addr: 0xbfa6, data: 0xdc59);
8043	ocp_reg_write(tp, addr: 0xb54c, data: 0x3c18);
8044	data = ocp_reg_read(tp, addr: 0xbfa4);
8045	data &= ~BIT(5);
8046	ocp_reg_write(tp, addr: 0xbfa4, data);
8047	data = sram_read(tp, addr: 0x817d);
8048	data |= BIT(12);
8049	sram_write(tp, addr: 0x817d, data);
8050	break;
8051	case RTL_VER_13:
8052	/* 2.5G INRX */
8053	data = ocp_reg_read(tp, addr: 0xac46);
8054	data &= ~0x00f0;
8055	data |= 0x0090;
8056	ocp_reg_write(tp, addr: 0xac46, data);
8057	data = ocp_reg_read(tp, addr: 0xad30);
8058	data &= ~0x0003;
8059	data |= 0x0001;
8060	ocp_reg_write(tp, addr: 0xad30, data);
8061	fallthrough;
8062	case RTL_VER_15:
8063	/* EEE parameter */
8064	ocp_reg_write(tp, addr: 0xb87c, data: 0x80f5);
8065	ocp_reg_write(tp, addr: 0xb87e, data: 0x760e);
8066	ocp_reg_write(tp, addr: 0xb87c, data: 0x8107);
8067	ocp_reg_write(tp, addr: 0xb87e, data: 0x360e);
8068	ocp_reg_write(tp, addr: 0xb87c, data: 0x8551);
8069	data = ocp_reg_read(tp, addr: 0xb87e);
8070	data &= ~0xff00;
8071	data |= 0x0800;
8072	ocp_reg_write(tp, addr: 0xb87e, data);
8073
8074	/* ADC_PGA parameter */
8075	data = ocp_reg_read(tp, addr: 0xbf00);
8076	data &= ~0xe000;
8077	data |= 0xa000;
8078	ocp_reg_write(tp, addr: 0xbf00, data);
8079	data = ocp_reg_read(tp, addr: 0xbf46);
8080	data &= ~0x0f00;
8081	data |= 0x0300;
8082	ocp_reg_write(tp, addr: 0xbf46, data);
8083
8084	/* Green Table-PGA, 1G full viterbi */
8085	sram_write(tp, addr: 0x8044, data: 0x2417);
8086	sram_write(tp, addr: 0x804a, data: 0x2417);
8087	sram_write(tp, addr: 0x8050, data: 0x2417);
8088	sram_write(tp, addr: 0x8056, data: 0x2417);
8089	sram_write(tp, addr: 0x805c, data: 0x2417);
8090	sram_write(tp, addr: 0x8062, data: 0x2417);
8091	sram_write(tp, addr: 0x8068, data: 0x2417);
8092	sram_write(tp, addr: 0x806e, data: 0x2417);
8093	sram_write(tp, addr: 0x8074, data: 0x2417);
8094	sram_write(tp, addr: 0x807a, data: 0x2417);
8095
8096	/* XG PLL */
8097	data = ocp_reg_read(tp, addr: 0xbf84);
8098	data &= ~0xe000;
8099	data |= 0xa000;
8100	ocp_reg_write(tp, addr: 0xbf84, data);
8101	break;
8102	default:
8103	break;
8104	}
8105
8106	/* Notify the MAC when the speed is changed to force mode. */
8107	data = ocp_reg_read(tp, OCP_INTR_EN);
8108	data |= INTR_SPEED_FORCE;
8109	ocp_reg_write(tp, OCP_INTR_EN, data);
8110
8111	if (rtl_phy_patch_request(tp, request: true, wait: true))
8112	return;
8113
8114	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
8115	ocp_data |= EEE_SPDWN_EN;
8116	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, data: ocp_data);
8117
8118	data = ocp_reg_read(tp, OCP_DOWN_SPEED);
8119	data &= ~(EN_EEE_100 | EN_EEE_1000);
8120	data |= EN_10M_CLKDIV;
8121	ocp_reg_write(tp, OCP_DOWN_SPEED, data);
8122	tp->ups_info._10m_ckdiv = true;
8123	tp->ups_info.eee_plloff_100 = false;
8124	tp->ups_info.eee_plloff_giga = false;
8125
8126	data = ocp_reg_read(tp, OCP_POWER_CFG);
8127	data &= ~EEE_CLKDIV_EN;
8128	ocp_reg_write(tp, OCP_POWER_CFG, data);
8129	tp->ups_info.eee_ckdiv = false;
8130
8131	rtl_phy_patch_request(tp, request: false, wait: true);
8132
8133	rtl_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
8134
8135	data = ocp_reg_read(tp, addr: 0xa428);
8136	data &= ~BIT(9);
8137	ocp_reg_write(tp, addr: 0xa428, data);
8138	data = ocp_reg_read(tp, addr: 0xa5ea);
8139	data &= ~BIT(0);
8140	ocp_reg_write(tp, addr: 0xa5ea, data);
8141	tp->ups_info.lite_mode = 0;
8142
8143	if (tp->eee_en)
8144	rtl_eee_enable(tp, enable: true);
8145
8146	r8153_aldps_en(tp, enable: true);
8147	r8152b_enable_fc(tp);
8148	r8153_u2p3en(tp, enable: true);
8149
8150	set_bit(nr: PHY_RESET, addr: &tp->flags);
8151	}
8152
8153	static void r8156_init(struct r8152 *tp)
8154	{
8155	u32 ocp_data;
8156	u16 data;
8157	int i;
8158
8159	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
8160	return;
8161
8162	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_ECM_OP);
8163	ocp_data &= ~EN_ALL_SPEED;
8164	ocp_write_byte(tp, MCU_TYPE_USB, USB_ECM_OP, data: ocp_data);
8165
8166	ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, data: 0);
8167
8168	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_ECM_OPTION);
8169	ocp_data |= BYPASS_MAC_RESET;
8170	ocp_write_word(tp, MCU_TYPE_USB, USB_ECM_OPTION, data: ocp_data);
8171
8172	r8153b_u1u2en(tp, enable: false);
8173
8174	for (i = 0; i < 500; i++) {
8175	if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
8176	AUTOLOAD_DONE)
8177	break;
8178
8179	msleep(msecs: 20);
8180	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
8181	return;
8182	}
8183
8184	data = r8153_phy_status(tp, desired: 0);
8185	if (data == PHY_STAT_EXT_INIT) {
8186	data = ocp_reg_read(tp, addr: 0xa468);
8187	data &= ~(BIT(3) | BIT(1));
8188	ocp_reg_write(tp, addr: 0xa468, data);
8189	}
8190
8191	data = r8152_mdio_read(tp, MII_BMCR);
8192	if (data & BMCR_PDOWN) {
8193	data &= ~BMCR_PDOWN;
8194	r8152_mdio_write(tp, MII_BMCR, value: data);
8195	}
8196
8197	data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
8198	WARN_ON_ONCE(data != PHY_STAT_LAN_ON);
8199
8200	r8153_u2p3en(tp, enable: false);
8201
8202	/* MSC timer = 0xfff * 8ms = 32760 ms */
8203	ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, data: 0x0fff);
8204
8205	/* U1/U2/L1 idle timer. 500 us */
8206	ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, data: 500);
8207
8208	r8153b_power_cut_en(tp, enable: false);
8209	r8156_ups_en(tp, enable: false);
8210	r8153_queue_wake(tp, enable: false);
8211	rtl_runtime_suspend_enable(tp, enable: false);
8212
8213	if (tp->udev->speed >= USB_SPEED_SUPER)
8214	r8153b_u1u2en(tp, enable: true);
8215
8216	usb_enable_lpm(udev: tp->udev);
8217
8218	r8156_mac_clk_spd(tp, enable: true);
8219
8220	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
8221	ocp_data &= ~PLA_MCU_SPDWN_EN;
8222	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, data: ocp_data);
8223
8224	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
8225	if (rtl8152_get_speed(tp) & LINK_STATUS)
8226	ocp_data |= CUR_LINK_OK;
8227	else
8228	ocp_data &= ~CUR_LINK_OK;
8229	ocp_data |= POLL_LINK_CHG;
8230	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, data: ocp_data);
8231
8232	set_bit(nr: GREEN_ETHERNET, addr: &tp->flags);
8233
8234	/* rx aggregation */
8235	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
8236	ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
8237	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, data: ocp_data);
8238
8239	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_CONFIG);
8240	ocp_data |= ACT_ODMA;
8241	ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_CONFIG, data: ocp_data);
8242
8243	r8156_mdio_force_mode(tp);
8244	rtl_tally_reset(tp);
8245
8246	tp->coalesce = 15000; /* 15 us */
8247	}
8248
8249	static void r8156b_init(struct r8152 *tp)
8250	{
8251	u32 ocp_data;
8252	u16 data;
8253	int i;
8254
8255	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
8256	return;
8257
8258	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_ECM_OP);
8259	ocp_data &= ~EN_ALL_SPEED;
8260	ocp_write_byte(tp, MCU_TYPE_USB, USB_ECM_OP, data: ocp_data);
8261
8262	ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, data: 0);
8263
8264	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_ECM_OPTION);
8265	ocp_data |= BYPASS_MAC_RESET;
8266	ocp_write_word(tp, MCU_TYPE_USB, USB_ECM_OPTION, data: ocp_data);
8267
8268	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
8269	ocp_data |= RX_DETECT8;
8270	ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, data: ocp_data);
8271
8272	r8153b_u1u2en(tp, enable: false);
8273
8274	switch (tp->version) {
8275	case RTL_VER_13:
8276	case RTL_VER_15:
8277	r8156b_wait_loading_flash(tp);
8278	break;
8279	default:
8280	break;
8281	}
8282
8283	for (i = 0; i < 500; i++) {
8284	if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
8285	AUTOLOAD_DONE)
8286	break;
8287
8288	msleep(msecs: 20);
8289	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
8290	return;
8291	}
8292
8293	data = r8153_phy_status(tp, desired: 0);
8294	if (data == PHY_STAT_EXT_INIT) {
8295	data = ocp_reg_read(tp, addr: 0xa468);
8296	data &= ~(BIT(3) | BIT(1));
8297	ocp_reg_write(tp, addr: 0xa468, data);
8298
8299	data = ocp_reg_read(tp, addr: 0xa466);
8300	data &= ~BIT(0);
8301	ocp_reg_write(tp, addr: 0xa466, data);
8302	}
8303
8304	data = r8152_mdio_read(tp, MII_BMCR);
8305	if (data & BMCR_PDOWN) {
8306	data &= ~BMCR_PDOWN;
8307	r8152_mdio_write(tp, MII_BMCR, value: data);
8308	}
8309
8310	data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
8311
8312	r8153_u2p3en(tp, enable: false);
8313
8314	/* MSC timer = 0xfff * 8ms = 32760 ms */
8315	ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, data: 0x0fff);
8316
8317	/* U1/U2/L1 idle timer. 500 us */
8318	ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, data: 500);
8319
8320	r8153b_power_cut_en(tp, enable: false);
8321	r8156_ups_en(tp, enable: false);
8322	r8153_queue_wake(tp, enable: false);
8323	rtl_runtime_suspend_enable(tp, enable: false);
8324
8325	if (tp->udev->speed >= USB_SPEED_SUPER)
8326	r8153b_u1u2en(tp, enable: true);
8327
8328	usb_enable_lpm(udev: tp->udev);
8329
8330	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RCR);
8331	ocp_data &= ~SLOT_EN;
8332	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RCR, data: ocp_data);
8333
8334	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
8335	ocp_data |= FLOW_CTRL_EN;
8336	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, data: ocp_data);
8337
8338	/* enable fc timer and set timer to 600 ms. */
8339	ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER,
8340	CTRL_TIMER_EN | (600 / 8));
8341
8342	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
8343	if (!(ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL) & DACK_DET_EN))
8344	ocp_data |= FLOW_CTRL_PATCH_2;
8345	ocp_data &= ~AUTO_SPEEDUP;
8346	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, data: ocp_data);
8347
8348	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
8349	ocp_data |= FC_PATCH_TASK;
8350	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, data: ocp_data);
8351
8352	r8156_mac_clk_spd(tp, enable: true);
8353
8354	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
8355	ocp_data &= ~PLA_MCU_SPDWN_EN;
8356	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, data: ocp_data);
8357
8358	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
8359	if (rtl8152_get_speed(tp) & LINK_STATUS)
8360	ocp_data |= CUR_LINK_OK;
8361	else
8362	ocp_data &= ~CUR_LINK_OK;
8363	ocp_data |= POLL_LINK_CHG;
8364	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, data: ocp_data);
8365
8366	set_bit(nr: GREEN_ETHERNET, addr: &tp->flags);
8367
8368	/* rx aggregation */
8369	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
8370	ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
8371	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, data: ocp_data);
8372
8373	r8156_mdio_force_mode(tp);
8374	rtl_tally_reset(tp);
8375
8376	tp->coalesce = 15000; /* 15 us */
8377	}
8378
8379	static bool rtl_check_vendor_ok(struct usb_interface *intf)
8380	{
8381	struct usb_host_interface *alt = intf->cur_altsetting;
8382	struct usb_endpoint_descriptor *in, *out, *intr;
8383
8384	if (usb_find_common_endpoints(alt, bulk_in: &in, bulk_out: &out, int_in: &intr, NULL) < 0) {
8385	dev_err(&intf->dev, "Expected endpoints are not found\n");
8386	return false;
8387	}
8388
8389	/* Check Rx endpoint address */
8390	if (usb_endpoint_num(epd: in) != 1) {
8391	dev_err(&intf->dev, "Invalid Rx endpoint address\n");
8392	return false;
8393	}
8394
8395	/* Check Tx endpoint address */
8396	if (usb_endpoint_num(epd: out) != 2) {
8397	dev_err(&intf->dev, "Invalid Tx endpoint address\n");
8398	return false;
8399	}
8400
8401	/* Check interrupt endpoint address */
8402	if (usb_endpoint_num(epd: intr) != 3) {
8403	dev_err(&intf->dev, "Invalid interrupt endpoint address\n");
8404	return false;
8405	}
8406
8407	return true;
8408	}
8409
8410	static int rtl8152_pre_reset(struct usb_interface *intf)
8411	{
8412	struct r8152 *tp = usb_get_intfdata(intf);
8413	struct net_device *netdev;
8414
8415	rtnl_lock();
8416
8417	if (!tp || !test_bit(PROBED_WITH_NO_ERRORS, &tp->flags))
8418	return 0;
8419
8420	netdev = tp->netdev;
8421	if (!netif_running(dev: netdev))
8422	return 0;
8423
8424	netif_stop_queue(dev: netdev);
8425	tasklet_disable(t: &tp->tx_tl);
8426	clear_bit(nr: WORK_ENABLE, addr: &tp->flags);
8427	usb_kill_urb(urb: tp->intr_urb);
8428	cancel_delayed_work_sync(dwork: &tp->schedule);
8429	napi_disable(n: &tp->napi);
8430	if (netif_carrier_ok(dev: netdev)) {
8431	mutex_lock(&tp->control);
8432	set_bit(nr: IN_PRE_RESET, addr: &tp->flags);
8433	tp->rtl_ops.disable(tp);
8434	clear_bit(nr: IN_PRE_RESET, addr: &tp->flags);
8435	mutex_unlock(lock: &tp->control);
8436	}
8437
8438	return 0;
8439	}
8440
8441	static int rtl8152_post_reset(struct usb_interface *intf)
8442	{
8443	struct r8152 *tp = usb_get_intfdata(intf);
8444	struct net_device *netdev;
8445	struct sockaddr sa;
8446
8447	if (!tp || !test_bit(PROBED_WITH_NO_ERRORS, &tp->flags))
8448	goto exit;
8449
8450	rtl_set_accessible(tp);
8451
8452	/* reset the MAC address in case of policy change */
8453	if (determine_ethernet_addr(tp, sa: &sa) >= 0)
8454	dev_set_mac_address (dev: tp->netdev, sa: &sa, NULL);
8455
8456	netdev = tp->netdev;
8457	if (!netif_running(dev: netdev))
8458	goto exit;
8459
8460	set_bit(nr: WORK_ENABLE, addr: &tp->flags);
8461	if (netif_carrier_ok(dev: netdev)) {
8462	mutex_lock(&tp->control);
8463	tp->rtl_ops.enable(tp);
8464	rtl_start_rx(tp);
8465	_rtl8152_set_rx_mode(netdev);
8466	mutex_unlock(lock: &tp->control);
8467	}
8468
8469	napi_enable(n: &tp->napi);
8470	tasklet_enable(t: &tp->tx_tl);
8471	netif_wake_queue(dev: netdev);
8472	usb_submit_urb(urb: tp->intr_urb, GFP_KERNEL);
8473
8474	if (!list_empty(head: &tp->rx_done))
8475	napi_schedule(n: &tp->napi);
8476
8477	exit:
8478	rtnl_unlock();
8479	return 0;
8480	}
8481
8482	static bool delay_autosuspend(struct r8152 *tp)
8483	{
8484	bool sw_linking = !!netif_carrier_ok(dev: tp->netdev);
8485	bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS);
8486
8487	/* This means a linking change occurs and the driver doesn't detect it,
8488	* yet. If the driver has disabled tx/rx and hw is linking on, the
8489	* device wouldn't wake up by receiving any packet.
8490	*/
8491	if (work_busy(work: &tp->schedule.work) || sw_linking != hw_linking)
8492	return true;
8493
8494	/* If the linking down is occurred by nway, the device may miss the
8495	* linking change event. And it wouldn't wake when linking on.
8496	*/
8497	if (!sw_linking && tp->rtl_ops.in_nway(tp))
8498	return true;
8499	else if (!skb_queue_empty(list: &tp->tx_queue))
8500	return true;
8501	else
8502	return false;
8503	}
8504
8505	static int rtl8152_runtime_resume(struct r8152 *tp)
8506	{
8507	struct net_device *netdev = tp->netdev;
8508
8509	if (netif_running(dev: netdev) && netdev->flags & IFF_UP) {
8510	struct napi_struct *napi = &tp->napi;
8511
8512	tp->rtl_ops.autosuspend_en(tp, false);
8513	napi_disable(n: napi);
8514	set_bit(nr: WORK_ENABLE, addr: &tp->flags);
8515
8516	if (netif_carrier_ok(dev: netdev)) {
8517	if (rtl8152_get_speed(tp) & LINK_STATUS) {
8518	rtl_start_rx(tp);
8519	} else {
8520	netif_carrier_off(dev: netdev);
8521	tp->rtl_ops.disable(tp);
8522	netif_info(tp, link, netdev, "linking down\n");
8523	}
8524	}
8525
8526	napi_enable(n: napi);
8527	clear_bit(nr: SELECTIVE_SUSPEND, addr: &tp->flags);
8528	smp_mb__after_atomic();
8529
8530	if (!list_empty(head: &tp->rx_done))
8531	napi_schedule(n: &tp->napi);
8532
8533	usb_submit_urb(urb: tp->intr_urb, GFP_NOIO);
8534	} else {
8535	if (netdev->flags & IFF_UP)
8536	tp->rtl_ops.autosuspend_en(tp, false);
8537
8538	clear_bit(nr: SELECTIVE_SUSPEND, addr: &tp->flags);
8539	}
8540
8541	return 0;
8542	}
8543
8544	static int rtl8152_system_resume(struct r8152 *tp)
8545	{
8546	struct net_device *netdev = tp->netdev;
8547
8548	netif_device_attach(dev: netdev);
8549
8550	if (netif_running(dev: netdev) && (netdev->flags & IFF_UP)) {
8551	tp->rtl_ops.up(tp);
8552	netif_carrier_off(dev: netdev);
8553	set_bit(nr: WORK_ENABLE, addr: &tp->flags);
8554	usb_submit_urb(urb: tp->intr_urb, GFP_NOIO);
8555	}
8556
8557	return 0;
8558	}
8559
8560	static int rtl8152_runtime_suspend(struct r8152 *tp)
8561	{
8562	struct net_device *netdev = tp->netdev;
8563	int ret = 0;
8564
8565	if (!tp->rtl_ops.autosuspend_en)
8566	return -EBUSY;
8567
8568	set_bit(nr: SELECTIVE_SUSPEND, addr: &tp->flags);
8569	smp_mb__after_atomic();
8570
8571	if (netif_running(dev: netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
8572	u32 rcr = 0;
8573
8574	if (netif_carrier_ok(dev: netdev)) {
8575	u32 ocp_data;
8576
8577	rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
8578	ocp_data = rcr & ~RCR_ACPT_ALL;
8579	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, data: ocp_data);
8580	rxdy_gated_en(tp, enable: true);
8581	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA,
8582	PLA_OOB_CTRL);
8583	if (!(ocp_data & RXFIFO_EMPTY)) {
8584	rxdy_gated_en(tp, enable: false);
8585	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, data: rcr);
8586	clear_bit(nr: SELECTIVE_SUSPEND, addr: &tp->flags);
8587	smp_mb__after_atomic();
8588	ret = -EBUSY;
8589	goto out1;
8590	}
8591	}
8592
8593	clear_bit(nr: WORK_ENABLE, addr: &tp->flags);
8594	usb_kill_urb(urb: tp->intr_urb);
8595
8596	tp->rtl_ops.autosuspend_en(tp, true);
8597
8598	if (netif_carrier_ok(dev: netdev)) {
8599	struct napi_struct *napi = &tp->napi;
8600
8601	napi_disable(n: napi);
8602	rtl_stop_rx(tp);
8603	rxdy_gated_en(tp, enable: false);
8604	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, data: rcr);
8605	napi_enable(n: napi);
8606	}
8607
8608	if (delay_autosuspend(tp)) {
8609	rtl8152_runtime_resume(tp);
8610	ret = -EBUSY;
8611	}
8612	}
8613
8614	out1:
8615	return ret;
8616	}
8617
8618	static int rtl8152_system_suspend(struct r8152 *tp)
8619	{
8620	struct net_device *netdev = tp->netdev;
8621
8622	netif_device_detach(dev: netdev);
8623
8624	if (netif_running(dev: netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
8625	struct napi_struct *napi = &tp->napi;
8626
8627	clear_bit(nr: WORK_ENABLE, addr: &tp->flags);
8628	usb_kill_urb(urb: tp->intr_urb);
8629	tasklet_disable(t: &tp->tx_tl);
8630	napi_disable(n: napi);
8631	cancel_delayed_work_sync(dwork: &tp->schedule);
8632	tp->rtl_ops.down(tp);
8633	napi_enable(n: napi);
8634	tasklet_enable(t: &tp->tx_tl);
8635	}
8636
8637	return 0;
8638	}
8639
8640	static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
8641	{
8642	struct r8152 *tp = usb_get_intfdata(intf);
8643	int ret;
8644
8645	mutex_lock(&tp->control);
8646
8647	if (PMSG_IS_AUTO(message))
8648	ret = rtl8152_runtime_suspend(tp);
8649	else
8650	ret = rtl8152_system_suspend(tp);
8651
8652	mutex_unlock(lock: &tp->control);
8653
8654	return ret;
8655	}
8656
8657	static int rtl8152_resume(struct usb_interface *intf)
8658	{
8659	struct r8152 *tp = usb_get_intfdata(intf);
8660	int ret;
8661
8662	mutex_lock(&tp->control);
8663
8664	rtl_reset_ocp_base(tp);
8665
8666	if (test_bit(SELECTIVE_SUSPEND, &tp->flags))
8667	ret = rtl8152_runtime_resume(tp);
8668	else
8669	ret = rtl8152_system_resume(tp);
8670
8671	mutex_unlock(lock: &tp->control);
8672
8673	return ret;
8674	}
8675
8676	static int rtl8152_reset_resume(struct usb_interface *intf)
8677	{
8678	struct r8152 *tp = usb_get_intfdata(intf);
8679
8680	clear_bit(nr: SELECTIVE_SUSPEND, addr: &tp->flags);
8681	rtl_reset_ocp_base(tp);
8682	tp->rtl_ops.init(tp);
8683	queue_delayed_work(wq: system_long_wq, dwork: &tp->hw_phy_work, delay: 0);
8684	set_ethernet_addr(tp, in_resume: true);
8685	return rtl8152_resume(intf);
8686	}
8687
8688	static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8689	{
8690	struct r8152 *tp = netdev_priv(dev);
8691
8692	if (usb_autopm_get_interface(intf: tp->intf) < 0)
8693	return;
8694
8695	if (!rtl_can_wakeup(tp)) {
8696	wol->supported = 0;
8697	wol->wolopts = 0;
8698	} else {
8699	mutex_lock(&tp->control);
8700	wol->supported = WAKE_ANY;
8701	wol->wolopts = __rtl_get_wol(tp);
8702	mutex_unlock(lock: &tp->control);
8703	}
8704
8705	usb_autopm_put_interface(intf: tp->intf);
8706	}
8707
8708	static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8709	{
8710	struct r8152 *tp = netdev_priv(dev);
8711	int ret;
8712
8713	if (!rtl_can_wakeup(tp))
8714	return -EOPNOTSUPP;
8715
8716	if (wol->wolopts & ~WAKE_ANY)
8717	return -EINVAL;
8718
8719	ret = usb_autopm_get_interface(intf: tp->intf);
8720	if (ret < 0)
8721	goto out_set_wol;
8722
8723	mutex_lock(&tp->control);
8724
8725	__rtl_set_wol(tp, wolopts: wol->wolopts);
8726	tp->saved_wolopts = wol->wolopts & WAKE_ANY;
8727
8728	mutex_unlock(lock: &tp->control);
8729
8730	usb_autopm_put_interface(intf: tp->intf);
8731
8732	out_set_wol:
8733	return ret;
8734	}
8735
8736	static u32 rtl8152_get_msglevel(struct net_device *dev)
8737	{
8738	struct r8152 *tp = netdev_priv(dev);
8739
8740	return tp->msg_enable;
8741	}
8742
8743	static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
8744	{
8745	struct r8152 *tp = netdev_priv(dev);
8746
8747	tp->msg_enable = value;
8748	}
8749
8750	static void rtl8152_get_drvinfo(struct net_device *netdev,
8751	struct ethtool_drvinfo *info)
8752	{
8753	struct r8152 *tp = netdev_priv(dev: netdev);
8754
8755	strscpy(info->driver, MODULENAME, sizeof(info->driver));
8756	strscpy(info->version, DRIVER_VERSION, sizeof(info->version));
8757	usb_make_path(dev: tp->udev, buf: info->bus_info, size: sizeof(info->bus_info));
8758	if (!IS_ERR_OR_NULL(ptr: tp->rtl_fw.fw))
8759	strscpy(info->fw_version, tp->rtl_fw.version,
8760	sizeof(info->fw_version));
8761	}
8762
8763	static
8764	int rtl8152_get_link_ksettings(struct net_device *netdev,
8765	struct ethtool_link_ksettings *cmd)
8766	{
8767	struct r8152 *tp = netdev_priv(dev: netdev);
8768	int ret;
8769
8770	if (!tp->mii.mdio_read)
8771	return -EOPNOTSUPP;
8772
8773	ret = usb_autopm_get_interface(intf: tp->intf);
8774	if (ret < 0)
8775	goto out;
8776
8777	mutex_lock(&tp->control);
8778
8779	mii_ethtool_get_link_ksettings(mii: &tp->mii, cmd);
8780
8781	linkmode_mod_bit(nr: ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
8782	addr: cmd->link_modes.supported, set: tp->support_2500full);
8783
8784	if (tp->support_2500full) {
8785	linkmode_mod_bit(nr: ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
8786	addr: cmd->link_modes.advertising,
8787	set: ocp_reg_read(tp, OCP_10GBT_CTRL) & MDIO_AN_10GBT_CTRL_ADV2_5G);
8788
8789	linkmode_mod_bit(nr: ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
8790	addr: cmd->link_modes.lp_advertising,
8791	set: ocp_reg_read(tp, OCP_10GBT_STAT) & MDIO_AN_10GBT_STAT_LP2_5G);
8792
8793	if (is_speed_2500(rtl8152_get_speed(tp)))
8794	cmd->base.speed = SPEED_2500;
8795	}
8796
8797	mutex_unlock(lock: &tp->control);
8798
8799	usb_autopm_put_interface(intf: tp->intf);
8800
8801	out:
8802	return ret;
8803	}
8804
8805	static int rtl8152_set_link_ksettings(struct net_device *dev,
8806	const struct ethtool_link_ksettings *cmd)
8807	{
8808	struct r8152 *tp = netdev_priv(dev);
8809	u32 advertising = 0;
8810	int ret;
8811
8812	ret = usb_autopm_get_interface(intf: tp->intf);
8813	if (ret < 0)
8814	goto out;
8815
8816	if (test_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
8817	cmd->link_modes.advertising))
8818	advertising |= RTL_ADVERTISED_10_HALF;
8819
8820	if (test_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
8821	cmd->link_modes.advertising))
8822	advertising |= RTL_ADVERTISED_10_FULL;
8823
8824	if (test_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
8825	cmd->link_modes.advertising))
8826	advertising |= RTL_ADVERTISED_100_HALF;
8827
8828	if (test_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
8829	cmd->link_modes.advertising))
8830	advertising |= RTL_ADVERTISED_100_FULL;
8831
8832	if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
8833	cmd->link_modes.advertising))
8834	advertising |= RTL_ADVERTISED_1000_HALF;
8835
8836	if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
8837	cmd->link_modes.advertising))
8838	advertising |= RTL_ADVERTISED_1000_FULL;
8839
8840	if (test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
8841	cmd->link_modes.advertising))
8842	advertising |= RTL_ADVERTISED_2500_FULL;
8843
8844	mutex_lock(&tp->control);
8845
8846	ret = rtl8152_set_speed(tp, autoneg: cmd->base.autoneg, speed: cmd->base.speed,
8847	duplex: cmd->base.duplex, advertising);
8848	if (!ret) {
8849	tp->autoneg = cmd->base.autoneg;
8850	tp->speed = cmd->base.speed;
8851	tp->duplex = cmd->base.duplex;
8852	tp->advertising = advertising;
8853	}
8854
8855	mutex_unlock(lock: &tp->control);
8856
8857	usb_autopm_put_interface(intf: tp->intf);
8858
8859	out:
8860	return ret;
8861	}
8862
8863	static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
8864	"tx_packets",
8865	"rx_packets",
8866	"tx_errors",
8867	"rx_errors",
8868	"rx_missed",
8869	"align_errors",
8870	"tx_single_collisions",
8871	"tx_multi_collisions",
8872	"rx_unicast",
8873	"rx_broadcast",
8874	"rx_multicast",
8875	"tx_aborted",
8876	"tx_underrun",
8877	};
8878
8879	static int rtl8152_get_sset_count(struct net_device *dev, int sset)
8880	{
8881	switch (sset) {
8882	case ETH_SS_STATS:
8883	return ARRAY_SIZE(rtl8152_gstrings);
8884	default:
8885	return -EOPNOTSUPP;
8886	}
8887	}
8888
8889	static void rtl8152_get_ethtool_stats(struct net_device *dev,
8890	struct ethtool_stats *stats, u64 *data)
8891	{
8892	struct r8152 *tp = netdev_priv(dev);
8893	struct tally_counter tally;
8894
8895	if (usb_autopm_get_interface(intf: tp->intf) < 0)
8896	return;
8897
8898	generic_ocp_read(tp, PLA_TALLYCNT, size: sizeof(tally), data: &tally, MCU_TYPE_PLA);
8899
8900	usb_autopm_put_interface(intf: tp->intf);
8901
8902	data[0] = le64_to_cpu(tally.tx_packets);
8903	data[1] = le64_to_cpu(tally.rx_packets);
8904	data[2] = le64_to_cpu(tally.tx_errors);
8905	data[3] = le32_to_cpu(tally.rx_errors);
8906	data[4] = le16_to_cpu(tally.rx_missed);
8907	data[5] = le16_to_cpu(tally.align_errors);
8908	data[6] = le32_to_cpu(tally.tx_one_collision);
8909	data[7] = le32_to_cpu(tally.tx_multi_collision);
8910	data[8] = le64_to_cpu(tally.rx_unicast);
8911	data[9] = le64_to_cpu(tally.rx_broadcast);
8912	data[10] = le32_to_cpu(tally.rx_multicast);
8913	data[11] = le16_to_cpu(tally.tx_aborted);
8914	data[12] = le16_to_cpu(tally.tx_underrun);
8915	}
8916
8917	static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
8918	{
8919	switch (stringset) {
8920	case ETH_SS_STATS:
8921	memcpy(data, rtl8152_gstrings, sizeof(rtl8152_gstrings));
8922	break;
8923	}
8924	}
8925
8926	static int r8152_get_eee(struct r8152 *tp, struct ethtool_keee *eee)
8927	{
8928	__ETHTOOL_DECLARE_LINK_MODE_MASK(common);
8929	u16 val;
8930
8931	val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
8932	mii_eee_cap1_mod_linkmode_t(adv: eee->supported, val);
8933
8934	val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
8935	mii_eee_cap1_mod_linkmode_t(adv: eee->advertised, val);
8936
8937	val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
8938	mii_eee_cap1_mod_linkmode_t(adv: eee->lp_advertised, val);
8939
8940	eee->eee_enabled = tp->eee_en;
8941
8942	linkmode_and(dst: common, a: eee->advertised, b: eee->lp_advertised);
8943	eee->eee_active = phy_check_valid(speed: tp->speed, duplex: tp->duplex, features: common);
8944
8945	return 0;
8946	}
8947
8948	static int r8152_set_eee(struct r8152 *tp, struct ethtool_keee *eee)
8949	{
8950	u16 val = linkmode_to_mii_eee_cap1_t(adv: eee->advertised);
8951
8952	tp->eee_en = eee->eee_enabled;
8953	tp->eee_adv = val;
8954
8955	rtl_eee_enable(tp, enable: tp->eee_en);
8956
8957	return 0;
8958	}
8959
8960	static int r8153_get_eee(struct r8152 *tp, struct ethtool_keee *eee)
8961	{
8962	__ETHTOOL_DECLARE_LINK_MODE_MASK(common);
8963	u16 val;
8964
8965	val = ocp_reg_read(tp, OCP_EEE_ABLE);
8966	mii_eee_cap1_mod_linkmode_t(adv: eee->supported, val);
8967
8968	val = ocp_reg_read(tp, OCP_EEE_ADV);
8969	mii_eee_cap1_mod_linkmode_t(adv: eee->advertised, val);
8970
8971	val = ocp_reg_read(tp, OCP_EEE_LPABLE);
8972	mii_eee_cap1_mod_linkmode_t(adv: eee->lp_advertised, val);
8973
8974	eee->eee_enabled = tp->eee_en;
8975
8976	linkmode_and(dst: common, a: eee->advertised, b: eee->lp_advertised);
8977	eee->eee_active = phy_check_valid(speed: tp->speed, duplex: tp->duplex, features: common);
8978
8979	return 0;
8980	}
8981
8982	static int
8983	rtl_ethtool_get_eee(struct net_device *net, struct ethtool_keee *edata)
8984	{
8985	struct r8152 *tp = netdev_priv(dev: net);
8986	int ret;
8987
8988	if (!tp->rtl_ops.eee_get) {
8989	ret = -EOPNOTSUPP;
8990	goto out;
8991	}
8992
8993	ret = usb_autopm_get_interface(intf: tp->intf);
8994	if (ret < 0)
8995	goto out;
8996
8997	mutex_lock(&tp->control);
8998
8999	ret = tp->rtl_ops.eee_get(tp, edata);
9000
9001	mutex_unlock(lock: &tp->control);
9002
9003	usb_autopm_put_interface(intf: tp->intf);
9004
9005	out:
9006	return ret;
9007	}
9008
9009	static int
9010	rtl_ethtool_set_eee(struct net_device *net, struct ethtool_keee *edata)
9011	{
9012	struct r8152 *tp = netdev_priv(dev: net);
9013	int ret;
9014
9015	if (!tp->rtl_ops.eee_set) {
9016	ret = -EOPNOTSUPP;
9017	goto out;
9018	}
9019
9020	ret = usb_autopm_get_interface(intf: tp->intf);
9021	if (ret < 0)
9022	goto out;
9023
9024	mutex_lock(&tp->control);
9025
9026	ret = tp->rtl_ops.eee_set(tp, edata);
9027	if (!ret)
9028	ret = mii_nway_restart(mii: &tp->mii);
9029
9030	mutex_unlock(lock: &tp->control);
9031
9032	usb_autopm_put_interface(intf: tp->intf);
9033
9034	out:
9035	return ret;
9036	}
9037
9038	static int rtl8152_nway_reset(struct net_device *dev)
9039	{
9040	struct r8152 *tp = netdev_priv(dev);
9041	int ret;
9042
9043	ret = usb_autopm_get_interface(intf: tp->intf);
9044	if (ret < 0)
9045	goto out;
9046
9047	mutex_lock(&tp->control);
9048
9049	ret = mii_nway_restart(mii: &tp->mii);
9050
9051	mutex_unlock(lock: &tp->control);
9052
9053	usb_autopm_put_interface(intf: tp->intf);
9054
9055	out:
9056	return ret;
9057	}
9058
9059	static int rtl8152_get_coalesce(struct net_device *netdev,
9060	struct ethtool_coalesce *coalesce,
9061	struct kernel_ethtool_coalesce *kernel_coal,
9062	struct netlink_ext_ack *extack)
9063	{
9064	struct r8152 *tp = netdev_priv(dev: netdev);
9065
9066	switch (tp->version) {
9067	case RTL_VER_01:
9068	case RTL_VER_02:
9069	case RTL_VER_07:
9070	return -EOPNOTSUPP;
9071	default:
9072	break;
9073	}
9074
9075	coalesce->rx_coalesce_usecs = tp->coalesce;
9076
9077	return 0;
9078	}
9079
9080	static int rtl8152_set_coalesce(struct net_device *netdev,
9081	struct ethtool_coalesce *coalesce,
9082	struct kernel_ethtool_coalesce *kernel_coal,
9083	struct netlink_ext_ack *extack)
9084	{
9085	struct r8152 *tp = netdev_priv(dev: netdev);
9086	int ret;
9087
9088	switch (tp->version) {
9089	case RTL_VER_01:
9090	case RTL_VER_02:
9091	case RTL_VER_07:
9092	return -EOPNOTSUPP;
9093	default:
9094	break;
9095	}
9096
9097	if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
9098	return -EINVAL;
9099
9100	ret = usb_autopm_get_interface(intf: tp->intf);
9101	if (ret < 0)
9102	return ret;
9103
9104	mutex_lock(&tp->control);
9105
9106	if (tp->coalesce != coalesce->rx_coalesce_usecs) {
9107	tp->coalesce = coalesce->rx_coalesce_usecs;
9108
9109	if (netif_running(dev: netdev) && netif_carrier_ok(dev: netdev)) {
9110	netif_stop_queue(dev: netdev);
9111	napi_disable(n: &tp->napi);
9112	tp->rtl_ops.disable(tp);
9113	tp->rtl_ops.enable(tp);
9114	rtl_start_rx(tp);
9115	clear_bit(nr: RTL8152_SET_RX_MODE, addr: &tp->flags);
9116	_rtl8152_set_rx_mode(netdev);
9117	napi_enable(n: &tp->napi);
9118	netif_wake_queue(dev: netdev);
9119	}
9120	}
9121
9122	mutex_unlock(lock: &tp->control);
9123
9124	usb_autopm_put_interface(intf: tp->intf);
9125
9126	return ret;
9127	}
9128
9129	static int rtl8152_get_tunable(struct net_device *netdev,
9130	const struct ethtool_tunable *tunable, void *d)
9131	{
9132	struct r8152 *tp = netdev_priv(dev: netdev);
9133
9134	switch (tunable->id) {
9135	case ETHTOOL_RX_COPYBREAK:
9136	*(u32 *)d = tp->rx_copybreak;
9137	break;
9138	default:
9139	return -EOPNOTSUPP;
9140	}
9141
9142	return 0;
9143	}
9144
9145	static int rtl8152_set_tunable(struct net_device *netdev,
9146	const struct ethtool_tunable *tunable,
9147	const void *d)
9148	{
9149	struct r8152 *tp = netdev_priv(dev: netdev);
9150	u32 val;
9151
9152	switch (tunable->id) {
9153	case ETHTOOL_RX_COPYBREAK:
9154	val = *(u32 *)d;
9155	if (val < ETH_ZLEN) {
9156	netif_err(tp, rx_err, netdev,
9157	"Invalid rx copy break value\n");
9158	return -EINVAL;
9159	}
9160
9161	if (tp->rx_copybreak != val) {
9162	if (netdev->flags & IFF_UP) {
9163	mutex_lock(&tp->control);
9164	napi_disable(n: &tp->napi);
9165	tp->rx_copybreak = val;
9166	napi_enable(n: &tp->napi);
9167	mutex_unlock(lock: &tp->control);
9168	} else {
9169	tp->rx_copybreak = val;
9170	}
9171	}
9172	break;
9173	default:
9174	return -EOPNOTSUPP;
9175	}
9176
9177	return 0;
9178	}
9179
9180	static void rtl8152_get_ringparam(struct net_device *netdev,
9181	struct ethtool_ringparam *ring,
9182	struct kernel_ethtool_ringparam *kernel_ring,
9183	struct netlink_ext_ack *extack)
9184	{
9185	struct r8152 *tp = netdev_priv(dev: netdev);
9186
9187	ring->rx_max_pending = RTL8152_RX_MAX_PENDING;
9188	ring->rx_pending = tp->rx_pending;
9189	}
9190
9191	static int rtl8152_set_ringparam(struct net_device *netdev,
9192	struct ethtool_ringparam *ring,
9193	struct kernel_ethtool_ringparam *kernel_ring,
9194	struct netlink_ext_ack *extack)
9195	{
9196	struct r8152 *tp = netdev_priv(dev: netdev);
9197
9198	if (ring->rx_pending < (RTL8152_MAX_RX * 2))
9199	return -EINVAL;
9200
9201	if (tp->rx_pending != ring->rx_pending) {
9202	if (netdev->flags & IFF_UP) {
9203	mutex_lock(&tp->control);
9204	napi_disable(n: &tp->napi);
9205	tp->rx_pending = ring->rx_pending;
9206	napi_enable(n: &tp->napi);
9207	mutex_unlock(lock: &tp->control);
9208	} else {
9209	tp->rx_pending = ring->rx_pending;
9210	}
9211	}
9212
9213	return 0;
9214	}
9215
9216	static void rtl8152_get_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *pause)
9217	{
9218	struct r8152 *tp = netdev_priv(dev: netdev);
9219	u16 bmcr, lcladv, rmtadv;
9220	u8 cap;
9221
9222	if (usb_autopm_get_interface(intf: tp->intf) < 0)
9223	return;
9224
9225	mutex_lock(&tp->control);
9226
9227	bmcr = r8152_mdio_read(tp, MII_BMCR);
9228	lcladv = r8152_mdio_read(tp, MII_ADVERTISE);
9229	rmtadv = r8152_mdio_read(tp, MII_LPA);
9230
9231	mutex_unlock(lock: &tp->control);
9232
9233	usb_autopm_put_interface(intf: tp->intf);
9234
9235	if (!(bmcr & BMCR_ANENABLE)) {
9236	pause->autoneg = 0;
9237	pause->rx_pause = 0;
9238	pause->tx_pause = 0;
9239	return;
9240	}
9241
9242	pause->autoneg = 1;
9243
9244	cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
9245
9246	if (cap & FLOW_CTRL_RX)
9247	pause->rx_pause = 1;
9248
9249	if (cap & FLOW_CTRL_TX)
9250	pause->tx_pause = 1;
9251	}
9252
9253	static int rtl8152_set_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *pause)
9254	{
9255	struct r8152 *tp = netdev_priv(dev: netdev);
9256	u16 old, new1;
9257	u8 cap = 0;
9258	int ret;
9259
9260	ret = usb_autopm_get_interface(intf: tp->intf);
9261	if (ret < 0)
9262	return ret;
9263
9264	mutex_lock(&tp->control);
9265
9266	if (pause->autoneg && !(r8152_mdio_read(tp, MII_BMCR) & BMCR_ANENABLE)) {
9267	ret = -EINVAL;
9268	goto out;
9269	}
9270
9271	if (pause->rx_pause)
9272	cap |= FLOW_CTRL_RX;
9273
9274	if (pause->tx_pause)
9275	cap |= FLOW_CTRL_TX;
9276
9277	old = r8152_mdio_read(tp, MII_ADVERTISE);
9278	new1 = (old & ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) | mii_advertise_flowctrl(cap);
9279	if (old != new1)
9280	r8152_mdio_write(tp, MII_ADVERTISE, value: new1);
9281
9282	out:
9283	mutex_unlock(lock: &tp->control);
9284	usb_autopm_put_interface(intf: tp->intf);
9285
9286	return ret;
9287	}
9288
9289	static const struct ethtool_ops ops = {
9290	.supported_coalesce_params = ETHTOOL_COALESCE_USECS,
9291	.get_drvinfo = rtl8152_get_drvinfo,
9292	.get_link = ethtool_op_get_link,
9293	.nway_reset = rtl8152_nway_reset,
9294	.get_msglevel = rtl8152_get_msglevel,
9295	.set_msglevel = rtl8152_set_msglevel,
9296	.get_wol = rtl8152_get_wol,
9297	.set_wol = rtl8152_set_wol,
9298	.get_strings = rtl8152_get_strings,
9299	.get_sset_count = rtl8152_get_sset_count,
9300	.get_ethtool_stats = rtl8152_get_ethtool_stats,
9301	.get_coalesce = rtl8152_get_coalesce,
9302	.set_coalesce = rtl8152_set_coalesce,
9303	.get_eee = rtl_ethtool_get_eee,
9304	.set_eee = rtl_ethtool_set_eee,
9305	.get_link_ksettings = rtl8152_get_link_ksettings,
9306	.set_link_ksettings = rtl8152_set_link_ksettings,
9307	.get_tunable = rtl8152_get_tunable,
9308	.set_tunable = rtl8152_set_tunable,
9309	.get_ringparam = rtl8152_get_ringparam,
9310	.set_ringparam = rtl8152_set_ringparam,
9311	.get_pauseparam = rtl8152_get_pauseparam,
9312	.set_pauseparam = rtl8152_set_pauseparam,
9313	};
9314
9315	static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
9316	{
9317	struct r8152 *tp = netdev_priv(dev: netdev);
9318	struct mii_ioctl_data *data = if_mii(rq);
9319	int res;
9320
9321	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
9322	return -ENODEV;
9323
9324	res = usb_autopm_get_interface(intf: tp->intf);
9325	if (res < 0)
9326	goto out;
9327
9328	switch (cmd) {
9329	case SIOCGMIIPHY:
9330	data->phy_id = R8152_PHY_ID; /* Internal PHY */
9331	break;
9332
9333	case SIOCGMIIREG:
9334	mutex_lock(&tp->control);
9335	data->val_out = r8152_mdio_read(tp, reg_addr: data->reg_num);
9336	mutex_unlock(lock: &tp->control);
9337	break;
9338
9339	case SIOCSMIIREG:
9340	if (!capable(CAP_NET_ADMIN)) {
9341	res = -EPERM;
9342	break;
9343	}
9344	mutex_lock(&tp->control);
9345	r8152_mdio_write(tp, reg_addr: data->reg_num, value: data->val_in);
9346	mutex_unlock(lock: &tp->control);
9347	break;
9348
9349	default:
9350	res = -EOPNOTSUPP;
9351	}
9352
9353	usb_autopm_put_interface(intf: tp->intf);
9354
9355	out:
9356	return res;
9357	}
9358
9359	static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
9360	{
9361	struct r8152 *tp = netdev_priv(dev);
9362	int ret;
9363
9364	switch (tp->version) {
9365	case RTL_VER_01:
9366	case RTL_VER_02:
9367	case RTL_VER_07:
9368	dev->mtu = new_mtu;
9369	return 0;
9370	default:
9371	break;
9372	}
9373
9374	ret = usb_autopm_get_interface(intf: tp->intf);
9375	if (ret < 0)
9376	return ret;
9377
9378	mutex_lock(&tp->control);
9379
9380	dev->mtu = new_mtu;
9381
9382	if (netif_running(dev)) {
9383	if (tp->rtl_ops.change_mtu)
9384	tp->rtl_ops.change_mtu(tp);
9385
9386	if (netif_carrier_ok(dev)) {
9387	netif_stop_queue(dev);
9388	napi_disable(n: &tp->napi);
9389	tasklet_disable(t: &tp->tx_tl);
9390	tp->rtl_ops.disable(tp);
9391	tp->rtl_ops.enable(tp);
9392	rtl_start_rx(tp);
9393	tasklet_enable(t: &tp->tx_tl);
9394	napi_enable(n: &tp->napi);
9395	rtl8152_set_rx_mode(netdev: dev);
9396	netif_wake_queue(dev);
9397	}
9398	}
9399
9400	mutex_unlock(lock: &tp->control);
9401
9402	usb_autopm_put_interface(intf: tp->intf);
9403
9404	return ret;
9405	}
9406
9407	static const struct net_device_ops rtl8152_netdev_ops = {
9408	.ndo_open = rtl8152_open,
9409	.ndo_stop = rtl8152_close,
9410	.ndo_eth_ioctl = rtl8152_ioctl,
9411	.ndo_start_xmit = rtl8152_start_xmit,
9412	.ndo_tx_timeout = rtl8152_tx_timeout,
9413	.ndo_set_features = rtl8152_set_features,
9414	.ndo_set_rx_mode = rtl8152_set_rx_mode,
9415	.ndo_set_mac_address = rtl8152_set_mac_address,
9416	.ndo_change_mtu = rtl8152_change_mtu,
9417	.ndo_validate_addr = eth_validate_addr,
9418	.ndo_features_check = rtl8152_features_check,
9419	};
9420
9421	static void rtl8152_unload(struct r8152 *tp)
9422	{
9423	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
9424	return;
9425
9426	if (tp->version != RTL_VER_01)
9427	r8152_power_cut_en(tp, enable: true);
9428	}
9429
9430	static void rtl8153_unload(struct r8152 *tp)
9431	{
9432	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
9433	return;
9434
9435	r8153_power_cut_en(tp, enable: false);
9436	}
9437
9438	static void rtl8153b_unload(struct r8152 *tp)
9439	{
9440	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
9441	return;
9442
9443	r8153b_power_cut_en(tp, enable: false);
9444	}
9445
9446	static int rtl_ops_init(struct r8152 *tp)
9447	{
9448	struct rtl_ops *ops = &tp->rtl_ops;
9449	int ret = 0;
9450
9451	switch (tp->version) {
9452	case RTL_VER_01:
9453	case RTL_VER_02:
9454	case RTL_VER_07:
9455	ops->init = r8152b_init;
9456	ops->enable = rtl8152_enable;
9457	ops->disable = rtl8152_disable;
9458	ops->up = rtl8152_up;
9459	ops->down = rtl8152_down;
9460	ops->unload = rtl8152_unload;
9461	ops->eee_get = r8152_get_eee;
9462	ops->eee_set = r8152_set_eee;
9463	ops->in_nway = rtl8152_in_nway;
9464	ops->hw_phy_cfg = r8152b_hw_phy_cfg;
9465	ops->autosuspend_en = rtl_runtime_suspend_enable;
9466	tp->rx_buf_sz = 16 * 1024;
9467	tp->eee_en = true;
9468	tp->eee_adv = MDIO_EEE_100TX;
9469	break;
9470
9471	case RTL_VER_03:
9472	case RTL_VER_04:
9473	case RTL_VER_05:
9474	case RTL_VER_06:
9475	ops->init = r8153_init;
9476	ops->enable = rtl8153_enable;
9477	ops->disable = rtl8153_disable;
9478	ops->up = rtl8153_up;
9479	ops->down = rtl8153_down;
9480	ops->unload = rtl8153_unload;
9481	ops->eee_get = r8153_get_eee;
9482	ops->eee_set = r8152_set_eee;
9483	ops->in_nway = rtl8153_in_nway;
9484	ops->hw_phy_cfg = r8153_hw_phy_cfg;
9485	ops->autosuspend_en = rtl8153_runtime_enable;
9486	ops->change_mtu = rtl8153_change_mtu;
9487	if (tp->udev->speed < USB_SPEED_SUPER)
9488	tp->rx_buf_sz = 16 * 1024;
9489	else
9490	tp->rx_buf_sz = 32 * 1024;
9491	tp->eee_en = true;
9492	tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
9493	break;
9494
9495	case RTL_VER_08:
9496	case RTL_VER_09:
9497	ops->init = r8153b_init;
9498	ops->enable = rtl8153_enable;
9499	ops->disable = rtl8153_disable;
9500	ops->up = rtl8153b_up;
9501	ops->down = rtl8153b_down;
9502	ops->unload = rtl8153b_unload;
9503	ops->eee_get = r8153_get_eee;
9504	ops->eee_set = r8152_set_eee;
9505	ops->in_nway = rtl8153_in_nway;
9506	ops->hw_phy_cfg = r8153b_hw_phy_cfg;
9507	ops->autosuspend_en = rtl8153b_runtime_enable;
9508	ops->change_mtu = rtl8153_change_mtu;
9509	tp->rx_buf_sz = 32 * 1024;
9510	tp->eee_en = true;
9511	tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
9512	break;
9513
9514	case RTL_VER_11:
9515	tp->eee_en = true;
9516	tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
9517	fallthrough;
9518	case RTL_VER_10:
9519	ops->init = r8156_init;
9520	ops->enable = rtl8156_enable;
9521	ops->disable = rtl8156_disable;
9522	ops->up = rtl8156_up;
9523	ops->down = rtl8156_down;
9524	ops->unload = rtl8153_unload;
9525	ops->eee_get = r8153_get_eee;
9526	ops->eee_set = r8152_set_eee;
9527	ops->in_nway = rtl8153_in_nway;
9528	ops->hw_phy_cfg = r8156_hw_phy_cfg;
9529	ops->autosuspend_en = rtl8156_runtime_enable;
9530	ops->change_mtu = rtl8156_change_mtu;
9531	tp->rx_buf_sz = 48 * 1024;
9532	tp->support_2500full = 1;
9533	break;
9534
9535	case RTL_VER_12:
9536	case RTL_VER_13:
9537	tp->support_2500full = 1;
9538	fallthrough;
9539	case RTL_VER_15:
9540	tp->eee_en = true;
9541	tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
9542	ops->init = r8156b_init;
9543	ops->enable = rtl8156b_enable;
9544	ops->disable = rtl8153_disable;
9545	ops->up = rtl8156_up;
9546	ops->down = rtl8156_down;
9547	ops->unload = rtl8153_unload;
9548	ops->eee_get = r8153_get_eee;
9549	ops->eee_set = r8152_set_eee;
9550	ops->in_nway = rtl8153_in_nway;
9551	ops->hw_phy_cfg = r8156b_hw_phy_cfg;
9552	ops->autosuspend_en = rtl8156_runtime_enable;
9553	ops->change_mtu = rtl8156_change_mtu;
9554	tp->rx_buf_sz = 48 * 1024;
9555	break;
9556
9557	case RTL_VER_14:
9558	ops->init = r8153c_init;
9559	ops->enable = rtl8153_enable;
9560	ops->disable = rtl8153_disable;
9561	ops->up = rtl8153c_up;
9562	ops->down = rtl8153b_down;
9563	ops->unload = rtl8153_unload;
9564	ops->eee_get = r8153_get_eee;
9565	ops->eee_set = r8152_set_eee;
9566	ops->in_nway = rtl8153_in_nway;
9567	ops->hw_phy_cfg = r8153c_hw_phy_cfg;
9568	ops->autosuspend_en = rtl8153c_runtime_enable;
9569	ops->change_mtu = rtl8153c_change_mtu;
9570	tp->rx_buf_sz = 32 * 1024;
9571	tp->eee_en = true;
9572	tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
9573	break;
9574
9575	default:
9576	ret = -ENODEV;
9577	dev_err(&tp->intf->dev, "Unknown Device\n");
9578	break;
9579	}
9580
9581	return ret;
9582	}
9583
9584	#define FIRMWARE_8153A_2 "rtl_nic/rtl8153a-2.fw"
9585	#define FIRMWARE_8153A_3 "rtl_nic/rtl8153a-3.fw"
9586	#define FIRMWARE_8153A_4 "rtl_nic/rtl8153a-4.fw"
9587	#define FIRMWARE_8153B_2 "rtl_nic/rtl8153b-2.fw"
9588	#define FIRMWARE_8153C_1 "rtl_nic/rtl8153c-1.fw"
9589	#define FIRMWARE_8156A_2 "rtl_nic/rtl8156a-2.fw"
9590	#define FIRMWARE_8156B_2 "rtl_nic/rtl8156b-2.fw"
9591
9592	MODULE_FIRMWARE(FIRMWARE_8153A_2);
9593	MODULE_FIRMWARE(FIRMWARE_8153A_3);
9594	MODULE_FIRMWARE(FIRMWARE_8153A_4);
9595	MODULE_FIRMWARE(FIRMWARE_8153B_2);
9596	MODULE_FIRMWARE(FIRMWARE_8153C_1);
9597	MODULE_FIRMWARE(FIRMWARE_8156A_2);
9598	MODULE_FIRMWARE(FIRMWARE_8156B_2);
9599
9600	static int rtl_fw_init(struct r8152 *tp)
9601	{
9602	struct rtl_fw *rtl_fw = &tp->rtl_fw;
9603
9604	switch (tp->version) {
9605	case RTL_VER_04:
9606	rtl_fw->fw_name = FIRMWARE_8153A_2;
9607	rtl_fw->pre_fw = r8153_pre_firmware_1;
9608	rtl_fw->post_fw = r8153_post_firmware_1;
9609	break;
9610	case RTL_VER_05:
9611	rtl_fw->fw_name = FIRMWARE_8153A_3;
9612	rtl_fw->pre_fw = r8153_pre_firmware_2;
9613	rtl_fw->post_fw = r8153_post_firmware_2;
9614	break;
9615	case RTL_VER_06:
9616	rtl_fw->fw_name = FIRMWARE_8153A_4;
9617	rtl_fw->post_fw = r8153_post_firmware_3;
9618	break;
9619	case RTL_VER_09:
9620	rtl_fw->fw_name = FIRMWARE_8153B_2;
9621	rtl_fw->pre_fw = r8153b_pre_firmware_1;
9622	rtl_fw->post_fw = r8153b_post_firmware_1;
9623	break;
9624	case RTL_VER_11:
9625	rtl_fw->fw_name = FIRMWARE_8156A_2;
9626	rtl_fw->post_fw = r8156a_post_firmware_1;
9627	break;
9628	case RTL_VER_13:
9629	case RTL_VER_15:
9630	rtl_fw->fw_name = FIRMWARE_8156B_2;
9631	break;
9632	case RTL_VER_14:
9633	rtl_fw->fw_name = FIRMWARE_8153C_1;
9634	rtl_fw->pre_fw = r8153b_pre_firmware_1;
9635	rtl_fw->post_fw = r8153c_post_firmware_1;
9636	break;
9637	default:
9638	break;
9639	}
9640
9641	return 0;
9642	}
9643
9644	static u8 __rtl_get_hw_ver(struct usb_device *udev)
9645	{
9646	u32 ocp_data = 0;
9647	__le32 *tmp;
9648	u8 version;
9649	int ret;
9650	int i;
9651
9652	tmp = kmalloc(size: sizeof(*tmp), GFP_KERNEL);
9653	if (!tmp)
9654	return 0;
9655
9656	/* Retry up to 3 times in case there is a transitory error. We do this
9657	* since retrying a read of the version is always safe and this
9658	* function doesn't take advantage of r8152_control_msg().
9659	*/
9660	for (i = 0; i < 3; i++) {
9661	ret = usb_control_msg(dev: udev, usb_rcvctrlpipe(udev, 0),
9662	RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
9663	PLA_TCR0, MCU_TYPE_PLA, data: tmp, size: sizeof(*tmp),
9664	USB_CTRL_GET_TIMEOUT);
9665	if (ret > 0) {
9666	ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK;
9667	break;
9668	}
9669	}
9670
9671	if (i != 0 && ret > 0)
9672	dev_warn(&udev->dev, "Needed %d retries to read version\n", i);
9673
9674	kfree(objp: tmp);
9675
9676	switch (ocp_data) {
9677	case 0x4c00:
9678	version = RTL_VER_01;
9679	break;
9680	case 0x4c10:
9681	version = RTL_VER_02;
9682	break;
9683	case 0x5c00:
9684	version = RTL_VER_03;
9685	break;
9686	case 0x5c10:
9687	version = RTL_VER_04;
9688	break;
9689	case 0x5c20:
9690	version = RTL_VER_05;
9691	break;
9692	case 0x5c30:
9693	version = RTL_VER_06;
9694	break;
9695	case 0x4800:
9696	version = RTL_VER_07;
9697	break;
9698	case 0x6000:
9699	version = RTL_VER_08;
9700	break;
9701	case 0x6010:
9702	version = RTL_VER_09;
9703	break;
9704	case 0x7010:
9705	version = RTL_TEST_01;
9706	break;
9707	case 0x7020:
9708	version = RTL_VER_10;
9709	break;
9710	case 0x7030:
9711	version = RTL_VER_11;
9712	break;
9713	case 0x7400:
9714	version = RTL_VER_12;
9715	break;
9716	case 0x7410:
9717	version = RTL_VER_13;
9718	break;
9719	case 0x6400:
9720	version = RTL_VER_14;
9721	break;
9722	case 0x7420:
9723	version = RTL_VER_15;
9724	break;
9725	default:
9726	version = RTL_VER_UNKNOWN;
9727	dev_info(&udev->dev, "Unknown version 0x%04x\n", ocp_data);
9728	break;
9729	}
9730
9731	return version;
9732	}
9733
9734	u8 rtl8152_get_version(struct usb_interface *intf)
9735	{
9736	u8 version;
9737
9738	version = __rtl_get_hw_ver(interface_to_usbdev(intf));
9739
9740	dev_dbg(&intf->dev, "Detected version 0x%04x\n", version);
9741
9742	return version;
9743	}
9744	EXPORT_SYMBOL_GPL(rtl8152_get_version);
9745
9746	static bool rtl8152_supports_lenovo_macpassthru(struct usb_device *udev)
9747	{
9748	int parent_vendor_id = le16_to_cpu(udev->parent->descriptor.idVendor);
9749	int product_id = le16_to_cpu(udev->descriptor.idProduct);
9750	int vendor_id = le16_to_cpu(udev->descriptor.idVendor);
9751
9752	if (vendor_id == VENDOR_ID_LENOVO) {
9753	switch (product_id) {
9754	case DEVICE_ID_LENOVO_USB_C_TRAVEL_HUB:
9755	case DEVICE_ID_THINKPAD_ONELINK_PLUS_DOCK:
9756	case DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2:
9757	case DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2:
9758	case DEVICE_ID_THINKPAD_USB_C_DOCK_GEN3:
9759	case DEVICE_ID_THINKPAD_USB_C_DONGLE:
9760	return 1;
9761	}
9762	} else if (vendor_id == VENDOR_ID_REALTEK && parent_vendor_id == VENDOR_ID_LENOVO) {
9763	switch (product_id) {
9764	case 0x8153:
9765	return 1;
9766	}
9767	}
9768	return 0;
9769	}
9770
9771	static int rtl8152_probe_once(struct usb_interface *intf,
9772	const struct usb_device_id *id, u8 version)
9773	{
9774	struct usb_device *udev = interface_to_usbdev(intf);
9775	struct r8152 *tp;
9776	struct net_device *netdev;
9777	int ret;
9778
9779	usb_reset_device(dev: udev);
9780	netdev = alloc_etherdev(sizeof(struct r8152));
9781	if (!netdev) {
9782	dev_err(&intf->dev, "Out of memory\n");
9783	return -ENOMEM;
9784	}
9785
9786	SET_NETDEV_DEV(netdev, &intf->dev);
9787	tp = netdev_priv(dev: netdev);
9788	tp->msg_enable = 0x7FFF;
9789
9790	tp->udev = udev;
9791	tp->netdev = netdev;
9792	tp->intf = intf;
9793	tp->version = version;
9794
9795	tp->pipe_ctrl_in = usb_rcvctrlpipe(udev, 0);
9796	tp->pipe_ctrl_out = usb_sndctrlpipe(udev, 0);
9797	tp->pipe_in = usb_rcvbulkpipe(udev, 1);
9798	tp->pipe_out = usb_sndbulkpipe(udev, 2);
9799	tp->pipe_intr = usb_rcvintpipe(udev, 3);
9800
9801	switch (version) {
9802	case RTL_VER_01:
9803	case RTL_VER_02:
9804	case RTL_VER_07:
9805	tp->mii.supports_gmii = 0;
9806	break;
9807	default:
9808	tp->mii.supports_gmii = 1;
9809	break;
9810	}
9811
9812	ret = rtl_ops_init(tp);
9813	if (ret)
9814	goto out;
9815
9816	rtl_fw_init(tp);
9817
9818	mutex_init(&tp->control);
9819	INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
9820	INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t);
9821	tasklet_setup(t: &tp->tx_tl, callback: bottom_half);
9822	tasklet_disable(t: &tp->tx_tl);
9823
9824	netdev->netdev_ops = &rtl8152_netdev_ops;
9825	netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
9826
9827	netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
9828	NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
9829	NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
9830	NETIF_F_HW_VLAN_CTAG_TX;
9831	netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
9832	NETIF_F_TSO | NETIF_F_FRAGLIST |
9833	NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
9834	NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
9835	netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
9836	NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
9837	NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
9838
9839	if (tp->version == RTL_VER_01) {
9840	netdev->features &= ~NETIF_F_RXCSUM;
9841	netdev->hw_features &= ~NETIF_F_RXCSUM;
9842	}
9843
9844	tp->lenovo_macpassthru = rtl8152_supports_lenovo_macpassthru(udev);
9845
9846	if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x3011 && udev->serial &&
9847	(!strcmp(udev->serial, "000001000000") ||
9848	!strcmp(udev->serial, "000002000000"))) {
9849	dev_info(&udev->dev, "Dell TB16 Dock, disable RX aggregation");
9850	tp->dell_tb_rx_agg_bug = 1;
9851	}
9852
9853	netdev->ethtool_ops = &ops;
9854	netif_set_tso_max_size(dev: netdev, RTL_LIMITED_TSO_SIZE);
9855
9856	/* MTU range: 68 - 1500 or 9194 */
9857	netdev->min_mtu = ETH_MIN_MTU;
9858	switch (tp->version) {
9859	case RTL_VER_03:
9860	case RTL_VER_04:
9861	case RTL_VER_05:
9862	case RTL_VER_06:
9863	case RTL_VER_08:
9864	case RTL_VER_09:
9865	case RTL_VER_14:
9866	netdev->max_mtu = size_to_mtu(9 * 1024);
9867	break;
9868	case RTL_VER_10:
9869	case RTL_VER_11:
9870	netdev->max_mtu = size_to_mtu(15 * 1024);
9871	break;
9872	case RTL_VER_12:
9873	case RTL_VER_13:
9874	case RTL_VER_15:
9875	netdev->max_mtu = size_to_mtu(16 * 1024);
9876	break;
9877	case RTL_VER_01:
9878	case RTL_VER_02:
9879	case RTL_VER_07:
9880	default:
9881	netdev->max_mtu = ETH_DATA_LEN;
9882	break;
9883	}
9884
9885	tp->mii.dev = netdev;
9886	tp->mii.mdio_read = read_mii_word;
9887	tp->mii.mdio_write = write_mii_word;
9888	tp->mii.phy_id_mask = 0x3f;
9889	tp->mii.reg_num_mask = 0x1f;
9890	tp->mii.phy_id = R8152_PHY_ID;
9891
9892	tp->autoneg = AUTONEG_ENABLE;
9893	tp->speed = SPEED_100;
9894	tp->advertising = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
9895	RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
9896	if (tp->mii.supports_gmii) {
9897	if (tp->support_2500full &&
9898	tp->udev->speed >= USB_SPEED_SUPER) {
9899	tp->speed = SPEED_2500;
9900	tp->advertising |= RTL_ADVERTISED_2500_FULL;
9901	} else {
9902	tp->speed = SPEED_1000;
9903	}
9904	tp->advertising |= RTL_ADVERTISED_1000_FULL;
9905	}
9906	tp->duplex = DUPLEX_FULL;
9907
9908	tp->rx_copybreak = RTL8152_RXFG_HEADSZ;
9909	tp->rx_pending = 10 * RTL8152_MAX_RX;
9910
9911	intf->needs_remote_wakeup = 1;
9912
9913	if (!rtl_can_wakeup(tp))
9914	__rtl_set_wol(tp, wolopts: 0);
9915	else
9916	tp->saved_wolopts = __rtl_get_wol(tp);
9917
9918	tp->rtl_ops.init(tp);
9919	#if IS_BUILTIN(CONFIG_USB_RTL8152)
9920	/* Retry in case request_firmware() is not ready yet. */
9921	tp->rtl_fw.retry = true;
9922	#endif
9923	queue_delayed_work(wq: system_long_wq, dwork: &tp->hw_phy_work, delay: 0);
9924	set_ethernet_addr(tp, in_resume: false);
9925
9926	usb_set_intfdata(intf, data: tp);
9927
9928	netif_napi_add(dev: netdev, napi: &tp->napi, poll: r8152_poll);
9929
9930	ret = register_netdev(dev: netdev);
9931	if (ret != 0) {
9932	dev_err(&intf->dev, "couldn't register the device\n");
9933	goto out1;
9934	}
9935
9936	if (tp->saved_wolopts)
9937	device_set_wakeup_enable(dev: &udev->dev, enable: true);
9938	else
9939	device_set_wakeup_enable(dev: &udev->dev, enable: false);
9940
9941	/* If we saw a control transfer error while probing then we may
9942	* want to try probe() again. Consider this an error.
9943	*/
9944	if (test_bit(PROBE_SHOULD_RETRY, &tp->flags))
9945	goto out2;
9946
9947	set_bit(nr: PROBED_WITH_NO_ERRORS, addr: &tp->flags);
9948	netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
9949
9950	return 0;
9951
9952	out2:
9953	unregister_netdev(dev: netdev);
9954
9955	out1:
9956	tasklet_kill(t: &tp->tx_tl);
9957	cancel_delayed_work_sync(dwork: &tp->hw_phy_work);
9958	if (tp->rtl_ops.unload)
9959	tp->rtl_ops.unload(tp);
9960	rtl8152_release_firmware(tp);
9961	usb_set_intfdata(intf, NULL);
9962	out:
9963	if (test_bit(PROBE_SHOULD_RETRY, &tp->flags))
9964	ret = -EAGAIN;
9965
9966	free_netdev(dev: netdev);
9967	return ret;
9968	}
9969
9970	#define RTL8152_PROBE_TRIES 3
9971
9972	static int rtl8152_probe(struct usb_interface *intf,
9973	const struct usb_device_id *id)
9974	{
9975	u8 version;
9976	int ret;
9977	int i;
9978
9979	if (intf->cur_altsetting->desc.bInterfaceClass != USB_CLASS_VENDOR_SPEC)
9980	return -ENODEV;
9981
9982	if (!rtl_check_vendor_ok(intf))
9983	return -ENODEV;
9984
9985	version = rtl8152_get_version(intf);
9986	if (version == RTL_VER_UNKNOWN)
9987	return -ENODEV;
9988
9989	for (i = 0; i < RTL8152_PROBE_TRIES; i++) {
9990	ret = rtl8152_probe_once(intf, id, version);
9991	if (ret != -EAGAIN)
9992	break;
9993	}
9994	if (ret == -EAGAIN) {
9995	dev_err(&intf->dev,
9996	"r8152 failed probe after %d tries; giving up\n", i);
9997	return -ENODEV;
9998	}
9999
10000	return ret;
10001	}
10002
10003	static void rtl8152_disconnect(struct usb_interface *intf)
10004	{
10005	struct r8152 *tp = usb_get_intfdata(intf);
10006
10007	usb_set_intfdata(intf, NULL);
10008	if (tp) {
10009	rtl_set_unplug(tp);
10010
10011	unregister_netdev(dev: tp->netdev);
10012	tasklet_kill(t: &tp->tx_tl);
10013	cancel_delayed_work_sync(dwork: &tp->hw_phy_work);
10014	if (tp->rtl_ops.unload)
10015	tp->rtl_ops.unload(tp);
10016	rtl8152_release_firmware(tp);
10017	free_netdev(dev: tp->netdev);
10018	}
10019	}
10020
10021	/* table of devices that work with this driver */
10022	static const struct usb_device_id rtl8152_table[] = {
10023	/* Realtek */
10024	{ USB_DEVICE(VENDOR_ID_REALTEK, 0x8050) },
10025	{ USB_DEVICE(VENDOR_ID_REALTEK, 0x8053) },
10026	{ USB_DEVICE(VENDOR_ID_REALTEK, 0x8152) },
10027	{ USB_DEVICE(VENDOR_ID_REALTEK, 0x8153) },
10028	{ USB_DEVICE(VENDOR_ID_REALTEK, 0x8155) },
10029	{ USB_DEVICE(VENDOR_ID_REALTEK, 0x8156) },
10030
10031	/* Microsoft */
10032	{ USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab) },
10033	{ USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6) },
10034	{ USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0927) },
10035	{ USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0c5e) },
10036	{ USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101) },
10037	{ USB_DEVICE(VENDOR_ID_LENOVO, 0x304f) },
10038	{ USB_DEVICE(VENDOR_ID_LENOVO, 0x3054) },
10039	{ USB_DEVICE(VENDOR_ID_LENOVO, 0x3062) },
10040	{ USB_DEVICE(VENDOR_ID_LENOVO, 0x3069) },
10041	{ USB_DEVICE(VENDOR_ID_LENOVO, 0x3082) },
10042	{ USB_DEVICE(VENDOR_ID_LENOVO, 0x7205) },
10043	{ USB_DEVICE(VENDOR_ID_LENOVO, 0x720c) },
10044	{ USB_DEVICE(VENDOR_ID_LENOVO, 0x7214) },
10045	{ USB_DEVICE(VENDOR_ID_LENOVO, 0x721e) },
10046	{ USB_DEVICE(VENDOR_ID_LENOVO, 0xa387) },
10047	{ USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041) },
10048	{ USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff) },
10049	{ USB_DEVICE(VENDOR_ID_TPLINK, 0x0601) },
10050	{ USB_DEVICE(VENDOR_ID_DLINK, 0xb301) },
10051	{ USB_DEVICE(VENDOR_ID_ASUS, 0x1976) },
10052	{}
10053	};
10054
10055	MODULE_DEVICE_TABLE(usb, rtl8152_table);
10056
10057	static struct usb_driver rtl8152_driver = {
10058	.name = MODULENAME,
10059	.id_table = rtl8152_table,
10060	.probe = rtl8152_probe,
10061	.disconnect = rtl8152_disconnect,
10062	.suspend = rtl8152_suspend,
10063	.resume = rtl8152_resume,
10064	.reset_resume = rtl8152_reset_resume,
10065	.pre_reset = rtl8152_pre_reset,
10066	.post_reset = rtl8152_post_reset,
10067	.supports_autosuspend = 1,
10068	.disable_hub_initiated_lpm = 1,
10069	};
10070
10071	static int rtl8152_cfgselector_choose_configuration(struct usb_device *udev)
10072	{
10073	struct usb_host_config *c;
10074	int i, num_configs;
10075
10076	/* Switch the device to vendor mode, if and only if the vendor mode
10077	* driver supports it.
10078	*/
10079	if (__rtl_get_hw_ver(udev) == RTL_VER_UNKNOWN)
10080	return -ENODEV;
10081
10082	/* The vendor mode is not always config #1, so to find it out. */
10083	c = udev->config;
10084	num_configs = udev->descriptor.bNumConfigurations;
10085	for (i = 0; i < num_configs; (i++, c++)) {
10086	struct usb_interface_descriptor *desc = NULL;
10087
10088	if (!c->desc.bNumInterfaces)
10089	continue;
10090	desc = &c->intf_cache[0]->altsetting->desc;
10091	if (desc->bInterfaceClass == USB_CLASS_VENDOR_SPEC)
10092	break;
10093	}
10094
10095	if (i == num_configs)
10096	return -ENODEV;
10097
10098	return c->desc.bConfigurationValue;
10099	}
10100
10101	static struct usb_device_driver rtl8152_cfgselector_driver = {
10102	.name = MODULENAME "-cfgselector",
10103	.choose_configuration = rtl8152_cfgselector_choose_configuration,
10104	.id_table = rtl8152_table,
10105	.generic_subclass = 1,
10106	.supports_autosuspend = 1,
10107	};
10108
10109	static int __init rtl8152_driver_init(void)
10110	{
10111	int ret;
10112
10113	ret = usb_register_device_driver(&rtl8152_cfgselector_driver, THIS_MODULE);
10114	if (ret)
10115	return ret;
10116	return usb_register(&rtl8152_driver);
10117	}
10118
10119	static void __exit rtl8152_driver_exit(void)
10120	{
10121	usb_deregister(&rtl8152_driver);
10122	usb_deregister_device_driver(&rtl8152_cfgselector_driver);
10123	}
10124
10125	module_init(rtl8152_driver_init);
10126	module_exit(rtl8152_driver_exit);
10127
10128	MODULE_AUTHOR(DRIVER_AUTHOR);
10129	MODULE_DESCRIPTION(DRIVER_DESC);
10130	MODULE_LICENSE("GPL");
10131	MODULE_VERSION(DRIVER_VERSION);
10132