1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | #include <linux/init.h> |
3 | |
4 | #include <linux/mm.h> |
5 | #include <linux/spinlock.h> |
6 | #include <linux/smp.h> |
7 | #include <linux/interrupt.h> |
8 | #include <linux/export.h> |
9 | #include <linux/cpu.h> |
10 | #include <linux/debugfs.h> |
11 | #include <linux/sched/smt.h> |
12 | #include <linux/task_work.h> |
13 | #include <linux/mmu_notifier.h> |
14 | |
15 | #include <asm/tlbflush.h> |
16 | #include <asm/mmu_context.h> |
17 | #include <asm/nospec-branch.h> |
18 | #include <asm/cache.h> |
19 | #include <asm/cacheflush.h> |
20 | #include <asm/apic.h> |
21 | #include <asm/perf_event.h> |
22 | |
23 | #include "mm_internal.h" |
24 | |
25 | #ifdef CONFIG_PARAVIRT |
26 | # define STATIC_NOPV |
27 | #else |
28 | # define STATIC_NOPV static |
29 | # define __flush_tlb_local native_flush_tlb_local |
30 | # define __flush_tlb_global native_flush_tlb_global |
31 | # define __flush_tlb_one_user(addr) native_flush_tlb_one_user(addr) |
32 | # define __flush_tlb_multi(msk, info) native_flush_tlb_multi(msk, info) |
33 | #endif |
34 | |
35 | /* |
36 | * TLB flushing, formerly SMP-only |
37 | * c/o Linus Torvalds. |
38 | * |
39 | * These mean you can really definitely utterly forget about |
40 | * writing to user space from interrupts. (Its not allowed anyway). |
41 | * |
42 | * Optimizations Manfred Spraul <manfred@colorfullife.com> |
43 | * |
44 | * More scalable flush, from Andi Kleen |
45 | * |
46 | * Implement flush IPI by CALL_FUNCTION_VECTOR, Alex Shi |
47 | */ |
48 | |
49 | /* |
50 | * Bits to mangle the TIF_SPEC_* state into the mm pointer which is |
51 | * stored in cpu_tlb_state.last_user_mm_spec. |
52 | */ |
53 | #define LAST_USER_MM_IBPB 0x1UL |
54 | #define LAST_USER_MM_L1D_FLUSH 0x2UL |
55 | #define LAST_USER_MM_SPEC_MASK (LAST_USER_MM_IBPB | LAST_USER_MM_L1D_FLUSH) |
56 | |
57 | /* Bits to set when tlbstate and flush is (re)initialized */ |
58 | #define LAST_USER_MM_INIT LAST_USER_MM_IBPB |
59 | |
60 | /* |
61 | * The x86 feature is called PCID (Process Context IDentifier). It is similar |
62 | * to what is traditionally called ASID on the RISC processors. |
63 | * |
64 | * We don't use the traditional ASID implementation, where each process/mm gets |
65 | * its own ASID and flush/restart when we run out of ASID space. |
66 | * |
67 | * Instead we have a small per-cpu array of ASIDs and cache the last few mm's |
68 | * that came by on this CPU, allowing cheaper switch_mm between processes on |
69 | * this CPU. |
70 | * |
71 | * We end up with different spaces for different things. To avoid confusion we |
72 | * use different names for each of them: |
73 | * |
74 | * ASID - [0, TLB_NR_DYN_ASIDS-1] |
75 | * the canonical identifier for an mm |
76 | * |
77 | * kPCID - [1, TLB_NR_DYN_ASIDS] |
78 | * the value we write into the PCID part of CR3; corresponds to the |
79 | * ASID+1, because PCID 0 is special. |
80 | * |
81 | * uPCID - [2048 + 1, 2048 + TLB_NR_DYN_ASIDS] |
82 | * for KPTI each mm has two address spaces and thus needs two |
83 | * PCID values, but we can still do with a single ASID denomination |
84 | * for each mm. Corresponds to kPCID + 2048. |
85 | * |
86 | */ |
87 | |
88 | /* There are 12 bits of space for ASIDS in CR3 */ |
89 | #define CR3_HW_ASID_BITS 12 |
90 | |
91 | /* |
92 | * When enabled, PAGE_TABLE_ISOLATION consumes a single bit for |
93 | * user/kernel switches |
94 | */ |
95 | #ifdef CONFIG_PAGE_TABLE_ISOLATION |
96 | # define PTI_CONSUMED_PCID_BITS 1 |
97 | #else |
98 | # define PTI_CONSUMED_PCID_BITS 0 |
99 | #endif |
100 | |
101 | #define CR3_AVAIL_PCID_BITS (X86_CR3_PCID_BITS - PTI_CONSUMED_PCID_BITS) |
102 | |
103 | /* |
104 | * ASIDs are zero-based: 0->MAX_AVAIL_ASID are valid. -1 below to account |
105 | * for them being zero-based. Another -1 is because PCID 0 is reserved for |
106 | * use by non-PCID-aware users. |
107 | */ |
108 | #define MAX_ASID_AVAILABLE ((1 << CR3_AVAIL_PCID_BITS) - 2) |
109 | |
110 | /* |
111 | * Given @asid, compute kPCID |
112 | */ |
113 | static inline u16 kern_pcid(u16 asid) |
114 | { |
115 | VM_WARN_ON_ONCE(asid > MAX_ASID_AVAILABLE); |
116 | |
117 | #ifdef CONFIG_PAGE_TABLE_ISOLATION |
118 | /* |
119 | * Make sure that the dynamic ASID space does not conflict with the |
120 | * bit we are using to switch between user and kernel ASIDs. |
121 | */ |
122 | BUILD_BUG_ON(TLB_NR_DYN_ASIDS >= (1 << X86_CR3_PTI_PCID_USER_BIT)); |
123 | |
124 | /* |
125 | * The ASID being passed in here should have respected the |
126 | * MAX_ASID_AVAILABLE and thus never have the switch bit set. |
127 | */ |
128 | VM_WARN_ON_ONCE(asid & (1 << X86_CR3_PTI_PCID_USER_BIT)); |
129 | #endif |
130 | /* |
131 | * The dynamically-assigned ASIDs that get passed in are small |
132 | * (<TLB_NR_DYN_ASIDS). They never have the high switch bit set, |
133 | * so do not bother to clear it. |
134 | * |
135 | * If PCID is on, ASID-aware code paths put the ASID+1 into the |
136 | * PCID bits. This serves two purposes. It prevents a nasty |
137 | * situation in which PCID-unaware code saves CR3, loads some other |
138 | * value (with PCID == 0), and then restores CR3, thus corrupting |
139 | * the TLB for ASID 0 if the saved ASID was nonzero. It also means |
140 | * that any bugs involving loading a PCID-enabled CR3 with |
141 | * CR4.PCIDE off will trigger deterministically. |
142 | */ |
143 | return asid + 1; |
144 | } |
145 | |
146 | /* |
147 | * Given @asid, compute uPCID |
148 | */ |
149 | static inline u16 user_pcid(u16 asid) |
150 | { |
151 | u16 ret = kern_pcid(asid); |
152 | #ifdef CONFIG_PAGE_TABLE_ISOLATION |
153 | ret |= 1 << X86_CR3_PTI_PCID_USER_BIT; |
154 | #endif |
155 | return ret; |
156 | } |
157 | |
158 | static inline unsigned long build_cr3(pgd_t *pgd, u16 asid, unsigned long lam) |
159 | { |
160 | unsigned long cr3 = __sme_pa(pgd) | lam; |
161 | |
162 | if (static_cpu_has(X86_FEATURE_PCID)) { |
163 | VM_WARN_ON_ONCE(asid > MAX_ASID_AVAILABLE); |
164 | cr3 |= kern_pcid(asid); |
165 | } else { |
166 | VM_WARN_ON_ONCE(asid != 0); |
167 | } |
168 | |
169 | return cr3; |
170 | } |
171 | |
172 | static inline unsigned long build_cr3_noflush(pgd_t *pgd, u16 asid, |
173 | unsigned long lam) |
174 | { |
175 | /* |
176 | * Use boot_cpu_has() instead of this_cpu_has() as this function |
177 | * might be called during early boot. This should work even after |
178 | * boot because all CPU's the have same capabilities: |
179 | */ |
180 | VM_WARN_ON_ONCE(!boot_cpu_has(X86_FEATURE_PCID)); |
181 | return build_cr3(pgd, asid, lam) | CR3_NOFLUSH; |
182 | } |
183 | |
184 | /* |
185 | * We get here when we do something requiring a TLB invalidation |
186 | * but could not go invalidate all of the contexts. We do the |
187 | * necessary invalidation by clearing out the 'ctx_id' which |
188 | * forces a TLB flush when the context is loaded. |
189 | */ |
190 | static void clear_asid_other(void) |
191 | { |
192 | u16 asid; |
193 | |
194 | /* |
195 | * This is only expected to be set if we have disabled |
196 | * kernel _PAGE_GLOBAL pages. |
197 | */ |
198 | if (!static_cpu_has(X86_FEATURE_PTI)) { |
199 | WARN_ON_ONCE(1); |
200 | return; |
201 | } |
202 | |
203 | for (asid = 0; asid < TLB_NR_DYN_ASIDS; asid++) { |
204 | /* Do not need to flush the current asid */ |
205 | if (asid == this_cpu_read(cpu_tlbstate.loaded_mm_asid)) |
206 | continue; |
207 | /* |
208 | * Make sure the next time we go to switch to |
209 | * this asid, we do a flush: |
210 | */ |
211 | this_cpu_write(cpu_tlbstate.ctxs[asid].ctx_id, 0); |
212 | } |
213 | this_cpu_write(cpu_tlbstate.invalidate_other, false); |
214 | } |
215 | |
216 | atomic64_t last_mm_ctx_id = ATOMIC64_INIT(1); |
217 | |
218 | |
219 | static void choose_new_asid(struct mm_struct *next, u64 next_tlb_gen, |
220 | u16 *new_asid, bool *need_flush) |
221 | { |
222 | u16 asid; |
223 | |
224 | if (!static_cpu_has(X86_FEATURE_PCID)) { |
225 | *new_asid = 0; |
226 | *need_flush = true; |
227 | return; |
228 | } |
229 | |
230 | if (this_cpu_read(cpu_tlbstate.invalidate_other)) |
231 | clear_asid_other(); |
232 | |
233 | for (asid = 0; asid < TLB_NR_DYN_ASIDS; asid++) { |
234 | if (this_cpu_read(cpu_tlbstate.ctxs[asid].ctx_id) != |
235 | next->context.ctx_id) |
236 | continue; |
237 | |
238 | *new_asid = asid; |
239 | *need_flush = (this_cpu_read(cpu_tlbstate.ctxs[asid].tlb_gen) < |
240 | next_tlb_gen); |
241 | return; |
242 | } |
243 | |
244 | /* |
245 | * We don't currently own an ASID slot on this CPU. |
246 | * Allocate a slot. |
247 | */ |
248 | *new_asid = this_cpu_add_return(cpu_tlbstate.next_asid, 1) - 1; |
249 | if (*new_asid >= TLB_NR_DYN_ASIDS) { |
250 | *new_asid = 0; |
251 | this_cpu_write(cpu_tlbstate.next_asid, 1); |
252 | } |
253 | *need_flush = true; |
254 | } |
255 | |
256 | /* |
257 | * Given an ASID, flush the corresponding user ASID. We can delay this |
258 | * until the next time we switch to it. |
259 | * |
260 | * See SWITCH_TO_USER_CR3. |
261 | */ |
262 | static inline void invalidate_user_asid(u16 asid) |
263 | { |
264 | /* There is no user ASID if address space separation is off */ |
265 | if (!IS_ENABLED(CONFIG_PAGE_TABLE_ISOLATION)) |
266 | return; |
267 | |
268 | /* |
269 | * We only have a single ASID if PCID is off and the CR3 |
270 | * write will have flushed it. |
271 | */ |
272 | if (!cpu_feature_enabled(X86_FEATURE_PCID)) |
273 | return; |
274 | |
275 | if (!static_cpu_has(X86_FEATURE_PTI)) |
276 | return; |
277 | |
278 | __set_bit(kern_pcid(asid), |
279 | (unsigned long *)this_cpu_ptr(&cpu_tlbstate.user_pcid_flush_mask)); |
280 | } |
281 | |
282 | static void load_new_mm_cr3(pgd_t *pgdir, u16 new_asid, unsigned long lam, |
283 | bool need_flush) |
284 | { |
285 | unsigned long new_mm_cr3; |
286 | |
287 | if (need_flush) { |
288 | invalidate_user_asid(asid: new_asid); |
289 | new_mm_cr3 = build_cr3(pgd: pgdir, asid: new_asid, lam); |
290 | } else { |
291 | new_mm_cr3 = build_cr3_noflush(pgd: pgdir, asid: new_asid, lam); |
292 | } |
293 | |
294 | /* |
295 | * Caution: many callers of this function expect |
296 | * that load_cr3() is serializing and orders TLB |
297 | * fills with respect to the mm_cpumask writes. |
298 | */ |
299 | write_cr3(x: new_mm_cr3); |
300 | } |
301 | |
302 | void leave_mm(int cpu) |
303 | { |
304 | struct mm_struct *loaded_mm = this_cpu_read(cpu_tlbstate.loaded_mm); |
305 | |
306 | /* |
307 | * It's plausible that we're in lazy TLB mode while our mm is init_mm. |
308 | * If so, our callers still expect us to flush the TLB, but there |
309 | * aren't any user TLB entries in init_mm to worry about. |
310 | * |
311 | * This needs to happen before any other sanity checks due to |
312 | * intel_idle's shenanigans. |
313 | */ |
314 | if (loaded_mm == &init_mm) |
315 | return; |
316 | |
317 | /* Warn if we're not lazy. */ |
318 | WARN_ON(!this_cpu_read(cpu_tlbstate_shared.is_lazy)); |
319 | |
320 | switch_mm(NULL, next: &init_mm, NULL); |
321 | } |
322 | EXPORT_SYMBOL_GPL(leave_mm); |
323 | |
324 | void switch_mm(struct mm_struct *prev, struct mm_struct *next, |
325 | struct task_struct *tsk) |
326 | { |
327 | unsigned long flags; |
328 | |
329 | local_irq_save(flags); |
330 | switch_mm_irqs_off(prev, next, tsk); |
331 | local_irq_restore(flags); |
332 | } |
333 | |
334 | /* |
335 | * Invoked from return to user/guest by a task that opted-in to L1D |
336 | * flushing but ended up running on an SMT enabled core due to wrong |
337 | * affinity settings or CPU hotplug. This is part of the paranoid L1D flush |
338 | * contract which this task requested. |
339 | */ |
340 | static void l1d_flush_force_sigbus(struct callback_head *ch) |
341 | { |
342 | force_sig(SIGBUS); |
343 | } |
344 | |
345 | static void l1d_flush_evaluate(unsigned long prev_mm, unsigned long next_mm, |
346 | struct task_struct *next) |
347 | { |
348 | /* Flush L1D if the outgoing task requests it */ |
349 | if (prev_mm & LAST_USER_MM_L1D_FLUSH) |
350 | wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH); |
351 | |
352 | /* Check whether the incoming task opted in for L1D flush */ |
353 | if (likely(!(next_mm & LAST_USER_MM_L1D_FLUSH))) |
354 | return; |
355 | |
356 | /* |
357 | * Validate that it is not running on an SMT sibling as this would |
358 | * make the excercise pointless because the siblings share L1D. If |
359 | * it runs on a SMT sibling, notify it with SIGBUS on return to |
360 | * user/guest |
361 | */ |
362 | if (this_cpu_read(cpu_info.smt_active)) { |
363 | clear_ti_thread_flag(ti: &next->thread_info, TIF_SPEC_L1D_FLUSH); |
364 | next->l1d_flush_kill.func = l1d_flush_force_sigbus; |
365 | task_work_add(task: next, twork: &next->l1d_flush_kill, mode: TWA_RESUME); |
366 | } |
367 | } |
368 | |
369 | static unsigned long mm_mangle_tif_spec_bits(struct task_struct *next) |
370 | { |
371 | unsigned long next_tif = read_task_thread_flags(next); |
372 | unsigned long spec_bits = (next_tif >> TIF_SPEC_IB) & LAST_USER_MM_SPEC_MASK; |
373 | |
374 | /* |
375 | * Ensure that the bit shift above works as expected and the two flags |
376 | * end up in bit 0 and 1. |
377 | */ |
378 | BUILD_BUG_ON(TIF_SPEC_L1D_FLUSH != TIF_SPEC_IB + 1); |
379 | |
380 | return (unsigned long)next->mm | spec_bits; |
381 | } |
382 | |
383 | static void cond_mitigation(struct task_struct *next) |
384 | { |
385 | unsigned long prev_mm, next_mm; |
386 | |
387 | if (!next || !next->mm) |
388 | return; |
389 | |
390 | next_mm = mm_mangle_tif_spec_bits(next); |
391 | prev_mm = this_cpu_read(cpu_tlbstate.last_user_mm_spec); |
392 | |
393 | /* |
394 | * Avoid user/user BTB poisoning by flushing the branch predictor |
395 | * when switching between processes. This stops one process from |
396 | * doing Spectre-v2 attacks on another. |
397 | * |
398 | * Both, the conditional and the always IBPB mode use the mm |
399 | * pointer to avoid the IBPB when switching between tasks of the |
400 | * same process. Using the mm pointer instead of mm->context.ctx_id |
401 | * opens a hypothetical hole vs. mm_struct reuse, which is more or |
402 | * less impossible to control by an attacker. Aside of that it |
403 | * would only affect the first schedule so the theoretically |
404 | * exposed data is not really interesting. |
405 | */ |
406 | if (static_branch_likely(&switch_mm_cond_ibpb)) { |
407 | /* |
408 | * This is a bit more complex than the always mode because |
409 | * it has to handle two cases: |
410 | * |
411 | * 1) Switch from a user space task (potential attacker) |
412 | * which has TIF_SPEC_IB set to a user space task |
413 | * (potential victim) which has TIF_SPEC_IB not set. |
414 | * |
415 | * 2) Switch from a user space task (potential attacker) |
416 | * which has TIF_SPEC_IB not set to a user space task |
417 | * (potential victim) which has TIF_SPEC_IB set. |
418 | * |
419 | * This could be done by unconditionally issuing IBPB when |
420 | * a task which has TIF_SPEC_IB set is either scheduled in |
421 | * or out. Though that results in two flushes when: |
422 | * |
423 | * - the same user space task is scheduled out and later |
424 | * scheduled in again and only a kernel thread ran in |
425 | * between. |
426 | * |
427 | * - a user space task belonging to the same process is |
428 | * scheduled in after a kernel thread ran in between |
429 | * |
430 | * - a user space task belonging to the same process is |
431 | * scheduled in immediately. |
432 | * |
433 | * Optimize this with reasonably small overhead for the |
434 | * above cases. Mangle the TIF_SPEC_IB bit into the mm |
435 | * pointer of the incoming task which is stored in |
436 | * cpu_tlbstate.last_user_mm_spec for comparison. |
437 | * |
438 | * Issue IBPB only if the mm's are different and one or |
439 | * both have the IBPB bit set. |
440 | */ |
441 | if (next_mm != prev_mm && |
442 | (next_mm | prev_mm) & LAST_USER_MM_IBPB) |
443 | indirect_branch_prediction_barrier(); |
444 | } |
445 | |
446 | if (static_branch_unlikely(&switch_mm_always_ibpb)) { |
447 | /* |
448 | * Only flush when switching to a user space task with a |
449 | * different context than the user space task which ran |
450 | * last on this CPU. |
451 | */ |
452 | if ((prev_mm & ~LAST_USER_MM_SPEC_MASK) != |
453 | (unsigned long)next->mm) |
454 | indirect_branch_prediction_barrier(); |
455 | } |
456 | |
457 | if (static_branch_unlikely(&switch_mm_cond_l1d_flush)) { |
458 | /* |
459 | * Flush L1D when the outgoing task requested it and/or |
460 | * check whether the incoming task requested L1D flushing |
461 | * and ended up on an SMT sibling. |
462 | */ |
463 | if (unlikely((prev_mm | next_mm) & LAST_USER_MM_L1D_FLUSH)) |
464 | l1d_flush_evaluate(prev_mm, next_mm, next); |
465 | } |
466 | |
467 | this_cpu_write(cpu_tlbstate.last_user_mm_spec, next_mm); |
468 | } |
469 | |
470 | #ifdef CONFIG_PERF_EVENTS |
471 | static inline void cr4_update_pce_mm(struct mm_struct *mm) |
472 | { |
473 | if (static_branch_unlikely(&rdpmc_always_available_key) || |
474 | (!static_branch_unlikely(&rdpmc_never_available_key) && |
475 | atomic_read(v: &mm->context.perf_rdpmc_allowed))) { |
476 | /* |
477 | * Clear the existing dirty counters to |
478 | * prevent the leak for an RDPMC task. |
479 | */ |
480 | perf_clear_dirty_counters(); |
481 | cr4_set_bits_irqsoff(X86_CR4_PCE); |
482 | } else |
483 | cr4_clear_bits_irqsoff(X86_CR4_PCE); |
484 | } |
485 | |
486 | void cr4_update_pce(void *ignored) |
487 | { |
488 | cr4_update_pce_mm(this_cpu_read(cpu_tlbstate.loaded_mm)); |
489 | } |
490 | |
491 | #else |
492 | static inline void cr4_update_pce_mm(struct mm_struct *mm) { } |
493 | #endif |
494 | |
495 | void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next, |
496 | struct task_struct *tsk) |
497 | { |
498 | struct mm_struct *real_prev = this_cpu_read(cpu_tlbstate.loaded_mm); |
499 | u16 prev_asid = this_cpu_read(cpu_tlbstate.loaded_mm_asid); |
500 | unsigned long new_lam = mm_lam_cr3_mask(mm: next); |
501 | bool was_lazy = this_cpu_read(cpu_tlbstate_shared.is_lazy); |
502 | unsigned cpu = smp_processor_id(); |
503 | u64 next_tlb_gen; |
504 | bool need_flush; |
505 | u16 new_asid; |
506 | |
507 | /* |
508 | * NB: The scheduler will call us with prev == next when switching |
509 | * from lazy TLB mode to normal mode if active_mm isn't changing. |
510 | * When this happens, we don't assume that CR3 (and hence |
511 | * cpu_tlbstate.loaded_mm) matches next. |
512 | * |
513 | * NB: leave_mm() calls us with prev == NULL and tsk == NULL. |
514 | */ |
515 | |
516 | /* We don't want flush_tlb_func() to run concurrently with us. */ |
517 | if (IS_ENABLED(CONFIG_PROVE_LOCKING)) |
518 | WARN_ON_ONCE(!irqs_disabled()); |
519 | |
520 | /* |
521 | * Verify that CR3 is what we think it is. This will catch |
522 | * hypothetical buggy code that directly switches to swapper_pg_dir |
523 | * without going through leave_mm() / switch_mm_irqs_off() or that |
524 | * does something like write_cr3(read_cr3_pa()). |
525 | * |
526 | * Only do this check if CONFIG_DEBUG_VM=y because __read_cr3() |
527 | * isn't free. |
528 | */ |
529 | #ifdef CONFIG_DEBUG_VM |
530 | if (WARN_ON_ONCE(__read_cr3() != build_cr3(real_prev->pgd, prev_asid, |
531 | tlbstate_lam_cr3_mask()))) { |
532 | /* |
533 | * If we were to BUG here, we'd be very likely to kill |
534 | * the system so hard that we don't see the call trace. |
535 | * Try to recover instead by ignoring the error and doing |
536 | * a global flush to minimize the chance of corruption. |
537 | * |
538 | * (This is far from being a fully correct recovery. |
539 | * Architecturally, the CPU could prefetch something |
540 | * back into an incorrect ASID slot and leave it there |
541 | * to cause trouble down the road. It's better than |
542 | * nothing, though.) |
543 | */ |
544 | __flush_tlb_all(); |
545 | } |
546 | #endif |
547 | if (was_lazy) |
548 | this_cpu_write(cpu_tlbstate_shared.is_lazy, false); |
549 | |
550 | /* |
551 | * The membarrier system call requires a full memory barrier and |
552 | * core serialization before returning to user-space, after |
553 | * storing to rq->curr, when changing mm. This is because |
554 | * membarrier() sends IPIs to all CPUs that are in the target mm |
555 | * to make them issue memory barriers. However, if another CPU |
556 | * switches to/from the target mm concurrently with |
557 | * membarrier(), it can cause that CPU not to receive an IPI |
558 | * when it really should issue a memory barrier. Writing to CR3 |
559 | * provides that full memory barrier and core serializing |
560 | * instruction. |
561 | */ |
562 | if (real_prev == next) { |
563 | /* Not actually switching mm's */ |
564 | VM_WARN_ON(this_cpu_read(cpu_tlbstate.ctxs[prev_asid].ctx_id) != |
565 | next->context.ctx_id); |
566 | |
567 | /* |
568 | * If this races with another thread that enables lam, 'new_lam' |
569 | * might not match tlbstate_lam_cr3_mask(). |
570 | */ |
571 | |
572 | /* |
573 | * Even in lazy TLB mode, the CPU should stay set in the |
574 | * mm_cpumask. The TLB shootdown code can figure out from |
575 | * cpu_tlbstate_shared.is_lazy whether or not to send an IPI. |
576 | */ |
577 | if (WARN_ON_ONCE(real_prev != &init_mm && |
578 | !cpumask_test_cpu(cpu, mm_cpumask(next)))) |
579 | cpumask_set_cpu(cpu, dstp: mm_cpumask(mm: next)); |
580 | |
581 | /* |
582 | * If the CPU is not in lazy TLB mode, we are just switching |
583 | * from one thread in a process to another thread in the same |
584 | * process. No TLB flush required. |
585 | */ |
586 | if (!was_lazy) |
587 | return; |
588 | |
589 | /* |
590 | * Read the tlb_gen to check whether a flush is needed. |
591 | * If the TLB is up to date, just use it. |
592 | * The barrier synchronizes with the tlb_gen increment in |
593 | * the TLB shootdown code. |
594 | */ |
595 | smp_mb(); |
596 | next_tlb_gen = atomic64_read(v: &next->context.tlb_gen); |
597 | if (this_cpu_read(cpu_tlbstate.ctxs[prev_asid].tlb_gen) == |
598 | next_tlb_gen) |
599 | return; |
600 | |
601 | /* |
602 | * TLB contents went out of date while we were in lazy |
603 | * mode. Fall through to the TLB switching code below. |
604 | */ |
605 | new_asid = prev_asid; |
606 | need_flush = true; |
607 | } else { |
608 | /* |
609 | * Apply process to process speculation vulnerability |
610 | * mitigations if applicable. |
611 | */ |
612 | cond_mitigation(next: tsk); |
613 | |
614 | /* |
615 | * Stop remote flushes for the previous mm. |
616 | * Skip kernel threads; we never send init_mm TLB flushing IPIs, |
617 | * but the bitmap manipulation can cause cache line contention. |
618 | */ |
619 | if (real_prev != &init_mm) { |
620 | VM_WARN_ON_ONCE(!cpumask_test_cpu(cpu, |
621 | mm_cpumask(real_prev))); |
622 | cpumask_clear_cpu(cpu, dstp: mm_cpumask(mm: real_prev)); |
623 | } |
624 | |
625 | /* |
626 | * Start remote flushes and then read tlb_gen. |
627 | */ |
628 | if (next != &init_mm) |
629 | cpumask_set_cpu(cpu, dstp: mm_cpumask(mm: next)); |
630 | next_tlb_gen = atomic64_read(v: &next->context.tlb_gen); |
631 | |
632 | choose_new_asid(next, next_tlb_gen, new_asid: &new_asid, need_flush: &need_flush); |
633 | |
634 | /* Let nmi_uaccess_okay() know that we're changing CR3. */ |
635 | this_cpu_write(cpu_tlbstate.loaded_mm, LOADED_MM_SWITCHING); |
636 | barrier(); |
637 | } |
638 | |
639 | set_tlbstate_lam_mode(next); |
640 | if (need_flush) { |
641 | this_cpu_write(cpu_tlbstate.ctxs[new_asid].ctx_id, next->context.ctx_id); |
642 | this_cpu_write(cpu_tlbstate.ctxs[new_asid].tlb_gen, next_tlb_gen); |
643 | load_new_mm_cr3(pgdir: next->pgd, new_asid, lam: new_lam, need_flush: true); |
644 | |
645 | trace_tlb_flush(reason: TLB_FLUSH_ON_TASK_SWITCH, TLB_FLUSH_ALL); |
646 | } else { |
647 | /* The new ASID is already up to date. */ |
648 | load_new_mm_cr3(pgdir: next->pgd, new_asid, lam: new_lam, need_flush: false); |
649 | |
650 | trace_tlb_flush(reason: TLB_FLUSH_ON_TASK_SWITCH, pages: 0); |
651 | } |
652 | |
653 | /* Make sure we write CR3 before loaded_mm. */ |
654 | barrier(); |
655 | |
656 | this_cpu_write(cpu_tlbstate.loaded_mm, next); |
657 | this_cpu_write(cpu_tlbstate.loaded_mm_asid, new_asid); |
658 | |
659 | if (next != real_prev) { |
660 | cr4_update_pce_mm(mm: next); |
661 | switch_ldt(prev: real_prev, next); |
662 | } |
663 | } |
664 | |
665 | /* |
666 | * Please ignore the name of this function. It should be called |
667 | * switch_to_kernel_thread(). |
668 | * |
669 | * enter_lazy_tlb() is a hint from the scheduler that we are entering a |
670 | * kernel thread or other context without an mm. Acceptable implementations |
671 | * include doing nothing whatsoever, switching to init_mm, or various clever |
672 | * lazy tricks to try to minimize TLB flushes. |
673 | * |
674 | * The scheduler reserves the right to call enter_lazy_tlb() several times |
675 | * in a row. It will notify us that we're going back to a real mm by |
676 | * calling switch_mm_irqs_off(). |
677 | */ |
678 | void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) |
679 | { |
680 | if (this_cpu_read(cpu_tlbstate.loaded_mm) == &init_mm) |
681 | return; |
682 | |
683 | this_cpu_write(cpu_tlbstate_shared.is_lazy, true); |
684 | } |
685 | |
686 | /* |
687 | * Call this when reinitializing a CPU. It fixes the following potential |
688 | * problems: |
689 | * |
690 | * - The ASID changed from what cpu_tlbstate thinks it is (most likely |
691 | * because the CPU was taken down and came back up with CR3's PCID |
692 | * bits clear. CPU hotplug can do this. |
693 | * |
694 | * - The TLB contains junk in slots corresponding to inactive ASIDs. |
695 | * |
696 | * - The CPU went so far out to lunch that it may have missed a TLB |
697 | * flush. |
698 | */ |
699 | void initialize_tlbstate_and_flush(void) |
700 | { |
701 | int i; |
702 | struct mm_struct *mm = this_cpu_read(cpu_tlbstate.loaded_mm); |
703 | u64 tlb_gen = atomic64_read(v: &init_mm.context.tlb_gen); |
704 | unsigned long cr3 = __read_cr3(); |
705 | |
706 | /* Assert that CR3 already references the right mm. */ |
707 | WARN_ON((cr3 & CR3_ADDR_MASK) != __pa(mm->pgd)); |
708 | |
709 | /* LAM expected to be disabled */ |
710 | WARN_ON(cr3 & (X86_CR3_LAM_U48 | X86_CR3_LAM_U57)); |
711 | WARN_ON(mm_lam_cr3_mask(mm)); |
712 | |
713 | /* |
714 | * Assert that CR4.PCIDE is set if needed. (CR4.PCIDE initialization |
715 | * doesn't work like other CR4 bits because it can only be set from |
716 | * long mode.) |
717 | */ |
718 | WARN_ON(boot_cpu_has(X86_FEATURE_PCID) && |
719 | !(cr4_read_shadow() & X86_CR4_PCIDE)); |
720 | |
721 | /* Disable LAM, force ASID 0 and force a TLB flush. */ |
722 | write_cr3(x: build_cr3(pgd: mm->pgd, asid: 0, lam: 0)); |
723 | |
724 | /* Reinitialize tlbstate. */ |
725 | this_cpu_write(cpu_tlbstate.last_user_mm_spec, LAST_USER_MM_INIT); |
726 | this_cpu_write(cpu_tlbstate.loaded_mm_asid, 0); |
727 | this_cpu_write(cpu_tlbstate.next_asid, 1); |
728 | this_cpu_write(cpu_tlbstate.ctxs[0].ctx_id, mm->context.ctx_id); |
729 | this_cpu_write(cpu_tlbstate.ctxs[0].tlb_gen, tlb_gen); |
730 | set_tlbstate_lam_mode(mm); |
731 | |
732 | for (i = 1; i < TLB_NR_DYN_ASIDS; i++) |
733 | this_cpu_write(cpu_tlbstate.ctxs[i].ctx_id, 0); |
734 | } |
735 | |
736 | /* |
737 | * flush_tlb_func()'s memory ordering requirement is that any |
738 | * TLB fills that happen after we flush the TLB are ordered after we |
739 | * read active_mm's tlb_gen. We don't need any explicit barriers |
740 | * because all x86 flush operations are serializing and the |
741 | * atomic64_read operation won't be reordered by the compiler. |
742 | */ |
743 | static void flush_tlb_func(void *info) |
744 | { |
745 | /* |
746 | * We have three different tlb_gen values in here. They are: |
747 | * |
748 | * - mm_tlb_gen: the latest generation. |
749 | * - local_tlb_gen: the generation that this CPU has already caught |
750 | * up to. |
751 | * - f->new_tlb_gen: the generation that the requester of the flush |
752 | * wants us to catch up to. |
753 | */ |
754 | const struct flush_tlb_info *f = info; |
755 | struct mm_struct *loaded_mm = this_cpu_read(cpu_tlbstate.loaded_mm); |
756 | u32 loaded_mm_asid = this_cpu_read(cpu_tlbstate.loaded_mm_asid); |
757 | u64 local_tlb_gen = this_cpu_read(cpu_tlbstate.ctxs[loaded_mm_asid].tlb_gen); |
758 | bool local = smp_processor_id() == f->initiating_cpu; |
759 | unsigned long nr_invalidate = 0; |
760 | u64 mm_tlb_gen; |
761 | |
762 | /* This code cannot presently handle being reentered. */ |
763 | VM_WARN_ON(!irqs_disabled()); |
764 | |
765 | if (!local) { |
766 | inc_irq_stat(irq_tlb_count); |
767 | count_vm_tlb_event(NR_TLB_REMOTE_FLUSH_RECEIVED); |
768 | |
769 | /* Can only happen on remote CPUs */ |
770 | if (f->mm && f->mm != loaded_mm) |
771 | return; |
772 | } |
773 | |
774 | if (unlikely(loaded_mm == &init_mm)) |
775 | return; |
776 | |
777 | VM_WARN_ON(this_cpu_read(cpu_tlbstate.ctxs[loaded_mm_asid].ctx_id) != |
778 | loaded_mm->context.ctx_id); |
779 | |
780 | if (this_cpu_read(cpu_tlbstate_shared.is_lazy)) { |
781 | /* |
782 | * We're in lazy mode. We need to at least flush our |
783 | * paging-structure cache to avoid speculatively reading |
784 | * garbage into our TLB. Since switching to init_mm is barely |
785 | * slower than a minimal flush, just switch to init_mm. |
786 | * |
787 | * This should be rare, with native_flush_tlb_multi() skipping |
788 | * IPIs to lazy TLB mode CPUs. |
789 | */ |
790 | switch_mm_irqs_off(NULL, next: &init_mm, NULL); |
791 | return; |
792 | } |
793 | |
794 | if (unlikely(f->new_tlb_gen != TLB_GENERATION_INVALID && |
795 | f->new_tlb_gen <= local_tlb_gen)) { |
796 | /* |
797 | * The TLB is already up to date in respect to f->new_tlb_gen. |
798 | * While the core might be still behind mm_tlb_gen, checking |
799 | * mm_tlb_gen unnecessarily would have negative caching effects |
800 | * so avoid it. |
801 | */ |
802 | return; |
803 | } |
804 | |
805 | /* |
806 | * Defer mm_tlb_gen reading as long as possible to avoid cache |
807 | * contention. |
808 | */ |
809 | mm_tlb_gen = atomic64_read(v: &loaded_mm->context.tlb_gen); |
810 | |
811 | if (unlikely(local_tlb_gen == mm_tlb_gen)) { |
812 | /* |
813 | * There's nothing to do: we're already up to date. This can |
814 | * happen if two concurrent flushes happen -- the first flush to |
815 | * be handled can catch us all the way up, leaving no work for |
816 | * the second flush. |
817 | */ |
818 | goto done; |
819 | } |
820 | |
821 | WARN_ON_ONCE(local_tlb_gen > mm_tlb_gen); |
822 | WARN_ON_ONCE(f->new_tlb_gen > mm_tlb_gen); |
823 | |
824 | /* |
825 | * If we get to this point, we know that our TLB is out of date. |
826 | * This does not strictly imply that we need to flush (it's |
827 | * possible that f->new_tlb_gen <= local_tlb_gen), but we're |
828 | * going to need to flush in the very near future, so we might |
829 | * as well get it over with. |
830 | * |
831 | * The only question is whether to do a full or partial flush. |
832 | * |
833 | * We do a partial flush if requested and two extra conditions |
834 | * are met: |
835 | * |
836 | * 1. f->new_tlb_gen == local_tlb_gen + 1. We have an invariant that |
837 | * we've always done all needed flushes to catch up to |
838 | * local_tlb_gen. If, for example, local_tlb_gen == 2 and |
839 | * f->new_tlb_gen == 3, then we know that the flush needed to bring |
840 | * us up to date for tlb_gen 3 is the partial flush we're |
841 | * processing. |
842 | * |
843 | * As an example of why this check is needed, suppose that there |
844 | * are two concurrent flushes. The first is a full flush that |
845 | * changes context.tlb_gen from 1 to 2. The second is a partial |
846 | * flush that changes context.tlb_gen from 2 to 3. If they get |
847 | * processed on this CPU in reverse order, we'll see |
848 | * local_tlb_gen == 1, mm_tlb_gen == 3, and end != TLB_FLUSH_ALL. |
849 | * If we were to use __flush_tlb_one_user() and set local_tlb_gen to |
850 | * 3, we'd be break the invariant: we'd update local_tlb_gen above |
851 | * 1 without the full flush that's needed for tlb_gen 2. |
852 | * |
853 | * 2. f->new_tlb_gen == mm_tlb_gen. This is purely an optimization. |
854 | * Partial TLB flushes are not all that much cheaper than full TLB |
855 | * flushes, so it seems unlikely that it would be a performance win |
856 | * to do a partial flush if that won't bring our TLB fully up to |
857 | * date. By doing a full flush instead, we can increase |
858 | * local_tlb_gen all the way to mm_tlb_gen and we can probably |
859 | * avoid another flush in the very near future. |
860 | */ |
861 | if (f->end != TLB_FLUSH_ALL && |
862 | f->new_tlb_gen == local_tlb_gen + 1 && |
863 | f->new_tlb_gen == mm_tlb_gen) { |
864 | /* Partial flush */ |
865 | unsigned long addr = f->start; |
866 | |
867 | /* Partial flush cannot have invalid generations */ |
868 | VM_WARN_ON(f->new_tlb_gen == TLB_GENERATION_INVALID); |
869 | |
870 | /* Partial flush must have valid mm */ |
871 | VM_WARN_ON(f->mm == NULL); |
872 | |
873 | nr_invalidate = (f->end - f->start) >> f->stride_shift; |
874 | |
875 | while (addr < f->end) { |
876 | flush_tlb_one_user(addr); |
877 | addr += 1UL << f->stride_shift; |
878 | } |
879 | if (local) |
880 | count_vm_tlb_events(NR_TLB_LOCAL_FLUSH_ONE, nr_invalidate); |
881 | } else { |
882 | /* Full flush. */ |
883 | nr_invalidate = TLB_FLUSH_ALL; |
884 | |
885 | flush_tlb_local(); |
886 | if (local) |
887 | count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL); |
888 | } |
889 | |
890 | /* Both paths above update our state to mm_tlb_gen. */ |
891 | this_cpu_write(cpu_tlbstate.ctxs[loaded_mm_asid].tlb_gen, mm_tlb_gen); |
892 | |
893 | /* Tracing is done in a unified manner to reduce the code size */ |
894 | done: |
895 | trace_tlb_flush(reason: !local ? TLB_REMOTE_SHOOTDOWN : |
896 | (f->mm == NULL) ? TLB_LOCAL_SHOOTDOWN : |
897 | TLB_LOCAL_MM_SHOOTDOWN, |
898 | pages: nr_invalidate); |
899 | } |
900 | |
901 | static bool tlb_is_not_lazy(int cpu, void *data) |
902 | { |
903 | return !per_cpu(cpu_tlbstate_shared.is_lazy, cpu); |
904 | } |
905 | |
906 | DEFINE_PER_CPU_SHARED_ALIGNED(struct tlb_state_shared, cpu_tlbstate_shared); |
907 | EXPORT_PER_CPU_SYMBOL(cpu_tlbstate_shared); |
908 | |
909 | STATIC_NOPV void native_flush_tlb_multi(const struct cpumask *cpumask, |
910 | const struct flush_tlb_info *info) |
911 | { |
912 | /* |
913 | * Do accounting and tracing. Note that there are (and have always been) |
914 | * cases in which a remote TLB flush will be traced, but eventually |
915 | * would not happen. |
916 | */ |
917 | count_vm_tlb_event(NR_TLB_REMOTE_FLUSH); |
918 | if (info->end == TLB_FLUSH_ALL) |
919 | trace_tlb_flush(reason: TLB_REMOTE_SEND_IPI, TLB_FLUSH_ALL); |
920 | else |
921 | trace_tlb_flush(reason: TLB_REMOTE_SEND_IPI, |
922 | pages: (info->end - info->start) >> PAGE_SHIFT); |
923 | |
924 | /* |
925 | * If no page tables were freed, we can skip sending IPIs to |
926 | * CPUs in lazy TLB mode. They will flush the CPU themselves |
927 | * at the next context switch. |
928 | * |
929 | * However, if page tables are getting freed, we need to send the |
930 | * IPI everywhere, to prevent CPUs in lazy TLB mode from tripping |
931 | * up on the new contents of what used to be page tables, while |
932 | * doing a speculative memory access. |
933 | */ |
934 | if (info->freed_tables) |
935 | on_each_cpu_mask(mask: cpumask, func: flush_tlb_func, info: (void *)info, wait: true); |
936 | else |
937 | on_each_cpu_cond_mask(cond_func: tlb_is_not_lazy, func: flush_tlb_func, |
938 | info: (void *)info, wait: 1, mask: cpumask); |
939 | } |
940 | |
941 | void flush_tlb_multi(const struct cpumask *cpumask, |
942 | const struct flush_tlb_info *info) |
943 | { |
944 | __flush_tlb_multi(cpumask, info); |
945 | } |
946 | |
947 | /* |
948 | * See Documentation/arch/x86/tlb.rst for details. We choose 33 |
949 | * because it is large enough to cover the vast majority (at |
950 | * least 95%) of allocations, and is small enough that we are |
951 | * confident it will not cause too much overhead. Each single |
952 | * flush is about 100 ns, so this caps the maximum overhead at |
953 | * _about_ 3,000 ns. |
954 | * |
955 | * This is in units of pages. |
956 | */ |
957 | unsigned long tlb_single_page_flush_ceiling __read_mostly = 33; |
958 | |
959 | static DEFINE_PER_CPU_SHARED_ALIGNED(struct flush_tlb_info, flush_tlb_info); |
960 | |
961 | #ifdef CONFIG_DEBUG_VM |
962 | static DEFINE_PER_CPU(unsigned int, flush_tlb_info_idx); |
963 | #endif |
964 | |
965 | static struct flush_tlb_info *get_flush_tlb_info(struct mm_struct *mm, |
966 | unsigned long start, unsigned long end, |
967 | unsigned int stride_shift, bool freed_tables, |
968 | u64 new_tlb_gen) |
969 | { |
970 | struct flush_tlb_info *info = this_cpu_ptr(&flush_tlb_info); |
971 | |
972 | #ifdef CONFIG_DEBUG_VM |
973 | /* |
974 | * Ensure that the following code is non-reentrant and flush_tlb_info |
975 | * is not overwritten. This means no TLB flushing is initiated by |
976 | * interrupt handlers and machine-check exception handlers. |
977 | */ |
978 | BUG_ON(this_cpu_inc_return(flush_tlb_info_idx) != 1); |
979 | #endif |
980 | |
981 | info->start = start; |
982 | info->end = end; |
983 | info->mm = mm; |
984 | info->stride_shift = stride_shift; |
985 | info->freed_tables = freed_tables; |
986 | info->new_tlb_gen = new_tlb_gen; |
987 | info->initiating_cpu = smp_processor_id(); |
988 | |
989 | return info; |
990 | } |
991 | |
992 | static void put_flush_tlb_info(void) |
993 | { |
994 | #ifdef CONFIG_DEBUG_VM |
995 | /* Complete reentrancy prevention checks */ |
996 | barrier(); |
997 | this_cpu_dec(flush_tlb_info_idx); |
998 | #endif |
999 | } |
1000 | |
1001 | void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start, |
1002 | unsigned long end, unsigned int stride_shift, |
1003 | bool freed_tables) |
1004 | { |
1005 | struct flush_tlb_info *info; |
1006 | u64 new_tlb_gen; |
1007 | int cpu; |
1008 | |
1009 | cpu = get_cpu(); |
1010 | |
1011 | /* Should we flush just the requested range? */ |
1012 | if ((end == TLB_FLUSH_ALL) || |
1013 | ((end - start) >> stride_shift) > tlb_single_page_flush_ceiling) { |
1014 | start = 0; |
1015 | end = TLB_FLUSH_ALL; |
1016 | } |
1017 | |
1018 | /* This is also a barrier that synchronizes with switch_mm(). */ |
1019 | new_tlb_gen = inc_mm_tlb_gen(mm); |
1020 | |
1021 | info = get_flush_tlb_info(mm, start, end, stride_shift, freed_tables, |
1022 | new_tlb_gen); |
1023 | |
1024 | /* |
1025 | * flush_tlb_multi() is not optimized for the common case in which only |
1026 | * a local TLB flush is needed. Optimize this use-case by calling |
1027 | * flush_tlb_func_local() directly in this case. |
1028 | */ |
1029 | if (cpumask_any_but(mask: mm_cpumask(mm), cpu) < nr_cpu_ids) { |
1030 | flush_tlb_multi(cpumask: mm_cpumask(mm), info); |
1031 | } else if (mm == this_cpu_read(cpu_tlbstate.loaded_mm)) { |
1032 | lockdep_assert_irqs_enabled(); |
1033 | local_irq_disable(); |
1034 | flush_tlb_func(info); |
1035 | local_irq_enable(); |
1036 | } |
1037 | |
1038 | put_flush_tlb_info(); |
1039 | put_cpu(); |
1040 | mmu_notifier_arch_invalidate_secondary_tlbs(mm, start, end); |
1041 | } |
1042 | |
1043 | |
1044 | static void do_flush_tlb_all(void *info) |
1045 | { |
1046 | count_vm_tlb_event(NR_TLB_REMOTE_FLUSH_RECEIVED); |
1047 | __flush_tlb_all(); |
1048 | } |
1049 | |
1050 | void flush_tlb_all(void) |
1051 | { |
1052 | count_vm_tlb_event(NR_TLB_REMOTE_FLUSH); |
1053 | on_each_cpu(func: do_flush_tlb_all, NULL, wait: 1); |
1054 | } |
1055 | |
1056 | static void do_kernel_range_flush(void *info) |
1057 | { |
1058 | struct flush_tlb_info *f = info; |
1059 | unsigned long addr; |
1060 | |
1061 | /* flush range by one by one 'invlpg' */ |
1062 | for (addr = f->start; addr < f->end; addr += PAGE_SIZE) |
1063 | flush_tlb_one_kernel(addr); |
1064 | } |
1065 | |
1066 | void flush_tlb_kernel_range(unsigned long start, unsigned long end) |
1067 | { |
1068 | /* Balance as user space task's flush, a bit conservative */ |
1069 | if (end == TLB_FLUSH_ALL || |
1070 | (end - start) > tlb_single_page_flush_ceiling << PAGE_SHIFT) { |
1071 | on_each_cpu(func: do_flush_tlb_all, NULL, wait: 1); |
1072 | } else { |
1073 | struct flush_tlb_info *info; |
1074 | |
1075 | preempt_disable(); |
1076 | info = get_flush_tlb_info(NULL, start, end, stride_shift: 0, freed_tables: false, |
1077 | TLB_GENERATION_INVALID); |
1078 | |
1079 | on_each_cpu(func: do_kernel_range_flush, info, wait: 1); |
1080 | |
1081 | put_flush_tlb_info(); |
1082 | preempt_enable(); |
1083 | } |
1084 | } |
1085 | |
1086 | /* |
1087 | * This can be used from process context to figure out what the value of |
1088 | * CR3 is without needing to do a (slow) __read_cr3(). |
1089 | * |
1090 | * It's intended to be used for code like KVM that sneakily changes CR3 |
1091 | * and needs to restore it. It needs to be used very carefully. |
1092 | */ |
1093 | unsigned long __get_current_cr3_fast(void) |
1094 | { |
1095 | unsigned long cr3 = |
1096 | build_cr3(this_cpu_read(cpu_tlbstate.loaded_mm)->pgd, |
1097 | this_cpu_read(cpu_tlbstate.loaded_mm_asid), |
1098 | lam: tlbstate_lam_cr3_mask()); |
1099 | |
1100 | /* For now, be very restrictive about when this can be called. */ |
1101 | VM_WARN_ON(in_nmi() || preemptible()); |
1102 | |
1103 | VM_BUG_ON(cr3 != __read_cr3()); |
1104 | return cr3; |
1105 | } |
1106 | EXPORT_SYMBOL_GPL(__get_current_cr3_fast); |
1107 | |
1108 | /* |
1109 | * Flush one page in the kernel mapping |
1110 | */ |
1111 | void flush_tlb_one_kernel(unsigned long addr) |
1112 | { |
1113 | count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ONE); |
1114 | |
1115 | /* |
1116 | * If PTI is off, then __flush_tlb_one_user() is just INVLPG or its |
1117 | * paravirt equivalent. Even with PCID, this is sufficient: we only |
1118 | * use PCID if we also use global PTEs for the kernel mapping, and |
1119 | * INVLPG flushes global translations across all address spaces. |
1120 | * |
1121 | * If PTI is on, then the kernel is mapped with non-global PTEs, and |
1122 | * __flush_tlb_one_user() will flush the given address for the current |
1123 | * kernel address space and for its usermode counterpart, but it does |
1124 | * not flush it for other address spaces. |
1125 | */ |
1126 | flush_tlb_one_user(addr); |
1127 | |
1128 | if (!static_cpu_has(X86_FEATURE_PTI)) |
1129 | return; |
1130 | |
1131 | /* |
1132 | * See above. We need to propagate the flush to all other address |
1133 | * spaces. In principle, we only need to propagate it to kernelmode |
1134 | * address spaces, but the extra bookkeeping we would need is not |
1135 | * worth it. |
1136 | */ |
1137 | this_cpu_write(cpu_tlbstate.invalidate_other, true); |
1138 | } |
1139 | |
1140 | /* |
1141 | * Flush one page in the user mapping |
1142 | */ |
1143 | STATIC_NOPV void native_flush_tlb_one_user(unsigned long addr) |
1144 | { |
1145 | u32 loaded_mm_asid; |
1146 | bool cpu_pcide; |
1147 | |
1148 | /* Flush 'addr' from the kernel PCID: */ |
1149 | asm volatile("invlpg (%0)" ::"r" (addr) : "memory" ); |
1150 | |
1151 | /* If PTI is off there is no user PCID and nothing to flush. */ |
1152 | if (!static_cpu_has(X86_FEATURE_PTI)) |
1153 | return; |
1154 | |
1155 | loaded_mm_asid = this_cpu_read(cpu_tlbstate.loaded_mm_asid); |
1156 | cpu_pcide = this_cpu_read(cpu_tlbstate.cr4) & X86_CR4_PCIDE; |
1157 | |
1158 | /* |
1159 | * invpcid_flush_one(pcid>0) will #GP if CR4.PCIDE==0. Check |
1160 | * 'cpu_pcide' to ensure that *this* CPU will not trigger those |
1161 | * #GP's even if called before CR4.PCIDE has been initialized. |
1162 | */ |
1163 | if (boot_cpu_has(X86_FEATURE_INVPCID) && cpu_pcide) |
1164 | invpcid_flush_one(pcid: user_pcid(asid: loaded_mm_asid), addr); |
1165 | else |
1166 | invalidate_user_asid(asid: loaded_mm_asid); |
1167 | } |
1168 | |
1169 | void flush_tlb_one_user(unsigned long addr) |
1170 | { |
1171 | __flush_tlb_one_user(addr); |
1172 | } |
1173 | |
1174 | /* |
1175 | * Flush everything |
1176 | */ |
1177 | STATIC_NOPV void native_flush_tlb_global(void) |
1178 | { |
1179 | unsigned long flags; |
1180 | |
1181 | if (static_cpu_has(X86_FEATURE_INVPCID)) { |
1182 | /* |
1183 | * Using INVPCID is considerably faster than a pair of writes |
1184 | * to CR4 sandwiched inside an IRQ flag save/restore. |
1185 | * |
1186 | * Note, this works with CR4.PCIDE=0 or 1. |
1187 | */ |
1188 | invpcid_flush_all(); |
1189 | return; |
1190 | } |
1191 | |
1192 | /* |
1193 | * Read-modify-write to CR4 - protect it from preemption and |
1194 | * from interrupts. (Use the raw variant because this code can |
1195 | * be called from deep inside debugging code.) |
1196 | */ |
1197 | raw_local_irq_save(flags); |
1198 | |
1199 | __native_tlb_flush_global(this_cpu_read(cpu_tlbstate.cr4)); |
1200 | |
1201 | raw_local_irq_restore(flags); |
1202 | } |
1203 | |
1204 | /* |
1205 | * Flush the entire current user mapping |
1206 | */ |
1207 | STATIC_NOPV void native_flush_tlb_local(void) |
1208 | { |
1209 | /* |
1210 | * Preemption or interrupts must be disabled to protect the access |
1211 | * to the per CPU variable and to prevent being preempted between |
1212 | * read_cr3() and write_cr3(). |
1213 | */ |
1214 | WARN_ON_ONCE(preemptible()); |
1215 | |
1216 | invalidate_user_asid(this_cpu_read(cpu_tlbstate.loaded_mm_asid)); |
1217 | |
1218 | /* If current->mm == NULL then the read_cr3() "borrows" an mm */ |
1219 | native_write_cr3(val: __native_read_cr3()); |
1220 | } |
1221 | |
1222 | void flush_tlb_local(void) |
1223 | { |
1224 | __flush_tlb_local(); |
1225 | } |
1226 | |
1227 | /* |
1228 | * Flush everything |
1229 | */ |
1230 | void __flush_tlb_all(void) |
1231 | { |
1232 | /* |
1233 | * This is to catch users with enabled preemption and the PGE feature |
1234 | * and don't trigger the warning in __native_flush_tlb(). |
1235 | */ |
1236 | VM_WARN_ON_ONCE(preemptible()); |
1237 | |
1238 | if (cpu_feature_enabled(X86_FEATURE_PGE)) { |
1239 | __flush_tlb_global(); |
1240 | } else { |
1241 | /* |
1242 | * !PGE -> !PCID (setup_pcid()), thus every flush is total. |
1243 | */ |
1244 | flush_tlb_local(); |
1245 | } |
1246 | } |
1247 | EXPORT_SYMBOL_GPL(__flush_tlb_all); |
1248 | |
1249 | void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch) |
1250 | { |
1251 | struct flush_tlb_info *info; |
1252 | |
1253 | int cpu = get_cpu(); |
1254 | |
1255 | info = get_flush_tlb_info(NULL, start: 0, TLB_FLUSH_ALL, stride_shift: 0, freed_tables: false, |
1256 | TLB_GENERATION_INVALID); |
1257 | /* |
1258 | * flush_tlb_multi() is not optimized for the common case in which only |
1259 | * a local TLB flush is needed. Optimize this use-case by calling |
1260 | * flush_tlb_func_local() directly in this case. |
1261 | */ |
1262 | if (cpumask_any_but(mask: &batch->cpumask, cpu) < nr_cpu_ids) { |
1263 | flush_tlb_multi(cpumask: &batch->cpumask, info); |
1264 | } else if (cpumask_test_cpu(cpu, cpumask: &batch->cpumask)) { |
1265 | lockdep_assert_irqs_enabled(); |
1266 | local_irq_disable(); |
1267 | flush_tlb_func(info); |
1268 | local_irq_enable(); |
1269 | } |
1270 | |
1271 | cpumask_clear(dstp: &batch->cpumask); |
1272 | |
1273 | put_flush_tlb_info(); |
1274 | put_cpu(); |
1275 | } |
1276 | |
1277 | /* |
1278 | * Blindly accessing user memory from NMI context can be dangerous |
1279 | * if we're in the middle of switching the current user task or |
1280 | * switching the loaded mm. It can also be dangerous if we |
1281 | * interrupted some kernel code that was temporarily using a |
1282 | * different mm. |
1283 | */ |
1284 | bool nmi_uaccess_okay(void) |
1285 | { |
1286 | struct mm_struct *loaded_mm = this_cpu_read(cpu_tlbstate.loaded_mm); |
1287 | struct mm_struct *current_mm = current->mm; |
1288 | |
1289 | VM_WARN_ON_ONCE(!loaded_mm); |
1290 | |
1291 | /* |
1292 | * The condition we want to check is |
1293 | * current_mm->pgd == __va(read_cr3_pa()). This may be slow, though, |
1294 | * if we're running in a VM with shadow paging, and nmi_uaccess_okay() |
1295 | * is supposed to be reasonably fast. |
1296 | * |
1297 | * Instead, we check the almost equivalent but somewhat conservative |
1298 | * condition below, and we rely on the fact that switch_mm_irqs_off() |
1299 | * sets loaded_mm to LOADED_MM_SWITCHING before writing to CR3. |
1300 | */ |
1301 | if (loaded_mm != current_mm) |
1302 | return false; |
1303 | |
1304 | VM_WARN_ON_ONCE(current_mm->pgd != __va(read_cr3_pa())); |
1305 | |
1306 | return true; |
1307 | } |
1308 | |
1309 | static ssize_t tlbflush_read_file(struct file *file, char __user *user_buf, |
1310 | size_t count, loff_t *ppos) |
1311 | { |
1312 | char buf[32]; |
1313 | unsigned int len; |
1314 | |
1315 | len = sprintf(buf, fmt: "%ld\n" , tlb_single_page_flush_ceiling); |
1316 | return simple_read_from_buffer(to: user_buf, count, ppos, from: buf, available: len); |
1317 | } |
1318 | |
1319 | static ssize_t tlbflush_write_file(struct file *file, |
1320 | const char __user *user_buf, size_t count, loff_t *ppos) |
1321 | { |
1322 | char buf[32]; |
1323 | ssize_t len; |
1324 | int ceiling; |
1325 | |
1326 | len = min(count, sizeof(buf) - 1); |
1327 | if (copy_from_user(to: buf, from: user_buf, n: len)) |
1328 | return -EFAULT; |
1329 | |
1330 | buf[len] = '\0'; |
1331 | if (kstrtoint(s: buf, base: 0, res: &ceiling)) |
1332 | return -EINVAL; |
1333 | |
1334 | if (ceiling < 0) |
1335 | return -EINVAL; |
1336 | |
1337 | tlb_single_page_flush_ceiling = ceiling; |
1338 | return count; |
1339 | } |
1340 | |
1341 | static const struct file_operations fops_tlbflush = { |
1342 | .read = tlbflush_read_file, |
1343 | .write = tlbflush_write_file, |
1344 | .llseek = default_llseek, |
1345 | }; |
1346 | |
1347 | static int __init create_tlb_single_page_flush_ceiling(void) |
1348 | { |
1349 | debugfs_create_file(name: "tlb_single_page_flush_ceiling" , S_IRUSR | S_IWUSR, |
1350 | parent: arch_debugfs_dir, NULL, fops: &fops_tlbflush); |
1351 | return 0; |
1352 | } |
1353 | late_initcall(create_tlb_single_page_flush_ceiling); |
1354 | |