1 | /* |
2 | * Copyright 2019 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | */ |
23 | |
24 | #include <linux/delay.h> |
25 | #include <linux/kernel.h> |
26 | #include <linux/firmware.h> |
27 | #include <linux/module.h> |
28 | #include <linux/pci.h> |
29 | #include "amdgpu.h" |
30 | #include "amdgpu_gfx.h" |
31 | #include "amdgpu_psp.h" |
32 | #include "nv.h" |
33 | #include "nvd.h" |
34 | |
35 | #include "gc/gc_10_1_0_offset.h" |
36 | #include "gc/gc_10_1_0_sh_mask.h" |
37 | #include "smuio/smuio_11_0_0_offset.h" |
38 | #include "smuio/smuio_11_0_0_sh_mask.h" |
39 | #include "navi10_enum.h" |
40 | #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h" |
41 | |
42 | #include "soc15.h" |
43 | #include "soc15d.h" |
44 | #include "soc15_common.h" |
45 | #include "clearstate_gfx10.h" |
46 | #include "v10_structs.h" |
47 | #include "gfx_v10_0.h" |
48 | #include "nbio_v2_3.h" |
49 | |
50 | /* |
51 | * Navi10 has two graphic rings to share each graphic pipe. |
52 | * 1. Primary ring |
53 | * 2. Async ring |
54 | */ |
55 | #define GFX10_NUM_GFX_RINGS_NV1X 1 |
56 | #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid 2 |
57 | #define GFX10_MEC_HPD_SIZE 2048 |
58 | |
59 | #define F32_CE_PROGRAM_RAM_SIZE 65536 |
60 | #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L |
61 | |
62 | #define mmCGTT_GS_NGG_CLK_CTRL 0x5087 |
63 | #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1 |
64 | #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a |
65 | #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1 |
66 | #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b |
67 | #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1 |
68 | |
69 | #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8 |
70 | #define GB_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L |
71 | |
72 | #define mmCGTS_TCC_DISABLE_gc_10_3 0x5006 |
73 | #define mmCGTS_TCC_DISABLE_gc_10_3_BASE_IDX 1 |
74 | #define mmCGTS_USER_TCC_DISABLE_gc_10_3 0x5007 |
75 | #define mmCGTS_USER_TCC_DISABLE_gc_10_3_BASE_IDX 1 |
76 | |
77 | #define mmCP_MEC_CNTL_Sienna_Cichlid 0x0f55 |
78 | #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX 0 |
79 | #define mmRLC_SAFE_MODE_Sienna_Cichlid 0x4ca0 |
80 | #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX 1 |
81 | #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid 0x4ca1 |
82 | #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX 1 |
83 | #define mmSPI_CONFIG_CNTL_Sienna_Cichlid 0x11ec |
84 | #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX 0 |
85 | #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid 0x0fc1 |
86 | #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 |
87 | #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid 0x0fc2 |
88 | #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 |
89 | #define mmVGT_TF_RING_SIZE_Sienna_Cichlid 0x0fc3 |
90 | #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 |
91 | #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid 0x0fc4 |
92 | #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX 0 |
93 | #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid 0x0fc5 |
94 | #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX 0 |
95 | #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid 0x0fc6 |
96 | #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0 |
97 | #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT 0x1a |
98 | #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK 0x04000000L |
99 | #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK 0x00000FFCL |
100 | #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT 0x2 |
101 | #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK 0x00000FFCL |
102 | #define mmGCR_GENERAL_CNTL_Sienna_Cichlid 0x1580 |
103 | #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX 0 |
104 | |
105 | #define mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish 0x0105 |
106 | #define mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish_BASE_IDX 1 |
107 | #define mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish 0x0106 |
108 | #define mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish_BASE_IDX 1 |
109 | |
110 | #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh 0x0025 |
111 | #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX 1 |
112 | #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh 0x0026 |
113 | #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX 1 |
114 | |
115 | #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6 0x002d |
116 | #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6_BASE_IDX 1 |
117 | #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6 0x002e |
118 | #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6_BASE_IDX 1 |
119 | |
120 | #define mmSPI_CONFIG_CNTL_1_Vangogh 0x2441 |
121 | #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX 1 |
122 | #define mmVGT_TF_MEMORY_BASE_HI_Vangogh 0x2261 |
123 | #define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1 |
124 | #define mmVGT_HS_OFFCHIP_PARAM_Vangogh 0x224f |
125 | #define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX 1 |
126 | #define mmVGT_TF_RING_SIZE_Vangogh 0x224e |
127 | #define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX 1 |
128 | #define mmVGT_GSVS_RING_SIZE_Vangogh 0x2241 |
129 | #define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX 1 |
130 | #define mmVGT_TF_MEMORY_BASE_Vangogh 0x2250 |
131 | #define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX 1 |
132 | #define mmVGT_ESGS_RING_SIZE_Vangogh 0x2240 |
133 | #define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX 1 |
134 | #define mmSPI_CONFIG_CNTL_Vangogh 0x2440 |
135 | #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX 1 |
136 | #define mmGCR_GENERAL_CNTL_Vangogh 0x1580 |
137 | #define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX 0 |
138 | #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh 0x0000FFFFL |
139 | |
140 | #define mmCP_HYP_PFP_UCODE_ADDR 0x5814 |
141 | #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1 |
142 | #define mmCP_HYP_PFP_UCODE_DATA 0x5815 |
143 | #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX 1 |
144 | #define mmCP_HYP_CE_UCODE_ADDR 0x5818 |
145 | #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX 1 |
146 | #define mmCP_HYP_CE_UCODE_DATA 0x5819 |
147 | #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX 1 |
148 | #define mmCP_HYP_ME_UCODE_ADDR 0x5816 |
149 | #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX 1 |
150 | #define mmCP_HYP_ME_UCODE_DATA 0x5817 |
151 | #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX 1 |
152 | |
153 | #define mmCPG_PSP_DEBUG 0x5c10 |
154 | #define mmCPG_PSP_DEBUG_BASE_IDX 1 |
155 | #define mmCPC_PSP_DEBUG 0x5c11 |
156 | #define mmCPC_PSP_DEBUG_BASE_IDX 1 |
157 | #define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L |
158 | #define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L |
159 | |
160 | //CC_GC_SA_UNIT_DISABLE |
161 | #define mmCC_GC_SA_UNIT_DISABLE 0x0fe9 |
162 | #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX 0 |
163 | #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 |
164 | #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L |
165 | //GC_USER_SA_UNIT_DISABLE |
166 | #define mmGC_USER_SA_UNIT_DISABLE 0x0fea |
167 | #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX 0 |
168 | #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 |
169 | #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L |
170 | //PA_SC_ENHANCE_3 |
171 | #define mmPA_SC_ENHANCE_3 0x1085 |
172 | #define mmPA_SC_ENHANCE_3_BASE_IDX 0 |
173 | #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3 |
174 | #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK 0x00000008L |
175 | |
176 | #define mmCGTT_SPI_CS_CLK_CTRL 0x507c |
177 | #define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX 1 |
178 | |
179 | #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid 0x16f3 |
180 | #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0 |
181 | #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid 0x15db |
182 | #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0 |
183 | |
184 | #define mmGC_THROTTLE_CTRL_Sienna_Cichlid 0x2030 |
185 | #define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX 0 |
186 | |
187 | #define mmRLC_SPARE_INT_0_Sienna_Cichlid 0x4ca5 |
188 | #define mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX 1 |
189 | |
190 | MODULE_FIRMWARE("amdgpu/navi10_ce.bin" ); |
191 | MODULE_FIRMWARE("amdgpu/navi10_pfp.bin" ); |
192 | MODULE_FIRMWARE("amdgpu/navi10_me.bin" ); |
193 | MODULE_FIRMWARE("amdgpu/navi10_mec.bin" ); |
194 | MODULE_FIRMWARE("amdgpu/navi10_mec2.bin" ); |
195 | MODULE_FIRMWARE("amdgpu/navi10_rlc.bin" ); |
196 | |
197 | MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin" ); |
198 | MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin" ); |
199 | MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin" ); |
200 | MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin" ); |
201 | MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin" ); |
202 | MODULE_FIRMWARE("amdgpu/navi14_ce.bin" ); |
203 | MODULE_FIRMWARE("amdgpu/navi14_pfp.bin" ); |
204 | MODULE_FIRMWARE("amdgpu/navi14_me.bin" ); |
205 | MODULE_FIRMWARE("amdgpu/navi14_mec.bin" ); |
206 | MODULE_FIRMWARE("amdgpu/navi14_mec2.bin" ); |
207 | MODULE_FIRMWARE("amdgpu/navi14_rlc.bin" ); |
208 | |
209 | MODULE_FIRMWARE("amdgpu/navi12_ce.bin" ); |
210 | MODULE_FIRMWARE("amdgpu/navi12_pfp.bin" ); |
211 | MODULE_FIRMWARE("amdgpu/navi12_me.bin" ); |
212 | MODULE_FIRMWARE("amdgpu/navi12_mec.bin" ); |
213 | MODULE_FIRMWARE("amdgpu/navi12_mec2.bin" ); |
214 | MODULE_FIRMWARE("amdgpu/navi12_rlc.bin" ); |
215 | |
216 | MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin" ); |
217 | MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin" ); |
218 | MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin" ); |
219 | MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin" ); |
220 | MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin" ); |
221 | MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin" ); |
222 | |
223 | MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin" ); |
224 | MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin" ); |
225 | MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin" ); |
226 | MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin" ); |
227 | MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin" ); |
228 | MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin" ); |
229 | |
230 | MODULE_FIRMWARE("amdgpu/vangogh_ce.bin" ); |
231 | MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin" ); |
232 | MODULE_FIRMWARE("amdgpu/vangogh_me.bin" ); |
233 | MODULE_FIRMWARE("amdgpu/vangogh_mec.bin" ); |
234 | MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin" ); |
235 | MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin" ); |
236 | |
237 | MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin" ); |
238 | MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin" ); |
239 | MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin" ); |
240 | MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin" ); |
241 | MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin" ); |
242 | MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin" ); |
243 | |
244 | MODULE_FIRMWARE("amdgpu/beige_goby_ce.bin" ); |
245 | MODULE_FIRMWARE("amdgpu/beige_goby_pfp.bin" ); |
246 | MODULE_FIRMWARE("amdgpu/beige_goby_me.bin" ); |
247 | MODULE_FIRMWARE("amdgpu/beige_goby_mec.bin" ); |
248 | MODULE_FIRMWARE("amdgpu/beige_goby_mec2.bin" ); |
249 | MODULE_FIRMWARE("amdgpu/beige_goby_rlc.bin" ); |
250 | |
251 | MODULE_FIRMWARE("amdgpu/yellow_carp_ce.bin" ); |
252 | MODULE_FIRMWARE("amdgpu/yellow_carp_pfp.bin" ); |
253 | MODULE_FIRMWARE("amdgpu/yellow_carp_me.bin" ); |
254 | MODULE_FIRMWARE("amdgpu/yellow_carp_mec.bin" ); |
255 | MODULE_FIRMWARE("amdgpu/yellow_carp_mec2.bin" ); |
256 | MODULE_FIRMWARE("amdgpu/yellow_carp_rlc.bin" ); |
257 | |
258 | MODULE_FIRMWARE("amdgpu/cyan_skillfish2_ce.bin" ); |
259 | MODULE_FIRMWARE("amdgpu/cyan_skillfish2_pfp.bin" ); |
260 | MODULE_FIRMWARE("amdgpu/cyan_skillfish2_me.bin" ); |
261 | MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec.bin" ); |
262 | MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec2.bin" ); |
263 | MODULE_FIRMWARE("amdgpu/cyan_skillfish2_rlc.bin" ); |
264 | |
265 | MODULE_FIRMWARE("amdgpu/gc_10_3_6_ce.bin" ); |
266 | MODULE_FIRMWARE("amdgpu/gc_10_3_6_pfp.bin" ); |
267 | MODULE_FIRMWARE("amdgpu/gc_10_3_6_me.bin" ); |
268 | MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec.bin" ); |
269 | MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec2.bin" ); |
270 | MODULE_FIRMWARE("amdgpu/gc_10_3_6_rlc.bin" ); |
271 | |
272 | MODULE_FIRMWARE("amdgpu/gc_10_3_7_ce.bin" ); |
273 | MODULE_FIRMWARE("amdgpu/gc_10_3_7_pfp.bin" ); |
274 | MODULE_FIRMWARE("amdgpu/gc_10_3_7_me.bin" ); |
275 | MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin" ); |
276 | MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin" ); |
277 | MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin" ); |
278 | |
279 | static const struct soc15_reg_golden golden_settings_gc_10_1[] = { |
280 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014), |
281 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100), |
282 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), |
283 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100), |
284 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100), |
285 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), |
286 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100), |
287 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), |
288 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), |
289 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff), |
290 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000), |
291 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), |
292 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), |
293 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000), |
294 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), |
295 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), |
296 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), |
297 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), |
298 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), |
299 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), |
300 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), |
301 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), |
302 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), |
303 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100), |
304 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), |
305 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188), |
306 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), |
307 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), |
308 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), |
309 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), |
310 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), |
311 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), |
312 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104), |
313 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), |
314 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130), |
315 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), |
316 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), |
317 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), |
318 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100), |
319 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000) |
320 | }; |
321 | |
322 | static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] = { |
323 | /* Pending on emulation bring up */ |
324 | }; |
325 | |
326 | static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] = { |
327 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0), |
328 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
329 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), |
330 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
331 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), |
332 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
333 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), |
334 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
335 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), |
336 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
337 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), |
338 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
339 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), |
340 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
341 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), |
342 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
343 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), |
344 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
345 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), |
346 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
347 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), |
348 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
349 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), |
350 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
351 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), |
352 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
353 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), |
354 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
355 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), |
356 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
357 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), |
358 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
359 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), |
360 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
361 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), |
362 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
363 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), |
364 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
365 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), |
366 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
367 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), |
368 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
369 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), |
370 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
371 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), |
372 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
373 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), |
374 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
375 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), |
376 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
377 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), |
378 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
379 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), |
380 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
381 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), |
382 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
383 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), |
384 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
385 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), |
386 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
387 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), |
388 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
389 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), |
390 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
391 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), |
392 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
393 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), |
394 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
395 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), |
396 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
397 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), |
398 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
399 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), |
400 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
401 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), |
402 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
403 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), |
404 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
405 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), |
406 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
407 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), |
408 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
409 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), |
410 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
411 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), |
412 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
413 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), |
414 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
415 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), |
416 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
417 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), |
418 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
419 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), |
420 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
421 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), |
422 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
423 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), |
424 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
425 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), |
426 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
427 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), |
428 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
429 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), |
430 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
431 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), |
432 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
433 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), |
434 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
435 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), |
436 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
437 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), |
438 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
439 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), |
440 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
441 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), |
442 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
443 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), |
444 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
445 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), |
446 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
447 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), |
448 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
449 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), |
450 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
451 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), |
452 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
453 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), |
454 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
455 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), |
456 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
457 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), |
458 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
459 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), |
460 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
461 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), |
462 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
463 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), |
464 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
465 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), |
466 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
467 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), |
468 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
469 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), |
470 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
471 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), |
472 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
473 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), |
474 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
475 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), |
476 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
477 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), |
478 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
479 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), |
480 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
481 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), |
482 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
483 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), |
484 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
485 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), |
486 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
487 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), |
488 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
489 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), |
490 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
491 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), |
492 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
493 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), |
494 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
495 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), |
496 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
497 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), |
498 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
499 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), |
500 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
501 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), |
502 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
503 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), |
504 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
505 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), |
506 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
507 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), |
508 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
509 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), |
510 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
511 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), |
512 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
513 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), |
514 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
515 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), |
516 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
517 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), |
518 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
519 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), |
520 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
521 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), |
522 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
523 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), |
524 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
525 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), |
526 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
527 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), |
528 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
529 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), |
530 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
531 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), |
532 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
533 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), |
534 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
535 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), |
536 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
537 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), |
538 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
539 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), |
540 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
541 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), |
542 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
543 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), |
544 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
545 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), |
546 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
547 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), |
548 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
549 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), |
550 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
551 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), |
552 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
553 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), |
554 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
555 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), |
556 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
557 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), |
558 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
559 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), |
560 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
561 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), |
562 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
563 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), |
564 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
565 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), |
566 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
567 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), |
568 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
569 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), |
570 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
571 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), |
572 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
573 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), |
574 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
575 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), |
576 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
577 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), |
578 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
579 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), |
580 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
581 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), |
582 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
583 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), |
584 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
585 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), |
586 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
587 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), |
588 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
589 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), |
590 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
591 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), |
592 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
593 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), |
594 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
595 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), |
596 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
597 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), |
598 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
599 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), |
600 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
601 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), |
602 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
603 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), |
604 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
605 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), |
606 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
607 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), |
608 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
609 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), |
610 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
611 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), |
612 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
613 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), |
614 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
615 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), |
616 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
617 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), |
618 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
619 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), |
620 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
621 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), |
622 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
623 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), |
624 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
625 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), |
626 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
627 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), |
628 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
629 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), |
630 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
631 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), |
632 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
633 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), |
634 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
635 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), |
636 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
637 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), |
638 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
639 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), |
640 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
641 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), |
642 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
643 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), |
644 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
645 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), |
646 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
647 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), |
648 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
649 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), |
650 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
651 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), |
652 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
653 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), |
654 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
655 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), |
656 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
657 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), |
658 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
659 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), |
660 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
661 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), |
662 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
663 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), |
664 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
665 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), |
666 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
667 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), |
668 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
669 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), |
670 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
671 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), |
672 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
673 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), |
674 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
675 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), |
676 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
677 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), |
678 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
679 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), |
680 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
681 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), |
682 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
683 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), |
684 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
685 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), |
686 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
687 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), |
688 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
689 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), |
690 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
691 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), |
692 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
693 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), |
694 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
695 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), |
696 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
697 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), |
698 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
699 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), |
700 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
701 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), |
702 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
703 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), |
704 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
705 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), |
706 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
707 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), |
708 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
709 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), |
710 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
711 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), |
712 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
713 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), |
714 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
715 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), |
716 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
717 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), |
718 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
719 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), |
720 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
721 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), |
722 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
723 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), |
724 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
725 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), |
726 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
727 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), |
728 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
729 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), |
730 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
731 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), |
732 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
733 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), |
734 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
735 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), |
736 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
737 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), |
738 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
739 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), |
740 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
741 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), |
742 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
743 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), |
744 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
745 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), |
746 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
747 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), |
748 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
749 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), |
750 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
751 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), |
752 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
753 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), |
754 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
755 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), |
756 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
757 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), |
758 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
759 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), |
760 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
761 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), |
762 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
763 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), |
764 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
765 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), |
766 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
767 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), |
768 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
769 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), |
770 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
771 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), |
772 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
773 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), |
774 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
775 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), |
776 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
777 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), |
778 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
779 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), |
780 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
781 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), |
782 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
783 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), |
784 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
785 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), |
786 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
787 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), |
788 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
789 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), |
790 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
791 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), |
792 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
793 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), |
794 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
795 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), |
796 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
797 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), |
798 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
799 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), |
800 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
801 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), |
802 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
803 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), |
804 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
805 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), |
806 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
807 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), |
808 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
809 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), |
810 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
811 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), |
812 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
813 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), |
814 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
815 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), |
816 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
817 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), |
818 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
819 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), |
820 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
821 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), |
822 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
823 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), |
824 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
825 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), |
826 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
827 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), |
828 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
829 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), |
830 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
831 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), |
832 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
833 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), |
834 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
835 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), |
836 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
837 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), |
838 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
839 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), |
840 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
841 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), |
842 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
843 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), |
844 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
845 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), |
846 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
847 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), |
848 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
849 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), |
850 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
851 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), |
852 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
853 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), |
854 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
855 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), |
856 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
857 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), |
858 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
859 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), |
860 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
861 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), |
862 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
863 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), |
864 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
865 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), |
866 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
867 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), |
868 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
869 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), |
870 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
871 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), |
872 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
873 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), |
874 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
875 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), |
876 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
877 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), |
878 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
879 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), |
880 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
881 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), |
882 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
883 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), |
884 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
885 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), |
886 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
887 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), |
888 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
889 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), |
890 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
891 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), |
892 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
893 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), |
894 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
895 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), |
896 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
897 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), |
898 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
899 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), |
900 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
901 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), |
902 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
903 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), |
904 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
905 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), |
906 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
907 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), |
908 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
909 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), |
910 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
911 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), |
912 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
913 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), |
914 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
915 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), |
916 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
917 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), |
918 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
919 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), |
920 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
921 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), |
922 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
923 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), |
924 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
925 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), |
926 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
927 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), |
928 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
929 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), |
930 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
931 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), |
932 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
933 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), |
934 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
935 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), |
936 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
937 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), |
938 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
939 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), |
940 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
941 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), |
942 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
943 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), |
944 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
945 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), |
946 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
947 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), |
948 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
949 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), |
950 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
951 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), |
952 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
953 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), |
954 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
955 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), |
956 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
957 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), |
958 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
959 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), |
960 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
961 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), |
962 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
963 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), |
964 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
965 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), |
966 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
967 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), |
968 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
969 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), |
970 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
971 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), |
972 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
973 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), |
974 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
975 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), |
976 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
977 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), |
978 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
979 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), |
980 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
981 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), |
982 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
983 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), |
984 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
985 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), |
986 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
987 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), |
988 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
989 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), |
990 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
991 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), |
992 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
993 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), |
994 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
995 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), |
996 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
997 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), |
998 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
999 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), |
1000 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1001 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), |
1002 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1003 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), |
1004 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1005 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), |
1006 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1007 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), |
1008 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1009 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), |
1010 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1011 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), |
1012 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1013 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), |
1014 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1015 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), |
1016 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1017 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), |
1018 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1019 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), |
1020 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1021 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), |
1022 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1023 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), |
1024 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1025 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), |
1026 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1027 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), |
1028 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1029 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), |
1030 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1031 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), |
1032 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1033 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), |
1034 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1035 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), |
1036 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1037 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), |
1038 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1039 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), |
1040 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1041 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), |
1042 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1043 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), |
1044 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1045 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), |
1046 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1047 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), |
1048 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1049 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), |
1050 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1051 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), |
1052 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1053 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), |
1054 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1055 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), |
1056 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1057 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), |
1058 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1059 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), |
1060 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1061 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), |
1062 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1063 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), |
1064 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1065 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), |
1066 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1067 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), |
1068 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1069 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), |
1070 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1071 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), |
1072 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1073 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), |
1074 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1075 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), |
1076 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1077 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), |
1078 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1079 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), |
1080 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1081 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), |
1082 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1083 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), |
1084 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1085 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), |
1086 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1087 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), |
1088 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1089 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), |
1090 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1091 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), |
1092 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1093 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), |
1094 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1095 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), |
1096 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1097 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), |
1098 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1099 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), |
1100 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1101 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), |
1102 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1103 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), |
1104 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1105 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), |
1106 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1107 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), |
1108 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1109 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), |
1110 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1111 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), |
1112 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1113 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), |
1114 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1115 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), |
1116 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1117 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), |
1118 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1119 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), |
1120 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1121 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), |
1122 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1123 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), |
1124 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1125 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), |
1126 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1127 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), |
1128 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1129 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), |
1130 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1131 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), |
1132 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1133 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), |
1134 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1135 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), |
1136 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1137 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), |
1138 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1139 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), |
1140 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1141 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), |
1142 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1143 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), |
1144 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1145 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), |
1146 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1147 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), |
1148 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1149 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), |
1150 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1151 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), |
1152 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1153 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), |
1154 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1155 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), |
1156 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1157 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), |
1158 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1159 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), |
1160 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1161 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), |
1162 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1163 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), |
1164 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1165 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), |
1166 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1167 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), |
1168 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1169 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), |
1170 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1171 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), |
1172 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1173 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), |
1174 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1175 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), |
1176 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1177 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), |
1178 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1179 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), |
1180 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1181 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), |
1182 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1183 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), |
1184 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1185 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), |
1186 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1187 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), |
1188 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1189 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), |
1190 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1191 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), |
1192 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1193 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), |
1194 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1195 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), |
1196 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1197 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), |
1198 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1199 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), |
1200 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1201 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), |
1202 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1203 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), |
1204 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1205 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), |
1206 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1207 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), |
1208 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1209 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), |
1210 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1211 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), |
1212 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1213 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), |
1214 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1215 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), |
1216 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1217 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), |
1218 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1219 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), |
1220 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1221 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), |
1222 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1223 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), |
1224 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1225 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), |
1226 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1227 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), |
1228 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1229 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), |
1230 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1231 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), |
1232 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1233 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), |
1234 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1235 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), |
1236 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1237 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), |
1238 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1239 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), |
1240 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1241 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), |
1242 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1243 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), |
1244 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1245 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), |
1246 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1247 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), |
1248 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1249 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), |
1250 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1251 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), |
1252 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1253 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), |
1254 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1255 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), |
1256 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1257 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), |
1258 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1259 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), |
1260 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1261 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), |
1262 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1263 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), |
1264 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1265 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), |
1266 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1267 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), |
1268 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1269 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), |
1270 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1271 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), |
1272 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1273 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), |
1274 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1275 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), |
1276 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1277 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), |
1278 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1279 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), |
1280 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1281 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), |
1282 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1283 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), |
1284 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1285 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), |
1286 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1287 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), |
1288 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1289 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), |
1290 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1291 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), |
1292 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1293 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), |
1294 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1295 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), |
1296 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1297 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), |
1298 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1299 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), |
1300 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1301 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), |
1302 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1303 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), |
1304 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1305 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), |
1306 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1307 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), |
1308 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1309 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), |
1310 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1311 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), |
1312 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1313 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), |
1314 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1315 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), |
1316 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1317 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), |
1318 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1319 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), |
1320 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1321 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), |
1322 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1323 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), |
1324 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1325 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), |
1326 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1327 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), |
1328 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1329 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), |
1330 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1331 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), |
1332 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1333 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), |
1334 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1335 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), |
1336 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1337 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), |
1338 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1339 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), |
1340 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1341 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), |
1342 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1343 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), |
1344 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1345 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), |
1346 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1347 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), |
1348 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1349 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), |
1350 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1351 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), |
1352 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1353 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), |
1354 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1355 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), |
1356 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1357 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), |
1358 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1359 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), |
1360 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1361 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), |
1362 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1363 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), |
1364 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1365 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19), |
1366 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1367 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20), |
1368 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1369 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5), |
1370 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1371 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa), |
1372 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1373 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14), |
1374 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
1375 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19), |
1376 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1377 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33), |
1378 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) |
1379 | }; |
1380 | |
1381 | static const struct soc15_reg_golden golden_settings_gc_10_1_1[] = { |
1382 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014), |
1383 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), |
1384 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), |
1385 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), |
1386 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100), |
1387 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100), |
1388 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), |
1389 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), |
1390 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), |
1391 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), |
1392 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), |
1393 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), |
1394 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), |
1395 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), |
1396 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000), |
1397 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), |
1398 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), |
1399 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), |
1400 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), |
1401 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), |
1402 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), |
1403 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), |
1404 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), |
1405 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), |
1406 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), |
1407 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), |
1408 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), |
1409 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), |
1410 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), |
1411 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), |
1412 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), |
1413 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105), |
1414 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), |
1415 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), |
1416 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), |
1417 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), |
1418 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), |
1419 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000), |
1420 | }; |
1421 | |
1422 | static const struct soc15_reg_golden golden_settings_gc_10_1_2[] = { |
1423 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014), |
1424 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), |
1425 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), |
1426 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100), |
1427 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100), |
1428 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100), |
1429 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), |
1430 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), |
1431 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), |
1432 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000), |
1433 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), |
1434 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), |
1435 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), |
1436 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), |
1437 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000), |
1438 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), |
1439 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), |
1440 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044), |
1441 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), |
1442 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe), |
1443 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), |
1444 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), |
1445 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), |
1446 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), |
1447 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), |
1448 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), |
1449 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), |
1450 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), |
1451 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02), |
1452 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), |
1453 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), |
1454 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000), |
1455 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820), |
1456 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), |
1457 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), |
1458 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104), |
1459 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), |
1460 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), |
1461 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), |
1462 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), |
1463 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010), |
1464 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00c00000) |
1465 | }; |
1466 | |
1467 | static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] = { |
1468 | /* Pending on emulation bring up */ |
1469 | }; |
1470 | |
1471 | static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] = { |
1472 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0), |
1473 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1474 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), |
1475 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1476 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), |
1477 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1478 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), |
1479 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1480 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), |
1481 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1482 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), |
1483 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1484 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), |
1485 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1486 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), |
1487 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1488 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), |
1489 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1490 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), |
1491 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1492 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), |
1493 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1494 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), |
1495 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1496 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), |
1497 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1498 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), |
1499 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1500 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), |
1501 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1502 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), |
1503 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1504 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), |
1505 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1506 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), |
1507 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1508 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), |
1509 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1510 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), |
1511 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1512 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), |
1513 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1514 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), |
1515 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1516 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), |
1517 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1518 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), |
1519 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1520 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), |
1521 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1522 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), |
1523 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1524 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), |
1525 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1526 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), |
1527 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1528 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), |
1529 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1530 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), |
1531 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1532 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), |
1533 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1534 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), |
1535 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1536 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), |
1537 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1538 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), |
1539 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1540 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), |
1541 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1542 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), |
1543 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1544 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), |
1545 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1546 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), |
1547 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1548 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), |
1549 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1550 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), |
1551 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1552 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), |
1553 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1554 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), |
1555 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1556 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), |
1557 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1558 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), |
1559 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1560 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), |
1561 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1562 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), |
1563 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1564 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), |
1565 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1566 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), |
1567 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1568 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), |
1569 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1570 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), |
1571 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1572 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), |
1573 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1574 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), |
1575 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1576 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), |
1577 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1578 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), |
1579 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1580 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), |
1581 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1582 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), |
1583 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1584 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), |
1585 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1586 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), |
1587 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1588 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), |
1589 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1590 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), |
1591 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1592 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), |
1593 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1594 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), |
1595 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1596 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), |
1597 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1598 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), |
1599 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1600 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), |
1601 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1602 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), |
1603 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1604 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), |
1605 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1606 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), |
1607 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1608 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), |
1609 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1610 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), |
1611 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1612 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), |
1613 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1614 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), |
1615 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1616 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), |
1617 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1618 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), |
1619 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1620 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), |
1621 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1622 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), |
1623 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1624 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), |
1625 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1626 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), |
1627 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1628 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), |
1629 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1630 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), |
1631 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1632 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), |
1633 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1634 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), |
1635 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1636 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), |
1637 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1638 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), |
1639 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1640 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), |
1641 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1642 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), |
1643 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1644 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), |
1645 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1646 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), |
1647 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1648 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), |
1649 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1650 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), |
1651 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1652 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), |
1653 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1654 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), |
1655 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1656 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), |
1657 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1658 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), |
1659 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1660 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), |
1661 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1662 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), |
1663 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1664 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), |
1665 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1666 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), |
1667 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1668 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), |
1669 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1670 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), |
1671 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1672 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), |
1673 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1674 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), |
1675 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1676 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), |
1677 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1678 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), |
1679 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1680 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), |
1681 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1682 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), |
1683 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1684 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), |
1685 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1686 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), |
1687 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1688 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), |
1689 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1690 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), |
1691 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1692 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), |
1693 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1694 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), |
1695 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1696 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), |
1697 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1698 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), |
1699 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1700 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), |
1701 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1702 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), |
1703 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1704 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), |
1705 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1706 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), |
1707 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1708 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), |
1709 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1710 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), |
1711 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1712 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), |
1713 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1714 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), |
1715 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1716 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), |
1717 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1718 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), |
1719 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1720 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), |
1721 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1722 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), |
1723 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1724 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), |
1725 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1726 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), |
1727 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1728 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), |
1729 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1730 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), |
1731 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1732 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), |
1733 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1734 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), |
1735 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1736 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), |
1737 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1738 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), |
1739 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1740 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), |
1741 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1742 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), |
1743 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1744 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), |
1745 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1746 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), |
1747 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1748 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), |
1749 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1750 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), |
1751 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1752 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), |
1753 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1754 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), |
1755 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1756 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), |
1757 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1758 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), |
1759 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1760 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), |
1761 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1762 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), |
1763 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1764 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), |
1765 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1766 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), |
1767 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1768 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), |
1769 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1770 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), |
1771 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1772 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), |
1773 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1774 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), |
1775 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1776 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), |
1777 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1778 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), |
1779 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1780 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), |
1781 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1782 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), |
1783 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1784 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), |
1785 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1786 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), |
1787 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1788 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), |
1789 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1790 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), |
1791 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1792 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), |
1793 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1794 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), |
1795 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1796 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), |
1797 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1798 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), |
1799 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1800 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), |
1801 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1802 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), |
1803 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1804 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), |
1805 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1806 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), |
1807 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1808 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), |
1809 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1810 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), |
1811 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1812 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), |
1813 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1814 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), |
1815 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1816 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), |
1817 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1818 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), |
1819 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1820 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), |
1821 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1822 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), |
1823 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1824 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), |
1825 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1826 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), |
1827 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1828 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), |
1829 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1830 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), |
1831 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1832 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), |
1833 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1834 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4), |
1835 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1836 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), |
1837 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1838 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), |
1839 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1840 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), |
1841 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1842 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), |
1843 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1844 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), |
1845 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1846 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), |
1847 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1848 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), |
1849 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1850 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), |
1851 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1852 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), |
1853 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1854 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), |
1855 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1856 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), |
1857 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1858 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), |
1859 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1860 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), |
1861 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1862 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), |
1863 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1864 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), |
1865 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1866 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), |
1867 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1868 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), |
1869 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1870 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), |
1871 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1872 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), |
1873 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1874 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), |
1875 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1876 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), |
1877 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1878 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), |
1879 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1880 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), |
1881 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1882 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), |
1883 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1884 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), |
1885 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1886 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), |
1887 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1888 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), |
1889 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1890 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), |
1891 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1892 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), |
1893 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1894 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), |
1895 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1896 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), |
1897 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1898 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), |
1899 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1900 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), |
1901 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1902 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), |
1903 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1904 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), |
1905 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1906 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), |
1907 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1908 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), |
1909 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1910 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), |
1911 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1912 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), |
1913 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1914 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), |
1915 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1916 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), |
1917 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1918 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), |
1919 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1920 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), |
1921 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1922 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), |
1923 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1924 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), |
1925 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1926 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), |
1927 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1928 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), |
1929 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1930 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), |
1931 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1932 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), |
1933 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1934 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), |
1935 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1936 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), |
1937 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1938 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), |
1939 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1940 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), |
1941 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1942 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), |
1943 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1944 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), |
1945 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1946 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), |
1947 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1948 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), |
1949 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1950 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), |
1951 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1952 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), |
1953 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1954 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), |
1955 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1956 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), |
1957 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1958 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), |
1959 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1960 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), |
1961 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1962 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), |
1963 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1964 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), |
1965 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1966 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), |
1967 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1968 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), |
1969 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1970 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), |
1971 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1972 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), |
1973 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1974 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), |
1975 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1976 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), |
1977 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1978 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), |
1979 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1980 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), |
1981 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1982 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), |
1983 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1984 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), |
1985 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1986 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), |
1987 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1988 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), |
1989 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1990 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), |
1991 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1992 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), |
1993 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1994 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), |
1995 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1996 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), |
1997 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
1998 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), |
1999 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2000 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), |
2001 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2002 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), |
2003 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2004 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), |
2005 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2006 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), |
2007 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2008 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), |
2009 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2010 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0), |
2011 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2012 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), |
2013 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2014 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4), |
2015 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2016 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), |
2017 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2018 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0), |
2019 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2020 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), |
2021 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2022 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4), |
2023 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2024 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), |
2025 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2026 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8), |
2027 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2028 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), |
2029 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2030 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac), |
2031 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2032 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), |
2033 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2034 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8), |
2035 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2036 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), |
2037 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2038 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc), |
2039 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2040 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), |
2041 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2042 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8), |
2043 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2044 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), |
2045 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2046 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc), |
2047 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2048 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), |
2049 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2050 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0), |
2051 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2052 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), |
2053 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2054 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4), |
2055 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2056 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), |
2057 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2058 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), |
2059 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2060 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), |
2061 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2062 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), |
2063 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2064 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), |
2065 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2066 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), |
2067 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2068 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), |
2069 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2070 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), |
2071 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2072 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), |
2073 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2074 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), |
2075 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2076 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), |
2077 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2078 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26), |
2079 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2080 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28), |
2081 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2082 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf), |
2083 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2084 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15), |
2085 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2086 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f), |
2087 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2088 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25), |
2089 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2090 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b), |
2091 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) |
2092 | }; |
2093 | |
2094 | static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] = { |
2095 | /* Pending on emulation bring up */ |
2096 | }; |
2097 | |
2098 | static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] = { |
2099 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0), |
2100 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2101 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), |
2102 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2103 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), |
2104 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2105 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), |
2106 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2107 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), |
2108 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2109 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), |
2110 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2111 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), |
2112 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2113 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), |
2114 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2115 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), |
2116 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2117 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), |
2118 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2119 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), |
2120 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2121 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), |
2122 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2123 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), |
2124 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2125 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), |
2126 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2127 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), |
2128 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2129 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), |
2130 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2131 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), |
2132 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2133 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), |
2134 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2135 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), |
2136 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2137 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), |
2138 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2139 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), |
2140 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2141 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), |
2142 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2143 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), |
2144 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2145 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), |
2146 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2147 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), |
2148 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2149 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), |
2150 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2151 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), |
2152 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2153 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), |
2154 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2155 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), |
2156 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2157 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), |
2158 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2159 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), |
2160 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2161 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), |
2162 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2163 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), |
2164 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2165 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), |
2166 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2167 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), |
2168 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2169 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), |
2170 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2171 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), |
2172 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2173 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), |
2174 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2175 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), |
2176 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2177 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), |
2178 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2179 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), |
2180 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2181 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), |
2182 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2183 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), |
2184 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2185 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), |
2186 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2187 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), |
2188 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2189 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), |
2190 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2191 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), |
2192 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2193 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), |
2194 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2195 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), |
2196 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2197 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), |
2198 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2199 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), |
2200 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2201 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), |
2202 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2203 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), |
2204 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2205 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), |
2206 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2207 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), |
2208 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2209 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), |
2210 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2211 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), |
2212 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2213 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), |
2214 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2215 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), |
2216 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2217 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), |
2218 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2219 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), |
2220 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2221 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), |
2222 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2223 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), |
2224 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2225 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), |
2226 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2227 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), |
2228 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2229 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), |
2230 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2231 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), |
2232 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2233 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), |
2234 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2235 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), |
2236 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2237 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), |
2238 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2239 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), |
2240 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2241 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), |
2242 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2243 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), |
2244 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2245 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), |
2246 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2247 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), |
2248 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2249 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), |
2250 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2251 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), |
2252 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2253 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), |
2254 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2255 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), |
2256 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2257 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), |
2258 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2259 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), |
2260 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2261 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), |
2262 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2263 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), |
2264 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2265 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), |
2266 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2267 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), |
2268 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2269 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), |
2270 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2271 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), |
2272 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2273 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), |
2274 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2275 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), |
2276 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2277 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), |
2278 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2279 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), |
2280 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2281 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), |
2282 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2283 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), |
2284 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2285 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), |
2286 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2287 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), |
2288 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2289 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), |
2290 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2291 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), |
2292 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2293 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), |
2294 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2295 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), |
2296 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2297 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), |
2298 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2299 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), |
2300 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2301 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), |
2302 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2303 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), |
2304 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2305 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), |
2306 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2307 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), |
2308 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2309 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), |
2310 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2311 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), |
2312 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2313 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), |
2314 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2315 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), |
2316 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2317 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), |
2318 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2319 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), |
2320 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2321 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), |
2322 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2323 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), |
2324 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2325 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), |
2326 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2327 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), |
2328 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2329 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), |
2330 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2331 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), |
2332 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2333 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), |
2334 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2335 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), |
2336 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2337 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), |
2338 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2339 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), |
2340 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2341 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), |
2342 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2343 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), |
2344 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2345 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), |
2346 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2347 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), |
2348 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2349 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), |
2350 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2351 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), |
2352 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2353 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), |
2354 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2355 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), |
2356 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2357 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), |
2358 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2359 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), |
2360 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2361 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), |
2362 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2363 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), |
2364 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2365 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), |
2366 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2367 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), |
2368 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2369 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), |
2370 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2371 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), |
2372 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2373 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), |
2374 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2375 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), |
2376 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2377 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), |
2378 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2379 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), |
2380 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2381 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), |
2382 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2383 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), |
2384 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2385 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), |
2386 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2387 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), |
2388 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2389 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), |
2390 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2391 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), |
2392 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2393 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), |
2394 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2395 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), |
2396 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2397 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), |
2398 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2399 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), |
2400 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2401 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), |
2402 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2403 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), |
2404 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2405 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), |
2406 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2407 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), |
2408 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2409 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), |
2410 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2411 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), |
2412 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2413 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), |
2414 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2415 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), |
2416 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2417 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), |
2418 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2419 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), |
2420 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2421 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), |
2422 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2423 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), |
2424 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2425 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), |
2426 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2427 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), |
2428 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2429 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), |
2430 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2431 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), |
2432 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2433 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), |
2434 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2435 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), |
2436 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2437 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), |
2438 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2439 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), |
2440 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2441 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), |
2442 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2443 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), |
2444 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2445 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), |
2446 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2447 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), |
2448 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2449 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), |
2450 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2451 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), |
2452 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2453 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), |
2454 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2455 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), |
2456 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2457 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), |
2458 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2459 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), |
2460 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2461 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), |
2462 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2463 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), |
2464 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2465 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), |
2466 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2467 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), |
2468 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2469 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), |
2470 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2471 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), |
2472 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2473 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), |
2474 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2475 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), |
2476 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2477 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), |
2478 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2479 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), |
2480 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2481 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), |
2482 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2483 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), |
2484 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2485 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), |
2486 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2487 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), |
2488 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2489 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), |
2490 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2491 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), |
2492 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2493 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), |
2494 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2495 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), |
2496 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2497 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), |
2498 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2499 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), |
2500 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2501 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), |
2502 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2503 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), |
2504 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2505 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), |
2506 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2507 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), |
2508 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2509 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), |
2510 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2511 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), |
2512 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2513 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), |
2514 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2515 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), |
2516 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2517 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), |
2518 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2519 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), |
2520 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2521 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), |
2522 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2523 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), |
2524 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2525 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), |
2526 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2527 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), |
2528 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2529 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), |
2530 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2531 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), |
2532 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2533 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), |
2534 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2535 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), |
2536 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2537 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), |
2538 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2539 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), |
2540 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2541 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), |
2542 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2543 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), |
2544 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2545 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), |
2546 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2547 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), |
2548 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2549 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), |
2550 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2551 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), |
2552 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2553 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), |
2554 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2555 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), |
2556 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2557 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), |
2558 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2559 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), |
2560 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2561 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), |
2562 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2563 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), |
2564 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2565 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), |
2566 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2567 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), |
2568 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2569 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), |
2570 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2571 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), |
2572 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2573 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), |
2574 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2575 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), |
2576 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2577 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), |
2578 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2579 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), |
2580 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2581 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), |
2582 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2583 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), |
2584 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2585 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), |
2586 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2587 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), |
2588 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2589 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), |
2590 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2591 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), |
2592 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2593 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), |
2594 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2595 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), |
2596 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2597 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), |
2598 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2599 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), |
2600 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2601 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), |
2602 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2603 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), |
2604 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2605 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), |
2606 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2607 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), |
2608 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2609 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), |
2610 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2611 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), |
2612 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2613 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), |
2614 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2615 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), |
2616 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2617 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), |
2618 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2619 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), |
2620 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2621 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), |
2622 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2623 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), |
2624 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2625 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), |
2626 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2627 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), |
2628 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2629 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), |
2630 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2631 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), |
2632 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2633 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), |
2634 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2635 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), |
2636 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2637 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), |
2638 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2639 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), |
2640 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2641 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), |
2642 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2643 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), |
2644 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2645 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), |
2646 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2647 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), |
2648 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2649 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), |
2650 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2651 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), |
2652 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2653 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), |
2654 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2655 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), |
2656 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2657 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), |
2658 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2659 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), |
2660 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2661 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), |
2662 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2663 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), |
2664 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2665 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), |
2666 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2667 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), |
2668 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2669 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), |
2670 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2671 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), |
2672 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2673 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), |
2674 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2675 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), |
2676 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2677 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), |
2678 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2679 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), |
2680 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2681 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), |
2682 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2683 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), |
2684 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2685 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), |
2686 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2687 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), |
2688 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2689 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), |
2690 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2691 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), |
2692 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2693 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), |
2694 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2695 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), |
2696 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2697 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), |
2698 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2699 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), |
2700 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2701 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), |
2702 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2703 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), |
2704 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2705 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), |
2706 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2707 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), |
2708 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2709 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), |
2710 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2711 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), |
2712 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2713 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), |
2714 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2715 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), |
2716 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2717 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), |
2718 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2719 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), |
2720 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2721 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), |
2722 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2723 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), |
2724 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2725 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), |
2726 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2727 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), |
2728 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2729 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), |
2730 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2731 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), |
2732 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2733 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), |
2734 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2735 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), |
2736 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2737 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), |
2738 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2739 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), |
2740 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2741 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), |
2742 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2743 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), |
2744 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2745 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), |
2746 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2747 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), |
2748 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2749 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), |
2750 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2751 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), |
2752 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2753 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), |
2754 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2755 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), |
2756 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2757 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), |
2758 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2759 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), |
2760 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2761 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), |
2762 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2763 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), |
2764 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2765 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), |
2766 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2767 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), |
2768 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2769 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), |
2770 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2771 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), |
2772 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2773 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), |
2774 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2775 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), |
2776 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2777 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), |
2778 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2779 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), |
2780 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2781 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), |
2782 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2783 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), |
2784 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2785 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), |
2786 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2787 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), |
2788 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2789 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), |
2790 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2791 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), |
2792 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2793 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), |
2794 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2795 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), |
2796 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2797 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), |
2798 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2799 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), |
2800 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2801 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), |
2802 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2803 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), |
2804 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2805 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), |
2806 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2807 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), |
2808 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2809 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), |
2810 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2811 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), |
2812 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2813 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), |
2814 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2815 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), |
2816 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2817 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), |
2818 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2819 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), |
2820 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2821 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), |
2822 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2823 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), |
2824 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2825 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), |
2826 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2827 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), |
2828 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2829 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), |
2830 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2831 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), |
2832 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2833 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), |
2834 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2835 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), |
2836 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2837 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), |
2838 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2839 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), |
2840 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2841 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), |
2842 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2843 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), |
2844 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2845 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), |
2846 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2847 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), |
2848 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2849 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), |
2850 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2851 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), |
2852 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2853 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), |
2854 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2855 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), |
2856 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2857 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), |
2858 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2859 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), |
2860 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2861 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), |
2862 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2863 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), |
2864 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2865 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), |
2866 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2867 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), |
2868 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2869 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), |
2870 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2871 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), |
2872 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2873 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), |
2874 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2875 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), |
2876 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2877 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), |
2878 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2879 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), |
2880 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2881 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), |
2882 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2883 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), |
2884 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2885 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), |
2886 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2887 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), |
2888 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2889 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), |
2890 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2891 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), |
2892 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2893 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), |
2894 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2895 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), |
2896 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2897 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), |
2898 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2899 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), |
2900 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2901 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), |
2902 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2903 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), |
2904 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2905 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), |
2906 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2907 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), |
2908 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2909 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), |
2910 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2911 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), |
2912 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2913 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), |
2914 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2915 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), |
2916 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2917 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), |
2918 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2919 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), |
2920 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2921 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), |
2922 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2923 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), |
2924 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2925 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), |
2926 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2927 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), |
2928 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2929 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), |
2930 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2931 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), |
2932 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2933 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), |
2934 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2935 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), |
2936 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2937 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), |
2938 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2939 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), |
2940 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2941 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), |
2942 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2943 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), |
2944 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2945 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), |
2946 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2947 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), |
2948 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2949 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), |
2950 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2951 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), |
2952 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2953 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), |
2954 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2955 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), |
2956 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2957 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), |
2958 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2959 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), |
2960 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2961 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), |
2962 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2963 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), |
2964 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2965 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), |
2966 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2967 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), |
2968 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2969 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), |
2970 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2971 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), |
2972 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2973 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), |
2974 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2975 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), |
2976 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2977 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), |
2978 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2979 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), |
2980 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2981 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), |
2982 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2983 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), |
2984 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2985 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), |
2986 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2987 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), |
2988 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2989 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), |
2990 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2991 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), |
2992 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2993 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), |
2994 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
2995 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), |
2996 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2997 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), |
2998 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
2999 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), |
3000 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
3001 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), |
3002 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
3003 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), |
3004 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
3005 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), |
3006 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
3007 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), |
3008 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
3009 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), |
3010 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
3011 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), |
3012 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
3013 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), |
3014 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
3015 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), |
3016 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
3017 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), |
3018 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
3019 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), |
3020 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
3021 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), |
3022 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
3023 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), |
3024 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
3025 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), |
3026 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
3027 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), |
3028 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
3029 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), |
3030 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
3031 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), |
3032 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
3033 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), |
3034 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
3035 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), |
3036 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
3037 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), |
3038 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
3039 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), |
3040 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
3041 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), |
3042 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
3043 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), |
3044 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
3045 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), |
3046 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
3047 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), |
3048 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
3049 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), |
3050 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
3051 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), |
3052 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
3053 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), |
3054 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
3055 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), |
3056 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
3057 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), |
3058 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
3059 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), |
3060 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
3061 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), |
3062 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
3063 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), |
3064 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
3065 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), |
3066 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
3067 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), |
3068 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
3069 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), |
3070 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
3071 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), |
3072 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
3073 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), |
3074 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
3075 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), |
3076 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
3077 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), |
3078 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
3079 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), |
3080 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
3081 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), |
3082 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
3083 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), |
3084 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
3085 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), |
3086 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
3087 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), |
3088 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
3089 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), |
3090 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
3091 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), |
3092 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
3093 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), |
3094 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
3095 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), |
3096 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
3097 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), |
3098 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
3099 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), |
3100 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
3101 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), |
3102 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
3103 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), |
3104 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
3105 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), |
3106 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
3107 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), |
3108 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
3109 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), |
3110 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
3111 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), |
3112 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
3113 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), |
3114 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
3115 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), |
3116 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
3117 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), |
3118 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
3119 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), |
3120 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
3121 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), |
3122 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
3123 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), |
3124 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
3125 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), |
3126 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
3127 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), |
3128 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
3129 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), |
3130 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
3131 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), |
3132 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
3133 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), |
3134 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
3135 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), |
3136 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
3137 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f), |
3138 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
3139 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22), |
3140 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
3141 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1), |
3142 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
3143 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6), |
3144 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
3145 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10), |
3146 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), |
3147 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15), |
3148 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), |
3149 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35), |
3150 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) |
3151 | }; |
3152 | |
3153 | static const struct soc15_reg_golden golden_settings_gc_10_3[] = { |
3154 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), |
3155 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100), |
3156 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), |
3157 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), |
3158 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), |
3159 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), |
3160 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), |
3161 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), |
3162 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100), |
3163 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088), |
3164 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), |
3165 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080), |
3166 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080), |
3167 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400), |
3168 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), |
3169 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), |
3170 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), |
3171 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988), |
3172 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), |
3173 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), |
3174 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), |
3175 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), |
3176 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104), |
3177 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), |
3178 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), |
3179 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), |
3180 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), |
3181 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), |
3182 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), |
3183 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), |
3184 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), |
3185 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), |
3186 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), |
3187 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), |
3188 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), |
3189 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), |
3190 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), |
3191 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), |
3192 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), |
3193 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), |
3194 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020), |
3195 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), |
3196 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000) |
3197 | }; |
3198 | |
3199 | static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] = { |
3200 | /* Pending on emulation bring up */ |
3201 | }; |
3202 | |
3203 | static const struct soc15_reg_golden golden_settings_gc_10_3_2[] = { |
3204 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), |
3205 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100), |
3206 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), |
3207 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), |
3208 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), |
3209 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), |
3210 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), |
3211 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), |
3212 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), |
3213 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080), |
3214 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080), |
3215 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400), |
3216 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), |
3217 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), |
3218 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), |
3219 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), |
3220 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), |
3221 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), |
3222 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), |
3223 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104), |
3224 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004), |
3225 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), |
3226 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), |
3227 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), |
3228 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), |
3229 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), |
3230 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), |
3231 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), |
3232 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), |
3233 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), |
3234 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), |
3235 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), |
3236 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), |
3237 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), |
3238 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), |
3239 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), |
3240 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), |
3241 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), |
3242 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), |
3243 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000), |
3244 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff), |
3245 | |
3246 | /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */ |
3247 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), |
3248 | }; |
3249 | |
3250 | static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] = { |
3251 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), |
3252 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), |
3253 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), |
3254 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), |
3255 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), |
3256 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), |
3257 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142), |
3258 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), |
3259 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), |
3260 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), |
3261 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), |
3262 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), |
3263 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), |
3264 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), |
3265 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), |
3266 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), |
3267 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), |
3268 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020), |
3269 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103), |
3270 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), |
3271 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020), |
3272 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), |
3273 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000), |
3274 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff), |
3275 | |
3276 | /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */ |
3277 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), |
3278 | }; |
3279 | |
3280 | static const struct soc15_reg_golden golden_settings_gc_10_3_3[] = { |
3281 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), |
3282 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), |
3283 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), |
3284 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), |
3285 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), |
3286 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000242), |
3287 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), |
3288 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), |
3289 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), |
3290 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), |
3291 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), |
3292 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), |
3293 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), |
3294 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), |
3295 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), |
3296 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), |
3297 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), |
3298 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), |
3299 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), |
3300 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000) |
3301 | }; |
3302 | |
3303 | static const struct soc15_reg_golden golden_settings_gc_10_3_4[] = { |
3304 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), |
3305 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100), |
3306 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100), |
3307 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), |
3308 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280), |
3309 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000), |
3310 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x00001d00, 0x00000500), |
3311 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400), |
3312 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), |
3313 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), |
3314 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008), |
3315 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988), |
3316 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007), |
3317 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), |
3318 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), |
3319 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070), |
3320 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), |
3321 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), |
3322 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), |
3323 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), |
3324 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), |
3325 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), |
3326 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), |
3327 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), |
3328 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), |
3329 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), |
3330 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), |
3331 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), |
3332 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), |
3333 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), |
3334 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), |
3335 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), |
3336 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020), |
3337 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000), |
3338 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000), |
3339 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020) |
3340 | }; |
3341 | |
3342 | static const struct soc15_reg_golden golden_settings_gc_10_3_5[] = { |
3343 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), |
3344 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xb0000ff0, 0x30000100), |
3345 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff000000, 0x7e000100), |
3346 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), |
3347 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), |
3348 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), |
3349 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), |
3350 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), |
3351 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), |
3352 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), |
3353 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), |
3354 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), |
3355 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), |
3356 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), |
3357 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), |
3358 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), |
3359 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), |
3360 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), |
3361 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), |
3362 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), |
3363 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), |
3364 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), |
3365 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), |
3366 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), |
3367 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), |
3368 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), |
3369 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), |
3370 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), |
3371 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), |
3372 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), |
3373 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), |
3374 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000) |
3375 | }; |
3376 | |
3377 | static const struct soc15_reg_golden golden_settings_gc_10_0_cyan_skillfish[] = { |
3378 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000), |
3379 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_FAST_CLKS, 0x3fffffff, 0x0000493e), |
3380 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100), |
3381 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x3c000100), |
3382 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0xa0000000, 0xa0000000), |
3383 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x00008000, 0x003c8014), |
3384 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_DRAM_BURST_CTRL, 0x00000010, 0x00000017), |
3385 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xd8d8d8d8), |
3386 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000003), |
3387 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), |
3388 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), |
3389 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), |
3390 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000), |
3391 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860210), |
3392 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044), |
3393 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00009d00, 0x00008500), |
3394 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END, 0xffffffff, 0x000fffff), |
3395 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_DRAM_BURST_CTRL, 0x00000010, 0x00000017), |
3396 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xfcfcfcfc, 0xd8d8d8d8), |
3397 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77707770, 0x21302130), |
3398 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77707770, 0x21302130), |
3399 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), |
3400 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), |
3401 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100), |
3402 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xfc02002f, 0x9402002f), |
3403 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00002188, 0x00000188), |
3404 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x08000009, 0x08000009), |
3405 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xcc3fcc03, 0x842a4c02), |
3406 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000000f, 0x00000000), |
3407 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffff3109, 0xffff3101), |
3408 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130), |
3409 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), |
3410 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x00030008, 0x01030000), |
3411 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000) |
3412 | }; |
3413 | |
3414 | static const struct soc15_reg_golden golden_settings_gc_10_3_6[] = { |
3415 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), |
3416 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x00000044), |
3417 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), |
3418 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), |
3419 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), |
3420 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000042), |
3421 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), |
3422 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x00000044), |
3423 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), |
3424 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), |
3425 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), |
3426 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), |
3427 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), |
3428 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), |
3429 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), |
3430 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), |
3431 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), |
3432 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), |
3433 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), |
3434 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020), |
3435 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), |
3436 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000) |
3437 | }; |
3438 | |
3439 | static const struct soc15_reg_golden golden_settings_gc_10_3_7[] = { |
3440 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), |
3441 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), |
3442 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), |
3443 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), |
3444 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), |
3445 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000041), |
3446 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), |
3447 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), |
3448 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), |
3449 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), |
3450 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff), |
3451 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff), |
3452 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), |
3453 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), |
3454 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), |
3455 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf000003f, 0x01200007), |
3456 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), |
3457 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), |
3458 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), |
3459 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020), |
3460 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), |
3461 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000) |
3462 | }; |
3463 | |
3464 | #define DEFAULT_SH_MEM_CONFIG \ |
3465 | ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ |
3466 | (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ |
3467 | (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \ |
3468 | (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) |
3469 | |
3470 | /* TODO: pending on golden setting value of gb address config */ |
3471 | #define CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN 0x00100044 |
3472 | |
3473 | static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev); |
3474 | static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev); |
3475 | static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev); |
3476 | static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev); |
3477 | static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev); |
3478 | static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, |
3479 | struct amdgpu_cu_info *cu_info); |
3480 | static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev); |
3481 | static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, |
3482 | u32 sh_num, u32 instance, int xcc_id); |
3483 | static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); |
3484 | |
3485 | static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev); |
3486 | static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev); |
3487 | static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev); |
3488 | static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); |
3489 | static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume); |
3490 | static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); |
3491 | static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); |
3492 | static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev); |
3493 | static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev); |
3494 | static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev); |
3495 | static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, |
3496 | uint16_t pasid, uint32_t flush_type, |
3497 | bool all_hub, uint8_t dst_sel); |
3498 | static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev, |
3499 | unsigned int vmid); |
3500 | |
3501 | static int gfx_v10_0_set_powergating_state(void *handle, |
3502 | enum amd_powergating_state state); |
3503 | static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) |
3504 | { |
3505 | amdgpu_ring_write(ring: kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); |
3506 | amdgpu_ring_write(ring: kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | |
3507 | PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ |
3508 | amdgpu_ring_write(ring: kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ |
3509 | amdgpu_ring_write(ring: kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ |
3510 | amdgpu_ring_write(ring: kiq_ring, v: 0); /* gws mask lo */ |
3511 | amdgpu_ring_write(ring: kiq_ring, v: 0); /* gws mask hi */ |
3512 | amdgpu_ring_write(ring: kiq_ring, v: 0); /* oac mask */ |
3513 | amdgpu_ring_write(ring: kiq_ring, v: 0); /* gds heap base:0, gds heap size:0 */ |
3514 | } |
3515 | |
3516 | static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring, |
3517 | struct amdgpu_ring *ring) |
3518 | { |
3519 | uint64_t mqd_addr = amdgpu_bo_gpu_offset(bo: ring->mqd_obj); |
3520 | uint64_t wptr_addr = ring->wptr_gpu_addr; |
3521 | uint32_t eng_sel = 0; |
3522 | |
3523 | switch (ring->funcs->type) { |
3524 | case AMDGPU_RING_TYPE_COMPUTE: |
3525 | eng_sel = 0; |
3526 | break; |
3527 | case AMDGPU_RING_TYPE_GFX: |
3528 | eng_sel = 4; |
3529 | break; |
3530 | case AMDGPU_RING_TYPE_MES: |
3531 | eng_sel = 5; |
3532 | break; |
3533 | default: |
3534 | WARN_ON(1); |
3535 | } |
3536 | |
3537 | amdgpu_ring_write(ring: kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); |
3538 | /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ |
3539 | amdgpu_ring_write(ring: kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ |
3540 | PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ |
3541 | PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ |
3542 | PACKET3_MAP_QUEUES_QUEUE(ring->queue) | |
3543 | PACKET3_MAP_QUEUES_PIPE(ring->pipe) | |
3544 | PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | |
3545 | PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ |
3546 | PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ |
3547 | PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | |
3548 | PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ |
3549 | amdgpu_ring_write(ring: kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); |
3550 | amdgpu_ring_write(ring: kiq_ring, lower_32_bits(mqd_addr)); |
3551 | amdgpu_ring_write(ring: kiq_ring, upper_32_bits(mqd_addr)); |
3552 | amdgpu_ring_write(ring: kiq_ring, lower_32_bits(wptr_addr)); |
3553 | amdgpu_ring_write(ring: kiq_ring, upper_32_bits(wptr_addr)); |
3554 | } |
3555 | |
3556 | static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, |
3557 | struct amdgpu_ring *ring, |
3558 | enum amdgpu_unmap_queues_action action, |
3559 | u64 gpu_addr, u64 seq) |
3560 | { |
3561 | struct amdgpu_device *adev = kiq_ring->adev; |
3562 | uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; |
3563 | |
3564 | if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { |
3565 | amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq); |
3566 | return; |
3567 | } |
3568 | |
3569 | amdgpu_ring_write(ring: kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); |
3570 | amdgpu_ring_write(ring: kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ |
3571 | PACKET3_UNMAP_QUEUES_ACTION(action) | |
3572 | PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | |
3573 | PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | |
3574 | PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); |
3575 | amdgpu_ring_write(ring: kiq_ring, |
3576 | PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); |
3577 | |
3578 | if (action == PREEMPT_QUEUES_NO_UNMAP) { |
3579 | amdgpu_ring_write(ring: kiq_ring, lower_32_bits(gpu_addr)); |
3580 | amdgpu_ring_write(ring: kiq_ring, upper_32_bits(gpu_addr)); |
3581 | amdgpu_ring_write(ring: kiq_ring, v: seq); |
3582 | } else { |
3583 | amdgpu_ring_write(ring: kiq_ring, v: 0); |
3584 | amdgpu_ring_write(ring: kiq_ring, v: 0); |
3585 | amdgpu_ring_write(ring: kiq_ring, v: 0); |
3586 | } |
3587 | } |
3588 | |
3589 | static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring, |
3590 | struct amdgpu_ring *ring, |
3591 | u64 addr, |
3592 | u64 seq) |
3593 | { |
3594 | uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; |
3595 | |
3596 | amdgpu_ring_write(ring: kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); |
3597 | amdgpu_ring_write(ring: kiq_ring, |
3598 | PACKET3_QUERY_STATUS_CONTEXT_ID(0) | |
3599 | PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | |
3600 | PACKET3_QUERY_STATUS_COMMAND(2)); |
3601 | amdgpu_ring_write(ring: kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ |
3602 | PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | |
3603 | PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); |
3604 | amdgpu_ring_write(ring: kiq_ring, lower_32_bits(addr)); |
3605 | amdgpu_ring_write(ring: kiq_ring, upper_32_bits(addr)); |
3606 | amdgpu_ring_write(ring: kiq_ring, lower_32_bits(seq)); |
3607 | amdgpu_ring_write(ring: kiq_ring, upper_32_bits(seq)); |
3608 | } |
3609 | |
3610 | static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, |
3611 | uint16_t pasid, uint32_t flush_type, |
3612 | bool all_hub) |
3613 | { |
3614 | gfx_v10_0_ring_invalidate_tlbs(ring: kiq_ring, pasid, flush_type, all_hub, dst_sel: 1); |
3615 | } |
3616 | |
3617 | static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = { |
3618 | .kiq_set_resources = gfx10_kiq_set_resources, |
3619 | .kiq_map_queues = gfx10_kiq_map_queues, |
3620 | .kiq_unmap_queues = gfx10_kiq_unmap_queues, |
3621 | .kiq_query_status = gfx10_kiq_query_status, |
3622 | .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs, |
3623 | .set_resources_size = 8, |
3624 | .map_queues_size = 7, |
3625 | .unmap_queues_size = 6, |
3626 | .query_status_size = 7, |
3627 | .invalidate_tlbs_size = 2, |
3628 | }; |
3629 | |
3630 | static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) |
3631 | { |
3632 | adev->gfx.kiq[0].pmf = &gfx_v10_0_kiq_pm4_funcs; |
3633 | } |
3634 | |
3635 | static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev) |
3636 | { |
3637 | switch (amdgpu_ip_version(adev, ip: GC_HWIP, inst: 0)) { |
3638 | case IP_VERSION(10, 1, 10): |
3639 | soc15_program_register_sequence(adev, |
3640 | registers: golden_settings_gc_rlc_spm_10_0_nv10, |
3641 | array_size: (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10)); |
3642 | break; |
3643 | case IP_VERSION(10, 1, 1): |
3644 | soc15_program_register_sequence(adev, |
3645 | registers: golden_settings_gc_rlc_spm_10_1_nv14, |
3646 | array_size: (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14)); |
3647 | break; |
3648 | case IP_VERSION(10, 1, 2): |
3649 | soc15_program_register_sequence(adev, |
3650 | registers: golden_settings_gc_rlc_spm_10_1_2_nv12, |
3651 | array_size: (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12)); |
3652 | break; |
3653 | default: |
3654 | break; |
3655 | } |
3656 | } |
3657 | |
3658 | static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev) |
3659 | { |
3660 | if (amdgpu_sriov_vf(adev)) |
3661 | return; |
3662 | |
3663 | switch (amdgpu_ip_version(adev, ip: GC_HWIP, inst: 0)) { |
3664 | case IP_VERSION(10, 1, 10): |
3665 | soc15_program_register_sequence(adev, |
3666 | registers: golden_settings_gc_10_1, |
3667 | array_size: (const u32)ARRAY_SIZE(golden_settings_gc_10_1)); |
3668 | soc15_program_register_sequence(adev, |
3669 | registers: golden_settings_gc_10_0_nv10, |
3670 | array_size: (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10)); |
3671 | break; |
3672 | case IP_VERSION(10, 1, 1): |
3673 | soc15_program_register_sequence(adev, |
3674 | registers: golden_settings_gc_10_1_1, |
3675 | array_size: (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1)); |
3676 | soc15_program_register_sequence(adev, |
3677 | registers: golden_settings_gc_10_1_nv14, |
3678 | array_size: (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14)); |
3679 | break; |
3680 | case IP_VERSION(10, 1, 2): |
3681 | soc15_program_register_sequence(adev, |
3682 | registers: golden_settings_gc_10_1_2, |
3683 | array_size: (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2)); |
3684 | soc15_program_register_sequence(adev, |
3685 | registers: golden_settings_gc_10_1_2_nv12, |
3686 | array_size: (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12)); |
3687 | break; |
3688 | case IP_VERSION(10, 3, 0): |
3689 | soc15_program_register_sequence(adev, |
3690 | registers: golden_settings_gc_10_3, |
3691 | array_size: (const u32)ARRAY_SIZE(golden_settings_gc_10_3)); |
3692 | soc15_program_register_sequence(adev, |
3693 | registers: golden_settings_gc_10_3_sienna_cichlid, |
3694 | array_size: (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid)); |
3695 | break; |
3696 | case IP_VERSION(10, 3, 2): |
3697 | soc15_program_register_sequence(adev, |
3698 | registers: golden_settings_gc_10_3_2, |
3699 | array_size: (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2)); |
3700 | break; |
3701 | case IP_VERSION(10, 3, 1): |
3702 | soc15_program_register_sequence(adev, |
3703 | registers: golden_settings_gc_10_3_vangogh, |
3704 | array_size: (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh)); |
3705 | break; |
3706 | case IP_VERSION(10, 3, 3): |
3707 | soc15_program_register_sequence(adev, |
3708 | registers: golden_settings_gc_10_3_3, |
3709 | array_size: (const u32)ARRAY_SIZE(golden_settings_gc_10_3_3)); |
3710 | break; |
3711 | case IP_VERSION(10, 3, 4): |
3712 | soc15_program_register_sequence(adev, |
3713 | registers: golden_settings_gc_10_3_4, |
3714 | array_size: (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4)); |
3715 | break; |
3716 | case IP_VERSION(10, 3, 5): |
3717 | soc15_program_register_sequence(adev, |
3718 | registers: golden_settings_gc_10_3_5, |
3719 | array_size: (const u32)ARRAY_SIZE(golden_settings_gc_10_3_5)); |
3720 | break; |
3721 | case IP_VERSION(10, 1, 3): |
3722 | case IP_VERSION(10, 1, 4): |
3723 | soc15_program_register_sequence(adev, |
3724 | registers: golden_settings_gc_10_0_cyan_skillfish, |
3725 | array_size: (const u32)ARRAY_SIZE(golden_settings_gc_10_0_cyan_skillfish)); |
3726 | break; |
3727 | case IP_VERSION(10, 3, 6): |
3728 | soc15_program_register_sequence(adev, |
3729 | registers: golden_settings_gc_10_3_6, |
3730 | array_size: (const u32)ARRAY_SIZE(golden_settings_gc_10_3_6)); |
3731 | break; |
3732 | case IP_VERSION(10, 3, 7): |
3733 | soc15_program_register_sequence(adev, |
3734 | registers: golden_settings_gc_10_3_7, |
3735 | array_size: (const u32)ARRAY_SIZE(golden_settings_gc_10_3_7)); |
3736 | break; |
3737 | default: |
3738 | break; |
3739 | } |
3740 | gfx_v10_0_init_spm_golden_registers(adev); |
3741 | } |
3742 | |
3743 | static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, |
3744 | bool wc, uint32_t reg, uint32_t val) |
3745 | { |
3746 | amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); |
3747 | amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | |
3748 | WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); |
3749 | amdgpu_ring_write(ring, v: reg); |
3750 | amdgpu_ring_write(ring, v: 0); |
3751 | amdgpu_ring_write(ring, v: val); |
3752 | } |
3753 | |
3754 | static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, |
3755 | int mem_space, int opt, uint32_t addr0, |
3756 | uint32_t addr1, uint32_t ref, uint32_t mask, |
3757 | uint32_t inv) |
3758 | { |
3759 | amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); |
3760 | amdgpu_ring_write(ring, |
3761 | /* memory (1) or register (0) */ |
3762 | v: (WAIT_REG_MEM_MEM_SPACE(mem_space) | |
3763 | WAIT_REG_MEM_OPERATION(opt) | /* wait */ |
3764 | WAIT_REG_MEM_FUNCTION(3) | /* equal */ |
3765 | WAIT_REG_MEM_ENGINE(eng_sel))); |
3766 | |
3767 | if (mem_space) |
3768 | BUG_ON(addr0 & 0x3); /* Dword align */ |
3769 | amdgpu_ring_write(ring, v: addr0); |
3770 | amdgpu_ring_write(ring, v: addr1); |
3771 | amdgpu_ring_write(ring, v: ref); |
3772 | amdgpu_ring_write(ring, v: mask); |
3773 | amdgpu_ring_write(ring, v: inv); /* poll interval */ |
3774 | } |
3775 | |
3776 | static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring) |
3777 | { |
3778 | struct amdgpu_device *adev = ring->adev; |
3779 | uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); |
3780 | uint32_t tmp = 0; |
3781 | unsigned int i; |
3782 | int r; |
3783 | |
3784 | WREG32(scratch, 0xCAFEDEAD); |
3785 | r = amdgpu_ring_alloc(ring, ndw: 3); |
3786 | if (r) { |
3787 | DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n" , |
3788 | ring->idx, r); |
3789 | return r; |
3790 | } |
3791 | |
3792 | amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); |
3793 | amdgpu_ring_write(ring, v: scratch - |
3794 | PACKET3_SET_UCONFIG_REG_START); |
3795 | amdgpu_ring_write(ring, v: 0xDEADBEEF); |
3796 | amdgpu_ring_commit(ring); |
3797 | |
3798 | for (i = 0; i < adev->usec_timeout; i++) { |
3799 | tmp = RREG32(scratch); |
3800 | if (tmp == 0xDEADBEEF) |
3801 | break; |
3802 | if (amdgpu_emu_mode == 1) |
3803 | msleep(msecs: 1); |
3804 | else |
3805 | udelay(1); |
3806 | } |
3807 | |
3808 | if (i >= adev->usec_timeout) |
3809 | r = -ETIMEDOUT; |
3810 | |
3811 | return r; |
3812 | } |
3813 | |
3814 | static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) |
3815 | { |
3816 | struct amdgpu_device *adev = ring->adev; |
3817 | struct amdgpu_ib ib; |
3818 | struct dma_fence *f = NULL; |
3819 | unsigned int index; |
3820 | uint64_t gpu_addr; |
3821 | volatile uint32_t *cpu_ptr; |
3822 | long r; |
3823 | |
3824 | memset(&ib, 0, sizeof(ib)); |
3825 | |
3826 | if (ring->is_mes_queue) { |
3827 | uint32_t padding, offset; |
3828 | |
3829 | offset = amdgpu_mes_ctx_get_offs(ring, id_offs: AMDGPU_MES_CTX_IB_OFFS); |
3830 | padding = amdgpu_mes_ctx_get_offs(ring, |
3831 | id_offs: AMDGPU_MES_CTX_PADDING_OFFS); |
3832 | |
3833 | ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); |
3834 | ib.ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); |
3835 | |
3836 | gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, padding); |
3837 | cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, padding); |
3838 | *cpu_ptr = cpu_to_le32(0xCAFEDEAD); |
3839 | } else { |
3840 | r = amdgpu_device_wb_get(adev, wb: &index); |
3841 | if (r) |
3842 | return r; |
3843 | |
3844 | gpu_addr = adev->wb.gpu_addr + (index * 4); |
3845 | adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); |
3846 | cpu_ptr = &adev->wb.wb[index]; |
3847 | |
3848 | r = amdgpu_ib_get(adev, NULL, size: 20, pool: AMDGPU_IB_POOL_DIRECT, ib: &ib); |
3849 | if (r) { |
3850 | DRM_ERROR("amdgpu: failed to get ib (%ld).\n" , r); |
3851 | goto err1; |
3852 | } |
3853 | } |
3854 | |
3855 | ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); |
3856 | ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; |
3857 | ib.ptr[2] = lower_32_bits(gpu_addr); |
3858 | ib.ptr[3] = upper_32_bits(gpu_addr); |
3859 | ib.ptr[4] = 0xDEADBEEF; |
3860 | ib.length_dw = 5; |
3861 | |
3862 | r = amdgpu_ib_schedule(ring, num_ibs: 1, ibs: &ib, NULL, f: &f); |
3863 | if (r) |
3864 | goto err2; |
3865 | |
3866 | r = dma_fence_wait_timeout(f, intr: false, timeout); |
3867 | if (r == 0) { |
3868 | r = -ETIMEDOUT; |
3869 | goto err2; |
3870 | } else if (r < 0) { |
3871 | goto err2; |
3872 | } |
3873 | |
3874 | if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) |
3875 | r = 0; |
3876 | else |
3877 | r = -EINVAL; |
3878 | err2: |
3879 | if (!ring->is_mes_queue) |
3880 | amdgpu_ib_free(adev, ib: &ib, NULL); |
3881 | dma_fence_put(fence: f); |
3882 | err1: |
3883 | if (!ring->is_mes_queue) |
3884 | amdgpu_device_wb_free(adev, wb: index); |
3885 | return r; |
3886 | } |
3887 | |
3888 | static void gfx_v10_0_free_microcode(struct amdgpu_device *adev) |
3889 | { |
3890 | amdgpu_ucode_release(fw: &adev->gfx.pfp_fw); |
3891 | amdgpu_ucode_release(fw: &adev->gfx.me_fw); |
3892 | amdgpu_ucode_release(fw: &adev->gfx.ce_fw); |
3893 | amdgpu_ucode_release(fw: &adev->gfx.rlc_fw); |
3894 | amdgpu_ucode_release(fw: &adev->gfx.mec_fw); |
3895 | amdgpu_ucode_release(fw: &adev->gfx.mec2_fw); |
3896 | |
3897 | kfree(objp: adev->gfx.rlc.register_list_format); |
3898 | } |
3899 | |
3900 | static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev) |
3901 | { |
3902 | adev->gfx.cp_fw_write_wait = false; |
3903 | |
3904 | switch (amdgpu_ip_version(adev, ip: GC_HWIP, inst: 0)) { |
3905 | case IP_VERSION(10, 1, 10): |
3906 | case IP_VERSION(10, 1, 2): |
3907 | case IP_VERSION(10, 1, 1): |
3908 | case IP_VERSION(10, 1, 3): |
3909 | case IP_VERSION(10, 1, 4): |
3910 | if ((adev->gfx.me_fw_version >= 0x00000046) && |
3911 | (adev->gfx.me_feature_version >= 27) && |
3912 | (adev->gfx.pfp_fw_version >= 0x00000068) && |
3913 | (adev->gfx.pfp_feature_version >= 27) && |
3914 | (adev->gfx.mec_fw_version >= 0x0000005b) && |
3915 | (adev->gfx.mec_feature_version >= 27)) |
3916 | adev->gfx.cp_fw_write_wait = true; |
3917 | break; |
3918 | case IP_VERSION(10, 3, 0): |
3919 | case IP_VERSION(10, 3, 2): |
3920 | case IP_VERSION(10, 3, 1): |
3921 | case IP_VERSION(10, 3, 4): |
3922 | case IP_VERSION(10, 3, 5): |
3923 | case IP_VERSION(10, 3, 6): |
3924 | case IP_VERSION(10, 3, 3): |
3925 | case IP_VERSION(10, 3, 7): |
3926 | adev->gfx.cp_fw_write_wait = true; |
3927 | break; |
3928 | default: |
3929 | break; |
3930 | } |
3931 | |
3932 | if (!adev->gfx.cp_fw_write_wait) |
3933 | DRM_WARN_ONCE("CP firmware version too old, please update!" ); |
3934 | } |
3935 | |
3936 | static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev) |
3937 | { |
3938 | bool ret = false; |
3939 | |
3940 | switch (adev->pdev->revision) { |
3941 | case 0xc2: |
3942 | case 0xc3: |
3943 | ret = true; |
3944 | break; |
3945 | default: |
3946 | ret = false; |
3947 | break; |
3948 | } |
3949 | |
3950 | return ret; |
3951 | } |
3952 | |
3953 | static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev) |
3954 | { |
3955 | switch (amdgpu_ip_version(adev, ip: GC_HWIP, inst: 0)) { |
3956 | case IP_VERSION(10, 1, 10): |
3957 | if (!gfx_v10_0_navi10_gfxoff_should_enable(adev)) |
3958 | adev->pm.pp_feature &= ~PP_GFXOFF_MASK; |
3959 | break; |
3960 | default: |
3961 | break; |
3962 | } |
3963 | } |
3964 | |
3965 | static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) |
3966 | { |
3967 | char fw_name[40]; |
3968 | char ucode_prefix[30]; |
3969 | const char *wks = "" ; |
3970 | int err; |
3971 | const struct rlc_firmware_header_v2_0 *rlc_hdr; |
3972 | uint16_t version_major; |
3973 | uint16_t version_minor; |
3974 | |
3975 | DRM_DEBUG("\n" ); |
3976 | |
3977 | if (amdgpu_ip_version(adev, ip: GC_HWIP, inst: 0) == IP_VERSION(10, 1, 1) && |
3978 | (!(adev->pdev->device == 0x7340 && adev->pdev->revision != 0x00))) |
3979 | wks = "_wks" ; |
3980 | amdgpu_ucode_ip_version_decode(adev, block_type: GC_HWIP, ucode_prefix, len: sizeof(ucode_prefix)); |
3981 | |
3982 | snprintf(buf: fw_name, size: sizeof(fw_name), fmt: "amdgpu/%s_pfp%s.bin" , ucode_prefix, wks); |
3983 | err = amdgpu_ucode_request(adev, fw: &adev->gfx.pfp_fw, fw_name); |
3984 | if (err) |
3985 | goto out; |
3986 | amdgpu_gfx_cp_init_microcode(adev, ucode_id: AMDGPU_UCODE_ID_CP_PFP); |
3987 | |
3988 | snprintf(buf: fw_name, size: sizeof(fw_name), fmt: "amdgpu/%s_me%s.bin" , ucode_prefix, wks); |
3989 | err = amdgpu_ucode_request(adev, fw: &adev->gfx.me_fw, fw_name); |
3990 | if (err) |
3991 | goto out; |
3992 | amdgpu_gfx_cp_init_microcode(adev, ucode_id: AMDGPU_UCODE_ID_CP_ME); |
3993 | |
3994 | snprintf(buf: fw_name, size: sizeof(fw_name), fmt: "amdgpu/%s_ce%s.bin" , ucode_prefix, wks); |
3995 | err = amdgpu_ucode_request(adev, fw: &adev->gfx.ce_fw, fw_name); |
3996 | if (err) |
3997 | goto out; |
3998 | amdgpu_gfx_cp_init_microcode(adev, ucode_id: AMDGPU_UCODE_ID_CP_CE); |
3999 | |
4000 | if (!amdgpu_sriov_vf(adev)) { |
4001 | snprintf(buf: fw_name, size: sizeof(fw_name), fmt: "amdgpu/%s_rlc.bin" , ucode_prefix); |
4002 | err = request_firmware(fw: &adev->gfx.rlc_fw, name: fw_name, device: adev->dev); |
4003 | if (err) |
4004 | goto out; |
4005 | |
4006 | /* don't validate this firmware. There are apparently firmwares |
4007 | * in the wild with incorrect size in the header |
4008 | */ |
4009 | rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; |
4010 | version_major = le16_to_cpu(rlc_hdr->header.header_version_major); |
4011 | version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); |
4012 | err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); |
4013 | if (err) |
4014 | goto out; |
4015 | } |
4016 | |
4017 | snprintf(buf: fw_name, size: sizeof(fw_name), fmt: "amdgpu/%s_mec%s.bin" , ucode_prefix, wks); |
4018 | err = amdgpu_ucode_request(adev, fw: &adev->gfx.mec_fw, fw_name); |
4019 | if (err) |
4020 | goto out; |
4021 | amdgpu_gfx_cp_init_microcode(adev, ucode_id: AMDGPU_UCODE_ID_CP_MEC1); |
4022 | amdgpu_gfx_cp_init_microcode(adev, ucode_id: AMDGPU_UCODE_ID_CP_MEC1_JT); |
4023 | |
4024 | snprintf(buf: fw_name, size: sizeof(fw_name), fmt: "amdgpu/%s_mec2%s.bin" , ucode_prefix, wks); |
4025 | err = amdgpu_ucode_request(adev, fw: &adev->gfx.mec2_fw, fw_name); |
4026 | if (!err) { |
4027 | amdgpu_gfx_cp_init_microcode(adev, ucode_id: AMDGPU_UCODE_ID_CP_MEC2); |
4028 | amdgpu_gfx_cp_init_microcode(adev, ucode_id: AMDGPU_UCODE_ID_CP_MEC2_JT); |
4029 | } else { |
4030 | err = 0; |
4031 | adev->gfx.mec2_fw = NULL; |
4032 | } |
4033 | |
4034 | gfx_v10_0_check_fw_write_wait(adev); |
4035 | out: |
4036 | if (err) { |
4037 | amdgpu_ucode_release(fw: &adev->gfx.pfp_fw); |
4038 | amdgpu_ucode_release(fw: &adev->gfx.me_fw); |
4039 | amdgpu_ucode_release(fw: &adev->gfx.ce_fw); |
4040 | amdgpu_ucode_release(fw: &adev->gfx.rlc_fw); |
4041 | amdgpu_ucode_release(fw: &adev->gfx.mec_fw); |
4042 | amdgpu_ucode_release(fw: &adev->gfx.mec2_fw); |
4043 | } |
4044 | |
4045 | gfx_v10_0_check_gfxoff_flag(adev); |
4046 | |
4047 | return err; |
4048 | } |
4049 | |
4050 | static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev) |
4051 | { |
4052 | u32 count = 0; |
4053 | const struct cs_section_def *sect = NULL; |
4054 | const struct cs_extent_def *ext = NULL; |
4055 | |
4056 | /* begin clear state */ |
4057 | count += 2; |
4058 | /* context control state */ |
4059 | count += 3; |
4060 | |
4061 | for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { |
4062 | for (ext = sect->section; ext->extent != NULL; ++ext) { |
4063 | if (sect->id == SECT_CONTEXT) |
4064 | count += 2 + ext->reg_count; |
4065 | else |
4066 | return 0; |
4067 | } |
4068 | } |
4069 | |
4070 | /* set PA_SC_TILE_STEERING_OVERRIDE */ |
4071 | count += 3; |
4072 | /* end clear state */ |
4073 | count += 2; |
4074 | /* clear state */ |
4075 | count += 2; |
4076 | |
4077 | return count; |
4078 | } |
4079 | |
4080 | static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev, |
4081 | volatile u32 *buffer) |
4082 | { |
4083 | u32 count = 0, i; |
4084 | const struct cs_section_def *sect = NULL; |
4085 | const struct cs_extent_def *ext = NULL; |
4086 | int ctx_reg_offset; |
4087 | |
4088 | if (adev->gfx.rlc.cs_data == NULL) |
4089 | return; |
4090 | if (buffer == NULL) |
4091 | return; |
4092 | |
4093 | buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); |
4094 | buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); |
4095 | |
4096 | buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); |
4097 | buffer[count++] = cpu_to_le32(0x80000000); |
4098 | buffer[count++] = cpu_to_le32(0x80000000); |
4099 | |
4100 | for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { |
4101 | for (ext = sect->section; ext->extent != NULL; ++ext) { |
4102 | if (sect->id == SECT_CONTEXT) { |
4103 | buffer[count++] = |
4104 | cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); |
4105 | buffer[count++] = cpu_to_le32(ext->reg_index - |
4106 | PACKET3_SET_CONTEXT_REG_START); |
4107 | for (i = 0; i < ext->reg_count; i++) |
4108 | buffer[count++] = cpu_to_le32(ext->extent[i]); |
4109 | } else { |
4110 | return; |
4111 | } |
4112 | } |
4113 | } |
4114 | |
4115 | ctx_reg_offset = |
4116 | SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; |
4117 | buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
4118 | buffer[count++] = cpu_to_le32(ctx_reg_offset); |
4119 | buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override); |
4120 | |
4121 | buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); |
4122 | buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); |
4123 | |
4124 | buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); |
4125 | buffer[count++] = cpu_to_le32(0); |
4126 | } |
4127 | |
4128 | static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev) |
4129 | { |
4130 | /* clear state block */ |
4131 | amdgpu_bo_free_kernel(bo: &adev->gfx.rlc.clear_state_obj, |
4132 | gpu_addr: &adev->gfx.rlc.clear_state_gpu_addr, |
4133 | cpu_addr: (void **)&adev->gfx.rlc.cs_ptr); |
4134 | |
4135 | /* jump table block */ |
4136 | amdgpu_bo_free_kernel(bo: &adev->gfx.rlc.cp_table_obj, |
4137 | gpu_addr: &adev->gfx.rlc.cp_table_gpu_addr, |
4138 | cpu_addr: (void **)&adev->gfx.rlc.cp_table_ptr); |
4139 | } |
4140 | |
4141 | static void gfx_v10_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) |
4142 | { |
4143 | struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; |
4144 | |
4145 | reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; |
4146 | reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); |
4147 | reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1); |
4148 | reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2); |
4149 | reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3); |
4150 | reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL); |
4151 | reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX); |
4152 | switch (amdgpu_ip_version(adev, ip: GC_HWIP, inst: 0)) { |
4153 | case IP_VERSION(10, 3, 0): |
4154 | reg_access_ctrl->spare_int = |
4155 | SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT_0_Sienna_Cichlid); |
4156 | break; |
4157 | default: |
4158 | reg_access_ctrl->spare_int = |
4159 | SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT); |
4160 | break; |
4161 | } |
4162 | adev->gfx.rlc.rlcg_reg_access_supported = true; |
4163 | } |
4164 | |
4165 | static int gfx_v10_0_rlc_init(struct amdgpu_device *adev) |
4166 | { |
4167 | const struct cs_section_def *cs_data; |
4168 | int r; |
4169 | |
4170 | adev->gfx.rlc.cs_data = gfx10_cs_data; |
4171 | |
4172 | cs_data = adev->gfx.rlc.cs_data; |
4173 | |
4174 | if (cs_data) { |
4175 | /* init clear state block */ |
4176 | r = amdgpu_gfx_rlc_init_csb(adev); |
4177 | if (r) |
4178 | return r; |
4179 | } |
4180 | |
4181 | return 0; |
4182 | } |
4183 | |
4184 | static void gfx_v10_0_mec_fini(struct amdgpu_device *adev) |
4185 | { |
4186 | amdgpu_bo_free_kernel(bo: &adev->gfx.mec.hpd_eop_obj, NULL, NULL); |
4187 | amdgpu_bo_free_kernel(bo: &adev->gfx.mec.mec_fw_obj, NULL, NULL); |
4188 | } |
4189 | |
4190 | static void gfx_v10_0_me_init(struct amdgpu_device *adev) |
4191 | { |
4192 | bitmap_zero(dst: adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); |
4193 | |
4194 | amdgpu_gfx_graphics_queue_acquire(adev); |
4195 | } |
4196 | |
4197 | static int gfx_v10_0_mec_init(struct amdgpu_device *adev) |
4198 | { |
4199 | int r; |
4200 | u32 *hpd; |
4201 | const __le32 *fw_data = NULL; |
4202 | unsigned int fw_size; |
4203 | u32 *fw = NULL; |
4204 | size_t mec_hpd_size; |
4205 | |
4206 | const struct gfx_firmware_header_v1_0 *mec_hdr = NULL; |
4207 | |
4208 | bitmap_zero(dst: adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); |
4209 | |
4210 | /* take ownership of the relevant compute queues */ |
4211 | amdgpu_gfx_compute_queue_acquire(adev); |
4212 | mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE; |
4213 | |
4214 | if (mec_hpd_size) { |
4215 | r = amdgpu_bo_create_reserved(adev, size: mec_hpd_size, PAGE_SIZE, |
4216 | AMDGPU_GEM_DOMAIN_GTT, |
4217 | bo_ptr: &adev->gfx.mec.hpd_eop_obj, |
4218 | gpu_addr: &adev->gfx.mec.hpd_eop_gpu_addr, |
4219 | cpu_addr: (void **)&hpd); |
4220 | if (r) { |
4221 | dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n" , r); |
4222 | gfx_v10_0_mec_fini(adev); |
4223 | return r; |
4224 | } |
4225 | |
4226 | memset(hpd, 0, mec_hpd_size); |
4227 | |
4228 | amdgpu_bo_kunmap(bo: adev->gfx.mec.hpd_eop_obj); |
4229 | amdgpu_bo_unreserve(bo: adev->gfx.mec.hpd_eop_obj); |
4230 | } |
4231 | |
4232 | if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { |
4233 | mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; |
4234 | |
4235 | fw_data = (const __le32 *) (adev->gfx.mec_fw->data + |
4236 | le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); |
4237 | fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); |
4238 | |
4239 | r = amdgpu_bo_create_reserved(adev, size: mec_hdr->header.ucode_size_bytes, |
4240 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, |
4241 | bo_ptr: &adev->gfx.mec.mec_fw_obj, |
4242 | gpu_addr: &adev->gfx.mec.mec_fw_gpu_addr, |
4243 | cpu_addr: (void **)&fw); |
4244 | if (r) { |
4245 | dev_err(adev->dev, "(%d) failed to create mec fw bo\n" , r); |
4246 | gfx_v10_0_mec_fini(adev); |
4247 | return r; |
4248 | } |
4249 | |
4250 | memcpy(fw, fw_data, fw_size); |
4251 | |
4252 | amdgpu_bo_kunmap(bo: adev->gfx.mec.mec_fw_obj); |
4253 | amdgpu_bo_unreserve(bo: adev->gfx.mec.mec_fw_obj); |
4254 | } |
4255 | |
4256 | return 0; |
4257 | } |
4258 | |
4259 | static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) |
4260 | { |
4261 | WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, |
4262 | (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | |
4263 | (address << SQ_IND_INDEX__INDEX__SHIFT)); |
4264 | return RREG32_SOC15(GC, 0, mmSQ_IND_DATA); |
4265 | } |
4266 | |
4267 | static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, |
4268 | uint32_t thread, uint32_t regno, |
4269 | uint32_t num, uint32_t *out) |
4270 | { |
4271 | WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, |
4272 | (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | |
4273 | (regno << SQ_IND_INDEX__INDEX__SHIFT) | |
4274 | (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | |
4275 | (SQ_IND_INDEX__AUTO_INCR_MASK)); |
4276 | while (num--) |
4277 | *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA); |
4278 | } |
4279 | |
4280 | static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) |
4281 | { |
4282 | /* in gfx10 the SIMD_ID is specified as part of the INSTANCE |
4283 | * field when performing a select_se_sh so it should be |
4284 | * zero here |
4285 | */ |
4286 | WARN_ON(simd != 0); |
4287 | |
4288 | /* type 2 wave data */ |
4289 | dst[(*no_fields)++] = 2; |
4290 | dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); |
4291 | dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); |
4292 | dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); |
4293 | dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); |
4294 | dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); |
4295 | dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); |
4296 | dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); |
4297 | dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0); |
4298 | dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); |
4299 | dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); |
4300 | dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS); |
4301 | dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); |
4302 | dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); |
4303 | dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); |
4304 | dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); |
4305 | dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); |
4306 | } |
4307 | |
4308 | static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, |
4309 | uint32_t wave, uint32_t start, |
4310 | uint32_t size, uint32_t *dst) |
4311 | { |
4312 | WARN_ON(simd != 0); |
4313 | |
4314 | wave_read_regs( |
4315 | adev, wave, thread: 0, regno: start + SQIND_WAVE_SGPRS_OFFSET, num: size, |
4316 | out: dst); |
4317 | } |
4318 | |
4319 | static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, |
4320 | uint32_t wave, uint32_t thread, |
4321 | uint32_t start, uint32_t size, |
4322 | uint32_t *dst) |
4323 | { |
4324 | wave_read_regs( |
4325 | adev, wave, thread, |
4326 | regno: start + SQIND_WAVE_VGPRS_OFFSET, num: size, out: dst); |
4327 | } |
4328 | |
4329 | static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev, |
4330 | u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) |
4331 | { |
4332 | nv_grbm_select(adev, me, pipe, queue: q, vmid: vm); |
4333 | } |
4334 | |
4335 | static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev, |
4336 | bool enable) |
4337 | { |
4338 | uint32_t data, def; |
4339 | |
4340 | data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL); |
4341 | |
4342 | if (enable) |
4343 | data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK; |
4344 | else |
4345 | data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK; |
4346 | |
4347 | if (data != def) |
4348 | WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data); |
4349 | } |
4350 | |
4351 | static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = { |
4352 | .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter, |
4353 | .select_se_sh = &gfx_v10_0_select_se_sh, |
4354 | .read_wave_data = &gfx_v10_0_read_wave_data, |
4355 | .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs, |
4356 | .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs, |
4357 | .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q, |
4358 | .init_spm_golden = &gfx_v10_0_init_spm_golden_registers, |
4359 | .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg, |
4360 | }; |
4361 | |
4362 | static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev) |
4363 | { |
4364 | u32 gb_addr_config; |
4365 | |
4366 | switch (amdgpu_ip_version(adev, ip: GC_HWIP, inst: 0)) { |
4367 | case IP_VERSION(10, 1, 10): |
4368 | case IP_VERSION(10, 1, 1): |
4369 | case IP_VERSION(10, 1, 2): |
4370 | adev->gfx.config.max_hw_contexts = 8; |
4371 | adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; |
4372 | adev->gfx.config.sc_prim_fifo_size_backend = 0x100; |
4373 | adev->gfx.config.sc_hiz_tile_fifo_size = 0; |
4374 | adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; |
4375 | gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); |
4376 | break; |
4377 | case IP_VERSION(10, 3, 0): |
4378 | case IP_VERSION(10, 3, 2): |
4379 | case IP_VERSION(10, 3, 1): |
4380 | case IP_VERSION(10, 3, 4): |
4381 | case IP_VERSION(10, 3, 5): |
4382 | case IP_VERSION(10, 3, 6): |
4383 | case IP_VERSION(10, 3, 3): |
4384 | case IP_VERSION(10, 3, 7): |
4385 | adev->gfx.config.max_hw_contexts = 8; |
4386 | adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; |
4387 | adev->gfx.config.sc_prim_fifo_size_backend = 0x100; |
4388 | adev->gfx.config.sc_hiz_tile_fifo_size = 0; |
4389 | adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; |
4390 | gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); |
4391 | adev->gfx.config.gb_addr_config_fields.num_pkrs = |
4392 | 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); |
4393 | break; |
4394 | case IP_VERSION(10, 1, 3): |
4395 | case IP_VERSION(10, 1, 4): |
4396 | adev->gfx.config.max_hw_contexts = 8; |
4397 | adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; |
4398 | adev->gfx.config.sc_prim_fifo_size_backend = 0x100; |
4399 | adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; |
4400 | adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; |
4401 | gb_addr_config = CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN; |
4402 | break; |
4403 | default: |
4404 | BUG(); |
4405 | break; |
4406 | } |
4407 | |
4408 | adev->gfx.config.gb_addr_config = gb_addr_config; |
4409 | |
4410 | adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << |
4411 | REG_GET_FIELD(adev->gfx.config.gb_addr_config, |
4412 | GB_ADDR_CONFIG, NUM_PIPES); |
4413 | |
4414 | adev->gfx.config.max_tile_pipes = |
4415 | adev->gfx.config.gb_addr_config_fields.num_pipes; |
4416 | |
4417 | adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << |
4418 | REG_GET_FIELD(adev->gfx.config.gb_addr_config, |
4419 | GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); |
4420 | adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << |
4421 | REG_GET_FIELD(adev->gfx.config.gb_addr_config, |
4422 | GB_ADDR_CONFIG, NUM_RB_PER_SE); |
4423 | adev->gfx.config.gb_addr_config_fields.num_se = 1 << |
4424 | REG_GET_FIELD(adev->gfx.config.gb_addr_config, |
4425 | GB_ADDR_CONFIG, NUM_SHADER_ENGINES); |
4426 | adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + |
4427 | REG_GET_FIELD(adev->gfx.config.gb_addr_config, |
4428 | GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); |
4429 | } |
4430 | |
4431 | static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, |
4432 | int me, int pipe, int queue) |
4433 | { |
4434 | struct amdgpu_ring *ring; |
4435 | unsigned int irq_type; |
4436 | unsigned int hw_prio; |
4437 | |
4438 | ring = &adev->gfx.gfx_ring[ring_id]; |
4439 | |
4440 | ring->me = me; |
4441 | ring->pipe = pipe; |
4442 | ring->queue = queue; |
4443 | |
4444 | ring->ring_obj = NULL; |
4445 | ring->use_doorbell = true; |
4446 | |
4447 | if (!ring_id) |
4448 | ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; |
4449 | else |
4450 | ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; |
4451 | ring->vm_hub = AMDGPU_GFXHUB(0); |
4452 | sprintf(buf: ring->name, fmt: "gfx_%d.%d.%d" , ring->me, ring->pipe, ring->queue); |
4453 | |
4454 | irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; |
4455 | hw_prio = amdgpu_gfx_is_high_priority_graphics_queue(adev, ring) ? |
4456 | AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; |
4457 | return amdgpu_ring_init(adev, ring, max_dw: 1024, irq_src: &adev->gfx.eop_irq, irq_type, |
4458 | hw_prio, NULL); |
4459 | } |
4460 | |
4461 | static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, |
4462 | int mec, int pipe, int queue) |
4463 | { |
4464 | unsigned int irq_type; |
4465 | struct amdgpu_ring *ring; |
4466 | unsigned int hw_prio; |
4467 | |
4468 | ring = &adev->gfx.compute_ring[ring_id]; |
4469 | |
4470 | /* mec0 is me1 */ |
4471 | ring->me = mec + 1; |
4472 | ring->pipe = pipe; |
4473 | ring->queue = queue; |
4474 | |
4475 | ring->ring_obj = NULL; |
4476 | ring->use_doorbell = true; |
4477 | ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; |
4478 | ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr |
4479 | + (ring_id * GFX10_MEC_HPD_SIZE); |
4480 | ring->vm_hub = AMDGPU_GFXHUB(0); |
4481 | sprintf(buf: ring->name, fmt: "comp_%d.%d.%d" , ring->me, ring->pipe, ring->queue); |
4482 | |
4483 | irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP |
4484 | + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) |
4485 | + ring->pipe; |
4486 | hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? |
4487 | AMDGPU_RING_PRIO_2 : AMDGPU_RING_PRIO_DEFAULT; |
4488 | /* type-2 packets are deprecated on MEC, use type-3 instead */ |
4489 | return amdgpu_ring_init(adev, ring, max_dw: 1024, irq_src: &adev->gfx.eop_irq, irq_type, |
4490 | hw_prio, NULL); |
4491 | } |
4492 | |
4493 | static int gfx_v10_0_sw_init(void *handle) |
4494 | { |
4495 | int i, j, k, r, ring_id = 0; |
4496 | int xcc_id = 0; |
4497 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
4498 | |
4499 | switch (amdgpu_ip_version(adev, ip: GC_HWIP, inst: 0)) { |
4500 | case IP_VERSION(10, 1, 10): |
4501 | case IP_VERSION(10, 1, 1): |
4502 | case IP_VERSION(10, 1, 2): |
4503 | case IP_VERSION(10, 1, 3): |
4504 | case IP_VERSION(10, 1, 4): |
4505 | adev->gfx.me.num_me = 1; |
4506 | adev->gfx.me.num_pipe_per_me = 1; |
4507 | adev->gfx.me.num_queue_per_pipe = 1; |
4508 | adev->gfx.mec.num_mec = 2; |
4509 | adev->gfx.mec.num_pipe_per_mec = 4; |
4510 | adev->gfx.mec.num_queue_per_pipe = 8; |
4511 | break; |
4512 | case IP_VERSION(10, 3, 0): |
4513 | case IP_VERSION(10, 3, 2): |
4514 | case IP_VERSION(10, 3, 1): |
4515 | case IP_VERSION(10, 3, 4): |
4516 | case IP_VERSION(10, 3, 5): |
4517 | case IP_VERSION(10, 3, 6): |
4518 | case IP_VERSION(10, 3, 3): |
4519 | case IP_VERSION(10, 3, 7): |
4520 | adev->gfx.me.num_me = 1; |
4521 | adev->gfx.me.num_pipe_per_me = 1; |
4522 | adev->gfx.me.num_queue_per_pipe = 1; |
4523 | adev->gfx.mec.num_mec = 2; |
4524 | adev->gfx.mec.num_pipe_per_mec = 4; |
4525 | adev->gfx.mec.num_queue_per_pipe = 4; |
4526 | break; |
4527 | default: |
4528 | adev->gfx.me.num_me = 1; |
4529 | adev->gfx.me.num_pipe_per_me = 1; |
4530 | adev->gfx.me.num_queue_per_pipe = 1; |
4531 | adev->gfx.mec.num_mec = 1; |
4532 | adev->gfx.mec.num_pipe_per_mec = 4; |
4533 | adev->gfx.mec.num_queue_per_pipe = 8; |
4534 | break; |
4535 | } |
4536 | |
4537 | /* KIQ event */ |
4538 | r = amdgpu_irq_add_id(adev, client_id: SOC15_IH_CLIENTID_GRBM_CP, |
4539 | GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT, |
4540 | source: &adev->gfx.kiq[0].irq); |
4541 | if (r) |
4542 | return r; |
4543 | |
4544 | /* EOP Event */ |
4545 | r = amdgpu_irq_add_id(adev, client_id: SOC15_IH_CLIENTID_GRBM_CP, |
4546 | GFX_10_1__SRCID__CP_EOP_INTERRUPT, |
4547 | source: &adev->gfx.eop_irq); |
4548 | if (r) |
4549 | return r; |
4550 | |
4551 | /* Privileged reg */ |
4552 | r = amdgpu_irq_add_id(adev, client_id: SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT, |
4553 | source: &adev->gfx.priv_reg_irq); |
4554 | if (r) |
4555 | return r; |
4556 | |
4557 | /* Privileged inst */ |
4558 | r = amdgpu_irq_add_id(adev, client_id: SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT, |
4559 | source: &adev->gfx.priv_inst_irq); |
4560 | if (r) |
4561 | return r; |
4562 | |
4563 | adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; |
4564 | |
4565 | gfx_v10_0_me_init(adev); |
4566 | |
4567 | if (adev->gfx.rlc.funcs) { |
4568 | if (adev->gfx.rlc.funcs->init) { |
4569 | r = adev->gfx.rlc.funcs->init(adev); |
4570 | if (r) { |
4571 | dev_err(adev->dev, "Failed to init rlc BOs!\n" ); |
4572 | return r; |
4573 | } |
4574 | } |
4575 | } |
4576 | |
4577 | r = gfx_v10_0_mec_init(adev); |
4578 | if (r) { |
4579 | DRM_ERROR("Failed to init MEC BOs!\n" ); |
4580 | return r; |
4581 | } |
4582 | |
4583 | /* set up the gfx ring */ |
4584 | for (i = 0; i < adev->gfx.me.num_me; i++) { |
4585 | for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { |
4586 | for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { |
4587 | if (!amdgpu_gfx_is_me_queue_enabled(adev, me: i, pipe: k, queue: j)) |
4588 | continue; |
4589 | |
4590 | r = gfx_v10_0_gfx_ring_init(adev, ring_id, |
4591 | me: i, pipe: k, queue: j); |
4592 | if (r) |
4593 | return r; |
4594 | ring_id++; |
4595 | } |
4596 | } |
4597 | } |
4598 | |
4599 | ring_id = 0; |
4600 | /* set up the compute queues - allocate horizontally across pipes */ |
4601 | for (i = 0; i < adev->gfx.mec.num_mec; ++i) { |
4602 | for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { |
4603 | for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { |
4604 | if (!amdgpu_gfx_is_mec_queue_enabled(adev, xcc_id: 0, mec: i, |
4605 | pipe: k, queue: j)) |
4606 | continue; |
4607 | |
4608 | r = gfx_v10_0_compute_ring_init(adev, ring_id, |
4609 | mec: i, pipe: k, queue: j); |
4610 | if (r) |
4611 | return r; |
4612 | |
4613 | ring_id++; |
4614 | } |
4615 | } |
4616 | } |
4617 | |
4618 | if (!adev->enable_mes_kiq) { |
4619 | r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE, xcc_id: 0); |
4620 | if (r) { |
4621 | DRM_ERROR("Failed to init KIQ BOs!\n" ); |
4622 | return r; |
4623 | } |
4624 | |
4625 | r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); |
4626 | if (r) |
4627 | return r; |
4628 | } |
4629 | |
4630 | r = amdgpu_gfx_mqd_sw_init(adev, mqd_size: sizeof(struct v10_compute_mqd), xcc_id: 0); |
4631 | if (r) |
4632 | return r; |
4633 | |
4634 | /* allocate visible FB for rlc auto-loading fw */ |
4635 | if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { |
4636 | r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev); |
4637 | if (r) |
4638 | return r; |
4639 | } |
4640 | |
4641 | adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE; |
4642 | |
4643 | gfx_v10_0_gpu_early_init(adev); |
4644 | |
4645 | return 0; |
4646 | } |
4647 | |
4648 | static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev) |
4649 | { |
4650 | amdgpu_bo_free_kernel(bo: &adev->gfx.pfp.pfp_fw_obj, |
4651 | gpu_addr: &adev->gfx.pfp.pfp_fw_gpu_addr, |
4652 | cpu_addr: (void **)&adev->gfx.pfp.pfp_fw_ptr); |
4653 | } |
4654 | |
4655 | static void gfx_v10_0_ce_fini(struct amdgpu_device *adev) |
4656 | { |
4657 | amdgpu_bo_free_kernel(bo: &adev->gfx.ce.ce_fw_obj, |
4658 | gpu_addr: &adev->gfx.ce.ce_fw_gpu_addr, |
4659 | cpu_addr: (void **)&adev->gfx.ce.ce_fw_ptr); |
4660 | } |
4661 | |
4662 | static void gfx_v10_0_me_fini(struct amdgpu_device *adev) |
4663 | { |
4664 | amdgpu_bo_free_kernel(bo: &adev->gfx.me.me_fw_obj, |
4665 | gpu_addr: &adev->gfx.me.me_fw_gpu_addr, |
4666 | cpu_addr: (void **)&adev->gfx.me.me_fw_ptr); |
4667 | } |
4668 | |
4669 | static int gfx_v10_0_sw_fini(void *handle) |
4670 | { |
4671 | int i; |
4672 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
4673 | |
4674 | for (i = 0; i < adev->gfx.num_gfx_rings; i++) |
4675 | amdgpu_ring_fini(ring: &adev->gfx.gfx_ring[i]); |
4676 | for (i = 0; i < adev->gfx.num_compute_rings; i++) |
4677 | amdgpu_ring_fini(ring: &adev->gfx.compute_ring[i]); |
4678 | |
4679 | amdgpu_gfx_mqd_sw_fini(adev, xcc_id: 0); |
4680 | |
4681 | if (!adev->enable_mes_kiq) { |
4682 | amdgpu_gfx_kiq_free_ring(ring: &adev->gfx.kiq[0].ring); |
4683 | amdgpu_gfx_kiq_fini(adev, xcc_id: 0); |
4684 | } |
4685 | |
4686 | gfx_v10_0_pfp_fini(adev); |
4687 | gfx_v10_0_ce_fini(adev); |
4688 | gfx_v10_0_me_fini(adev); |
4689 | gfx_v10_0_rlc_fini(adev); |
4690 | gfx_v10_0_mec_fini(adev); |
4691 | |
4692 | if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) |
4693 | gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev); |
4694 | |
4695 | gfx_v10_0_free_microcode(adev); |
4696 | |
4697 | return 0; |
4698 | } |
4699 | |
4700 | static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, |
4701 | u32 sh_num, u32 instance, int xcc_id) |
4702 | { |
4703 | u32 data; |
4704 | |
4705 | if (instance == 0xffffffff) |
4706 | data = REG_SET_FIELD(0, GRBM_GFX_INDEX, |
4707 | INSTANCE_BROADCAST_WRITES, 1); |
4708 | else |
4709 | data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, |
4710 | instance); |
4711 | |
4712 | if (se_num == 0xffffffff) |
4713 | data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, |
4714 | 1); |
4715 | else |
4716 | data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); |
4717 | |
4718 | if (sh_num == 0xffffffff) |
4719 | data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, |
4720 | 1); |
4721 | else |
4722 | data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); |
4723 | |
4724 | WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); |
4725 | } |
4726 | |
4727 | static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev) |
4728 | { |
4729 | u32 data, mask; |
4730 | |
4731 | data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE); |
4732 | data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE); |
4733 | |
4734 | data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; |
4735 | data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; |
4736 | |
4737 | mask = amdgpu_gfx_create_bitmask(bit_width: adev->gfx.config.max_backends_per_se / |
4738 | adev->gfx.config.max_sh_per_se); |
4739 | |
4740 | return (~data) & mask; |
4741 | } |
4742 | |
4743 | static void gfx_v10_0_setup_rb(struct amdgpu_device *adev) |
4744 | { |
4745 | int i, j; |
4746 | u32 data; |
4747 | u32 active_rbs = 0; |
4748 | u32 bitmap; |
4749 | u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / |
4750 | adev->gfx.config.max_sh_per_se; |
4751 | |
4752 | mutex_lock(&adev->grbm_idx_mutex); |
4753 | for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { |
4754 | for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { |
4755 | bitmap = i * adev->gfx.config.max_sh_per_se + j; |
4756 | if (((amdgpu_ip_version(adev, ip: GC_HWIP, inst: 0) == |
4757 | IP_VERSION(10, 3, 0)) || |
4758 | (amdgpu_ip_version(adev, ip: GC_HWIP, inst: 0) == |
4759 | IP_VERSION(10, 3, 3)) || |
4760 | (amdgpu_ip_version(adev, ip: GC_HWIP, inst: 0) == |
4761 | IP_VERSION(10, 3, 6))) && |
4762 | ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1)) |
4763 | continue; |
4764 | gfx_v10_0_select_se_sh(adev, se_num: i, sh_num: j, instance: 0xffffffff, xcc_id: 0); |
4765 | data = gfx_v10_0_get_rb_active_bitmap(adev); |
4766 | active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * |
4767 | rb_bitmap_width_per_sh); |
4768 | } |
4769 | } |
4770 | gfx_v10_0_select_se_sh(adev, se_num: 0xffffffff, sh_num: 0xffffffff, instance: 0xffffffff, xcc_id: 0); |
4771 | mutex_unlock(lock: &adev->grbm_idx_mutex); |
4772 | |
4773 | adev->gfx.config.backend_enable_mask = active_rbs; |
4774 | adev->gfx.config.num_rbs = hweight32(active_rbs); |
4775 | } |
4776 | |
4777 | static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev) |
4778 | { |
4779 | uint32_t num_sc; |
4780 | uint32_t enabled_rb_per_sh; |
4781 | uint32_t active_rb_bitmap; |
4782 | uint32_t num_rb_per_sc; |
4783 | uint32_t num_packer_per_sc; |
4784 | uint32_t pa_sc_tile_steering_override; |
4785 | |
4786 | /* for ASICs that integrates GFX v10.3 |
4787 | * pa_sc_tile_steering_override should be set to 0 |
4788 | */ |
4789 | if (amdgpu_ip_version(adev, ip: GC_HWIP, inst: 0) >= IP_VERSION(10, 3, 0)) |
4790 | return 0; |
4791 | |
4792 | /* init num_sc */ |
4793 | num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se * |
4794 | adev->gfx.config.num_sc_per_sh; |
4795 | /* init num_rb_per_sc */ |
4796 | active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev); |
4797 | enabled_rb_per_sh = hweight32(active_rb_bitmap); |
4798 | num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh; |
4799 | /* init num_packer_per_sc */ |
4800 | num_packer_per_sc = adev->gfx.config.num_packer_per_sc; |
4801 | |
4802 | pa_sc_tile_steering_override = 0; |
4803 | pa_sc_tile_steering_override |= |
4804 | (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) & |
4805 | PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK; |
4806 | pa_sc_tile_steering_override |= |
4807 | (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) & |
4808 | PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK; |
4809 | pa_sc_tile_steering_override |= |
4810 | (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) & |
4811 | PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK; |
4812 | |
4813 | return pa_sc_tile_steering_override; |
4814 | } |
4815 | |
4816 | #define DEFAULT_SH_MEM_BASES (0x6000) |
4817 | |
4818 | static void gfx_v10_0_debug_trap_config_init(struct amdgpu_device *adev, |
4819 | uint32_t first_vmid, |
4820 | uint32_t last_vmid) |
4821 | { |
4822 | uint32_t data; |
4823 | uint32_t trap_config_vmid_mask = 0; |
4824 | int i; |
4825 | |
4826 | /* Calculate trap config vmid mask */ |
4827 | for (i = first_vmid; i < last_vmid; i++) |
4828 | trap_config_vmid_mask |= (1 << i); |
4829 | |
4830 | data = REG_SET_FIELD(0, SPI_GDBG_TRAP_CONFIG, |
4831 | VMID_SEL, trap_config_vmid_mask); |
4832 | data = REG_SET_FIELD(data, SPI_GDBG_TRAP_CONFIG, |
4833 | TRAP_EN, 1); |
4834 | WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_CONFIG), data); |
4835 | WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0); |
4836 | |
4837 | WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA0), 0); |
4838 | WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA1), 0); |
4839 | } |
4840 | |
4841 | static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev) |
4842 | { |
4843 | int i; |
4844 | uint32_t sh_mem_bases; |
4845 | |
4846 | /* |
4847 | * Configure apertures: |
4848 | * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) |
4849 | * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) |
4850 | * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) |
4851 | */ |
4852 | sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); |
4853 | |
4854 | mutex_lock(&adev->srbm_mutex); |
4855 | for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { |
4856 | nv_grbm_select(adev, me: 0, pipe: 0, queue: 0, vmid: i); |
4857 | /* CP and shaders */ |
4858 | WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); |
4859 | WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); |
4860 | } |
4861 | nv_grbm_select(adev, me: 0, pipe: 0, queue: 0, vmid: 0); |
4862 | mutex_unlock(lock: &adev->srbm_mutex); |
4863 | |
4864 | /* |
4865 | * Initialize all compute VMIDs to have no GDS, GWS, or OA |
4866 | * access. These should be enabled by FW for target VMIDs. |
4867 | */ |
4868 | for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { |
4869 | WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0); |
4870 | WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0); |
4871 | WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0); |
4872 | WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0); |
4873 | } |
4874 | |
4875 | gfx_v10_0_debug_trap_config_init(adev, first_vmid: adev->vm_manager.first_kfd_vmid, |
4876 | AMDGPU_NUM_VMID); |
4877 | } |
4878 | |
4879 | static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev) |
4880 | { |
4881 | int vmid; |
4882 | |
4883 | /* |
4884 | * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA |
4885 | * access. Compute VMIDs should be enabled by FW for target VMIDs, |
4886 | * the driver can enable them for graphics. VMID0 should maintain |
4887 | * access so that HWS firmware can save/restore entries. |
4888 | */ |
4889 | for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { |
4890 | WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0); |
4891 | WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0); |
4892 | WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0); |
4893 | WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0); |
4894 | } |
4895 | } |
4896 | |
4897 | |
4898 | static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev) |
4899 | { |
4900 | int i, j, k; |
4901 | int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1; |
4902 | u32 tmp, wgp_active_bitmap = 0; |
4903 | u32 gcrd_targets_disable_tcp = 0; |
4904 | u32 utcl_invreq_disable = 0; |
4905 | /* |
4906 | * GCRD_TARGETS_DISABLE field contains |
4907 | * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0] |
4908 | * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0] |
4909 | */ |
4910 | u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask( |
4911 | bit_width: 2 * max_wgp_per_sh + /* TCP */ |
4912 | max_wgp_per_sh + /* SQC */ |
4913 | 4); /* GL1C */ |
4914 | /* |
4915 | * UTCL1_UTCL0_INVREQ_DISABLE field contains |
4916 | * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0] |
4917 | * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0] |
4918 | */ |
4919 | u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask( |
4920 | bit_width: 2 * max_wgp_per_sh + /* TCP */ |
4921 | 2 * max_wgp_per_sh + /* SQC */ |
4922 | 4 + /* RMI */ |
4923 | 1); /* SQG */ |
4924 | |
4925 | mutex_lock(&adev->grbm_idx_mutex); |
4926 | for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { |
4927 | for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { |
4928 | gfx_v10_0_select_se_sh(adev, se_num: i, sh_num: j, instance: 0xffffffff, xcc_id: 0); |
4929 | wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); |
4930 | /* |
4931 | * Set corresponding TCP bits for the inactive WGPs in |
4932 | * GCRD_SA_TARGETS_DISABLE |
4933 | */ |
4934 | gcrd_targets_disable_tcp = 0; |
4935 | /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */ |
4936 | utcl_invreq_disable = 0; |
4937 | |
4938 | for (k = 0; k < max_wgp_per_sh; k++) { |
4939 | if (!(wgp_active_bitmap & (1 << k))) { |
4940 | gcrd_targets_disable_tcp |= 3 << (2 * k); |
4941 | gcrd_targets_disable_tcp |= 1 << (k + (max_wgp_per_sh * 2)); |
4942 | utcl_invreq_disable |= (3 << (2 * k)) | |
4943 | (3 << (2 * (max_wgp_per_sh + k))); |
4944 | } |
4945 | } |
4946 | |
4947 | tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE); |
4948 | /* only override TCP & SQC bits */ |
4949 | tmp &= (0xffffffffU << (4 * max_wgp_per_sh)); |
4950 | tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask); |
4951 | WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp); |
4952 | |
4953 | tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE); |
4954 | /* only override TCP & SQC bits */ |
4955 | tmp &= (0xffffffffU << (3 * max_wgp_per_sh)); |
4956 | tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask); |
4957 | WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp); |
4958 | } |
4959 | } |
4960 | |
4961 | gfx_v10_0_select_se_sh(adev, se_num: 0xffffffff, sh_num: 0xffffffff, instance: 0xffffffff, xcc_id: 0); |
4962 | mutex_unlock(lock: &adev->grbm_idx_mutex); |
4963 | } |
4964 | |
4965 | static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev) |
4966 | { |
4967 | /* TCCs are global (not instanced). */ |
4968 | uint32_t tcc_disable; |
4969 | |
4970 | if (amdgpu_ip_version(adev, ip: GC_HWIP, inst: 0) >= IP_VERSION(10, 3, 0)) { |
4971 | tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) | |
4972 | RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3); |
4973 | } else { |
4974 | tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) | |
4975 | RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE); |
4976 | } |
4977 | |
4978 | adev->gfx.config.tcc_disabled_mask = |
4979 | REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) | |
4980 | (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16); |
4981 | } |
4982 | |
4983 | static void gfx_v10_0_constants_init(struct amdgpu_device *adev) |
4984 | { |
4985 | u32 tmp; |
4986 | int i; |
4987 | |
4988 | if (!amdgpu_sriov_vf(adev)) |
4989 | WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); |
4990 | |
4991 | gfx_v10_0_setup_rb(adev); |
4992 | gfx_v10_0_get_cu_info(adev, cu_info: &adev->gfx.cu_info); |
4993 | gfx_v10_0_get_tcc_info(adev); |
4994 | adev->gfx.config.pa_sc_tile_steering_override = |
4995 | gfx_v10_0_init_pa_sc_tile_steering_override(adev); |
4996 | |
4997 | /* XXX SH_MEM regs */ |
4998 | /* where to put LDS, scratch, GPUVM in FSA64 space */ |
4999 | mutex_lock(&adev->srbm_mutex); |
5000 | for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { |
5001 | nv_grbm_select(adev, me: 0, pipe: 0, queue: 0, vmid: i); |
5002 | /* CP and shaders */ |
5003 | WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); |
5004 | if (i != 0) { |
5005 | tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, |
5006 | (adev->gmc.private_aperture_start >> 48)); |
5007 | tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, |
5008 | (adev->gmc.shared_aperture_start >> 48)); |
5009 | WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp); |
5010 | } |
5011 | } |
5012 | nv_grbm_select(adev, me: 0, pipe: 0, queue: 0, vmid: 0); |
5013 | |
5014 | mutex_unlock(lock: &adev->srbm_mutex); |
5015 | |
5016 | gfx_v10_0_init_compute_vmid(adev); |
5017 | gfx_v10_0_init_gds_vmid(adev); |
5018 | |
5019 | } |
5020 | |
5021 | static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, |
5022 | bool enable) |
5023 | { |
5024 | u32 tmp; |
5025 | |
5026 | if (amdgpu_sriov_vf(adev)) |
5027 | return; |
5028 | |
5029 | tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); |
5030 | |
5031 | tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, |
5032 | enable ? 1 : 0); |
5033 | tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, |
5034 | enable ? 1 : 0); |
5035 | tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, |
5036 | enable ? 1 : 0); |
5037 | tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, |
5038 | enable ? 1 : 0); |
5039 | |
5040 | WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); |
5041 | } |
5042 | |
5043 | static int gfx_v10_0_init_csb(struct amdgpu_device *adev) |
5044 | { |
5045 | adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); |
5046 | |
5047 | /* csib */ |
5048 | if (amdgpu_ip_version(adev, ip: GC_HWIP, inst: 0) == IP_VERSION(10, 1, 2)) { |
5049 | WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI, |
5050 | adev->gfx.rlc.clear_state_gpu_addr >> 32); |
5051 | WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO, |
5052 | adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); |
5053 | WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); |
5054 | } else { |
5055 | WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI, |
5056 | adev->gfx.rlc.clear_state_gpu_addr >> 32); |
5057 | WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO, |
5058 | adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); |
5059 | WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); |
5060 | } |
5061 | return 0; |
5062 | } |
5063 | |
5064 | static void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) |
5065 | { |
5066 | u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); |
5067 | |
5068 | tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); |
5069 | WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp); |
5070 | } |
5071 | |
5072 | static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev) |
5073 | { |
5074 | WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); |
5075 | udelay(50); |
5076 | WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); |
5077 | udelay(50); |
5078 | } |
5079 | |
5080 | static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, |
5081 | bool enable) |
5082 | { |
5083 | uint32_t rlc_pg_cntl; |
5084 | |
5085 | rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); |
5086 | |
5087 | if (!enable) { |
5088 | /* RLC_PG_CNTL[23] = 0 (default) |
5089 | * RLC will wait for handshake acks with SMU |
5090 | * GFXOFF will be enabled |
5091 | * RLC_PG_CNTL[23] = 1 |
5092 | * RLC will not issue any message to SMU |
5093 | * hence no handshake between SMU & RLC |
5094 | * GFXOFF will be disabled |
5095 | */ |
5096 | rlc_pg_cntl |= 0x800000; |
5097 | } else |
5098 | rlc_pg_cntl &= ~0x800000; |
5099 | WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl); |
5100 | } |
5101 | |
5102 | static void gfx_v10_0_rlc_start(struct amdgpu_device *adev) |
5103 | { |
5104 | /* |
5105 | * TODO: enable rlc & smu handshake until smu |
5106 | * and gfxoff feature works as expected |
5107 | */ |
5108 | if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) |
5109 | gfx_v10_0_rlc_smu_handshake_cntl(adev, enable: false); |
5110 | |
5111 | WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); |
5112 | udelay(50); |
5113 | } |
5114 | |
5115 | static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev) |
5116 | { |
5117 | uint32_t tmp; |
5118 | |
5119 | /* enable Save Restore Machine */ |
5120 | tmp = RREG32_SOC15(GC, 0, mmRLC_SRM_CNTL); |
5121 | tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; |
5122 | tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; |
5123 | WREG32_SOC15(GC, 0, mmRLC_SRM_CNTL, tmp); |
5124 | } |
5125 | |
5126 | static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev) |
5127 | { |
5128 | const struct rlc_firmware_header_v2_0 *hdr; |
5129 | const __le32 *fw_data; |
5130 | unsigned int i, fw_size; |
5131 | |
5132 | if (!adev->gfx.rlc_fw) |
5133 | return -EINVAL; |
5134 | |
5135 | hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; |
5136 | amdgpu_ucode_print_rlc_hdr(hdr: &hdr->header); |
5137 | |
5138 | fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + |
5139 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)); |
5140 | fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; |
5141 | |
5142 | WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, |
5143 | RLCG_UCODE_LOADING_START_ADDRESS); |
5144 | |
5145 | for (i = 0; i < fw_size; i++) |
5146 | WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, |
5147 | le32_to_cpup(fw_data++)); |
5148 | |
5149 | WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); |
5150 | |
5151 | return 0; |
5152 | } |
5153 | |
5154 | static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) |
5155 | { |
5156 | int r; |
5157 | |
5158 | if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && |
5159 | adev->psp.autoload_supported) { |
5160 | |
5161 | r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); |
5162 | if (r) |
5163 | return r; |
5164 | |
5165 | gfx_v10_0_init_csb(adev); |
5166 | |
5167 | gfx_v10_0_update_spm_vmid_internal(adev, vmid: 0xf); |
5168 | |
5169 | if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ |
5170 | gfx_v10_0_rlc_enable_srm(adev); |
5171 | } else { |
5172 | if (amdgpu_sriov_vf(adev)) { |
5173 | gfx_v10_0_init_csb(adev); |
5174 | return 0; |
5175 | } |
5176 | |
5177 | adev->gfx.rlc.funcs->stop(adev); |
5178 | |
5179 | /* disable CG */ |
5180 | WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); |
5181 | |
5182 | /* disable PG */ |
5183 | WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0); |
5184 | |
5185 | if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { |
5186 | /* legacy rlc firmware loading */ |
5187 | r = gfx_v10_0_rlc_load_microcode(adev); |
5188 | if (r) |
5189 | return r; |
5190 | } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { |
5191 | /* rlc backdoor autoload firmware */ |
5192 | r = gfx_v10_0_rlc_backdoor_autoload_enable(adev); |
5193 | if (r) |
5194 | return r; |
5195 | } |
5196 | |
5197 | gfx_v10_0_init_csb(adev); |
5198 | |
5199 | gfx_v10_0_update_spm_vmid_internal(adev, vmid: 0xf); |
5200 | |
5201 | adev->gfx.rlc.funcs->start(adev); |
5202 | |
5203 | if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { |
5204 | r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); |
5205 | if (r) |
5206 | return r; |
5207 | } |
5208 | } |
5209 | |
5210 | return 0; |
5211 | } |
5212 | |
5213 | static struct { |
5214 | FIRMWARE_ID id; |
5215 | unsigned int offset; |
5216 | unsigned int size; |
5217 | } rlc_autoload_info[FIRMWARE_ID_MAX]; |
5218 | |
5219 | static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev) |
5220 | { |
5221 | int ret; |
5222 | RLC_TABLE_OF_CONTENT *rlc_toc; |
5223 | |
5224 | ret = amdgpu_bo_create_reserved(adev, size: adev->psp.toc.size_bytes, PAGE_SIZE, |
5225 | AMDGPU_GEM_DOMAIN_GTT, |
5226 | bo_ptr: &adev->gfx.rlc.rlc_toc_bo, |
5227 | gpu_addr: &adev->gfx.rlc.rlc_toc_gpu_addr, |
5228 | cpu_addr: (void **)&adev->gfx.rlc.rlc_toc_buf); |
5229 | if (ret) { |
5230 | dev_err(adev->dev, "(%d) failed to create rlc toc bo\n" , ret); |
5231 | return ret; |
5232 | } |
5233 | |
5234 | /* Copy toc from psp sos fw to rlc toc buffer */ |
5235 | memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc.start_addr, adev->psp.toc.size_bytes); |
5236 | |
5237 | rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf; |
5238 | while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) && |
5239 | (rlc_toc->id < FIRMWARE_ID_MAX)) { |
5240 | if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) && |
5241 | (rlc_toc->id <= FIRMWARE_ID_CP_MES)) { |
5242 | /* Offset needs 4KB alignment */ |
5243 | rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE); |
5244 | } |
5245 | |
5246 | rlc_autoload_info[rlc_toc->id].id = rlc_toc->id; |
5247 | rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4; |
5248 | rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4; |
5249 | |
5250 | rlc_toc++; |
5251 | } |
5252 | |
5253 | return 0; |
5254 | } |
5255 | |
5256 | static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev) |
5257 | { |
5258 | uint32_t total_size = 0; |
5259 | FIRMWARE_ID id; |
5260 | int ret; |
5261 | |
5262 | ret = gfx_v10_0_parse_rlc_toc(adev); |
5263 | if (ret) { |
5264 | dev_err(adev->dev, "failed to parse rlc toc\n" ); |
5265 | return 0; |
5266 | } |
5267 | |
5268 | for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++) |
5269 | total_size += rlc_autoload_info[id].size; |
5270 | |
5271 | /* In case the offset in rlc toc ucode is aligned */ |
5272 | if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset) |
5273 | total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset + |
5274 | rlc_autoload_info[FIRMWARE_ID_MAX-1].size; |
5275 | |
5276 | return total_size; |
5277 | } |
5278 | |
5279 | static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev) |
5280 | { |
5281 | int r; |
5282 | uint32_t total_size; |
5283 | |
5284 | total_size = gfx_v10_0_calc_toc_total_size(adev); |
5285 | |
5286 | r = amdgpu_bo_create_reserved(adev, size: total_size, PAGE_SIZE, |
5287 | AMDGPU_GEM_DOMAIN_GTT, |
5288 | bo_ptr: &adev->gfx.rlc.rlc_autoload_bo, |
5289 | gpu_addr: &adev->gfx.rlc.rlc_autoload_gpu_addr, |
5290 | cpu_addr: (void **)&adev->gfx.rlc.rlc_autoload_ptr); |
5291 | if (r) { |
5292 | dev_err(adev->dev, "(%d) failed to create fw autoload bo\n" , r); |
5293 | return r; |
5294 | } |
5295 | |
5296 | return 0; |
5297 | } |
5298 | |
5299 | static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev) |
5300 | { |
5301 | amdgpu_bo_free_kernel(bo: &adev->gfx.rlc.rlc_toc_bo, |
5302 | gpu_addr: &adev->gfx.rlc.rlc_toc_gpu_addr, |
5303 | cpu_addr: (void **)&adev->gfx.rlc.rlc_toc_buf); |
5304 | amdgpu_bo_free_kernel(bo: &adev->gfx.rlc.rlc_autoload_bo, |
5305 | gpu_addr: &adev->gfx.rlc.rlc_autoload_gpu_addr, |
5306 | cpu_addr: (void **)&adev->gfx.rlc.rlc_autoload_ptr); |
5307 | } |
5308 | |
5309 | static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, |
5310 | FIRMWARE_ID id, |
5311 | const void *fw_data, |
5312 | uint32_t fw_size) |
5313 | { |
5314 | uint32_t toc_offset; |
5315 | uint32_t toc_fw_size; |
5316 | char *ptr = adev->gfx.rlc.rlc_autoload_ptr; |
5317 | |
5318 | if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX) |
5319 | return; |
5320 | |
5321 | toc_offset = rlc_autoload_info[id].offset; |
5322 | toc_fw_size = rlc_autoload_info[id].size; |
5323 | |
5324 | if (fw_size == 0) |
5325 | fw_size = toc_fw_size; |
5326 | |
5327 | if (fw_size > toc_fw_size) |
5328 | fw_size = toc_fw_size; |
5329 | |
5330 | memcpy(ptr + toc_offset, fw_data, fw_size); |
5331 | |
5332 | if (fw_size < toc_fw_size) |
5333 | memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); |
5334 | } |
5335 | |
5336 | static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev) |
5337 | { |
5338 | void *data; |
5339 | uint32_t size; |
5340 | |
5341 | data = adev->gfx.rlc.rlc_toc_buf; |
5342 | size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size; |
5343 | |
5344 | gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, |
5345 | id: FIRMWARE_ID_RLC_TOC, |
5346 | fw_data: data, fw_size: size); |
5347 | } |
5348 | |
5349 | static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev) |
5350 | { |
5351 | const __le32 *fw_data; |
5352 | uint32_t fw_size; |
5353 | const struct gfx_firmware_header_v1_0 *cp_hdr; |
5354 | const struct rlc_firmware_header_v2_0 *rlc_hdr; |
5355 | |
5356 | /* pfp ucode */ |
5357 | cp_hdr = (const struct gfx_firmware_header_v1_0 *) |
5358 | adev->gfx.pfp_fw->data; |
5359 | fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + |
5360 | le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); |
5361 | fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); |
5362 | gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, |
5363 | id: FIRMWARE_ID_CP_PFP, |
5364 | fw_data, fw_size); |
5365 | |
5366 | /* ce ucode */ |
5367 | cp_hdr = (const struct gfx_firmware_header_v1_0 *) |
5368 | adev->gfx.ce_fw->data; |
5369 | fw_data = (const __le32 *)(adev->gfx.ce_fw->data + |
5370 | le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); |
5371 | fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); |
5372 | gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, |
5373 | id: FIRMWARE_ID_CP_CE, |
5374 | fw_data, fw_size); |
5375 | |
5376 | /* me ucode */ |
5377 | cp_hdr = (const struct gfx_firmware_header_v1_0 *) |
5378 | adev->gfx.me_fw->data; |
5379 | fw_data = (const __le32 *)(adev->gfx.me_fw->data + |
5380 | le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); |
5381 | fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); |
5382 | gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, |
5383 | id: FIRMWARE_ID_CP_ME, |
5384 | fw_data, fw_size); |
5385 | |
5386 | /* rlc ucode */ |
5387 | rlc_hdr = (const struct rlc_firmware_header_v2_0 *) |
5388 | adev->gfx.rlc_fw->data; |
5389 | fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + |
5390 | le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); |
5391 | fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); |
5392 | gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, |
5393 | id: FIRMWARE_ID_RLC_G_UCODE, |
5394 | fw_data, fw_size); |
5395 | |
5396 | /* mec1 ucode */ |
5397 | cp_hdr = (const struct gfx_firmware_header_v1_0 *) |
5398 | adev->gfx.mec_fw->data; |
5399 | fw_data = (const __le32 *) (adev->gfx.mec_fw->data + |
5400 | le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); |
5401 | fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) - |
5402 | cp_hdr->jt_size * 4; |
5403 | gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, |
5404 | id: FIRMWARE_ID_CP_MEC, |
5405 | fw_data, fw_size); |
5406 | /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */ |
5407 | } |
5408 | |
5409 | /* Temporarily put sdma part here */ |
5410 | static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev) |
5411 | { |
5412 | const __le32 *fw_data; |
5413 | uint32_t fw_size; |
5414 | const struct sdma_firmware_header_v1_0 *sdma_hdr; |
5415 | int i; |
5416 | |
5417 | for (i = 0; i < adev->sdma.num_instances; i++) { |
5418 | sdma_hdr = (const struct sdma_firmware_header_v1_0 *) |
5419 | adev->sdma.instance[i].fw->data; |
5420 | fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data + |
5421 | le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes)); |
5422 | fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes); |
5423 | |
5424 | if (i == 0) { |
5425 | gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, |
5426 | id: FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size); |
5427 | gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, |
5428 | id: FIRMWARE_ID_SDMA0_JT, |
5429 | fw_data: (uint32_t *)fw_data + |
5430 | sdma_hdr->jt_offset, |
5431 | fw_size: sdma_hdr->jt_size * 4); |
5432 | } else if (i == 1) { |
5433 | gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, |
5434 | id: FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size); |
5435 | gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, |
5436 | id: FIRMWARE_ID_SDMA1_JT, |
5437 | fw_data: (uint32_t *)fw_data + |
5438 | sdma_hdr->jt_offset, |
5439 | fw_size: sdma_hdr->jt_size * 4); |
5440 | } |
5441 | } |
5442 | } |
5443 | |
5444 | static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) |
5445 | { |
5446 | uint32_t rlc_g_offset, rlc_g_size, tmp; |
5447 | uint64_t gpu_addr; |
5448 | |
5449 | gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev); |
5450 | gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev); |
5451 | gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev); |
5452 | |
5453 | rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset; |
5454 | rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size; |
5455 | gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset; |
5456 | |
5457 | WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr)); |
5458 | WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr)); |
5459 | WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size); |
5460 | |
5461 | tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR); |
5462 | if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK | |
5463 | RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) { |
5464 | DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n" ); |
5465 | return -EINVAL; |
5466 | } |
5467 | |
5468 | tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); |
5469 | if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) { |
5470 | DRM_ERROR("RLC ROM should halt itself\n" ); |
5471 | return -EINVAL; |
5472 | } |
5473 | |
5474 | return 0; |
5475 | } |
5476 | |
5477 | static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev) |
5478 | { |
5479 | uint32_t usec_timeout = 50000; /* wait for 50ms */ |
5480 | uint32_t tmp; |
5481 | int i; |
5482 | uint64_t addr; |
5483 | |
5484 | /* Trigger an invalidation of the L1 instruction caches */ |
5485 | tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); |
5486 | tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); |
5487 | WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); |
5488 | |
5489 | /* Wait for invalidation complete */ |
5490 | for (i = 0; i < usec_timeout; i++) { |
5491 | tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); |
5492 | if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, |
5493 | INVALIDATE_CACHE_COMPLETE)) |
5494 | break; |
5495 | udelay(1); |
5496 | } |
5497 | |
5498 | if (i >= usec_timeout) { |
5499 | dev_err(adev->dev, "failed to invalidate instruction cache\n" ); |
5500 | return -EINVAL; |
5501 | } |
5502 | |
5503 | /* Program me ucode address into intruction cache address register */ |
5504 | addr = adev->gfx.rlc.rlc_autoload_gpu_addr + |
5505 | rlc_autoload_info[FIRMWARE_ID_CP_ME].offset; |
5506 | WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, |
5507 | lower_32_bits(addr) & 0xFFFFF000); |
5508 | WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, |
5509 | upper_32_bits(addr)); |
5510 | |
5511 | return 0; |
5512 | } |
5513 | |
5514 | static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev) |
5515 | { |
5516 | uint32_t usec_timeout = 50000; /* wait for 50ms */ |
5517 | uint32_t tmp; |
5518 | int i; |
5519 | uint64_t addr; |
5520 | |
5521 | /* Trigger an invalidation of the L1 instruction caches */ |
5522 | tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); |
5523 | tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); |
5524 | WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); |
5525 | |
5526 | /* Wait for invalidation complete */ |
5527 | for (i = 0; i < usec_timeout; i++) { |
5528 | tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); |
5529 | if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, |
5530 | INVALIDATE_CACHE_COMPLETE)) |
5531 | break; |
5532 | udelay(1); |
5533 | } |
5534 | |
5535 | if (i >= usec_timeout) { |
5536 | dev_err(adev->dev, "failed to invalidate instruction cache\n" ); |
5537 | return -EINVAL; |
5538 | } |
5539 | |
5540 | /* Program ce ucode address into intruction cache address register */ |
5541 | addr = adev->gfx.rlc.rlc_autoload_gpu_addr + |
5542 | rlc_autoload_info[FIRMWARE_ID_CP_CE].offset; |
5543 | WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, |
5544 | lower_32_bits(addr) & 0xFFFFF000); |
5545 | WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, |
5546 | upper_32_bits(addr)); |
5547 | |
5548 | return 0; |
5549 | } |
5550 | |
5551 | static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev) |
5552 | { |
5553 | uint32_t usec_timeout = 50000; /* wait for 50ms */ |
5554 | uint32_t tmp; |
5555 | int i; |
5556 | uint64_t addr; |
5557 | |
5558 | /* Trigger an invalidation of the L1 instruction caches */ |
5559 | tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); |
5560 | tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); |
5561 | WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); |
5562 | |
5563 | /* Wait for invalidation complete */ |
5564 | for (i = 0; i < usec_timeout; i++) { |
5565 | tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); |
5566 | if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, |
5567 | INVALIDATE_CACHE_COMPLETE)) |
5568 | break; |
5569 | udelay(1); |
5570 | } |
5571 | |
5572 | if (i >= usec_timeout) { |
5573 | dev_err(adev->dev, "failed to invalidate instruction cache\n" ); |
5574 | return -EINVAL; |
5575 | } |
5576 | |
5577 | /* Program pfp ucode address into intruction cache address register */ |
5578 | addr = adev->gfx.rlc.rlc_autoload_gpu_addr + |
5579 | rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset; |
5580 | WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, |
5581 | lower_32_bits(addr) & 0xFFFFF000); |
5582 | WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, |
5583 | upper_32_bits(addr)); |
5584 | |
5585 | return 0; |
5586 | } |
5587 | |
5588 | static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev) |
5589 | { |
5590 | uint32_t usec_timeout = 50000; /* wait for 50ms */ |
5591 | uint32_t tmp; |
5592 | int i; |
5593 | uint64_t addr; |
5594 | |
5595 | /* Trigger an invalidation of the L1 instruction caches */ |
5596 | tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); |
5597 | tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); |
5598 | WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); |
5599 | |
5600 | /* Wait for invalidation complete */ |
5601 | for (i = 0; i < usec_timeout; i++) { |
5602 | tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); |
5603 | if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, |
5604 | INVALIDATE_CACHE_COMPLETE)) |
5605 | break; |
5606 | udelay(1); |
5607 | } |
5608 | |
5609 | if (i >= usec_timeout) { |
5610 | dev_err(adev->dev, "failed to invalidate instruction cache\n" ); |
5611 | return -EINVAL; |
5612 | } |
5613 | |
5614 | /* Program mec1 ucode address into intruction cache address register */ |
5615 | addr = adev->gfx.rlc.rlc_autoload_gpu_addr + |
5616 | rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset; |
5617 | WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, |
5618 | lower_32_bits(addr) & 0xFFFFF000); |
5619 | WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, |
5620 | upper_32_bits(addr)); |
5621 | |
5622 | return 0; |
5623 | } |
5624 | |
5625 | static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) |
5626 | { |
5627 | uint32_t cp_status; |
5628 | uint32_t bootload_status; |
5629 | int i, r; |
5630 | |
5631 | for (i = 0; i < adev->usec_timeout; i++) { |
5632 | cp_status = RREG32_SOC15(GC, 0, mmCP_STAT); |
5633 | bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS); |
5634 | if ((cp_status == 0) && |
5635 | (REG_GET_FIELD(bootload_status, |
5636 | RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { |
5637 | break; |
5638 | } |
5639 | udelay(1); |
5640 | } |
5641 | |
5642 | if (i >= adev->usec_timeout) { |
5643 | dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n" ); |
5644 | return -ETIMEDOUT; |
5645 | } |
5646 | |
5647 | if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { |
5648 | r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev); |
5649 | if (r) |
5650 | return r; |
5651 | |
5652 | r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev); |
5653 | if (r) |
5654 | return r; |
5655 | |
5656 | r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev); |
5657 | if (r) |
5658 | return r; |
5659 | |
5660 | r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev); |
5661 | if (r) |
5662 | return r; |
5663 | } |
5664 | |
5665 | return 0; |
5666 | } |
5667 | |
5668 | static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) |
5669 | { |
5670 | int i; |
5671 | u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); |
5672 | |
5673 | tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); |
5674 | tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); |
5675 | tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1); |
5676 | |
5677 | if (amdgpu_ip_version(adev, ip: GC_HWIP, inst: 0) == IP_VERSION(10, 1, 2)) |
5678 | WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp); |
5679 | else |
5680 | WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp); |
5681 | |
5682 | if (adev->job_hang && !enable) |
5683 | return 0; |
5684 | |
5685 | for (i = 0; i < adev->usec_timeout; i++) { |
5686 | if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0) |
5687 | break; |
5688 | udelay(1); |
5689 | } |
5690 | |
5691 | if (i >= adev->usec_timeout) |
5692 | DRM_ERROR("failed to %s cp gfx\n" , enable ? "unhalt" : "halt" ); |
5693 | |
5694 | return 0; |
5695 | } |
5696 | |
5697 | static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev) |
5698 | { |
5699 | int r; |
5700 | const struct gfx_firmware_header_v1_0 *pfp_hdr; |
5701 | const __le32 *fw_data; |
5702 | unsigned int i, fw_size; |
5703 | uint32_t tmp; |
5704 | uint32_t usec_timeout = 50000; /* wait for 50ms */ |
5705 | |
5706 | pfp_hdr = (const struct gfx_firmware_header_v1_0 *) |
5707 | adev->gfx.pfp_fw->data; |
5708 | |
5709 | amdgpu_ucode_print_gfx_hdr(hdr: &pfp_hdr->header); |
5710 | |
5711 | fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + |
5712 | le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); |
5713 | fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes); |
5714 | |
5715 | r = amdgpu_bo_create_reserved(adev, size: pfp_hdr->header.ucode_size_bytes, |
5716 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, |
5717 | bo_ptr: &adev->gfx.pfp.pfp_fw_obj, |
5718 | gpu_addr: &adev->gfx.pfp.pfp_fw_gpu_addr, |
5719 | cpu_addr: (void **)&adev->gfx.pfp.pfp_fw_ptr); |
5720 | if (r) { |
5721 | dev_err(adev->dev, "(%d) failed to create pfp fw bo\n" , r); |
5722 | gfx_v10_0_pfp_fini(adev); |
5723 | return r; |
5724 | } |
5725 | |
5726 | memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size); |
5727 | |
5728 | amdgpu_bo_kunmap(bo: adev->gfx.pfp.pfp_fw_obj); |
5729 | amdgpu_bo_unreserve(bo: adev->gfx.pfp.pfp_fw_obj); |
5730 | |
5731 | /* Trigger an invalidation of the L1 instruction caches */ |
5732 | tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); |
5733 | tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); |
5734 | WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); |
5735 | |
5736 | /* Wait for invalidation complete */ |
5737 | for (i = 0; i < usec_timeout; i++) { |
5738 | tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); |
5739 | if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, |
5740 | INVALIDATE_CACHE_COMPLETE)) |
5741 | break; |
5742 | udelay(1); |
5743 | } |
5744 | |
5745 | if (i >= usec_timeout) { |
5746 | dev_err(adev->dev, "failed to invalidate instruction cache\n" ); |
5747 | return -EINVAL; |
5748 | } |
5749 | |
5750 | if (amdgpu_emu_mode == 1) |
5751 | adev->hdp.funcs->flush_hdp(adev, NULL); |
5752 | |
5753 | tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL); |
5754 | tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); |
5755 | tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); |
5756 | tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); |
5757 | tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1); |
5758 | WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp); |
5759 | WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, |
5760 | adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000); |
5761 | WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, |
5762 | upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); |
5763 | |
5764 | WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0); |
5765 | |
5766 | for (i = 0; i < pfp_hdr->jt_size; i++) |
5767 | WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA, |
5768 | le32_to_cpup(fw_data + pfp_hdr->jt_offset + i)); |
5769 | |
5770 | WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); |
5771 | |
5772 | return 0; |
5773 | } |
5774 | |
5775 | static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev) |
5776 | { |
5777 | int r; |
5778 | const struct gfx_firmware_header_v1_0 *ce_hdr; |
5779 | const __le32 *fw_data; |
5780 | unsigned int i, fw_size; |
5781 | uint32_t tmp; |
5782 | uint32_t usec_timeout = 50000; /* wait for 50ms */ |
5783 | |
5784 | ce_hdr = (const struct gfx_firmware_header_v1_0 *) |
5785 | adev->gfx.ce_fw->data; |
5786 | |
5787 | amdgpu_ucode_print_gfx_hdr(hdr: &ce_hdr->header); |
5788 | |
5789 | fw_data = (const __le32 *)(adev->gfx.ce_fw->data + |
5790 | le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); |
5791 | fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes); |
5792 | |
5793 | r = amdgpu_bo_create_reserved(adev, size: ce_hdr->header.ucode_size_bytes, |
5794 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, |
5795 | bo_ptr: &adev->gfx.ce.ce_fw_obj, |
5796 | gpu_addr: &adev->gfx.ce.ce_fw_gpu_addr, |
5797 | cpu_addr: (void **)&adev->gfx.ce.ce_fw_ptr); |
5798 | if (r) { |
5799 | dev_err(adev->dev, "(%d) failed to create ce fw bo\n" , r); |
5800 | gfx_v10_0_ce_fini(adev); |
5801 | return r; |
5802 | } |
5803 | |
5804 | memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size); |
5805 | |
5806 | amdgpu_bo_kunmap(bo: adev->gfx.ce.ce_fw_obj); |
5807 | amdgpu_bo_unreserve(bo: adev->gfx.ce.ce_fw_obj); |
5808 | |
5809 | /* Trigger an invalidation of the L1 instruction caches */ |
5810 | tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); |
5811 | tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); |
5812 | WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); |
5813 | |
5814 | /* Wait for invalidation complete */ |
5815 | for (i = 0; i < usec_timeout; i++) { |
5816 | tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); |
5817 | if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, |
5818 | INVALIDATE_CACHE_COMPLETE)) |
5819 | break; |
5820 | udelay(1); |
5821 | } |
5822 | |
5823 | if (i >= usec_timeout) { |
5824 | dev_err(adev->dev, "failed to invalidate instruction cache\n" ); |
5825 | return -EINVAL; |
5826 | } |
5827 | |
5828 | if (amdgpu_emu_mode == 1) |
5829 | adev->hdp.funcs->flush_hdp(adev, NULL); |
5830 | |
5831 | tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL); |
5832 | tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0); |
5833 | tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0); |
5834 | tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0); |
5835 | tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1); |
5836 | WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, |
5837 | adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000); |
5838 | WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, |
5839 | upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr)); |
5840 | |
5841 | WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0); |
5842 | |
5843 | for (i = 0; i < ce_hdr->jt_size; i++) |
5844 | WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA, |
5845 | le32_to_cpup(fw_data + ce_hdr->jt_offset + i)); |
5846 | |
5847 | WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); |
5848 | |
5849 | return 0; |
5850 | } |
5851 | |
5852 | static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev) |
5853 | { |
5854 | int r; |
5855 | const struct gfx_firmware_header_v1_0 *me_hdr; |
5856 | const __le32 *fw_data; |
5857 | unsigned int i, fw_size; |
5858 | uint32_t tmp; |
5859 | uint32_t usec_timeout = 50000; /* wait for 50ms */ |
5860 | |
5861 | me_hdr = (const struct gfx_firmware_header_v1_0 *) |
5862 | adev->gfx.me_fw->data; |
5863 | |
5864 | amdgpu_ucode_print_gfx_hdr(hdr: &me_hdr->header); |
5865 | |
5866 | fw_data = (const __le32 *)(adev->gfx.me_fw->data + |
5867 | le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); |
5868 | fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes); |
5869 | |
5870 | r = amdgpu_bo_create_reserved(adev, size: me_hdr->header.ucode_size_bytes, |
5871 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, |
5872 | bo_ptr: &adev->gfx.me.me_fw_obj, |
5873 | gpu_addr: &adev->gfx.me.me_fw_gpu_addr, |
5874 | cpu_addr: (void **)&adev->gfx.me.me_fw_ptr); |
5875 | if (r) { |
5876 | dev_err(adev->dev, "(%d) failed to create me fw bo\n" , r); |
5877 | gfx_v10_0_me_fini(adev); |
5878 | return r; |
5879 | } |
5880 | |
5881 | memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); |
5882 | |
5883 | amdgpu_bo_kunmap(bo: adev->gfx.me.me_fw_obj); |
5884 | amdgpu_bo_unreserve(bo: adev->gfx.me.me_fw_obj); |
5885 | |
5886 | /* Trigger an invalidation of the L1 instruction caches */ |
5887 | tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); |
5888 | tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); |
5889 | WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); |
5890 | |
5891 | /* Wait for invalidation complete */ |
5892 | for (i = 0; i < usec_timeout; i++) { |
5893 | tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); |
5894 | if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, |
5895 | INVALIDATE_CACHE_COMPLETE)) |
5896 | break; |
5897 | udelay(1); |
5898 | } |
5899 | |
5900 | if (i >= usec_timeout) { |
5901 | dev_err(adev->dev, "failed to invalidate instruction cache\n" ); |
5902 | return -EINVAL; |
5903 | } |
5904 | |
5905 | if (amdgpu_emu_mode == 1) |
5906 | adev->hdp.funcs->flush_hdp(adev, NULL); |
5907 | |
5908 | tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL); |
5909 | tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); |
5910 | tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); |
5911 | tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); |
5912 | tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1); |
5913 | WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, |
5914 | adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000); |
5915 | WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, |
5916 | upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); |
5917 | |
5918 | WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0); |
5919 | |
5920 | for (i = 0; i < me_hdr->jt_size; i++) |
5921 | WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA, |
5922 | le32_to_cpup(fw_data + me_hdr->jt_offset + i)); |
5923 | |
5924 | WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version); |
5925 | |
5926 | return 0; |
5927 | } |
5928 | |
5929 | static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev) |
5930 | { |
5931 | int r; |
5932 | |
5933 | if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) |
5934 | return -EINVAL; |
5935 | |
5936 | gfx_v10_0_cp_gfx_enable(adev, enable: false); |
5937 | |
5938 | r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev); |
5939 | if (r) { |
5940 | dev_err(adev->dev, "(%d) failed to load pfp fw\n" , r); |
5941 | return r; |
5942 | } |
5943 | |
5944 | r = gfx_v10_0_cp_gfx_load_ce_microcode(adev); |
5945 | if (r) { |
5946 | dev_err(adev->dev, "(%d) failed to load ce fw\n" , r); |
5947 | return r; |
5948 | } |
5949 | |
5950 | r = gfx_v10_0_cp_gfx_load_me_microcode(adev); |
5951 | if (r) { |
5952 | dev_err(adev->dev, "(%d) failed to load me fw\n" , r); |
5953 | return r; |
5954 | } |
5955 | |
5956 | return 0; |
5957 | } |
5958 | |
5959 | static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev) |
5960 | { |
5961 | struct amdgpu_ring *ring; |
5962 | const struct cs_section_def *sect = NULL; |
5963 | const struct cs_extent_def *ext = NULL; |
5964 | int r, i; |
5965 | int ctx_reg_offset; |
5966 | |
5967 | /* init the CP */ |
5968 | WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, |
5969 | adev->gfx.config.max_hw_contexts - 1); |
5970 | WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1); |
5971 | |
5972 | gfx_v10_0_cp_gfx_enable(adev, enable: true); |
5973 | |
5974 | ring = &adev->gfx.gfx_ring[0]; |
5975 | r = amdgpu_ring_alloc(ring, ndw: gfx_v10_0_get_csb_size(adev) + 4); |
5976 | if (r) { |
5977 | DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n" , r); |
5978 | return r; |
5979 | } |
5980 | |
5981 | amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); |
5982 | amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); |
5983 | |
5984 | amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); |
5985 | amdgpu_ring_write(ring, v: 0x80000000); |
5986 | amdgpu_ring_write(ring, v: 0x80000000); |
5987 | |
5988 | for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { |
5989 | for (ext = sect->section; ext->extent != NULL; ++ext) { |
5990 | if (sect->id == SECT_CONTEXT) { |
5991 | amdgpu_ring_write(ring, |
5992 | PACKET3(PACKET3_SET_CONTEXT_REG, |
5993 | ext->reg_count)); |
5994 | amdgpu_ring_write(ring, v: ext->reg_index - |
5995 | PACKET3_SET_CONTEXT_REG_START); |
5996 | for (i = 0; i < ext->reg_count; i++) |
5997 | amdgpu_ring_write(ring, v: ext->extent[i]); |
5998 | } |
5999 | } |
6000 | } |
6001 | |
6002 | ctx_reg_offset = |
6003 | SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; |
6004 | amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
6005 | amdgpu_ring_write(ring, v: ctx_reg_offset); |
6006 | amdgpu_ring_write(ring, v: adev->gfx.config.pa_sc_tile_steering_override); |
6007 | |
6008 | amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); |
6009 | amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); |
6010 | |
6011 | amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); |
6012 | amdgpu_ring_write(ring, v: 0); |
6013 | |
6014 | amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); |
6015 | amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); |
6016 | amdgpu_ring_write(ring, v: 0x8000); |
6017 | amdgpu_ring_write(ring, v: 0x8000); |
6018 | |
6019 | amdgpu_ring_commit(ring); |
6020 | |
6021 | /* submit cs packet to copy state 0 to next available state */ |
6022 | if (adev->gfx.num_gfx_rings > 1) { |
6023 | /* maximum supported gfx ring is 2 */ |
6024 | ring = &adev->gfx.gfx_ring[1]; |
6025 | r = amdgpu_ring_alloc(ring, ndw: 2); |
6026 | if (r) { |
6027 | DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n" , r); |
6028 | return r; |
6029 | } |
6030 | |
6031 | amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); |
6032 | amdgpu_ring_write(ring, v: 0); |
6033 | |
6034 | amdgpu_ring_commit(ring); |
6035 | } |
6036 | return 0; |
6037 | } |
6038 | |
6039 | static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, |
6040 | CP_PIPE_ID pipe) |
6041 | { |
6042 | u32 tmp; |
6043 | |
6044 | tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL); |
6045 | tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); |
6046 | |
6047 | WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp); |
6048 | } |
6049 | |
6050 | static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, |
6051 | struct amdgpu_ring *ring) |
6052 | { |
6053 | u32 tmp; |
6054 | |
6055 | if (!amdgpu_async_gfx_ring) { |
6056 | tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); |
6057 | if (ring->use_doorbell) { |
6058 | tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, |
6059 | DOORBELL_OFFSET, ring->doorbell_index); |
6060 | tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, |
6061 | DOORBELL_EN, 1); |
6062 | } else { |
6063 | tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, |
6064 | DOORBELL_EN, 0); |
6065 | } |
6066 | WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp); |
6067 | } |
6068 | switch (amdgpu_ip_version(adev, ip: GC_HWIP, inst: 0)) { |
6069 | case IP_VERSION(10, 3, 0): |
6070 | case IP_VERSION(10, 3, 2): |
6071 | case IP_VERSION(10, 3, 1): |
6072 | case IP_VERSION(10, 3, 4): |
6073 | case IP_VERSION(10, 3, 5): |
6074 | case IP_VERSION(10, 3, 6): |
6075 | case IP_VERSION(10, 3, 3): |
6076 | case IP_VERSION(10, 3, 7): |
6077 | tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, |
6078 | DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index); |
6079 | WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); |
6080 | |
6081 | WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, |
6082 | CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK); |
6083 | break; |
6084 | default: |
6085 | tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, |
6086 | DOORBELL_RANGE_LOWER, ring->doorbell_index); |
6087 | WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); |
6088 | |
6089 | WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, |
6090 | CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); |
6091 | break; |
6092 | } |
6093 | } |
6094 | |
6095 | static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev) |
6096 | { |
6097 | struct amdgpu_ring *ring; |
6098 | u32 tmp; |
6099 | u32 rb_bufsz; |
6100 | u64 rb_addr, rptr_addr, wptr_gpu_addr; |
6101 | |
6102 | /* Set the write pointer delay */ |
6103 | WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0); |
6104 | |
6105 | /* set the RB to use vmid 0 */ |
6106 | WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0); |
6107 | |
6108 | /* Init gfx ring 0 for pipe 0 */ |
6109 | mutex_lock(&adev->srbm_mutex); |
6110 | gfx_v10_0_cp_gfx_switch_pipe(adev, pipe: PIPE_ID0); |
6111 | |
6112 | /* Set ring buffer size */ |
6113 | ring = &adev->gfx.gfx_ring[0]; |
6114 | rb_bufsz = order_base_2(ring->ring_size / 8); |
6115 | tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); |
6116 | tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); |
6117 | #ifdef __BIG_ENDIAN |
6118 | tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); |
6119 | #endif |
6120 | WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); |
6121 | |
6122 | /* Initialize the ring buffer's write pointers */ |
6123 | ring->wptr = 0; |
6124 | WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); |
6125 | WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); |
6126 | |
6127 | /* set the wb address wether it's enabled or not */ |
6128 | rptr_addr = ring->rptr_gpu_addr; |
6129 | WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); |
6130 | WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & |
6131 | CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); |
6132 | |
6133 | wptr_gpu_addr = ring->wptr_gpu_addr; |
6134 | WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, |
6135 | lower_32_bits(wptr_gpu_addr)); |
6136 | WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, |
6137 | upper_32_bits(wptr_gpu_addr)); |
6138 | |
6139 | mdelay(1); |
6140 | WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); |
6141 | |
6142 | rb_addr = ring->gpu_addr >> 8; |
6143 | WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr); |
6144 | WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); |
6145 | |
6146 | WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1); |
6147 | |
6148 | gfx_v10_0_cp_gfx_set_doorbell(adev, ring); |
6149 | mutex_unlock(lock: &adev->srbm_mutex); |
6150 | |
6151 | /* Init gfx ring 1 for pipe 1 */ |
6152 | if (adev->gfx.num_gfx_rings > 1) { |
6153 | mutex_lock(&adev->srbm_mutex); |
6154 | gfx_v10_0_cp_gfx_switch_pipe(adev, pipe: PIPE_ID1); |
6155 | /* maximum supported gfx ring is 2 */ |
6156 | ring = &adev->gfx.gfx_ring[1]; |
6157 | rb_bufsz = order_base_2(ring->ring_size / 8); |
6158 | tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); |
6159 | tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); |
6160 | WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); |
6161 | /* Initialize the ring buffer's write pointers */ |
6162 | ring->wptr = 0; |
6163 | WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr)); |
6164 | WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); |
6165 | /* Set the wb address wether it's enabled or not */ |
6166 | rptr_addr = ring->rptr_gpu_addr; |
6167 | WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); |
6168 | WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & |
6169 | CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); |
6170 | wptr_gpu_addr = ring->wptr_gpu_addr; |
6171 | WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, |
6172 | lower_32_bits(wptr_gpu_addr)); |
6173 | WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, |
6174 | upper_32_bits(wptr_gpu_addr)); |
6175 | |
6176 | mdelay(1); |
6177 | WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); |
6178 | |
6179 | rb_addr = ring->gpu_addr >> 8; |
6180 | WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr); |
6181 | WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr)); |
6182 | WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1); |
6183 | |
6184 | gfx_v10_0_cp_gfx_set_doorbell(adev, ring); |
6185 | mutex_unlock(lock: &adev->srbm_mutex); |
6186 | } |
6187 | /* Switch to pipe 0 */ |
6188 | mutex_lock(&adev->srbm_mutex); |
6189 | gfx_v10_0_cp_gfx_switch_pipe(adev, pipe: PIPE_ID0); |
6190 | mutex_unlock(lock: &adev->srbm_mutex); |
6191 | |
6192 | /* start the ring */ |
6193 | gfx_v10_0_cp_gfx_start(adev); |
6194 | |
6195 | return 0; |
6196 | } |
6197 | |
6198 | static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) |
6199 | { |
6200 | if (enable) { |
6201 | switch (amdgpu_ip_version(adev, ip: GC_HWIP, inst: 0)) { |
6202 | case IP_VERSION(10, 3, 0): |
6203 | case IP_VERSION(10, 3, 2): |
6204 | case IP_VERSION(10, 3, 1): |
6205 | case IP_VERSION(10, 3, 4): |
6206 | case IP_VERSION(10, 3, 5): |
6207 | case IP_VERSION(10, 3, 6): |
6208 | case IP_VERSION(10, 3, 3): |
6209 | case IP_VERSION(10, 3, 7): |
6210 | WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0); |
6211 | break; |
6212 | default: |
6213 | WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0); |
6214 | break; |
6215 | } |
6216 | } else { |
6217 | switch (amdgpu_ip_version(adev, ip: GC_HWIP, inst: 0)) { |
6218 | case IP_VERSION(10, 3, 0): |
6219 | case IP_VERSION(10, 3, 2): |
6220 | case IP_VERSION(10, 3, 1): |
6221 | case IP_VERSION(10, 3, 4): |
6222 | case IP_VERSION(10, 3, 5): |
6223 | case IP_VERSION(10, 3, 6): |
6224 | case IP_VERSION(10, 3, 3): |
6225 | case IP_VERSION(10, 3, 7): |
6226 | WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, |
6227 | (CP_MEC_CNTL__MEC_ME1_HALT_MASK | |
6228 | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); |
6229 | break; |
6230 | default: |
6231 | WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, |
6232 | (CP_MEC_CNTL__MEC_ME1_HALT_MASK | |
6233 | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); |
6234 | break; |
6235 | } |
6236 | adev->gfx.kiq[0].ring.sched.ready = false; |
6237 | } |
6238 | udelay(50); |
6239 | } |
6240 | |
6241 | static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev) |
6242 | { |
6243 | const struct gfx_firmware_header_v1_0 *mec_hdr; |
6244 | const __le32 *fw_data; |
6245 | unsigned int i; |
6246 | u32 tmp; |
6247 | u32 usec_timeout = 50000; /* Wait for 50 ms */ |
6248 | |
6249 | if (!adev->gfx.mec_fw) |
6250 | return -EINVAL; |
6251 | |
6252 | gfx_v10_0_cp_compute_enable(adev, enable: false); |
6253 | |
6254 | mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; |
6255 | amdgpu_ucode_print_gfx_hdr(hdr: &mec_hdr->header); |
6256 | |
6257 | fw_data = (const __le32 *) |
6258 | (adev->gfx.mec_fw->data + |
6259 | le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); |
6260 | |
6261 | /* Trigger an invalidation of the L1 instruction caches */ |
6262 | tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); |
6263 | tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); |
6264 | WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); |
6265 | |
6266 | /* Wait for invalidation complete */ |
6267 | for (i = 0; i < usec_timeout; i++) { |
6268 | tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); |
6269 | if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, |
6270 | INVALIDATE_CACHE_COMPLETE)) |
6271 | break; |
6272 | udelay(1); |
6273 | } |
6274 | |
6275 | if (i >= usec_timeout) { |
6276 | dev_err(adev->dev, "failed to invalidate instruction cache\n" ); |
6277 | return -EINVAL; |
6278 | } |
6279 | |
6280 | if (amdgpu_emu_mode == 1) |
6281 | adev->hdp.funcs->flush_hdp(adev, NULL); |
6282 | |
6283 | tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL); |
6284 | tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); |
6285 | tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); |
6286 | tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1); |
6287 | WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp); |
6288 | |
6289 | WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr & |
6290 | 0xFFFFF000); |
6291 | WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, |
6292 | upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); |
6293 | |
6294 | /* MEC1 */ |
6295 | WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0); |
6296 | |
6297 | for (i = 0; i < mec_hdr->jt_size; i++) |
6298 | WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA, |
6299 | le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); |
6300 | |
6301 | WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); |
6302 | |
6303 | /* |
6304 | * TODO: Loading MEC2 firmware is only necessary if MEC2 should run |
6305 | * different microcode than MEC1. |
6306 | */ |
6307 | |
6308 | return 0; |
6309 | } |
6310 | |
6311 | static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring) |
6312 | { |
6313 | uint32_t tmp; |
6314 | struct amdgpu_device *adev = ring->adev; |
6315 | |
6316 | /* tell RLC which is KIQ queue */ |
6317 | switch (amdgpu_ip_version(adev, ip: GC_HWIP, inst: 0)) { |
6318 | case IP_VERSION(10, 3, 0): |
6319 | case IP_VERSION(10, 3, 2): |
6320 | case IP_VERSION(10, 3, 1): |
6321 | case IP_VERSION(10, 3, 4): |
6322 | case IP_VERSION(10, 3, 5): |
6323 | case IP_VERSION(10, 3, 6): |
6324 | case IP_VERSION(10, 3, 3): |
6325 | case IP_VERSION(10, 3, 7): |
6326 | tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid); |
6327 | tmp &= 0xffffff00; |
6328 | tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); |
6329 | WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); |
6330 | tmp |= 0x80; |
6331 | WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); |
6332 | break; |
6333 | default: |
6334 | tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); |
6335 | tmp &= 0xffffff00; |
6336 | tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); |
6337 | WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); |
6338 | tmp |= 0x80; |
6339 | WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); |
6340 | break; |
6341 | } |
6342 | } |
6343 | |
6344 | static void gfx_v10_0_gfx_mqd_set_priority(struct amdgpu_device *adev, |
6345 | struct v10_gfx_mqd *mqd, |
6346 | struct amdgpu_mqd_prop *prop) |
6347 | { |
6348 | bool priority = 0; |
6349 | u32 tmp; |
6350 | |
6351 | /* set up default queue priority level |
6352 | * 0x0 = low priority, 0x1 = high priority |
6353 | */ |
6354 | if (prop->hqd_pipe_priority == AMDGPU_GFX_PIPE_PRIO_HIGH) |
6355 | priority = 1; |
6356 | |
6357 | tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY); |
6358 | tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, priority); |
6359 | mqd->cp_gfx_hqd_queue_priority = tmp; |
6360 | } |
6361 | |
6362 | static int gfx_v10_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, |
6363 | struct amdgpu_mqd_prop *prop) |
6364 | { |
6365 | struct v10_gfx_mqd *mqd = m; |
6366 | uint64_t hqd_gpu_addr, wb_gpu_addr; |
6367 | uint32_t tmp; |
6368 | uint32_t rb_bufsz; |
6369 | |
6370 | /* set up gfx hqd wptr */ |
6371 | mqd->cp_gfx_hqd_wptr = 0; |
6372 | mqd->cp_gfx_hqd_wptr_hi = 0; |
6373 | |
6374 | /* set the pointer to the MQD */ |
6375 | mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc; |
6376 | mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); |
6377 | |
6378 | /* set up mqd control */ |
6379 | tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL); |
6380 | tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); |
6381 | tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); |
6382 | tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); |
6383 | mqd->cp_gfx_mqd_control = tmp; |
6384 | |
6385 | /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ |
6386 | tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID); |
6387 | tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); |
6388 | mqd->cp_gfx_hqd_vmid = 0; |
6389 | |
6390 | /* set up gfx queue priority */ |
6391 | gfx_v10_0_gfx_mqd_set_priority(adev, mqd, prop); |
6392 | |
6393 | /* set up time quantum */ |
6394 | tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM); |
6395 | tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); |
6396 | mqd->cp_gfx_hqd_quantum = tmp; |
6397 | |
6398 | /* set up gfx hqd base. this is similar as CP_RB_BASE */ |
6399 | hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; |
6400 | mqd->cp_gfx_hqd_base = hqd_gpu_addr; |
6401 | mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); |
6402 | |
6403 | /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ |
6404 | wb_gpu_addr = prop->rptr_gpu_addr; |
6405 | mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; |
6406 | mqd->cp_gfx_hqd_rptr_addr_hi = |
6407 | upper_32_bits(wb_gpu_addr) & 0xffff; |
6408 | |
6409 | /* set up rb_wptr_poll addr */ |
6410 | wb_gpu_addr = prop->wptr_gpu_addr; |
6411 | mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; |
6412 | mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; |
6413 | |
6414 | /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ |
6415 | rb_bufsz = order_base_2(prop->queue_size / 4) - 1; |
6416 | tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL); |
6417 | tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); |
6418 | tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); |
6419 | #ifdef __BIG_ENDIAN |
6420 | tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); |
6421 | #endif |
6422 | mqd->cp_gfx_hqd_cntl = tmp; |
6423 | |
6424 | /* set up cp_doorbell_control */ |
6425 | tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); |
6426 | if (prop->use_doorbell) { |
6427 | tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, |
6428 | DOORBELL_OFFSET, prop->doorbell_index); |
6429 | tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, |
6430 | DOORBELL_EN, 1); |
6431 | } else |
6432 | tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, |
6433 | DOORBELL_EN, 0); |
6434 | mqd->cp_rb_doorbell_control = tmp; |
6435 | |
6436 | /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ |
6437 | mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR); |
6438 | |
6439 | /* active the queue */ |
6440 | mqd->cp_gfx_hqd_active = 1; |
6441 | |
6442 | return 0; |
6443 | } |
6444 | |
6445 | static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring) |
6446 | { |
6447 | struct amdgpu_device *adev = ring->adev; |
6448 | struct v10_gfx_mqd *mqd = ring->mqd_ptr; |
6449 | int mqd_idx = ring - &adev->gfx.gfx_ring[0]; |
6450 | |
6451 | if (!amdgpu_in_reset(adev) && !adev->in_suspend) { |
6452 | memset((void *)mqd, 0, sizeof(*mqd)); |
6453 | mutex_lock(&adev->srbm_mutex); |
6454 | nv_grbm_select(adev, me: ring->me, pipe: ring->pipe, queue: ring->queue, vmid: 0); |
6455 | amdgpu_ring_init_mqd(ring); |
6456 | |
6457 | /* |
6458 | * if there are 2 gfx rings, set the lower doorbell |
6459 | * range of the first ring, otherwise the range of |
6460 | * the second ring will override the first ring |
6461 | */ |
6462 | if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1) |
6463 | gfx_v10_0_cp_gfx_set_doorbell(adev, ring); |
6464 | |
6465 | nv_grbm_select(adev, me: 0, pipe: 0, queue: 0, vmid: 0); |
6466 | mutex_unlock(lock: &adev->srbm_mutex); |
6467 | if (adev->gfx.me.mqd_backup[mqd_idx]) |
6468 | memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); |
6469 | } else { |
6470 | mutex_lock(&adev->srbm_mutex); |
6471 | nv_grbm_select(adev, me: ring->me, pipe: ring->pipe, queue: ring->queue, vmid: 0); |
6472 | if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1) |
6473 | gfx_v10_0_cp_gfx_set_doorbell(adev, ring); |
6474 | |
6475 | nv_grbm_select(adev, me: 0, pipe: 0, queue: 0, vmid: 0); |
6476 | mutex_unlock(lock: &adev->srbm_mutex); |
6477 | /* restore mqd with the backup copy */ |
6478 | if (adev->gfx.me.mqd_backup[mqd_idx]) |
6479 | memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); |
6480 | /* reset the ring */ |
6481 | ring->wptr = 0; |
6482 | *ring->wptr_cpu_addr = 0; |
6483 | amdgpu_ring_clear_ring(ring); |
6484 | } |
6485 | |
6486 | return 0; |
6487 | } |
6488 | |
6489 | static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) |
6490 | { |
6491 | int r, i; |
6492 | struct amdgpu_ring *ring; |
6493 | |
6494 | for (i = 0; i < adev->gfx.num_gfx_rings; i++) { |
6495 | ring = &adev->gfx.gfx_ring[i]; |
6496 | |
6497 | r = amdgpu_bo_reserve(bo: ring->mqd_obj, no_intr: false); |
6498 | if (unlikely(r != 0)) |
6499 | return r; |
6500 | |
6501 | r = amdgpu_bo_kmap(bo: ring->mqd_obj, ptr: (void **)&ring->mqd_ptr); |
6502 | if (!r) { |
6503 | r = gfx_v10_0_gfx_init_queue(ring); |
6504 | amdgpu_bo_kunmap(bo: ring->mqd_obj); |
6505 | ring->mqd_ptr = NULL; |
6506 | } |
6507 | amdgpu_bo_unreserve(bo: ring->mqd_obj); |
6508 | if (r) |
6509 | return r; |
6510 | } |
6511 | |
6512 | r = amdgpu_gfx_enable_kgq(adev, xcc_id: 0); |
6513 | if (r) |
6514 | return r; |
6515 | |
6516 | return gfx_v10_0_cp_gfx_start(adev); |
6517 | } |
6518 | |
6519 | static int gfx_v10_0_compute_mqd_init(struct amdgpu_device *adev, void *m, |
6520 | struct amdgpu_mqd_prop *prop) |
6521 | { |
6522 | struct v10_compute_mqd *mqd = m; |
6523 | uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; |
6524 | uint32_t tmp; |
6525 | |
6526 | mqd->header = 0xC0310800; |
6527 | mqd->compute_pipelinestat_enable = 0x00000001; |
6528 | mqd->compute_static_thread_mgmt_se0 = 0xffffffff; |
6529 | mqd->compute_static_thread_mgmt_se1 = 0xffffffff; |
6530 | mqd->compute_static_thread_mgmt_se2 = 0xffffffff; |
6531 | mqd->compute_static_thread_mgmt_se3 = 0xffffffff; |
6532 | mqd->compute_misc_reserved = 0x00000003; |
6533 | |
6534 | eop_base_addr = prop->eop_gpu_addr >> 8; |
6535 | mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; |
6536 | mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); |
6537 | |
6538 | /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ |
6539 | tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); |
6540 | tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, |
6541 | (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1)); |
6542 | |
6543 | mqd->cp_hqd_eop_control = tmp; |
6544 | |
6545 | /* enable doorbell? */ |
6546 | tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); |
6547 | |
6548 | if (prop->use_doorbell) { |
6549 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, |
6550 | DOORBELL_OFFSET, prop->doorbell_index); |
6551 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, |
6552 | DOORBELL_EN, 1); |
6553 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, |
6554 | DOORBELL_SOURCE, 0); |
6555 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, |
6556 | DOORBELL_HIT, 0); |
6557 | } else { |
6558 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, |
6559 | DOORBELL_EN, 0); |
6560 | } |
6561 | |
6562 | mqd->cp_hqd_pq_doorbell_control = tmp; |
6563 | |
6564 | /* disable the queue if it's active */ |
6565 | mqd->cp_hqd_dequeue_request = 0; |
6566 | mqd->cp_hqd_pq_rptr = 0; |
6567 | mqd->cp_hqd_pq_wptr_lo = 0; |
6568 | mqd->cp_hqd_pq_wptr_hi = 0; |
6569 | |
6570 | /* set the pointer to the MQD */ |
6571 | mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; |
6572 | mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); |
6573 | |
6574 | /* set MQD vmid to 0 */ |
6575 | tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); |
6576 | tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); |
6577 | mqd->cp_mqd_control = tmp; |
6578 | |
6579 | /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ |
6580 | hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; |
6581 | mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; |
6582 | mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); |
6583 | |
6584 | /* set up the HQD, this is similar to CP_RB0_CNTL */ |
6585 | tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); |
6586 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, |
6587 | (order_base_2(prop->queue_size / 4) - 1)); |
6588 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, |
6589 | (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); |
6590 | #ifdef __BIG_ENDIAN |
6591 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); |
6592 | #endif |
6593 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); |
6594 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, |
6595 | prop->allow_tunneling); |
6596 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); |
6597 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); |
6598 | mqd->cp_hqd_pq_control = tmp; |
6599 | |
6600 | /* set the wb address whether it's enabled or not */ |
6601 | wb_gpu_addr = prop->rptr_gpu_addr; |
6602 | mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; |
6603 | mqd->cp_hqd_pq_rptr_report_addr_hi = |
6604 | upper_32_bits(wb_gpu_addr) & 0xffff; |
6605 | |
6606 | /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ |
6607 | wb_gpu_addr = prop->wptr_gpu_addr; |
6608 | mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; |
6609 | mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; |
6610 | |
6611 | /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ |
6612 | mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); |
6613 | |
6614 | /* set the vmid for the queue */ |
6615 | mqd->cp_hqd_vmid = 0; |
6616 | |
6617 | tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE); |
6618 | tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); |
6619 | mqd->cp_hqd_persistent_state = tmp; |
6620 | |
6621 | /* set MIN_IB_AVAIL_SIZE */ |
6622 | tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); |
6623 | tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); |
6624 | mqd->cp_hqd_ib_control = tmp; |
6625 | |
6626 | /* set static priority for a compute queue/ring */ |
6627 | mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; |
6628 | mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; |
6629 | |
6630 | mqd->cp_hqd_active = prop->hqd_active; |
6631 | |
6632 | return 0; |
6633 | } |
6634 | |
6635 | static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring) |
6636 | { |
6637 | struct amdgpu_device *adev = ring->adev; |
6638 | struct v10_compute_mqd *mqd = ring->mqd_ptr; |
6639 | int j; |
6640 | |
6641 | /* inactivate the queue */ |
6642 | if (amdgpu_sriov_vf(adev)) |
6643 | WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0); |
6644 | |
6645 | /* disable wptr polling */ |
6646 | WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); |
6647 | |
6648 | /* disable the queue if it's active */ |
6649 | if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { |
6650 | WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); |
6651 | for (j = 0; j < adev->usec_timeout; j++) { |
6652 | if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) |
6653 | break; |
6654 | udelay(1); |
6655 | } |
6656 | WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, |
6657 | mqd->cp_hqd_dequeue_request); |
6658 | WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, |
6659 | mqd->cp_hqd_pq_rptr); |
6660 | WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, |
6661 | mqd->cp_hqd_pq_wptr_lo); |
6662 | WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, |
6663 | mqd->cp_hqd_pq_wptr_hi); |
6664 | } |
6665 | |
6666 | /* disable doorbells */ |
6667 | WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0); |
6668 | |
6669 | /* write the EOP addr */ |
6670 | WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR, |
6671 | mqd->cp_hqd_eop_base_addr_lo); |
6672 | WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, |
6673 | mqd->cp_hqd_eop_base_addr_hi); |
6674 | |
6675 | /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ |
6676 | WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL, |
6677 | mqd->cp_hqd_eop_control); |
6678 | |
6679 | /* set the pointer to the MQD */ |
6680 | WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, |
6681 | mqd->cp_mqd_base_addr_lo); |
6682 | WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, |
6683 | mqd->cp_mqd_base_addr_hi); |
6684 | |
6685 | /* set MQD vmid to 0 */ |
6686 | WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL, |
6687 | mqd->cp_mqd_control); |
6688 | |
6689 | /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ |
6690 | WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE, |
6691 | mqd->cp_hqd_pq_base_lo); |
6692 | WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, |
6693 | mqd->cp_hqd_pq_base_hi); |
6694 | |
6695 | /* set up the HQD, this is similar to CP_RB0_CNTL */ |
6696 | WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, |
6697 | mqd->cp_hqd_pq_control); |
6698 | |
6699 | /* set the wb address whether it's enabled or not */ |
6700 | WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, |
6701 | mqd->cp_hqd_pq_rptr_report_addr_lo); |
6702 | WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, |
6703 | mqd->cp_hqd_pq_rptr_report_addr_hi); |
6704 | |
6705 | /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ |
6706 | WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, |
6707 | mqd->cp_hqd_pq_wptr_poll_addr_lo); |
6708 | WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, |
6709 | mqd->cp_hqd_pq_wptr_poll_addr_hi); |
6710 | |
6711 | /* enable the doorbell if requested */ |
6712 | if (ring->use_doorbell) { |
6713 | WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, |
6714 | (adev->doorbell_index.kiq * 2) << 2); |
6715 | WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, |
6716 | (adev->doorbell_index.userqueue_end * 2) << 2); |
6717 | } |
6718 | |
6719 | WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, |
6720 | mqd->cp_hqd_pq_doorbell_control); |
6721 | |
6722 | /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ |
6723 | WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, |
6724 | mqd->cp_hqd_pq_wptr_lo); |
6725 | WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, |
6726 | mqd->cp_hqd_pq_wptr_hi); |
6727 | |
6728 | /* set the vmid for the queue */ |
6729 | WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid); |
6730 | |
6731 | WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, |
6732 | mqd->cp_hqd_persistent_state); |
6733 | |
6734 | /* activate the queue */ |
6735 | WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, |
6736 | mqd->cp_hqd_active); |
6737 | |
6738 | if (ring->use_doorbell) |
6739 | WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); |
6740 | |
6741 | return 0; |
6742 | } |
6743 | |
6744 | static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring) |
6745 | { |
6746 | struct amdgpu_device *adev = ring->adev; |
6747 | struct v10_compute_mqd *mqd = ring->mqd_ptr; |
6748 | |
6749 | gfx_v10_0_kiq_setting(ring); |
6750 | |
6751 | if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ |
6752 | /* reset MQD to a clean status */ |
6753 | if (adev->gfx.kiq[0].mqd_backup) |
6754 | memcpy_toio(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(*mqd)); |
6755 | |
6756 | /* reset ring buffer */ |
6757 | ring->wptr = 0; |
6758 | amdgpu_ring_clear_ring(ring); |
6759 | |
6760 | mutex_lock(&adev->srbm_mutex); |
6761 | nv_grbm_select(adev, me: ring->me, pipe: ring->pipe, queue: ring->queue, vmid: 0); |
6762 | gfx_v10_0_kiq_init_register(ring); |
6763 | nv_grbm_select(adev, me: 0, pipe: 0, queue: 0, vmid: 0); |
6764 | mutex_unlock(lock: &adev->srbm_mutex); |
6765 | } else { |
6766 | memset((void *)mqd, 0, sizeof(*mqd)); |
6767 | if (amdgpu_sriov_vf(adev) && adev->in_suspend) |
6768 | amdgpu_ring_clear_ring(ring); |
6769 | mutex_lock(&adev->srbm_mutex); |
6770 | nv_grbm_select(adev, me: ring->me, pipe: ring->pipe, queue: ring->queue, vmid: 0); |
6771 | amdgpu_ring_init_mqd(ring); |
6772 | gfx_v10_0_kiq_init_register(ring); |
6773 | nv_grbm_select(adev, me: 0, pipe: 0, queue: 0, vmid: 0); |
6774 | mutex_unlock(lock: &adev->srbm_mutex); |
6775 | |
6776 | if (adev->gfx.kiq[0].mqd_backup) |
6777 | memcpy_fromio(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(*mqd)); |
6778 | } |
6779 | |
6780 | return 0; |
6781 | } |
6782 | |
6783 | static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring) |
6784 | { |
6785 | struct amdgpu_device *adev = ring->adev; |
6786 | struct v10_compute_mqd *mqd = ring->mqd_ptr; |
6787 | int mqd_idx = ring - &adev->gfx.compute_ring[0]; |
6788 | |
6789 | if (!amdgpu_in_reset(adev) && !adev->in_suspend) { |
6790 | memset((void *)mqd, 0, sizeof(*mqd)); |
6791 | mutex_lock(&adev->srbm_mutex); |
6792 | nv_grbm_select(adev, me: ring->me, pipe: ring->pipe, queue: ring->queue, vmid: 0); |
6793 | amdgpu_ring_init_mqd(ring); |
6794 | nv_grbm_select(adev, me: 0, pipe: 0, queue: 0, vmid: 0); |
6795 | mutex_unlock(lock: &adev->srbm_mutex); |
6796 | |
6797 | if (adev->gfx.mec.mqd_backup[mqd_idx]) |
6798 | memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); |
6799 | } else { |
6800 | /* restore MQD to a clean status */ |
6801 | if (adev->gfx.mec.mqd_backup[mqd_idx]) |
6802 | memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); |
6803 | /* reset ring buffer */ |
6804 | ring->wptr = 0; |
6805 | atomic64_set(v: (atomic64_t *)ring->wptr_cpu_addr, i: 0); |
6806 | amdgpu_ring_clear_ring(ring); |
6807 | } |
6808 | |
6809 | return 0; |
6810 | } |
6811 | |
6812 | static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev) |
6813 | { |
6814 | struct amdgpu_ring *ring; |
6815 | int r; |
6816 | |
6817 | ring = &adev->gfx.kiq[0].ring; |
6818 | |
6819 | r = amdgpu_bo_reserve(bo: ring->mqd_obj, no_intr: false); |
6820 | if (unlikely(r != 0)) |
6821 | return r; |
6822 | |
6823 | r = amdgpu_bo_kmap(bo: ring->mqd_obj, ptr: (void **)&ring->mqd_ptr); |
6824 | if (unlikely(r != 0)) { |
6825 | amdgpu_bo_unreserve(bo: ring->mqd_obj); |
6826 | return r; |
6827 | } |
6828 | |
6829 | gfx_v10_0_kiq_init_queue(ring); |
6830 | amdgpu_bo_kunmap(bo: ring->mqd_obj); |
6831 | ring->mqd_ptr = NULL; |
6832 | amdgpu_bo_unreserve(bo: ring->mqd_obj); |
6833 | return 0; |
6834 | } |
6835 | |
6836 | static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev) |
6837 | { |
6838 | struct amdgpu_ring *ring = NULL; |
6839 | int r = 0, i; |
6840 | |
6841 | gfx_v10_0_cp_compute_enable(adev, enable: true); |
6842 | |
6843 | for (i = 0; i < adev->gfx.num_compute_rings; i++) { |
6844 | ring = &adev->gfx.compute_ring[i]; |
6845 | |
6846 | r = amdgpu_bo_reserve(bo: ring->mqd_obj, no_intr: false); |
6847 | if (unlikely(r != 0)) |
6848 | goto done; |
6849 | r = amdgpu_bo_kmap(bo: ring->mqd_obj, ptr: (void **)&ring->mqd_ptr); |
6850 | if (!r) { |
6851 | r = gfx_v10_0_kcq_init_queue(ring); |
6852 | amdgpu_bo_kunmap(bo: ring->mqd_obj); |
6853 | ring->mqd_ptr = NULL; |
6854 | } |
6855 | amdgpu_bo_unreserve(bo: ring->mqd_obj); |
6856 | if (r) |
6857 | goto done; |
6858 | } |
6859 | |
6860 | r = amdgpu_gfx_enable_kcq(adev, xcc_id: 0); |
6861 | done: |
6862 | return r; |
6863 | } |
6864 | |
6865 | static int gfx_v10_0_cp_resume(struct amdgpu_device *adev) |
6866 | { |
6867 | int r, i; |
6868 | struct amdgpu_ring *ring; |
6869 | |
6870 | if (!(adev->flags & AMD_IS_APU)) |
6871 | gfx_v10_0_enable_gui_idle_interrupt(adev, enable: false); |
6872 | |
6873 | if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { |
6874 | /* legacy firmware loading */ |
6875 | r = gfx_v10_0_cp_gfx_load_microcode(adev); |
6876 | if (r) |
6877 | return r; |
6878 | |
6879 | r = gfx_v10_0_cp_compute_load_microcode(adev); |
6880 | if (r) |
6881 | return r; |
6882 | } |
6883 | |
6884 | if (adev->enable_mes_kiq && adev->mes.kiq_hw_init) |
6885 | r = amdgpu_mes_kiq_hw_init(adev); |
6886 | else |
6887 | r = gfx_v10_0_kiq_resume(adev); |
6888 | if (r) |
6889 | return r; |
6890 | |
6891 | r = gfx_v10_0_kcq_resume(adev); |
6892 | if (r) |
6893 | return r; |
6894 | |
6895 | if (!amdgpu_async_gfx_ring) { |
6896 | r = gfx_v10_0_cp_gfx_resume(adev); |
6897 | if (r) |
6898 | return r; |
6899 | } else { |
6900 | r = gfx_v10_0_cp_async_gfx_ring_resume(adev); |
6901 | if (r) |
6902 | return r; |
6903 | } |
6904 | |
6905 | for (i = 0; i < adev->gfx.num_gfx_rings; i++) { |
6906 | ring = &adev->gfx.gfx_ring[i]; |
6907 | r = amdgpu_ring_test_helper(ring); |
6908 | if (r) |
6909 | return r; |
6910 | } |
6911 | |
6912 | for (i = 0; i < adev->gfx.num_compute_rings; i++) { |
6913 | ring = &adev->gfx.compute_ring[i]; |
6914 | r = amdgpu_ring_test_helper(ring); |
6915 | if (r) |
6916 | return r; |
6917 | } |
6918 | |
6919 | return 0; |
6920 | } |
6921 | |
6922 | static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable) |
6923 | { |
6924 | gfx_v10_0_cp_gfx_enable(adev, enable); |
6925 | gfx_v10_0_cp_compute_enable(adev, enable); |
6926 | } |
6927 | |
6928 | static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev) |
6929 | { |
6930 | uint32_t data, pattern = 0xDEADBEEF; |
6931 | |
6932 | /* |
6933 | * check if mmVGT_ESGS_RING_SIZE_UMD |
6934 | * has been remapped to mmVGT_ESGS_RING_SIZE |
6935 | */ |
6936 | switch (amdgpu_ip_version(adev, ip: GC_HWIP, inst: 0)) { |
6937 | case IP_VERSION(10, 3, 0): |
6938 | case IP_VERSION(10, 3, 2): |
6939 | case IP_VERSION(10, 3, 4): |
6940 | case IP_VERSION(10, 3, 5): |
6941 | data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid); |
6942 | WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0); |
6943 | WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); |
6944 | |
6945 | if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) { |
6946 | WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data); |
6947 | return true; |
6948 | } |
6949 | WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data); |
6950 | break; |
6951 | case IP_VERSION(10, 3, 1): |
6952 | case IP_VERSION(10, 3, 3): |
6953 | case IP_VERSION(10, 3, 6): |
6954 | case IP_VERSION(10, 3, 7): |
6955 | return true; |
6956 | default: |
6957 | data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE); |
6958 | WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0); |
6959 | WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); |
6960 | |
6961 | if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) { |
6962 | WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data); |
6963 | return true; |
6964 | } |
6965 | WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data); |
6966 | break; |
6967 | } |
6968 | |
6969 | return false; |
6970 | } |
6971 | |
6972 | static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev) |
6973 | { |
6974 | uint32_t data; |
6975 | |
6976 | if (amdgpu_sriov_vf(adev)) |
6977 | return; |
6978 | |
6979 | /* |
6980 | * Initialize cam_index to 0 |
6981 | * index will auto-inc after each data writing |
6982 | */ |
6983 | WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0); |
6984 | |
6985 | switch (amdgpu_ip_version(adev, ip: GC_HWIP, inst: 0)) { |
6986 | case IP_VERSION(10, 3, 0): |
6987 | case IP_VERSION(10, 3, 2): |
6988 | case IP_VERSION(10, 3, 1): |
6989 | case IP_VERSION(10, 3, 4): |
6990 | case IP_VERSION(10, 3, 5): |
6991 | case IP_VERSION(10, 3, 6): |
6992 | case IP_VERSION(10, 3, 3): |
6993 | case IP_VERSION(10, 3, 7): |
6994 | /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ |
6995 | data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << |
6996 | GRBM_CAM_DATA__CAM_ADDR__SHIFT) | |
6997 | (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) << |
6998 | GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); |
6999 | WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); |
7000 | WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); |
7001 | |
7002 | /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ |
7003 | data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << |
7004 | GRBM_CAM_DATA__CAM_ADDR__SHIFT) | |
7005 | (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) << |
7006 | GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); |
7007 | WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); |
7008 | WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); |
7009 | |
7010 | /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ |
7011 | data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << |
7012 | GRBM_CAM_DATA__CAM_ADDR__SHIFT) | |
7013 | (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) << |
7014 | GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); |
7015 | WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); |
7016 | WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); |
7017 | |
7018 | /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ |
7019 | data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << |
7020 | GRBM_CAM_DATA__CAM_ADDR__SHIFT) | |
7021 | (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) << |
7022 | GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); |
7023 | WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); |
7024 | WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); |
7025 | |
7026 | /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ |
7027 | data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << |
7028 | GRBM_CAM_DATA__CAM_ADDR__SHIFT) | |
7029 | (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) << |
7030 | GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); |
7031 | WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); |
7032 | WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); |
7033 | |
7034 | /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ |
7035 | data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << |
7036 | GRBM_CAM_DATA__CAM_ADDR__SHIFT) | |
7037 | (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) << |
7038 | GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); |
7039 | WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); |
7040 | WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); |
7041 | |
7042 | /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ |
7043 | data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << |
7044 | GRBM_CAM_DATA__CAM_ADDR__SHIFT) | |
7045 | (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) << |
7046 | GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); |
7047 | break; |
7048 | default: |
7049 | /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ |
7050 | data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << |
7051 | GRBM_CAM_DATA__CAM_ADDR__SHIFT) | |
7052 | (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) << |
7053 | GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); |
7054 | WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); |
7055 | WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); |
7056 | |
7057 | /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ |
7058 | data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << |
7059 | GRBM_CAM_DATA__CAM_ADDR__SHIFT) | |
7060 | (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) << |
7061 | GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); |
7062 | WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); |
7063 | WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); |
7064 | |
7065 | /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ |
7066 | data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << |
7067 | GRBM_CAM_DATA__CAM_ADDR__SHIFT) | |
7068 | (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) << |
7069 | GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); |
7070 | WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); |
7071 | WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); |
7072 | |
7073 | /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ |
7074 | data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << |
7075 | GRBM_CAM_DATA__CAM_ADDR__SHIFT) | |
7076 | (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) << |
7077 | GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); |
7078 | WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); |
7079 | WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); |
7080 | |
7081 | /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ |
7082 | data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << |
7083 | GRBM_CAM_DATA__CAM_ADDR__SHIFT) | |
7084 | (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) << |
7085 | GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); |
7086 | WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); |
7087 | WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); |
7088 | |
7089 | /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ |
7090 | data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << |
7091 | GRBM_CAM_DATA__CAM_ADDR__SHIFT) | |
7092 | (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) << |
7093 | GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); |
7094 | WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); |
7095 | WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); |
7096 | |
7097 | /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ |
7098 | data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << |
7099 | GRBM_CAM_DATA__CAM_ADDR__SHIFT) | |
7100 | (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) << |
7101 | GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); |
7102 | break; |
7103 | } |
7104 | |
7105 | WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); |
7106 | WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); |
7107 | } |
7108 | |
7109 | static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev) |
7110 | { |
7111 | uint32_t data; |
7112 | |
7113 | data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG); |
7114 | data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; |
7115 | WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data); |
7116 | |
7117 | data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG); |
7118 | data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; |
7119 | WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data); |
7120 | } |
7121 | |
7122 | static int gfx_v10_0_hw_init(void *handle) |
7123 | { |
7124 | int r; |
7125 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
7126 | |
7127 | if (!amdgpu_emu_mode) |
7128 | gfx_v10_0_init_golden_registers(adev); |
7129 | |
7130 | if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { |
7131 | /** |
7132 | * For gfx 10, rlc firmware loading relies on smu firmware is |
7133 | * loaded firstly, so in direct type, it has to load smc ucode |
7134 | * here before rlc. |
7135 | */ |
7136 | if (!(adev->flags & AMD_IS_APU)) { |
7137 | r = amdgpu_pm_load_smu_firmware(adev, NULL); |
7138 | if (r) |
7139 | return r; |
7140 | } |
7141 | gfx_v10_0_disable_gpa_mode(adev); |
7142 | } |
7143 | |
7144 | /* if GRBM CAM not remapped, set up the remapping */ |
7145 | if (!gfx_v10_0_check_grbm_cam_remapping(adev)) |
7146 | gfx_v10_0_setup_grbm_cam_remapping(adev); |
7147 | |
7148 | gfx_v10_0_constants_init(adev); |
7149 | |
7150 | r = gfx_v10_0_rlc_resume(adev); |
7151 | if (r) |
7152 | return r; |
7153 | |
7154 | /* |
7155 | * init golden registers and rlc resume may override some registers, |
7156 | * reconfig them here |
7157 | */ |
7158 | if (amdgpu_ip_version(adev, ip: GC_HWIP, inst: 0) == IP_VERSION(10, 1, 10) || |
7159 | amdgpu_ip_version(adev, ip: GC_HWIP, inst: 0) == IP_VERSION(10, 1, 1) || |
7160 | amdgpu_ip_version(adev, ip: GC_HWIP, inst: 0) == IP_VERSION(10, 1, 2)) |
7161 | gfx_v10_0_tcp_harvest(adev); |
7162 | |
7163 | r = gfx_v10_0_cp_resume(adev); |
7164 | if (r) |
7165 | return r; |
7166 | |
7167 | if (amdgpu_ip_version(adev, ip: GC_HWIP, inst: 0) == IP_VERSION(10, 3, 0)) |
7168 | gfx_v10_3_program_pbb_mode(adev); |
7169 | |
7170 | if (amdgpu_ip_version(adev, ip: GC_HWIP, inst: 0) >= IP_VERSION(10, 3, 0) && !amdgpu_sriov_vf(adev)) |
7171 | gfx_v10_3_set_power_brake_sequence(adev); |
7172 | |
7173 | return r; |
7174 | } |
7175 | |
7176 | static int gfx_v10_0_hw_fini(void *handle) |
7177 | { |
7178 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
7179 | |
7180 | amdgpu_irq_put(adev, src: &adev->gfx.priv_reg_irq, type: 0); |
7181 | amdgpu_irq_put(adev, src: &adev->gfx.priv_inst_irq, type: 0); |
7182 | |
7183 | /* WA added for Vangogh asic fixing the SMU suspend failure |
7184 | * It needs to set power gating again during gfxoff control |
7185 | * otherwise the gfxoff disallowing will be failed to set. |
7186 | */ |
7187 | if (amdgpu_ip_version(adev, ip: GC_HWIP, inst: 0) == IP_VERSION(10, 3, 1)) |
7188 | gfx_v10_0_set_powergating_state(handle, state: AMD_PG_STATE_UNGATE); |
7189 | |
7190 | if (!adev->no_hw_access) { |
7191 | if (amdgpu_async_gfx_ring) { |
7192 | if (amdgpu_gfx_disable_kgq(adev, xcc_id: 0)) |
7193 | DRM_ERROR("KGQ disable failed\n" ); |
7194 | } |
7195 | |
7196 | if (amdgpu_gfx_disable_kcq(adev, xcc_id: 0)) |
7197 | DRM_ERROR("KCQ disable failed\n" ); |
7198 | } |
7199 | |
7200 | if (amdgpu_sriov_vf(adev)) { |
7201 | gfx_v10_0_cp_gfx_enable(adev, enable: false); |
7202 | /* Remove the steps of clearing KIQ position. |
7203 | * It causes GFX hang when another Win guest is rendering. |
7204 | */ |
7205 | return 0; |
7206 | } |
7207 | gfx_v10_0_cp_enable(adev, enable: false); |
7208 | gfx_v10_0_enable_gui_idle_interrupt(adev, enable: false); |
7209 | |
7210 | return 0; |
7211 | } |
7212 | |
7213 | static int gfx_v10_0_suspend(void *handle) |
7214 | { |
7215 | return gfx_v10_0_hw_fini(handle); |
7216 | } |
7217 | |
7218 | static int gfx_v10_0_resume(void *handle) |
7219 | { |
7220 | return gfx_v10_0_hw_init(handle); |
7221 | } |
7222 | |
7223 | static bool gfx_v10_0_is_idle(void *handle) |
7224 | { |
7225 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
7226 | |
7227 | if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS), |
7228 | GRBM_STATUS, GUI_ACTIVE)) |
7229 | return false; |
7230 | else |
7231 | return true; |
7232 | } |
7233 | |
7234 | static int gfx_v10_0_wait_for_idle(void *handle) |
7235 | { |
7236 | unsigned int i; |
7237 | u32 tmp; |
7238 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
7239 | |
7240 | for (i = 0; i < adev->usec_timeout; i++) { |
7241 | /* read MC_STATUS */ |
7242 | tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) & |
7243 | GRBM_STATUS__GUI_ACTIVE_MASK; |
7244 | |
7245 | if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) |
7246 | return 0; |
7247 | udelay(1); |
7248 | } |
7249 | return -ETIMEDOUT; |
7250 | } |
7251 | |
7252 | static int gfx_v10_0_soft_reset(void *handle) |
7253 | { |
7254 | u32 grbm_soft_reset = 0; |
7255 | u32 tmp; |
7256 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
7257 | |
7258 | /* GRBM_STATUS */ |
7259 | tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS); |
7260 | if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | |
7261 | GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | |
7262 | GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK | |
7263 | GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK | |
7264 | GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) { |
7265 | grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, |
7266 | GRBM_SOFT_RESET, SOFT_RESET_CP, |
7267 | 1); |
7268 | grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, |
7269 | GRBM_SOFT_RESET, SOFT_RESET_GFX, |
7270 | 1); |
7271 | } |
7272 | |
7273 | if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { |
7274 | grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, |
7275 | GRBM_SOFT_RESET, SOFT_RESET_CP, |
7276 | 1); |
7277 | } |
7278 | |
7279 | /* GRBM_STATUS2 */ |
7280 | tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2); |
7281 | switch (amdgpu_ip_version(adev, ip: GC_HWIP, inst: 0)) { |
7282 | case IP_VERSION(10, 3, 0): |
7283 | case IP_VERSION(10, 3, 2): |
7284 | case IP_VERSION(10, 3, 1): |
7285 | case IP_VERSION(10, 3, 4): |
7286 | case IP_VERSION(10, 3, 5): |
7287 | case IP_VERSION(10, 3, 6): |
7288 | case IP_VERSION(10, 3, 3): |
7289 | if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid)) |
7290 | grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, |
7291 | GRBM_SOFT_RESET, |
7292 | SOFT_RESET_RLC, |
7293 | 1); |
7294 | break; |
7295 | default: |
7296 | if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) |
7297 | grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, |
7298 | GRBM_SOFT_RESET, |
7299 | SOFT_RESET_RLC, |
7300 | 1); |
7301 | break; |
7302 | } |
7303 | |
7304 | if (grbm_soft_reset) { |
7305 | /* stop the rlc */ |
7306 | gfx_v10_0_rlc_stop(adev); |
7307 | |
7308 | /* Disable GFX parsing/prefetching */ |
7309 | gfx_v10_0_cp_gfx_enable(adev, enable: false); |
7310 | |
7311 | /* Disable MEC parsing/prefetching */ |
7312 | gfx_v10_0_cp_compute_enable(adev, enable: false); |
7313 | |
7314 | if (grbm_soft_reset) { |
7315 | tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); |
7316 | tmp |= grbm_soft_reset; |
7317 | dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n" , tmp); |
7318 | WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); |
7319 | tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); |
7320 | |
7321 | udelay(50); |
7322 | |
7323 | tmp &= ~grbm_soft_reset; |
7324 | WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); |
7325 | tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); |
7326 | } |
7327 | |
7328 | /* Wait a little for things to settle down */ |
7329 | udelay(50); |
7330 | } |
7331 | return 0; |
7332 | } |
7333 | |
7334 | static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev) |
7335 | { |
7336 | uint64_t clock, clock_lo, clock_hi, hi_check; |
7337 | |
7338 | switch (amdgpu_ip_version(adev, ip: GC_HWIP, inst: 0)) { |
7339 | case IP_VERSION(10, 1, 3): |
7340 | case IP_VERSION(10, 1, 4): |
7341 | preempt_disable(); |
7342 | clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish); |
7343 | clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish); |
7344 | hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish); |
7345 | /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over |
7346 | * roughly every 42 seconds. |
7347 | */ |
7348 | if (hi_check != clock_hi) { |
7349 | clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish); |
7350 | clock_hi = hi_check; |
7351 | } |
7352 | preempt_enable(); |
7353 | clock = clock_lo | (clock_hi << 32ULL); |
7354 | break; |
7355 | case IP_VERSION(10, 3, 1): |
7356 | case IP_VERSION(10, 3, 3): |
7357 | case IP_VERSION(10, 3, 7): |
7358 | preempt_disable(); |
7359 | clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh); |
7360 | clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh); |
7361 | hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh); |
7362 | /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over |
7363 | * roughly every 42 seconds. |
7364 | */ |
7365 | if (hi_check != clock_hi) { |
7366 | clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh); |
7367 | clock_hi = hi_check; |
7368 | } |
7369 | preempt_enable(); |
7370 | clock = clock_lo | (clock_hi << 32ULL); |
7371 | break; |
7372 | case IP_VERSION(10, 3, 6): |
7373 | preempt_disable(); |
7374 | clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6); |
7375 | clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6); |
7376 | hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6); |
7377 | /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over |
7378 | * roughly every 42 seconds. |
7379 | */ |
7380 | if (hi_check != clock_hi) { |
7381 | clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6); |
7382 | clock_hi = hi_check; |
7383 | } |
7384 | preempt_enable(); |
7385 | clock = clock_lo | (clock_hi << 32ULL); |
7386 | break; |
7387 | default: |
7388 | preempt_disable(); |
7389 | clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER); |
7390 | clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER); |
7391 | hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER); |
7392 | /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over |
7393 | * roughly every 42 seconds. |
7394 | */ |
7395 | if (hi_check != clock_hi) { |
7396 | clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER); |
7397 | clock_hi = hi_check; |
7398 | } |
7399 | preempt_enable(); |
7400 | clock = clock_lo | (clock_hi << 32ULL); |
7401 | break; |
7402 | } |
7403 | return clock; |
7404 | } |
7405 | |
7406 | static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring, |
7407 | uint32_t vmid, |
7408 | uint32_t gds_base, uint32_t gds_size, |
7409 | uint32_t gws_base, uint32_t gws_size, |
7410 | uint32_t oa_base, uint32_t oa_size) |
7411 | { |
7412 | struct amdgpu_device *adev = ring->adev; |
7413 | |
7414 | /* GDS Base */ |
7415 | gfx_v10_0_write_data_to_reg(ring, eng_sel: 0, wc: false, |
7416 | SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid, |
7417 | val: gds_base); |
7418 | |
7419 | /* GDS Size */ |
7420 | gfx_v10_0_write_data_to_reg(ring, eng_sel: 0, wc: false, |
7421 | SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid, |
7422 | val: gds_size); |
7423 | |
7424 | /* GWS */ |
7425 | gfx_v10_0_write_data_to_reg(ring, eng_sel: 0, wc: false, |
7426 | SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid, |
7427 | val: gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); |
7428 | |
7429 | /* OA */ |
7430 | gfx_v10_0_write_data_to_reg(ring, eng_sel: 0, wc: false, |
7431 | SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid, |
7432 | val: (1 << (oa_size + oa_base)) - (1 << oa_base)); |
7433 | } |
7434 | |
7435 | static int gfx_v10_0_early_init(void *handle) |
7436 | { |
7437 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
7438 | |
7439 | adev->gfx.funcs = &gfx_v10_0_gfx_funcs; |
7440 | |
7441 | switch (amdgpu_ip_version(adev, ip: GC_HWIP, inst: 0)) { |
7442 | case IP_VERSION(10, 1, 10): |
7443 | case IP_VERSION(10, 1, 1): |
7444 | case IP_VERSION(10, 1, 2): |
7445 | case IP_VERSION(10, 1, 3): |
7446 | case IP_VERSION(10, 1, 4): |
7447 | adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X; |
7448 | break; |
7449 | case IP_VERSION(10, 3, 0): |
7450 | case IP_VERSION(10, 3, 2): |
7451 | case IP_VERSION(10, 3, 1): |
7452 | case IP_VERSION(10, 3, 4): |
7453 | case IP_VERSION(10, 3, 5): |
7454 | case IP_VERSION(10, 3, 6): |
7455 | case IP_VERSION(10, 3, 3): |
7456 | case IP_VERSION(10, 3, 7): |
7457 | adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid; |
7458 | break; |
7459 | default: |
7460 | break; |
7461 | } |
7462 | |
7463 | adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), |
7464 | AMDGPU_MAX_COMPUTE_RINGS); |
7465 | |
7466 | gfx_v10_0_set_kiq_pm4_funcs(adev); |
7467 | gfx_v10_0_set_ring_funcs(adev); |
7468 | gfx_v10_0_set_irq_funcs(adev); |
7469 | gfx_v10_0_set_gds_init(adev); |
7470 | gfx_v10_0_set_rlc_funcs(adev); |
7471 | gfx_v10_0_set_mqd_funcs(adev); |
7472 | |
7473 | /* init rlcg reg access ctrl */ |
7474 | gfx_v10_0_init_rlcg_reg_access_ctrl(adev); |
7475 | |
7476 | return gfx_v10_0_init_microcode(adev); |
7477 | } |
7478 | |
7479 | static int gfx_v10_0_late_init(void *handle) |
7480 | { |
7481 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
7482 | int r; |
7483 | |
7484 | r = amdgpu_irq_get(adev, src: &adev->gfx.priv_reg_irq, type: 0); |
7485 | if (r) |
7486 | return r; |
7487 | |
7488 | r = amdgpu_irq_get(adev, src: &adev->gfx.priv_inst_irq, type: 0); |
7489 | if (r) |
7490 | return r; |
7491 | |
7492 | return 0; |
7493 | } |
7494 | |
7495 | static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev) |
7496 | { |
7497 | uint32_t rlc_cntl; |
7498 | |
7499 | /* if RLC is not enabled, do nothing */ |
7500 | rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL); |
7501 | return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; |
7502 | } |
7503 | |
7504 | static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id) |
7505 | { |
7506 | uint32_t data; |
7507 | unsigned int i; |
7508 | |
7509 | data = RLC_SAFE_MODE__CMD_MASK; |
7510 | data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); |
7511 | |
7512 | switch (amdgpu_ip_version(adev, ip: GC_HWIP, inst: 0)) { |
7513 | case IP_VERSION(10, 3, 0): |
7514 | case IP_VERSION(10, 3, 2): |
7515 | case IP_VERSION(10, 3, 1): |
7516 | case IP_VERSION(10, 3, 4): |
7517 | case IP_VERSION(10, 3, 5): |
7518 | case IP_VERSION(10, 3, 6): |
7519 | case IP_VERSION(10, 3, 3): |
7520 | case IP_VERSION(10, 3, 7): |
7521 | WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data); |
7522 | |
7523 | /* wait for RLC_SAFE_MODE */ |
7524 | for (i = 0; i < adev->usec_timeout; i++) { |
7525 | if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid), |
7526 | RLC_SAFE_MODE, CMD)) |
7527 | break; |
7528 | udelay(1); |
7529 | } |
7530 | break; |
7531 | default: |
7532 | WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); |
7533 | |
7534 | /* wait for RLC_SAFE_MODE */ |
7535 | for (i = 0; i < adev->usec_timeout; i++) { |
7536 | if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), |
7537 | RLC_SAFE_MODE, CMD)) |
7538 | break; |
7539 | udelay(1); |
7540 | } |
7541 | break; |
7542 | } |
7543 | } |
7544 | |
7545 | static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id) |
7546 | { |
7547 | uint32_t data; |
7548 | |
7549 | data = RLC_SAFE_MODE__CMD_MASK; |
7550 | switch (amdgpu_ip_version(adev, ip: GC_HWIP, inst: 0)) { |
7551 | case IP_VERSION(10, 3, 0): |
7552 | case IP_VERSION(10, 3, 2): |
7553 | case IP_VERSION(10, 3, 1): |
7554 | case IP_VERSION(10, 3, 4): |
7555 | case IP_VERSION(10, 3, 5): |
7556 | case IP_VERSION(10, 3, 6): |
7557 | case IP_VERSION(10, 3, 3): |
7558 | case IP_VERSION(10, 3, 7): |
7559 | WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data); |
7560 | break; |
7561 | default: |
7562 | WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); |
7563 | break; |
7564 | } |
7565 | } |
7566 | |
7567 | static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, |
7568 | bool enable) |
7569 | { |
7570 | uint32_t data, def; |
7571 | |
7572 | if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS))) |
7573 | return; |
7574 | |
7575 | /* It is disabled by HW by default */ |
7576 | if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { |
7577 | /* 0 - Disable some blocks' MGCG */ |
7578 | WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000); |
7579 | WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000); |
7580 | WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000); |
7581 | WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000); |
7582 | |
7583 | /* 1 - RLC_CGTT_MGCG_OVERRIDE */ |
7584 | def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); |
7585 | data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | |
7586 | RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | |
7587 | RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | |
7588 | RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK | |
7589 | RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK | |
7590 | RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK); |
7591 | |
7592 | if (def != data) |
7593 | WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); |
7594 | |
7595 | /* MGLS is a global flag to control all MGLS in GFX */ |
7596 | if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { |
7597 | /* 2 - RLC memory Light sleep */ |
7598 | if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { |
7599 | def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); |
7600 | data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; |
7601 | if (def != data) |
7602 | WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); |
7603 | } |
7604 | /* 3 - CP memory Light sleep */ |
7605 | if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { |
7606 | def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); |
7607 | data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; |
7608 | if (def != data) |
7609 | WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); |
7610 | } |
7611 | } |
7612 | } else if (!enable || !(adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { |
7613 | /* 1 - MGCG_OVERRIDE */ |
7614 | def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); |
7615 | data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | |
7616 | RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | |
7617 | RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | |
7618 | RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK | |
7619 | RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK | |
7620 | RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK); |
7621 | if (def != data) |
7622 | WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); |
7623 | |
7624 | /* 2 - disable MGLS in CP */ |
7625 | data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); |
7626 | if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { |
7627 | data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; |
7628 | WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); |
7629 | } |
7630 | |
7631 | /* 3 - disable MGLS in RLC */ |
7632 | data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); |
7633 | if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { |
7634 | data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; |
7635 | WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); |
7636 | } |
7637 | |
7638 | } |
7639 | } |
7640 | |
7641 | static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev, |
7642 | bool enable) |
7643 | { |
7644 | uint32_t data, def; |
7645 | |
7646 | if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS))) |
7647 | return; |
7648 | |
7649 | /* Enable 3D CGCG/CGLS */ |
7650 | if (enable) { |
7651 | /* write cmd to clear cgcg/cgls ov */ |
7652 | def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); |
7653 | |
7654 | /* unset CGCG override */ |
7655 | if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) |
7656 | data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; |
7657 | |
7658 | /* update CGCG and CGLS override bits */ |
7659 | if (def != data) |
7660 | WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); |
7661 | |
7662 | /* enable 3Dcgcg FSM(0x0000363f) */ |
7663 | def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); |
7664 | data = 0; |
7665 | |
7666 | if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) |
7667 | data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | |
7668 | RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; |
7669 | |
7670 | if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) |
7671 | data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | |
7672 | RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; |
7673 | |
7674 | if (def != data) |
7675 | WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); |
7676 | |
7677 | /* set IDLE_POLL_COUNT(0x00900100) */ |
7678 | def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); |
7679 | data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | |
7680 | (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); |
7681 | if (def != data) |
7682 | WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); |
7683 | } else { |
7684 | /* Disable CGCG/CGLS */ |
7685 | def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); |
7686 | |
7687 | /* disable cgcg, cgls should be disabled */ |
7688 | if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) |
7689 | data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; |
7690 | |
7691 | if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) |
7692 | data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; |
7693 | |
7694 | /* disable cgcg and cgls in FSM */ |
7695 | if (def != data) |
7696 | WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); |
7697 | } |
7698 | } |
7699 | |
7700 | static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, |
7701 | bool enable) |
7702 | { |
7703 | uint32_t def, data; |
7704 | |
7705 | if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS))) |
7706 | return; |
7707 | |
7708 | if (enable) { |
7709 | def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); |
7710 | |
7711 | /* unset CGCG override */ |
7712 | if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) |
7713 | data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; |
7714 | |
7715 | if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) |
7716 | data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; |
7717 | |
7718 | /* update CGCG and CGLS override bits */ |
7719 | if (def != data) |
7720 | WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); |
7721 | |
7722 | /* enable cgcg FSM(0x0000363F) */ |
7723 | def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); |
7724 | data = 0; |
7725 | |
7726 | if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) |
7727 | data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | |
7728 | RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; |
7729 | |
7730 | if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) |
7731 | data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | |
7732 | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; |
7733 | |
7734 | if (def != data) |
7735 | WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); |
7736 | |
7737 | /* set IDLE_POLL_COUNT(0x00900100) */ |
7738 | def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); |
7739 | data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | |
7740 | (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); |
7741 | if (def != data) |
7742 | WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); |
7743 | } else { |
7744 | def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); |
7745 | |
7746 | /* reset CGCG/CGLS bits */ |
7747 | if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) |
7748 | data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; |
7749 | |
7750 | if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) |
7751 | data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; |
7752 | |
7753 | /* disable cgcg and cgls in FSM */ |
7754 | if (def != data) |
7755 | WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); |
7756 | } |
7757 | } |
7758 | |
7759 | static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev, |
7760 | bool enable) |
7761 | { |
7762 | uint32_t def, data; |
7763 | |
7764 | if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) |
7765 | return; |
7766 | |
7767 | if (enable) { |
7768 | def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); |
7769 | /* unset FGCG override */ |
7770 | data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; |
7771 | /* update FGCG override bits */ |
7772 | if (def != data) |
7773 | WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); |
7774 | |
7775 | def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL); |
7776 | /* unset RLC SRAM CLK GATER override */ |
7777 | data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; |
7778 | /* update RLC SRAM CLK GATER override bits */ |
7779 | if (def != data) |
7780 | WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data); |
7781 | } else { |
7782 | def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); |
7783 | /* reset FGCG bits */ |
7784 | data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; |
7785 | /* disable FGCG*/ |
7786 | if (def != data) |
7787 | WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); |
7788 | |
7789 | def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL); |
7790 | /* reset RLC SRAM CLK GATER bits */ |
7791 | data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; |
7792 | /* disable RLC SRAM CLK*/ |
7793 | if (def != data) |
7794 | WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data); |
7795 | } |
7796 | } |
7797 | |
7798 | static void gfx_v10_0_apply_medium_grain_clock_gating_workaround(struct amdgpu_device *adev) |
7799 | { |
7800 | uint32_t reg_data = 0; |
7801 | uint32_t reg_idx = 0; |
7802 | uint32_t i; |
7803 | |
7804 | const uint32_t tcp_ctrl_regs[] = { |
7805 | mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG, |
7806 | mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG, |
7807 | mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG, |
7808 | mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG, |
7809 | mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG, |
7810 | mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG, |
7811 | mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG, |
7812 | mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG, |
7813 | mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG, |
7814 | mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG, |
7815 | mmCGTS_SA0_WGP12_CU0_TCP_CTRL_REG, |
7816 | mmCGTS_SA0_WGP12_CU1_TCP_CTRL_REG, |
7817 | mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG, |
7818 | mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG, |
7819 | mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG, |
7820 | mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG, |
7821 | mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG, |
7822 | mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG, |
7823 | mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG, |
7824 | mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG, |
7825 | mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG, |
7826 | mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG, |
7827 | mmCGTS_SA1_WGP12_CU0_TCP_CTRL_REG, |
7828 | mmCGTS_SA1_WGP12_CU1_TCP_CTRL_REG |
7829 | }; |
7830 | |
7831 | const uint32_t tcp_ctrl_regs_nv12[] = { |
7832 | mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG, |
7833 | mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG, |
7834 | mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG, |
7835 | mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG, |
7836 | mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG, |
7837 | mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG, |
7838 | mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG, |
7839 | mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG, |
7840 | mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG, |
7841 | mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG, |
7842 | mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG, |
7843 | mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG, |
7844 | mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG, |
7845 | mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG, |
7846 | mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG, |
7847 | mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG, |
7848 | mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG, |
7849 | mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG, |
7850 | mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG, |
7851 | mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG, |
7852 | }; |
7853 | |
7854 | const uint32_t sm_ctlr_regs[] = { |
7855 | mmCGTS_SA0_QUAD0_SM_CTRL_REG, |
7856 | mmCGTS_SA0_QUAD1_SM_CTRL_REG, |
7857 | mmCGTS_SA1_QUAD0_SM_CTRL_REG, |
7858 | mmCGTS_SA1_QUAD1_SM_CTRL_REG |
7859 | }; |
7860 | |
7861 | if (amdgpu_ip_version(adev, ip: GC_HWIP, inst: 0) == IP_VERSION(10, 1, 2)) { |
7862 | for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs_nv12); i++) { |
7863 | reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] + |
7864 | tcp_ctrl_regs_nv12[i]; |
7865 | reg_data = RREG32(reg_idx); |
7866 | reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK; |
7867 | WREG32(reg_idx, reg_data); |
7868 | } |
7869 | } else { |
7870 | for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs); i++) { |
7871 | reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] + |
7872 | tcp_ctrl_regs[i]; |
7873 | reg_data = RREG32(reg_idx); |
7874 | reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK; |
7875 | WREG32(reg_idx, reg_data); |
7876 | } |
7877 | } |
7878 | |
7879 | for (i = 0; i < ARRAY_SIZE(sm_ctlr_regs); i++) { |
7880 | reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_QUAD0_SM_CTRL_REG_BASE_IDX] + |
7881 | sm_ctlr_regs[i]; |
7882 | reg_data = RREG32(reg_idx); |
7883 | reg_data &= ~CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE_MASK; |
7884 | reg_data |= 2 << CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE__SHIFT; |
7885 | WREG32(reg_idx, reg_data); |
7886 | } |
7887 | } |
7888 | |
7889 | static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev, |
7890 | bool enable) |
7891 | { |
7892 | amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id: 0); |
7893 | |
7894 | if (enable) { |
7895 | /* enable FGCG firstly*/ |
7896 | gfx_v10_0_update_fine_grain_clock_gating(adev, enable); |
7897 | /* CGCG/CGLS should be enabled after MGCG/MGLS |
7898 | * === MGCG + MGLS === |
7899 | */ |
7900 | gfx_v10_0_update_medium_grain_clock_gating(adev, enable); |
7901 | /* === CGCG /CGLS for GFX 3D Only === */ |
7902 | gfx_v10_0_update_3d_clock_gating(adev, enable); |
7903 | /* === CGCG + CGLS === */ |
7904 | gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); |
7905 | |
7906 | if ((amdgpu_ip_version(adev, ip: GC_HWIP, inst: 0) == |
7907 | IP_VERSION(10, 1, 10)) || |
7908 | (amdgpu_ip_version(adev, ip: GC_HWIP, inst: 0) == |
7909 | IP_VERSION(10, 1, 1)) || |
7910 | (amdgpu_ip_version(adev, ip: GC_HWIP, inst: 0) == |
7911 | IP_VERSION(10, 1, 2))) |
7912 | gfx_v10_0_apply_medium_grain_clock_gating_workaround(adev); |
7913 | } else { |
7914 | /* CGCG/CGLS should be disabled before MGCG/MGLS |
7915 | * === CGCG + CGLS === |
7916 | */ |
7917 | gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); |
7918 | /* === CGCG /CGLS for GFX 3D Only === */ |
7919 | gfx_v10_0_update_3d_clock_gating(adev, enable); |
7920 | /* === MGCG + MGLS === */ |
7921 | gfx_v10_0_update_medium_grain_clock_gating(adev, enable); |
7922 | /* disable fgcg at last*/ |
7923 | gfx_v10_0_update_fine_grain_clock_gating(adev, enable); |
7924 | } |
7925 | |
7926 | if (adev->cg_flags & |
7927 | (AMD_CG_SUPPORT_GFX_MGCG | |
7928 | AMD_CG_SUPPORT_GFX_CGLS | |
7929 | AMD_CG_SUPPORT_GFX_CGCG | |
7930 | AMD_CG_SUPPORT_GFX_3D_CGCG | |
7931 | AMD_CG_SUPPORT_GFX_3D_CGLS)) |
7932 | gfx_v10_0_enable_gui_idle_interrupt(adev, enable); |
7933 | |
7934 | amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id: 0); |
7935 | |
7936 | return 0; |
7937 | } |
7938 | |
7939 | static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev, |
7940 | unsigned int vmid) |
7941 | { |
7942 | u32 data; |
7943 | |
7944 | /* not for *_SOC15 */ |
7945 | data = RREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL); |
7946 | |
7947 | data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; |
7948 | data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; |
7949 | |
7950 | WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data); |
7951 | } |
7952 | |
7953 | static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned int vmid) |
7954 | { |
7955 | amdgpu_gfx_off_ctrl(adev, enable: false); |
7956 | |
7957 | gfx_v10_0_update_spm_vmid_internal(adev, vmid); |
7958 | |
7959 | amdgpu_gfx_off_ctrl(adev, enable: true); |
7960 | } |
7961 | |
7962 | static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev, |
7963 | uint32_t offset, |
7964 | struct soc15_reg_rlcg *entries, int arr_size) |
7965 | { |
7966 | int i; |
7967 | uint32_t reg; |
7968 | |
7969 | if (!entries) |
7970 | return false; |
7971 | |
7972 | for (i = 0; i < arr_size; i++) { |
7973 | const struct soc15_reg_rlcg *entry; |
7974 | |
7975 | entry = &entries[i]; |
7976 | reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; |
7977 | if (offset == reg) |
7978 | return true; |
7979 | } |
7980 | |
7981 | return false; |
7982 | } |
7983 | |
7984 | static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) |
7985 | { |
7986 | return gfx_v10_0_check_rlcg_range(adev, offset, NULL, arr_size: 0); |
7987 | } |
7988 | |
7989 | static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable) |
7990 | { |
7991 | u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); |
7992 | |
7993 | if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) |
7994 | data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; |
7995 | else |
7996 | data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; |
7997 | |
7998 | WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data); |
7999 | |
8000 | /* |
8001 | * CGPG enablement required and the register to program the hysteresis value |
8002 | * RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value |
8003 | * in refclk count. Note that RLC FW is modified to take 16 bits from |
8004 | * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits. |
8005 | * |
8006 | * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us as part) |
8007 | * of CGPG enablement starting point. |
8008 | * Power/performance team will optimize it and might give a new value later. |
8009 | */ |
8010 | if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { |
8011 | switch (amdgpu_ip_version(adev, ip: GC_HWIP, inst: 0)) { |
8012 | case IP_VERSION(10, 3, 1): |
8013 | case IP_VERSION(10, 3, 3): |
8014 | case IP_VERSION(10, 3, 6): |
8015 | case IP_VERSION(10, 3, 7): |
8016 | data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh; |
8017 | WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data); |
8018 | break; |
8019 | default: |
8020 | break; |
8021 | } |
8022 | } |
8023 | } |
8024 | |
8025 | static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable) |
8026 | { |
8027 | amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id: 0); |
8028 | |
8029 | gfx_v10_cntl_power_gating(adev, enable); |
8030 | |
8031 | amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id: 0); |
8032 | } |
8033 | |
8034 | static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = { |
8035 | .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, |
8036 | .set_safe_mode = gfx_v10_0_set_safe_mode, |
8037 | .unset_safe_mode = gfx_v10_0_unset_safe_mode, |
8038 | .init = gfx_v10_0_rlc_init, |
8039 | .get_csb_size = gfx_v10_0_get_csb_size, |
8040 | .get_csb_buffer = gfx_v10_0_get_csb_buffer, |
8041 | .resume = gfx_v10_0_rlc_resume, |
8042 | .stop = gfx_v10_0_rlc_stop, |
8043 | .reset = gfx_v10_0_rlc_reset, |
8044 | .start = gfx_v10_0_rlc_start, |
8045 | .update_spm_vmid = gfx_v10_0_update_spm_vmid, |
8046 | }; |
8047 | |
8048 | static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = { |
8049 | .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, |
8050 | .set_safe_mode = gfx_v10_0_set_safe_mode, |
8051 | .unset_safe_mode = gfx_v10_0_unset_safe_mode, |
8052 | .init = gfx_v10_0_rlc_init, |
8053 | .get_csb_size = gfx_v10_0_get_csb_size, |
8054 | .get_csb_buffer = gfx_v10_0_get_csb_buffer, |
8055 | .resume = gfx_v10_0_rlc_resume, |
8056 | .stop = gfx_v10_0_rlc_stop, |
8057 | .reset = gfx_v10_0_rlc_reset, |
8058 | .start = gfx_v10_0_rlc_start, |
8059 | .update_spm_vmid = gfx_v10_0_update_spm_vmid, |
8060 | .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range, |
8061 | }; |
8062 | |
8063 | static int gfx_v10_0_set_powergating_state(void *handle, |
8064 | enum amd_powergating_state state) |
8065 | { |
8066 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
8067 | bool enable = (state == AMD_PG_STATE_GATE); |
8068 | |
8069 | if (amdgpu_sriov_vf(adev)) |
8070 | return 0; |
8071 | |
8072 | switch (amdgpu_ip_version(adev, ip: GC_HWIP, inst: 0)) { |
8073 | case IP_VERSION(10, 1, 10): |
8074 | case IP_VERSION(10, 1, 1): |
8075 | case IP_VERSION(10, 1, 2): |
8076 | case IP_VERSION(10, 3, 0): |
8077 | case IP_VERSION(10, 3, 2): |
8078 | case IP_VERSION(10, 3, 4): |
8079 | case IP_VERSION(10, 3, 5): |
8080 | amdgpu_gfx_off_ctrl(adev, enable); |
8081 | break; |
8082 | case IP_VERSION(10, 3, 1): |
8083 | case IP_VERSION(10, 3, 3): |
8084 | case IP_VERSION(10, 3, 6): |
8085 | case IP_VERSION(10, 3, 7): |
8086 | if (!enable) |
8087 | amdgpu_gfx_off_ctrl(adev, enable: false); |
8088 | |
8089 | gfx_v10_cntl_pg(adev, enable); |
8090 | |
8091 | if (enable) |
8092 | amdgpu_gfx_off_ctrl(adev, enable: true); |
8093 | |
8094 | break; |
8095 | default: |
8096 | break; |
8097 | } |
8098 | return 0; |
8099 | } |
8100 | |
8101 | static int gfx_v10_0_set_clockgating_state(void *handle, |
8102 | enum amd_clockgating_state state) |
8103 | { |
8104 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
8105 | |
8106 | if (amdgpu_sriov_vf(adev)) |
8107 | return 0; |
8108 | |
8109 | switch (amdgpu_ip_version(adev, ip: GC_HWIP, inst: 0)) { |
8110 | case IP_VERSION(10, 1, 10): |
8111 | case IP_VERSION(10, 1, 1): |
8112 | case IP_VERSION(10, 1, 2): |
8113 | case IP_VERSION(10, 3, 0): |
8114 | case IP_VERSION(10, 3, 2): |
8115 | case IP_VERSION(10, 3, 1): |
8116 | case IP_VERSION(10, 3, 4): |
8117 | case IP_VERSION(10, 3, 5): |
8118 | case IP_VERSION(10, 3, 6): |
8119 | case IP_VERSION(10, 3, 3): |
8120 | case IP_VERSION(10, 3, 7): |
8121 | gfx_v10_0_update_gfx_clock_gating(adev, |
8122 | enable: state == AMD_CG_STATE_GATE); |
8123 | break; |
8124 | default: |
8125 | break; |
8126 | } |
8127 | return 0; |
8128 | } |
8129 | |
8130 | static void gfx_v10_0_get_clockgating_state(void *handle, u64 *flags) |
8131 | { |
8132 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
8133 | int data; |
8134 | |
8135 | /* AMD_CG_SUPPORT_GFX_FGCG */ |
8136 | data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); |
8137 | if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) |
8138 | *flags |= AMD_CG_SUPPORT_GFX_FGCG; |
8139 | |
8140 | /* AMD_CG_SUPPORT_GFX_MGCG */ |
8141 | data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); |
8142 | if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) |
8143 | *flags |= AMD_CG_SUPPORT_GFX_MGCG; |
8144 | |
8145 | /* AMD_CG_SUPPORT_GFX_CGCG */ |
8146 | data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL)); |
8147 | if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) |
8148 | *flags |= AMD_CG_SUPPORT_GFX_CGCG; |
8149 | |
8150 | /* AMD_CG_SUPPORT_GFX_CGLS */ |
8151 | if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) |
8152 | *flags |= AMD_CG_SUPPORT_GFX_CGLS; |
8153 | |
8154 | /* AMD_CG_SUPPORT_GFX_RLC_LS */ |
8155 | data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL)); |
8156 | if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) |
8157 | *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; |
8158 | |
8159 | /* AMD_CG_SUPPORT_GFX_CP_LS */ |
8160 | data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL)); |
8161 | if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) |
8162 | *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; |
8163 | |
8164 | /* AMD_CG_SUPPORT_GFX_3D_CGCG */ |
8165 | data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D)); |
8166 | if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) |
8167 | *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; |
8168 | |
8169 | /* AMD_CG_SUPPORT_GFX_3D_CGLS */ |
8170 | if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) |
8171 | *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; |
8172 | } |
8173 | |
8174 | static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) |
8175 | { |
8176 | /* gfx10 is 32bit rptr*/ |
8177 | return *(uint32_t *)ring->rptr_cpu_addr; |
8178 | } |
8179 | |
8180 | static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) |
8181 | { |
8182 | struct amdgpu_device *adev = ring->adev; |
8183 | u64 wptr; |
8184 | |
8185 | /* XXX check if swapping is necessary on BE */ |
8186 | if (ring->use_doorbell) { |
8187 | wptr = atomic64_read(v: (atomic64_t *)ring->wptr_cpu_addr); |
8188 | } else { |
8189 | wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); |
8190 | wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; |
8191 | } |
8192 | |
8193 | return wptr; |
8194 | } |
8195 | |
8196 | static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) |
8197 | { |
8198 | struct amdgpu_device *adev = ring->adev; |
8199 | uint32_t *wptr_saved; |
8200 | uint32_t *is_queue_unmap; |
8201 | uint64_t aggregated_db_index; |
8202 | uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_GFX].mqd_size; |
8203 | uint64_t wptr_tmp; |
8204 | |
8205 | if (ring->is_mes_queue) { |
8206 | wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size); |
8207 | is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size + |
8208 | sizeof(uint32_t)); |
8209 | aggregated_db_index = |
8210 | amdgpu_mes_get_aggregated_doorbell_index(adev, |
8211 | prio: AMDGPU_MES_PRIORITY_LEVEL_NORMAL); |
8212 | |
8213 | wptr_tmp = ring->wptr & ring->buf_mask; |
8214 | atomic64_set(v: (atomic64_t *)ring->wptr_cpu_addr, i: wptr_tmp); |
8215 | *wptr_saved = wptr_tmp; |
8216 | /* assume doorbell always being used by mes mapped queue */ |
8217 | if (*is_queue_unmap) { |
8218 | WDOORBELL64(aggregated_db_index, wptr_tmp); |
8219 | WDOORBELL64(ring->doorbell_index, wptr_tmp); |
8220 | } else { |
8221 | WDOORBELL64(ring->doorbell_index, wptr_tmp); |
8222 | |
8223 | if (*is_queue_unmap) |
8224 | WDOORBELL64(aggregated_db_index, wptr_tmp); |
8225 | } |
8226 | } else { |
8227 | if (ring->use_doorbell) { |
8228 | /* XXX check if swapping is necessary on BE */ |
8229 | atomic64_set(v: (atomic64_t *)ring->wptr_cpu_addr, |
8230 | i: ring->wptr); |
8231 | WDOORBELL64(ring->doorbell_index, ring->wptr); |
8232 | } else { |
8233 | WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, |
8234 | lower_32_bits(ring->wptr)); |
8235 | WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, |
8236 | upper_32_bits(ring->wptr)); |
8237 | } |
8238 | } |
8239 | } |
8240 | |
8241 | static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring) |
8242 | { |
8243 | /* gfx10 hardware is 32bit rptr */ |
8244 | return *(uint32_t *)ring->rptr_cpu_addr; |
8245 | } |
8246 | |
8247 | static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring) |
8248 | { |
8249 | u64 wptr; |
8250 | |
8251 | /* XXX check if swapping is necessary on BE */ |
8252 | if (ring->use_doorbell) |
8253 | wptr = atomic64_read(v: (atomic64_t *)ring->wptr_cpu_addr); |
8254 | else |
8255 | BUG(); |
8256 | return wptr; |
8257 | } |
8258 | |
8259 | static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring) |
8260 | { |
8261 | struct amdgpu_device *adev = ring->adev; |
8262 | uint32_t *wptr_saved; |
8263 | uint32_t *is_queue_unmap; |
8264 | uint64_t aggregated_db_index; |
8265 | uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size; |
8266 | uint64_t wptr_tmp; |
8267 | |
8268 | if (ring->is_mes_queue) { |
8269 | wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size); |
8270 | is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size + |
8271 | sizeof(uint32_t)); |
8272 | aggregated_db_index = |
8273 | amdgpu_mes_get_aggregated_doorbell_index(adev, |
8274 | prio: AMDGPU_MES_PRIORITY_LEVEL_NORMAL); |
8275 | |
8276 | wptr_tmp = ring->wptr & ring->buf_mask; |
8277 | atomic64_set(v: (atomic64_t *)ring->wptr_cpu_addr, i: wptr_tmp); |
8278 | *wptr_saved = wptr_tmp; |
8279 | /* assume doorbell always used by mes mapped queue */ |
8280 | if (*is_queue_unmap) { |
8281 | WDOORBELL64(aggregated_db_index, wptr_tmp); |
8282 | WDOORBELL64(ring->doorbell_index, wptr_tmp); |
8283 | } else { |
8284 | WDOORBELL64(ring->doorbell_index, wptr_tmp); |
8285 | |
8286 | if (*is_queue_unmap) |
8287 | WDOORBELL64(aggregated_db_index, wptr_tmp); |
8288 | } |
8289 | } else { |
8290 | /* XXX check if swapping is necessary on BE */ |
8291 | if (ring->use_doorbell) { |
8292 | atomic64_set(v: (atomic64_t *)ring->wptr_cpu_addr, |
8293 | i: ring->wptr); |
8294 | WDOORBELL64(ring->doorbell_index, ring->wptr); |
8295 | } else { |
8296 | BUG(); /* only DOORBELL method supported on gfx10 now */ |
8297 | } |
8298 | } |
8299 | } |
8300 | |
8301 | static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) |
8302 | { |
8303 | struct amdgpu_device *adev = ring->adev; |
8304 | u32 ref_and_mask, reg_mem_engine; |
8305 | const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; |
8306 | |
8307 | if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { |
8308 | switch (ring->me) { |
8309 | case 1: |
8310 | ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; |
8311 | break; |
8312 | case 2: |
8313 | ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; |
8314 | break; |
8315 | default: |
8316 | return; |
8317 | } |
8318 | reg_mem_engine = 0; |
8319 | } else { |
8320 | ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; |
8321 | reg_mem_engine = 1; /* pfp */ |
8322 | } |
8323 | |
8324 | gfx_v10_0_wait_reg_mem(ring, eng_sel: reg_mem_engine, mem_space: 0, opt: 1, |
8325 | addr0: adev->nbio.funcs->get_hdp_flush_req_offset(adev), |
8326 | addr1: adev->nbio.funcs->get_hdp_flush_done_offset(adev), |
8327 | ref: ref_and_mask, mask: ref_and_mask, inv: 0x20); |
8328 | } |
8329 | |
8330 | static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, |
8331 | struct amdgpu_job *job, |
8332 | struct amdgpu_ib *ib, |
8333 | uint32_t flags) |
8334 | { |
8335 | unsigned int vmid = AMDGPU_JOB_GET_VMID(job); |
8336 | u32 , control = 0; |
8337 | |
8338 | if (ib->flags & AMDGPU_IB_FLAG_CE) |
8339 | header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2); |
8340 | else |
8341 | header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); |
8342 | |
8343 | control |= ib->length_dw | (vmid << 24); |
8344 | |
8345 | if (ring->adev->gfx.mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { |
8346 | control |= INDIRECT_BUFFER_PRE_ENB(1); |
8347 | |
8348 | if (flags & AMDGPU_IB_PREEMPTED) |
8349 | control |= INDIRECT_BUFFER_PRE_RESUME(1); |
8350 | |
8351 | if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid) |
8352 | gfx_v10_0_ring_emit_de_meta(ring, |
8353 | resume: (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); |
8354 | } |
8355 | |
8356 | if (ring->is_mes_queue) |
8357 | /* inherit vmid from mqd */ |
8358 | control |= 0x400000; |
8359 | |
8360 | amdgpu_ring_write(ring, v: header); |
8361 | BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ |
8362 | amdgpu_ring_write(ring, |
8363 | #ifdef __BIG_ENDIAN |
8364 | (2 << 0) | |
8365 | #endif |
8366 | lower_32_bits(ib->gpu_addr)); |
8367 | amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); |
8368 | amdgpu_ring_write(ring, v: control); |
8369 | } |
8370 | |
8371 | static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring, |
8372 | struct amdgpu_job *job, |
8373 | struct amdgpu_ib *ib, |
8374 | uint32_t flags) |
8375 | { |
8376 | unsigned int vmid = AMDGPU_JOB_GET_VMID(job); |
8377 | u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); |
8378 | |
8379 | if (ring->is_mes_queue) |
8380 | /* inherit vmid from mqd */ |
8381 | control |= 0x40000000; |
8382 | |
8383 | /* Currently, there is a high possibility to get wave ID mismatch |
8384 | * between ME and GDS, leading to a hw deadlock, because ME generates |
8385 | * different wave IDs than the GDS expects. This situation happens |
8386 | * randomly when at least 5 compute pipes use GDS ordered append. |
8387 | * The wave IDs generated by ME are also wrong after suspend/resume. |
8388 | * Those are probably bugs somewhere else in the kernel driver. |
8389 | * |
8390 | * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and |
8391 | * GDS to 0 for this ring (me/pipe). |
8392 | */ |
8393 | if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { |
8394 | amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
8395 | amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID); |
8396 | amdgpu_ring_write(ring, v: ring->adev->gds.gds_compute_max_wave_id); |
8397 | } |
8398 | |
8399 | amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); |
8400 | BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ |
8401 | amdgpu_ring_write(ring, |
8402 | #ifdef __BIG_ENDIAN |
8403 | (2 << 0) | |
8404 | #endif |
8405 | lower_32_bits(ib->gpu_addr)); |
8406 | amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); |
8407 | amdgpu_ring_write(ring, v: control); |
8408 | } |
8409 | |
8410 | static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, |
8411 | u64 seq, unsigned int flags) |
8412 | { |
8413 | bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; |
8414 | bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; |
8415 | |
8416 | /* RELEASE_MEM - flush caches, send int */ |
8417 | amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); |
8418 | amdgpu_ring_write(ring, v: (PACKET3_RELEASE_MEM_GCR_SEQ | |
8419 | PACKET3_RELEASE_MEM_GCR_GL2_WB | |
8420 | PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */ |
8421 | PACKET3_RELEASE_MEM_GCR_GLM_WB | |
8422 | PACKET3_RELEASE_MEM_CACHE_POLICY(3) | |
8423 | PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | |
8424 | PACKET3_RELEASE_MEM_EVENT_INDEX(5))); |
8425 | amdgpu_ring_write(ring, v: (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | |
8426 | PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); |
8427 | |
8428 | /* |
8429 | * the address should be Qword aligned if 64bit write, Dword |
8430 | * aligned if only send 32bit data low (discard data high) |
8431 | */ |
8432 | if (write64bit) |
8433 | BUG_ON(addr & 0x7); |
8434 | else |
8435 | BUG_ON(addr & 0x3); |
8436 | amdgpu_ring_write(ring, lower_32_bits(addr)); |
8437 | amdgpu_ring_write(ring, upper_32_bits(addr)); |
8438 | amdgpu_ring_write(ring, lower_32_bits(seq)); |
8439 | amdgpu_ring_write(ring, upper_32_bits(seq)); |
8440 | amdgpu_ring_write(ring, v: ring->is_mes_queue ? |
8441 | (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0); |
8442 | } |
8443 | |
8444 | static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) |
8445 | { |
8446 | int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); |
8447 | uint32_t seq = ring->fence_drv.sync_seq; |
8448 | uint64_t addr = ring->fence_drv.gpu_addr; |
8449 | |
8450 | gfx_v10_0_wait_reg_mem(ring, eng_sel: usepfp, mem_space: 1, opt: 0, lower_32_bits(addr), |
8451 | upper_32_bits(addr), ref: seq, mask: 0xffffffff, inv: 4); |
8452 | } |
8453 | |
8454 | static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, |
8455 | uint16_t pasid, uint32_t flush_type, |
8456 | bool all_hub, uint8_t dst_sel) |
8457 | { |
8458 | amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); |
8459 | amdgpu_ring_write(ring, |
8460 | PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) | |
8461 | PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | |
8462 | PACKET3_INVALIDATE_TLBS_PASID(pasid) | |
8463 | PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); |
8464 | } |
8465 | |
8466 | static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring, |
8467 | unsigned int vmid, uint64_t pd_addr) |
8468 | { |
8469 | if (ring->is_mes_queue) |
8470 | gfx_v10_0_ring_invalidate_tlbs(ring, pasid: 0, flush_type: 0, all_hub: false, dst_sel: 0); |
8471 | else |
8472 | amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); |
8473 | |
8474 | /* compute doesn't have PFP */ |
8475 | if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { |
8476 | /* sync PFP to ME, otherwise we might get invalid PFP reads */ |
8477 | amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); |
8478 | amdgpu_ring_write(ring, v: 0x0); |
8479 | } |
8480 | } |
8481 | |
8482 | static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, |
8483 | u64 seq, unsigned int flags) |
8484 | { |
8485 | struct amdgpu_device *adev = ring->adev; |
8486 | |
8487 | /* we only allocate 32bit for each seq wb address */ |
8488 | BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); |
8489 | |
8490 | /* write fence seq to the "addr" */ |
8491 | amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); |
8492 | amdgpu_ring_write(ring, v: (WRITE_DATA_ENGINE_SEL(0) | |
8493 | WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); |
8494 | amdgpu_ring_write(ring, lower_32_bits(addr)); |
8495 | amdgpu_ring_write(ring, upper_32_bits(addr)); |
8496 | amdgpu_ring_write(ring, lower_32_bits(seq)); |
8497 | |
8498 | if (flags & AMDGPU_FENCE_FLAG_INT) { |
8499 | /* set register to trigger INT */ |
8500 | amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); |
8501 | amdgpu_ring_write(ring, v: (WRITE_DATA_ENGINE_SEL(0) | |
8502 | WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); |
8503 | amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)); |
8504 | amdgpu_ring_write(ring, v: 0); |
8505 | amdgpu_ring_write(ring, v: 0x20000000); /* src_id is 178 */ |
8506 | } |
8507 | } |
8508 | |
8509 | static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring) |
8510 | { |
8511 | amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); |
8512 | amdgpu_ring_write(ring, v: 0); |
8513 | } |
8514 | |
8515 | static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, |
8516 | uint32_t flags) |
8517 | { |
8518 | uint32_t dw2 = 0; |
8519 | |
8520 | if (ring->adev->gfx.mcbp) |
8521 | gfx_v10_0_ring_emit_ce_meta(ring, |
8522 | resume: (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); |
8523 | |
8524 | dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ |
8525 | if (flags & AMDGPU_HAVE_CTX_SWITCH) { |
8526 | /* set load_global_config & load_global_uconfig */ |
8527 | dw2 |= 0x8001; |
8528 | /* set load_cs_sh_regs */ |
8529 | dw2 |= 0x01000000; |
8530 | /* set load_per_context_state & load_gfx_sh_regs for GFX */ |
8531 | dw2 |= 0x10002; |
8532 | |
8533 | /* set load_ce_ram if preamble presented */ |
8534 | if (AMDGPU_PREAMBLE_IB_PRESENT & flags) |
8535 | dw2 |= 0x10000000; |
8536 | } else { |
8537 | /* still load_ce_ram if this is the first time preamble presented |
8538 | * although there is no context switch happens. |
8539 | */ |
8540 | if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags) |
8541 | dw2 |= 0x10000000; |
8542 | } |
8543 | |
8544 | amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); |
8545 | amdgpu_ring_write(ring, v: dw2); |
8546 | amdgpu_ring_write(ring, v: 0); |
8547 | } |
8548 | |
8549 | static unsigned int gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring, |
8550 | uint64_t addr) |
8551 | { |
8552 | unsigned int ret; |
8553 | |
8554 | amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); |
8555 | amdgpu_ring_write(ring, lower_32_bits(addr)); |
8556 | amdgpu_ring_write(ring, upper_32_bits(addr)); |
8557 | /* discard following DWs if *cond_exec_gpu_addr==0 */ |
8558 | amdgpu_ring_write(ring, v: 0); |
8559 | ret = ring->wptr & ring->buf_mask; |
8560 | /* patch dummy value later */ |
8561 | amdgpu_ring_write(ring, v: 0); |
8562 | |
8563 | return ret; |
8564 | } |
8565 | |
8566 | static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring) |
8567 | { |
8568 | int i, r = 0; |
8569 | struct amdgpu_device *adev = ring->adev; |
8570 | struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; |
8571 | struct amdgpu_ring *kiq_ring = &kiq->ring; |
8572 | unsigned long flags; |
8573 | |
8574 | if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) |
8575 | return -EINVAL; |
8576 | |
8577 | spin_lock_irqsave(&kiq->ring_lock, flags); |
8578 | |
8579 | if (amdgpu_ring_alloc(ring: kiq_ring, ndw: kiq->pmf->unmap_queues_size)) { |
8580 | spin_unlock_irqrestore(lock: &kiq->ring_lock, flags); |
8581 | return -ENOMEM; |
8582 | } |
8583 | |
8584 | /* assert preemption condition */ |
8585 | amdgpu_ring_set_preempt_cond_exec(ring, cond_exec: false); |
8586 | |
8587 | /* assert IB preemption, emit the trailing fence */ |
8588 | kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, |
8589 | ring->trail_fence_gpu_addr, |
8590 | ++ring->trail_seq); |
8591 | amdgpu_ring_commit(ring: kiq_ring); |
8592 | |
8593 | spin_unlock_irqrestore(lock: &kiq->ring_lock, flags); |
8594 | |
8595 | /* poll the trailing fence */ |
8596 | for (i = 0; i < adev->usec_timeout; i++) { |
8597 | if (ring->trail_seq == |
8598 | le32_to_cpu(*(ring->trail_fence_cpu_addr))) |
8599 | break; |
8600 | udelay(1); |
8601 | } |
8602 | |
8603 | if (i >= adev->usec_timeout) { |
8604 | r = -EINVAL; |
8605 | DRM_ERROR("ring %d failed to preempt ib\n" , ring->idx); |
8606 | } |
8607 | |
8608 | /* deassert preemption condition */ |
8609 | amdgpu_ring_set_preempt_cond_exec(ring, cond_exec: true); |
8610 | return r; |
8611 | } |
8612 | |
8613 | static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume) |
8614 | { |
8615 | struct amdgpu_device *adev = ring->adev; |
8616 | struct v10_ce_ib_state ce_payload = {0}; |
8617 | uint64_t offset, ce_payload_gpu_addr; |
8618 | void *ce_payload_cpu_addr; |
8619 | int cnt; |
8620 | |
8621 | cnt = (sizeof(ce_payload) >> 2) + 4 - 2; |
8622 | |
8623 | if (ring->is_mes_queue) { |
8624 | offset = offsetof(struct amdgpu_mes_ctx_meta_data, |
8625 | gfx[0].gfx_meta_data) + |
8626 | offsetof(struct v10_gfx_meta_data, ce_payload); |
8627 | ce_payload_gpu_addr = |
8628 | amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); |
8629 | ce_payload_cpu_addr = |
8630 | amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); |
8631 | } else { |
8632 | offset = offsetof(struct v10_gfx_meta_data, ce_payload); |
8633 | ce_payload_gpu_addr = amdgpu_csa_vaddr(adev: ring->adev) + offset; |
8634 | ce_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; |
8635 | } |
8636 | |
8637 | amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); |
8638 | amdgpu_ring_write(ring, v: (WRITE_DATA_ENGINE_SEL(2) | |
8639 | WRITE_DATA_DST_SEL(8) | |
8640 | WR_CONFIRM) | |
8641 | WRITE_DATA_CACHE_POLICY(0)); |
8642 | amdgpu_ring_write(ring, lower_32_bits(ce_payload_gpu_addr)); |
8643 | amdgpu_ring_write(ring, upper_32_bits(ce_payload_gpu_addr)); |
8644 | |
8645 | if (resume) |
8646 | amdgpu_ring_write_multiple(ring, src: ce_payload_cpu_addr, |
8647 | count_dw: sizeof(ce_payload) >> 2); |
8648 | else |
8649 | amdgpu_ring_write_multiple(ring, src: (void *)&ce_payload, |
8650 | count_dw: sizeof(ce_payload) >> 2); |
8651 | } |
8652 | |
8653 | static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) |
8654 | { |
8655 | struct amdgpu_device *adev = ring->adev; |
8656 | struct v10_de_ib_state de_payload = {0}; |
8657 | uint64_t offset, gds_addr, de_payload_gpu_addr; |
8658 | void *de_payload_cpu_addr; |
8659 | int cnt; |
8660 | |
8661 | if (ring->is_mes_queue) { |
8662 | offset = offsetof(struct amdgpu_mes_ctx_meta_data, |
8663 | gfx[0].gfx_meta_data) + |
8664 | offsetof(struct v10_gfx_meta_data, de_payload); |
8665 | de_payload_gpu_addr = |
8666 | amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); |
8667 | de_payload_cpu_addr = |
8668 | amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); |
8669 | |
8670 | offset = offsetof(struct amdgpu_mes_ctx_meta_data, |
8671 | gfx[0].gds_backup) + |
8672 | offsetof(struct v10_gfx_meta_data, de_payload); |
8673 | gds_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); |
8674 | } else { |
8675 | offset = offsetof(struct v10_gfx_meta_data, de_payload); |
8676 | de_payload_gpu_addr = amdgpu_csa_vaddr(adev: ring->adev) + offset; |
8677 | de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; |
8678 | |
8679 | gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) + |
8680 | AMDGPU_CSA_SIZE - adev->gds.gds_size, |
8681 | PAGE_SIZE); |
8682 | } |
8683 | |
8684 | de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); |
8685 | de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); |
8686 | |
8687 | cnt = (sizeof(de_payload) >> 2) + 4 - 2; |
8688 | amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); |
8689 | amdgpu_ring_write(ring, v: (WRITE_DATA_ENGINE_SEL(1) | |
8690 | WRITE_DATA_DST_SEL(8) | |
8691 | WR_CONFIRM) | |
8692 | WRITE_DATA_CACHE_POLICY(0)); |
8693 | amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr)); |
8694 | amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr)); |
8695 | |
8696 | if (resume) |
8697 | amdgpu_ring_write_multiple(ring, src: de_payload_cpu_addr, |
8698 | count_dw: sizeof(de_payload) >> 2); |
8699 | else |
8700 | amdgpu_ring_write_multiple(ring, src: (void *)&de_payload, |
8701 | count_dw: sizeof(de_payload) >> 2); |
8702 | } |
8703 | |
8704 | static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, |
8705 | bool secure) |
8706 | { |
8707 | uint32_t v = secure ? FRAME_TMZ : 0; |
8708 | |
8709 | amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); |
8710 | amdgpu_ring_write(ring, v: v | FRAME_CMD(start ? 0 : 1)); |
8711 | } |
8712 | |
8713 | static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, |
8714 | uint32_t reg_val_offs) |
8715 | { |
8716 | struct amdgpu_device *adev = ring->adev; |
8717 | |
8718 | amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); |
8719 | amdgpu_ring_write(ring, v: 0 | /* src: register*/ |
8720 | (5 << 8) | /* dst: memory */ |
8721 | (1 << 20)); /* write confirm */ |
8722 | amdgpu_ring_write(ring, v: reg); |
8723 | amdgpu_ring_write(ring, v: 0); |
8724 | amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + |
8725 | reg_val_offs * 4)); |
8726 | amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + |
8727 | reg_val_offs * 4)); |
8728 | } |
8729 | |
8730 | static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, |
8731 | uint32_t val) |
8732 | { |
8733 | uint32_t cmd = 0; |
8734 | |
8735 | switch (ring->funcs->type) { |
8736 | case AMDGPU_RING_TYPE_GFX: |
8737 | cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; |
8738 | break; |
8739 | case AMDGPU_RING_TYPE_KIQ: |
8740 | cmd = (1 << 16); /* no inc addr */ |
8741 | break; |
8742 | default: |
8743 | cmd = WR_CONFIRM; |
8744 | break; |
8745 | } |
8746 | amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); |
8747 | amdgpu_ring_write(ring, v: cmd); |
8748 | amdgpu_ring_write(ring, v: reg); |
8749 | amdgpu_ring_write(ring, v: 0); |
8750 | amdgpu_ring_write(ring, v: val); |
8751 | } |
8752 | |
8753 | static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, |
8754 | uint32_t val, uint32_t mask) |
8755 | { |
8756 | gfx_v10_0_wait_reg_mem(ring, eng_sel: 0, mem_space: 0, opt: 0, addr0: reg, addr1: 0, ref: val, mask, inv: 0x20); |
8757 | } |
8758 | |
8759 | static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, |
8760 | uint32_t reg0, uint32_t reg1, |
8761 | uint32_t ref, uint32_t mask) |
8762 | { |
8763 | int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); |
8764 | struct amdgpu_device *adev = ring->adev; |
8765 | bool fw_version_ok = false; |
8766 | |
8767 | fw_version_ok = adev->gfx.cp_fw_write_wait; |
8768 | |
8769 | if (fw_version_ok) |
8770 | gfx_v10_0_wait_reg_mem(ring, eng_sel: usepfp, mem_space: 0, opt: 1, addr0: reg0, addr1: reg1, |
8771 | ref, mask, inv: 0x20); |
8772 | else |
8773 | amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, val0: reg1, |
8774 | reg1: ref, val1: mask); |
8775 | } |
8776 | |
8777 | static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring, |
8778 | unsigned int vmid) |
8779 | { |
8780 | struct amdgpu_device *adev = ring->adev; |
8781 | uint32_t value = 0; |
8782 | |
8783 | value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); |
8784 | value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); |
8785 | value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); |
8786 | value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); |
8787 | WREG32_SOC15(GC, 0, mmSQ_CMD, value); |
8788 | } |
8789 | |
8790 | static void |
8791 | gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, |
8792 | uint32_t me, uint32_t pipe, |
8793 | enum amdgpu_interrupt_state state) |
8794 | { |
8795 | uint32_t cp_int_cntl, cp_int_cntl_reg; |
8796 | |
8797 | if (!me) { |
8798 | switch (pipe) { |
8799 | case 0: |
8800 | cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0); |
8801 | break; |
8802 | case 1: |
8803 | cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1); |
8804 | break; |
8805 | default: |
8806 | DRM_DEBUG("invalid pipe %d\n" , pipe); |
8807 | return; |
8808 | } |
8809 | } else { |
8810 | DRM_DEBUG("invalid me %d\n" , me); |
8811 | return; |
8812 | } |
8813 | |
8814 | switch (state) { |
8815 | case AMDGPU_IRQ_STATE_DISABLE: |
8816 | cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); |
8817 | cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, |
8818 | TIME_STAMP_INT_ENABLE, 0); |
8819 | WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); |
8820 | break; |
8821 | case AMDGPU_IRQ_STATE_ENABLE: |
8822 | cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); |
8823 | cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, |
8824 | TIME_STAMP_INT_ENABLE, 1); |
8825 | WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); |
8826 | break; |
8827 | default: |
8828 | break; |
8829 | } |
8830 | } |
8831 | |
8832 | static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, |
8833 | int me, int pipe, |
8834 | enum amdgpu_interrupt_state state) |
8835 | { |
8836 | u32 mec_int_cntl, mec_int_cntl_reg; |
8837 | |
8838 | /* |
8839 | * amdgpu controls only the first MEC. That's why this function only |
8840 | * handles the setting of interrupts for this specific MEC. All other |
8841 | * pipes' interrupts are set by amdkfd. |
8842 | */ |
8843 | |
8844 | if (me == 1) { |
8845 | switch (pipe) { |
8846 | case 0: |
8847 | mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); |
8848 | break; |
8849 | case 1: |
8850 | mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); |
8851 | break; |
8852 | case 2: |
8853 | mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); |
8854 | break; |
8855 | case 3: |
8856 | mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); |
8857 | break; |
8858 | default: |
8859 | DRM_DEBUG("invalid pipe %d\n" , pipe); |
8860 | return; |
8861 | } |
8862 | } else { |
8863 | DRM_DEBUG("invalid me %d\n" , me); |
8864 | return; |
8865 | } |
8866 | |
8867 | switch (state) { |
8868 | case AMDGPU_IRQ_STATE_DISABLE: |
8869 | mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); |
8870 | mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, |
8871 | TIME_STAMP_INT_ENABLE, 0); |
8872 | WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); |
8873 | break; |
8874 | case AMDGPU_IRQ_STATE_ENABLE: |
8875 | mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); |
8876 | mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, |
8877 | TIME_STAMP_INT_ENABLE, 1); |
8878 | WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); |
8879 | break; |
8880 | default: |
8881 | break; |
8882 | } |
8883 | } |
8884 | |
8885 | static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev, |
8886 | struct amdgpu_irq_src *src, |
8887 | unsigned int type, |
8888 | enum amdgpu_interrupt_state state) |
8889 | { |
8890 | switch (type) { |
8891 | case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: |
8892 | gfx_v10_0_set_gfx_eop_interrupt_state(adev, me: 0, pipe: 0, state); |
8893 | break; |
8894 | case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: |
8895 | gfx_v10_0_set_gfx_eop_interrupt_state(adev, me: 0, pipe: 1, state); |
8896 | break; |
8897 | case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: |
8898 | gfx_v10_0_set_compute_eop_interrupt_state(adev, me: 1, pipe: 0, state); |
8899 | break; |
8900 | case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: |
8901 | gfx_v10_0_set_compute_eop_interrupt_state(adev, me: 1, pipe: 1, state); |
8902 | break; |
8903 | case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: |
8904 | gfx_v10_0_set_compute_eop_interrupt_state(adev, me: 1, pipe: 2, state); |
8905 | break; |
8906 | case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: |
8907 | gfx_v10_0_set_compute_eop_interrupt_state(adev, me: 1, pipe: 3, state); |
8908 | break; |
8909 | case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: |
8910 | gfx_v10_0_set_compute_eop_interrupt_state(adev, me: 2, pipe: 0, state); |
8911 | break; |
8912 | case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: |
8913 | gfx_v10_0_set_compute_eop_interrupt_state(adev, me: 2, pipe: 1, state); |
8914 | break; |
8915 | case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: |
8916 | gfx_v10_0_set_compute_eop_interrupt_state(adev, me: 2, pipe: 2, state); |
8917 | break; |
8918 | case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: |
8919 | gfx_v10_0_set_compute_eop_interrupt_state(adev, me: 2, pipe: 3, state); |
8920 | break; |
8921 | default: |
8922 | break; |
8923 | } |
8924 | return 0; |
8925 | } |
8926 | |
8927 | static int gfx_v10_0_eop_irq(struct amdgpu_device *adev, |
8928 | struct amdgpu_irq_src *source, |
8929 | struct amdgpu_iv_entry *entry) |
8930 | { |
8931 | int i; |
8932 | u8 me_id, pipe_id, queue_id; |
8933 | struct amdgpu_ring *ring; |
8934 | uint32_t mes_queue_id = entry->src_data[0]; |
8935 | |
8936 | DRM_DEBUG("IH: CP EOP\n" ); |
8937 | |
8938 | if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { |
8939 | struct amdgpu_mes_queue *queue; |
8940 | |
8941 | mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; |
8942 | |
8943 | spin_lock(lock: &adev->mes.queue_id_lock); |
8944 | queue = idr_find(&adev->mes.queue_id_idr, id: mes_queue_id); |
8945 | if (queue) { |
8946 | DRM_DEBUG("process mes queue id = %d\n" , mes_queue_id); |
8947 | amdgpu_fence_process(ring: queue->ring); |
8948 | } |
8949 | spin_unlock(lock: &adev->mes.queue_id_lock); |
8950 | } else { |
8951 | me_id = (entry->ring_id & 0x0c) >> 2; |
8952 | pipe_id = (entry->ring_id & 0x03) >> 0; |
8953 | queue_id = (entry->ring_id & 0x70) >> 4; |
8954 | |
8955 | switch (me_id) { |
8956 | case 0: |
8957 | if (pipe_id == 0) |
8958 | amdgpu_fence_process(ring: &adev->gfx.gfx_ring[0]); |
8959 | else |
8960 | amdgpu_fence_process(ring: &adev->gfx.gfx_ring[1]); |
8961 | break; |
8962 | case 1: |
8963 | case 2: |
8964 | for (i = 0; i < adev->gfx.num_compute_rings; i++) { |
8965 | ring = &adev->gfx.compute_ring[i]; |
8966 | /* Per-queue interrupt is supported for MEC starting from VI. |
8967 | * The interrupt can only be enabled/disabled per pipe instead |
8968 | * of per queue. |
8969 | */ |
8970 | if ((ring->me == me_id) && |
8971 | (ring->pipe == pipe_id) && |
8972 | (ring->queue == queue_id)) |
8973 | amdgpu_fence_process(ring); |
8974 | } |
8975 | break; |
8976 | } |
8977 | } |
8978 | |
8979 | return 0; |
8980 | } |
8981 | |
8982 | static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev, |
8983 | struct amdgpu_irq_src *source, |
8984 | unsigned int type, |
8985 | enum amdgpu_interrupt_state state) |
8986 | { |
8987 | switch (state) { |
8988 | case AMDGPU_IRQ_STATE_DISABLE: |
8989 | case AMDGPU_IRQ_STATE_ENABLE: |
8990 | WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, |
8991 | PRIV_REG_INT_ENABLE, |
8992 | state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); |
8993 | break; |
8994 | default: |
8995 | break; |
8996 | } |
8997 | |
8998 | return 0; |
8999 | } |
9000 | |
9001 | static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev, |
9002 | struct amdgpu_irq_src *source, |
9003 | unsigned int type, |
9004 | enum amdgpu_interrupt_state state) |
9005 | { |
9006 | switch (state) { |
9007 | case AMDGPU_IRQ_STATE_DISABLE: |
9008 | case AMDGPU_IRQ_STATE_ENABLE: |
9009 | WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, |
9010 | PRIV_INSTR_INT_ENABLE, |
9011 | state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); |
9012 | break; |
9013 | default: |
9014 | break; |
9015 | } |
9016 | |
9017 | return 0; |
9018 | } |
9019 | |
9020 | static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev, |
9021 | struct amdgpu_iv_entry *entry) |
9022 | { |
9023 | u8 me_id, pipe_id, queue_id; |
9024 | struct amdgpu_ring *ring; |
9025 | int i; |
9026 | |
9027 | me_id = (entry->ring_id & 0x0c) >> 2; |
9028 | pipe_id = (entry->ring_id & 0x03) >> 0; |
9029 | queue_id = (entry->ring_id & 0x70) >> 4; |
9030 | |
9031 | switch (me_id) { |
9032 | case 0: |
9033 | for (i = 0; i < adev->gfx.num_gfx_rings; i++) { |
9034 | ring = &adev->gfx.gfx_ring[i]; |
9035 | /* we only enabled 1 gfx queue per pipe for now */ |
9036 | if (ring->me == me_id && ring->pipe == pipe_id) |
9037 | drm_sched_fault(sched: &ring->sched); |
9038 | } |
9039 | break; |
9040 | case 1: |
9041 | case 2: |
9042 | for (i = 0; i < adev->gfx.num_compute_rings; i++) { |
9043 | ring = &adev->gfx.compute_ring[i]; |
9044 | if (ring->me == me_id && ring->pipe == pipe_id && |
9045 | ring->queue == queue_id) |
9046 | drm_sched_fault(sched: &ring->sched); |
9047 | } |
9048 | break; |
9049 | default: |
9050 | BUG(); |
9051 | } |
9052 | } |
9053 | |
9054 | static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev, |
9055 | struct amdgpu_irq_src *source, |
9056 | struct amdgpu_iv_entry *entry) |
9057 | { |
9058 | DRM_ERROR("Illegal register access in command stream\n" ); |
9059 | gfx_v10_0_handle_priv_fault(adev, entry); |
9060 | return 0; |
9061 | } |
9062 | |
9063 | static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev, |
9064 | struct amdgpu_irq_src *source, |
9065 | struct amdgpu_iv_entry *entry) |
9066 | { |
9067 | DRM_ERROR("Illegal instruction in command stream\n" ); |
9068 | gfx_v10_0_handle_priv_fault(adev, entry); |
9069 | return 0; |
9070 | } |
9071 | |
9072 | static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev, |
9073 | struct amdgpu_irq_src *src, |
9074 | unsigned int type, |
9075 | enum amdgpu_interrupt_state state) |
9076 | { |
9077 | uint32_t tmp, target; |
9078 | struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring); |
9079 | |
9080 | if (ring->me == 1) |
9081 | target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); |
9082 | else |
9083 | target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL); |
9084 | target += ring->pipe; |
9085 | |
9086 | switch (type) { |
9087 | case AMDGPU_CP_KIQ_IRQ_DRIVER0: |
9088 | if (state == AMDGPU_IRQ_STATE_DISABLE) { |
9089 | tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); |
9090 | tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, |
9091 | GENERIC2_INT_ENABLE, 0); |
9092 | WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); |
9093 | |
9094 | tmp = RREG32_SOC15_IP(GC, target); |
9095 | tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, |
9096 | GENERIC2_INT_ENABLE, 0); |
9097 | WREG32_SOC15_IP(GC, target, tmp); |
9098 | } else { |
9099 | tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); |
9100 | tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, |
9101 | GENERIC2_INT_ENABLE, 1); |
9102 | WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); |
9103 | |
9104 | tmp = RREG32_SOC15_IP(GC, target); |
9105 | tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, |
9106 | GENERIC2_INT_ENABLE, 1); |
9107 | WREG32_SOC15_IP(GC, target, tmp); |
9108 | } |
9109 | break; |
9110 | default: |
9111 | BUG(); /* kiq only support GENERIC2_INT now */ |
9112 | break; |
9113 | } |
9114 | return 0; |
9115 | } |
9116 | |
9117 | static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev, |
9118 | struct amdgpu_irq_src *source, |
9119 | struct amdgpu_iv_entry *entry) |
9120 | { |
9121 | u8 me_id, pipe_id, queue_id; |
9122 | struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring); |
9123 | |
9124 | me_id = (entry->ring_id & 0x0c) >> 2; |
9125 | pipe_id = (entry->ring_id & 0x03) >> 0; |
9126 | queue_id = (entry->ring_id & 0x70) >> 4; |
9127 | DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n" , |
9128 | me_id, pipe_id, queue_id); |
9129 | |
9130 | amdgpu_fence_process(ring); |
9131 | return 0; |
9132 | } |
9133 | |
9134 | static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring) |
9135 | { |
9136 | const unsigned int gcr_cntl = |
9137 | PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | |
9138 | PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | |
9139 | PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | |
9140 | PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | |
9141 | PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | |
9142 | PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | |
9143 | PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | |
9144 | PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); |
9145 | |
9146 | /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ |
9147 | amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); |
9148 | amdgpu_ring_write(ring, v: 0); /* CP_COHER_CNTL */ |
9149 | amdgpu_ring_write(ring, v: 0xffffffff); /* CP_COHER_SIZE */ |
9150 | amdgpu_ring_write(ring, v: 0xffffff); /* CP_COHER_SIZE_HI */ |
9151 | amdgpu_ring_write(ring, v: 0); /* CP_COHER_BASE */ |
9152 | amdgpu_ring_write(ring, v: 0); /* CP_COHER_BASE_HI */ |
9153 | amdgpu_ring_write(ring, v: 0x0000000A); /* POLL_INTERVAL */ |
9154 | amdgpu_ring_write(ring, v: gcr_cntl); /* GCR_CNTL */ |
9155 | } |
9156 | |
9157 | static const struct amd_ip_funcs gfx_v10_0_ip_funcs = { |
9158 | .name = "gfx_v10_0" , |
9159 | .early_init = gfx_v10_0_early_init, |
9160 | .late_init = gfx_v10_0_late_init, |
9161 | .sw_init = gfx_v10_0_sw_init, |
9162 | .sw_fini = gfx_v10_0_sw_fini, |
9163 | .hw_init = gfx_v10_0_hw_init, |
9164 | .hw_fini = gfx_v10_0_hw_fini, |
9165 | .suspend = gfx_v10_0_suspend, |
9166 | .resume = gfx_v10_0_resume, |
9167 | .is_idle = gfx_v10_0_is_idle, |
9168 | .wait_for_idle = gfx_v10_0_wait_for_idle, |
9169 | .soft_reset = gfx_v10_0_soft_reset, |
9170 | .set_clockgating_state = gfx_v10_0_set_clockgating_state, |
9171 | .set_powergating_state = gfx_v10_0_set_powergating_state, |
9172 | .get_clockgating_state = gfx_v10_0_get_clockgating_state, |
9173 | }; |
9174 | |
9175 | static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = { |
9176 | .type = AMDGPU_RING_TYPE_GFX, |
9177 | .align_mask = 0xff, |
9178 | .nop = PACKET3(PACKET3_NOP, 0x3FFF), |
9179 | .support_64bit_ptrs = true, |
9180 | .secure_submission_supported = true, |
9181 | .get_rptr = gfx_v10_0_ring_get_rptr_gfx, |
9182 | .get_wptr = gfx_v10_0_ring_get_wptr_gfx, |
9183 | .set_wptr = gfx_v10_0_ring_set_wptr_gfx, |
9184 | .emit_frame_size = /* totally 242 maximum if 16 IBs */ |
9185 | 5 + /* COND_EXEC */ |
9186 | 7 + /* PIPELINE_SYNC */ |
9187 | SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + |
9188 | SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + |
9189 | 2 + /* VM_FLUSH */ |
9190 | 8 + /* FENCE for VM_FLUSH */ |
9191 | 20 + /* GDS switch */ |
9192 | 4 + /* double SWITCH_BUFFER, |
9193 | * the first COND_EXEC jump to the place |
9194 | * just prior to this double SWITCH_BUFFER |
9195 | */ |
9196 | 5 + /* COND_EXEC */ |
9197 | 7 + /* HDP_flush */ |
9198 | 4 + /* VGT_flush */ |
9199 | 14 + /* CE_META */ |
9200 | 31 + /* DE_META */ |
9201 | 3 + /* CNTX_CTRL */ |
9202 | 5 + /* HDP_INVL */ |
9203 | 8 + 8 + /* FENCE x2 */ |
9204 | 2 + /* SWITCH_BUFFER */ |
9205 | 8, /* gfx_v10_0_emit_mem_sync */ |
9206 | .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */ |
9207 | .emit_ib = gfx_v10_0_ring_emit_ib_gfx, |
9208 | .emit_fence = gfx_v10_0_ring_emit_fence, |
9209 | .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, |
9210 | .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, |
9211 | .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, |
9212 | .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, |
9213 | .test_ring = gfx_v10_0_ring_test_ring, |
9214 | .test_ib = gfx_v10_0_ring_test_ib, |
9215 | .insert_nop = amdgpu_ring_insert_nop, |
9216 | .pad_ib = amdgpu_ring_generic_pad_ib, |
9217 | .emit_switch_buffer = gfx_v10_0_ring_emit_sb, |
9218 | .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl, |
9219 | .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec, |
9220 | .preempt_ib = gfx_v10_0_ring_preempt_ib, |
9221 | .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl, |
9222 | .emit_wreg = gfx_v10_0_ring_emit_wreg, |
9223 | .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, |
9224 | .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, |
9225 | .soft_recovery = gfx_v10_0_ring_soft_recovery, |
9226 | .emit_mem_sync = gfx_v10_0_emit_mem_sync, |
9227 | }; |
9228 | |
9229 | static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = { |
9230 | .type = AMDGPU_RING_TYPE_COMPUTE, |
9231 | .align_mask = 0xff, |
9232 | .nop = PACKET3(PACKET3_NOP, 0x3FFF), |
9233 | .support_64bit_ptrs = true, |
9234 | .get_rptr = gfx_v10_0_ring_get_rptr_compute, |
9235 | .get_wptr = gfx_v10_0_ring_get_wptr_compute, |
9236 | .set_wptr = gfx_v10_0_ring_set_wptr_compute, |
9237 | .emit_frame_size = |
9238 | 20 + /* gfx_v10_0_ring_emit_gds_switch */ |
9239 | 7 + /* gfx_v10_0_ring_emit_hdp_flush */ |
9240 | 5 + /* hdp invalidate */ |
9241 | 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ |
9242 | SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + |
9243 | SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + |
9244 | 2 + /* gfx_v10_0_ring_emit_vm_flush */ |
9245 | 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */ |
9246 | 8, /* gfx_v10_0_emit_mem_sync */ |
9247 | .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ |
9248 | .emit_ib = gfx_v10_0_ring_emit_ib_compute, |
9249 | .emit_fence = gfx_v10_0_ring_emit_fence, |
9250 | .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, |
9251 | .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, |
9252 | .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, |
9253 | .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, |
9254 | .test_ring = gfx_v10_0_ring_test_ring, |
9255 | .test_ib = gfx_v10_0_ring_test_ib, |
9256 | .insert_nop = amdgpu_ring_insert_nop, |
9257 | .pad_ib = amdgpu_ring_generic_pad_ib, |
9258 | .emit_wreg = gfx_v10_0_ring_emit_wreg, |
9259 | .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, |
9260 | .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, |
9261 | .emit_mem_sync = gfx_v10_0_emit_mem_sync, |
9262 | }; |
9263 | |
9264 | static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = { |
9265 | .type = AMDGPU_RING_TYPE_KIQ, |
9266 | .align_mask = 0xff, |
9267 | .nop = PACKET3(PACKET3_NOP, 0x3FFF), |
9268 | .support_64bit_ptrs = true, |
9269 | .get_rptr = gfx_v10_0_ring_get_rptr_compute, |
9270 | .get_wptr = gfx_v10_0_ring_get_wptr_compute, |
9271 | .set_wptr = gfx_v10_0_ring_set_wptr_compute, |
9272 | .emit_frame_size = |
9273 | 20 + /* gfx_v10_0_ring_emit_gds_switch */ |
9274 | 7 + /* gfx_v10_0_ring_emit_hdp_flush */ |
9275 | 5 + /*hdp invalidate */ |
9276 | 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ |
9277 | SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + |
9278 | SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + |
9279 | 2 + /* gfx_v10_0_ring_emit_vm_flush */ |
9280 | 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */ |
9281 | .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ |
9282 | .emit_ib = gfx_v10_0_ring_emit_ib_compute, |
9283 | .emit_fence = gfx_v10_0_ring_emit_fence_kiq, |
9284 | .test_ring = gfx_v10_0_ring_test_ring, |
9285 | .test_ib = gfx_v10_0_ring_test_ib, |
9286 | .insert_nop = amdgpu_ring_insert_nop, |
9287 | .pad_ib = amdgpu_ring_generic_pad_ib, |
9288 | .emit_rreg = gfx_v10_0_ring_emit_rreg, |
9289 | .emit_wreg = gfx_v10_0_ring_emit_wreg, |
9290 | .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, |
9291 | .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, |
9292 | }; |
9293 | |
9294 | static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev) |
9295 | { |
9296 | int i; |
9297 | |
9298 | adev->gfx.kiq[0].ring.funcs = &gfx_v10_0_ring_funcs_kiq; |
9299 | |
9300 | for (i = 0; i < adev->gfx.num_gfx_rings; i++) |
9301 | adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx; |
9302 | |
9303 | for (i = 0; i < adev->gfx.num_compute_rings; i++) |
9304 | adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute; |
9305 | } |
9306 | |
9307 | static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = { |
9308 | .set = gfx_v10_0_set_eop_interrupt_state, |
9309 | .process = gfx_v10_0_eop_irq, |
9310 | }; |
9311 | |
9312 | static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = { |
9313 | .set = gfx_v10_0_set_priv_reg_fault_state, |
9314 | .process = gfx_v10_0_priv_reg_irq, |
9315 | }; |
9316 | |
9317 | static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = { |
9318 | .set = gfx_v10_0_set_priv_inst_fault_state, |
9319 | .process = gfx_v10_0_priv_inst_irq, |
9320 | }; |
9321 | |
9322 | static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = { |
9323 | .set = gfx_v10_0_kiq_set_interrupt_state, |
9324 | .process = gfx_v10_0_kiq_irq, |
9325 | }; |
9326 | |
9327 | static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev) |
9328 | { |
9329 | adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; |
9330 | adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs; |
9331 | |
9332 | adev->gfx.kiq[0].irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST; |
9333 | adev->gfx.kiq[0].irq.funcs = &gfx_v10_0_kiq_irq_funcs; |
9334 | |
9335 | adev->gfx.priv_reg_irq.num_types = 1; |
9336 | adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs; |
9337 | |
9338 | adev->gfx.priv_inst_irq.num_types = 1; |
9339 | adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs; |
9340 | } |
9341 | |
9342 | static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev) |
9343 | { |
9344 | switch (amdgpu_ip_version(adev, ip: GC_HWIP, inst: 0)) { |
9345 | case IP_VERSION(10, 1, 10): |
9346 | case IP_VERSION(10, 1, 1): |
9347 | case IP_VERSION(10, 1, 3): |
9348 | case IP_VERSION(10, 1, 4): |
9349 | case IP_VERSION(10, 3, 2): |
9350 | case IP_VERSION(10, 3, 1): |
9351 | case IP_VERSION(10, 3, 4): |
9352 | case IP_VERSION(10, 3, 5): |
9353 | case IP_VERSION(10, 3, 6): |
9354 | case IP_VERSION(10, 3, 3): |
9355 | case IP_VERSION(10, 3, 7): |
9356 | adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs; |
9357 | break; |
9358 | case IP_VERSION(10, 1, 2): |
9359 | case IP_VERSION(10, 3, 0): |
9360 | adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov; |
9361 | break; |
9362 | default: |
9363 | break; |
9364 | } |
9365 | } |
9366 | |
9367 | static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev) |
9368 | { |
9369 | unsigned int total_cu = adev->gfx.config.max_cu_per_sh * |
9370 | adev->gfx.config.max_sh_per_se * |
9371 | adev->gfx.config.max_shader_engines; |
9372 | |
9373 | adev->gds.gds_size = 0x10000; |
9374 | adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1; |
9375 | adev->gds.gws_size = 64; |
9376 | adev->gds.oa_size = 16; |
9377 | } |
9378 | |
9379 | static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev) |
9380 | { |
9381 | /* set gfx eng mqd */ |
9382 | adev->mqds[AMDGPU_HW_IP_GFX].mqd_size = |
9383 | sizeof(struct v10_gfx_mqd); |
9384 | adev->mqds[AMDGPU_HW_IP_GFX].init_mqd = |
9385 | gfx_v10_0_gfx_mqd_init; |
9386 | /* set compute eng mqd */ |
9387 | adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size = |
9388 | sizeof(struct v10_compute_mqd); |
9389 | adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd = |
9390 | gfx_v10_0_compute_mqd_init; |
9391 | } |
9392 | |
9393 | static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, |
9394 | u32 bitmap) |
9395 | { |
9396 | u32 data; |
9397 | |
9398 | if (!bitmap) |
9399 | return; |
9400 | |
9401 | data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; |
9402 | data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; |
9403 | |
9404 | WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data); |
9405 | } |
9406 | |
9407 | static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) |
9408 | { |
9409 | u32 disabled_mask = |
9410 | ~amdgpu_gfx_create_bitmask(bit_width: adev->gfx.config.max_cu_per_sh >> 1); |
9411 | u32 efuse_setting = 0; |
9412 | u32 vbios_setting = 0; |
9413 | |
9414 | efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG); |
9415 | efuse_setting &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; |
9416 | efuse_setting >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; |
9417 | |
9418 | vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG); |
9419 | vbios_setting &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; |
9420 | vbios_setting >>= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; |
9421 | |
9422 | disabled_mask |= efuse_setting | vbios_setting; |
9423 | |
9424 | return (~disabled_mask); |
9425 | } |
9426 | |
9427 | static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) |
9428 | { |
9429 | u32 wgp_idx, wgp_active_bitmap; |
9430 | u32 cu_bitmap_per_wgp, cu_active_bitmap; |
9431 | |
9432 | wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); |
9433 | cu_active_bitmap = 0; |
9434 | |
9435 | for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { |
9436 | /* if there is one WGP enabled, it means 2 CUs will be enabled */ |
9437 | cu_bitmap_per_wgp = 3 << (2 * wgp_idx); |
9438 | if (wgp_active_bitmap & (1 << wgp_idx)) |
9439 | cu_active_bitmap |= cu_bitmap_per_wgp; |
9440 | } |
9441 | |
9442 | return cu_active_bitmap; |
9443 | } |
9444 | |
9445 | static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, |
9446 | struct amdgpu_cu_info *cu_info) |
9447 | { |
9448 | int i, j, k, counter, active_cu_number = 0; |
9449 | u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; |
9450 | unsigned int disable_masks[4 * 2]; |
9451 | |
9452 | if (!adev || !cu_info) |
9453 | return -EINVAL; |
9454 | |
9455 | amdgpu_gfx_parse_disable_cu(mask: disable_masks, max_se: 4, max_sh: 2); |
9456 | |
9457 | mutex_lock(&adev->grbm_idx_mutex); |
9458 | for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { |
9459 | for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { |
9460 | bitmap = i * adev->gfx.config.max_sh_per_se + j; |
9461 | if (((amdgpu_ip_version(adev, ip: GC_HWIP, inst: 0) == |
9462 | IP_VERSION(10, 3, 0)) || |
9463 | (amdgpu_ip_version(adev, ip: GC_HWIP, inst: 0) == |
9464 | IP_VERSION(10, 3, 3)) || |
9465 | (amdgpu_ip_version(adev, ip: GC_HWIP, inst: 0) == |
9466 | IP_VERSION(10, 3, 6)) || |
9467 | (amdgpu_ip_version(adev, ip: GC_HWIP, inst: 0) == |
9468 | IP_VERSION(10, 3, 7))) && |
9469 | ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1)) |
9470 | continue; |
9471 | mask = 1; |
9472 | ao_bitmap = 0; |
9473 | counter = 0; |
9474 | gfx_v10_0_select_se_sh(adev, se_num: i, sh_num: j, instance: 0xffffffff, xcc_id: 0); |
9475 | if (i < 4 && j < 2) |
9476 | gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh( |
9477 | adev, bitmap: disable_masks[i * 2 + j]); |
9478 | bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev); |
9479 | cu_info->bitmap[0][i][j] = bitmap; |
9480 | |
9481 | for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { |
9482 | if (bitmap & mask) { |
9483 | if (counter < adev->gfx.config.max_cu_per_sh) |
9484 | ao_bitmap |= mask; |
9485 | counter++; |
9486 | } |
9487 | mask <<= 1; |
9488 | } |
9489 | active_cu_number += counter; |
9490 | if (i < 2 && j < 2) |
9491 | ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); |
9492 | cu_info->ao_cu_bitmap[i][j] = ao_bitmap; |
9493 | } |
9494 | } |
9495 | gfx_v10_0_select_se_sh(adev, se_num: 0xffffffff, sh_num: 0xffffffff, instance: 0xffffffff, xcc_id: 0); |
9496 | mutex_unlock(lock: &adev->grbm_idx_mutex); |
9497 | |
9498 | cu_info->number = active_cu_number; |
9499 | cu_info->ao_cu_mask = ao_cu_mask; |
9500 | cu_info->simd_per_cu = NUM_SIMD_PER_CU; |
9501 | |
9502 | return 0; |
9503 | } |
9504 | |
9505 | static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev) |
9506 | { |
9507 | uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask; |
9508 | |
9509 | efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE); |
9510 | efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK; |
9511 | efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; |
9512 | |
9513 | vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE); |
9514 | vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK; |
9515 | vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; |
9516 | |
9517 | max_sa_mask = amdgpu_gfx_create_bitmask(bit_width: adev->gfx.config.max_sh_per_se * |
9518 | adev->gfx.config.max_shader_engines); |
9519 | disabled_sa = efuse_setting | vbios_setting; |
9520 | disabled_sa &= max_sa_mask; |
9521 | |
9522 | return disabled_sa; |
9523 | } |
9524 | |
9525 | static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev) |
9526 | { |
9527 | uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines; |
9528 | uint32_t disabled_sa_mask, se_index, disabled_sa_per_se; |
9529 | |
9530 | disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev); |
9531 | |
9532 | max_sa_per_se = adev->gfx.config.max_sh_per_se; |
9533 | max_sa_per_se_mask = (1 << max_sa_per_se) - 1; |
9534 | max_shader_engines = adev->gfx.config.max_shader_engines; |
9535 | |
9536 | for (se_index = 0; max_shader_engines > se_index; se_index++) { |
9537 | disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se); |
9538 | disabled_sa_per_se &= max_sa_per_se_mask; |
9539 | if (disabled_sa_per_se == max_sa_per_se_mask) { |
9540 | WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1); |
9541 | break; |
9542 | } |
9543 | } |
9544 | } |
9545 | |
9546 | static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev) |
9547 | { |
9548 | WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, |
9549 | (0x1 << GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT) | |
9550 | (0x1 << GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT) | |
9551 | (0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT)); |
9552 | |
9553 | WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL); |
9554 | WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, |
9555 | (0x1 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT) | |
9556 | (0x12 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT) | |
9557 | (0x13 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT) | |
9558 | (0xf << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT)); |
9559 | |
9560 | WREG32_SOC15(GC, 0, mmGC_THROTTLE_CTRL_Sienna_Cichlid, |
9561 | (0x1 << GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT) | |
9562 | (0x1 << GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT) | |
9563 | (0x5 << GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT)); |
9564 | |
9565 | WREG32_SOC15(GC, 0, mmDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL); |
9566 | |
9567 | WREG32_SOC15(GC, 0, mmDIDT_IND_DATA, |
9568 | (0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT)); |
9569 | } |
9570 | |
9571 | const struct amdgpu_ip_block_version gfx_v10_0_ip_block = { |
9572 | .type = AMD_IP_BLOCK_TYPE_GFX, |
9573 | .major = 10, |
9574 | .minor = 0, |
9575 | .rev = 0, |
9576 | .funcs = &gfx_v10_0_ip_funcs, |
9577 | }; |
9578 | |