1/*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27#include "dm_services.h"
28#include "dc.h"
29
30#include "dcn30_init.h"
31
32#include "resource.h"
33#include "include/irq_service_interface.h"
34#include "dcn20/dcn20_resource.h"
35
36#include "dcn30_resource.h"
37
38#include "dcn10/dcn10_ipp.h"
39#include "dcn30/dcn30_hubbub.h"
40#include "dcn30/dcn30_mpc.h"
41#include "dcn30/dcn30_hubp.h"
42#include "irq/dcn30/irq_service_dcn30.h"
43#include "dcn30/dcn30_dpp.h"
44#include "dcn30/dcn30_optc.h"
45#include "dcn20/dcn20_hwseq.h"
46#include "dcn30/dcn30_hwseq.h"
47#include "dce110/dce110_hwseq.h"
48#include "dcn30/dcn30_opp.h"
49#include "dcn20/dcn20_dsc.h"
50#include "dcn30/dcn30_vpg.h"
51#include "dcn30/dcn30_afmt.h"
52#include "dcn30/dcn30_dio_stream_encoder.h"
53#include "dcn30/dcn30_dio_link_encoder.h"
54#include "dce/dce_clock_source.h"
55#include "dce/dce_audio.h"
56#include "dce/dce_hwseq.h"
57#include "clk_mgr.h"
58#include "virtual/virtual_stream_encoder.h"
59#include "dce110/dce110_resource.h"
60#include "dml/display_mode_vba.h"
61#include "dcn30/dcn30_dccg.h"
62#include "dcn10/dcn10_resource.h"
63#include "link.h"
64#include "dce/dce_panel_cntl.h"
65
66#include "dcn30/dcn30_dwb.h"
67#include "dcn30/dcn30_mmhubbub.h"
68
69#include "sienna_cichlid_ip_offset.h"
70#include "dcn/dcn_3_0_0_offset.h"
71#include "dcn/dcn_3_0_0_sh_mask.h"
72
73#include "nbio/nbio_7_4_offset.h"
74
75#include "dpcs/dpcs_3_0_0_offset.h"
76#include "dpcs/dpcs_3_0_0_sh_mask.h"
77
78#include "mmhub/mmhub_2_0_0_offset.h"
79#include "mmhub/mmhub_2_0_0_sh_mask.h"
80
81#include "reg_helper.h"
82#include "dce/dmub_abm.h"
83#include "dce/dmub_psr.h"
84#include "dce/dce_aux.h"
85#include "dce/dce_i2c.h"
86
87#include "dml/dcn30/dcn30_fpu.h"
88#include "dml/dcn30/display_mode_vba_30.h"
89#include "vm_helper.h"
90#include "dcn20/dcn20_vmid.h"
91#include "amdgpu_socbb.h"
92#include "dc_dmub_srv.h"
93
94#define DC_LOGGER \
95 dc->ctx->logger
96#define DC_LOGGER_INIT(logger)
97
98enum dcn30_clk_src_array_id {
99 DCN30_CLK_SRC_PLL0,
100 DCN30_CLK_SRC_PLL1,
101 DCN30_CLK_SRC_PLL2,
102 DCN30_CLK_SRC_PLL3,
103 DCN30_CLK_SRC_PLL4,
104 DCN30_CLK_SRC_PLL5,
105 DCN30_CLK_SRC_TOTAL
106};
107
108/* begin *********************
109 * macros to expend register list macro defined in HW object header file
110 */
111
112/* DCN */
113#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
114
115#define BASE(seg) BASE_INNER(seg)
116
117#define SR(reg_name)\
118 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
119 mm ## reg_name
120
121#define SRI(reg_name, block, id)\
122 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
123 mm ## block ## id ## _ ## reg_name
124
125#define SRI2(reg_name, block, id)\
126 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
127 mm ## reg_name
128
129#define SRIR(var_name, reg_name, block, id)\
130 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
131 mm ## block ## id ## _ ## reg_name
132
133#define SRII(reg_name, block, id)\
134 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
135 mm ## block ## id ## _ ## reg_name
136
137#define SRII_MPC_RMU(reg_name, block, id)\
138 .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
139 mm ## block ## id ## _ ## reg_name
140
141#define SRII_DWB(reg_name, temp_name, block, id)\
142 .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
143 mm ## block ## id ## _ ## temp_name
144
145#define SF_DWB2(reg_name, block, id, field_name, post_fix) \
146 .field_name = reg_name ## __ ## field_name ## post_fix
147
148#define DCCG_SRII(reg_name, block, id)\
149 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
150 mm ## block ## id ## _ ## reg_name
151
152#define VUPDATE_SRII(reg_name, block, id)\
153 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
154 mm ## reg_name ## _ ## block ## id
155
156/* NBIO */
157#define NBIO_BASE_INNER(seg) \
158 NBIO_BASE__INST0_SEG ## seg
159
160#define NBIO_BASE(seg) \
161 NBIO_BASE_INNER(seg)
162
163#define NBIO_SR(reg_name)\
164 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
165 mm ## reg_name
166
167/* MMHUB */
168#define MMHUB_BASE_INNER(seg) \
169 MMHUB_BASE__INST0_SEG ## seg
170
171#define MMHUB_BASE(seg) \
172 MMHUB_BASE_INNER(seg)
173
174#define MMHUB_SR(reg_name)\
175 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
176 mmMM ## reg_name
177
178/* CLOCK */
179#define CLK_BASE_INNER(seg) \
180 CLK_BASE__INST0_SEG ## seg
181
182#define CLK_BASE(seg) \
183 CLK_BASE_INNER(seg)
184
185#define CLK_SRI(reg_name, block, inst)\
186 .reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
187 mm ## block ## _ ## inst ## _ ## reg_name
188
189
190static const struct bios_registers bios_regs = {
191 NBIO_SR(BIOS_SCRATCH_3),
192 NBIO_SR(BIOS_SCRATCH_6)
193};
194
195#define clk_src_regs(index, pllid)\
196[index] = {\
197 CS_COMMON_REG_LIST_DCN2_0(index, pllid),\
198}
199
200static const struct dce110_clk_src_regs clk_src_regs[] = {
201 clk_src_regs(0, A),
202 clk_src_regs(1, B),
203 clk_src_regs(2, C),
204 clk_src_regs(3, D),
205 clk_src_regs(4, E),
206 clk_src_regs(5, F)
207};
208
209static const struct dce110_clk_src_shift cs_shift = {
210 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
211};
212
213static const struct dce110_clk_src_mask cs_mask = {
214 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
215};
216
217#define abm_regs(id)\
218[id] = {\
219 ABM_DCN30_REG_LIST(id)\
220}
221
222static const struct dce_abm_registers abm_regs[] = {
223 abm_regs(0),
224 abm_regs(1),
225 abm_regs(2),
226 abm_regs(3),
227 abm_regs(4),
228 abm_regs(5),
229};
230
231static const struct dce_abm_shift abm_shift = {
232 ABM_MASK_SH_LIST_DCN30(__SHIFT)
233};
234
235static const struct dce_abm_mask abm_mask = {
236 ABM_MASK_SH_LIST_DCN30(_MASK)
237};
238
239
240
241#define audio_regs(id)\
242[id] = {\
243 AUD_COMMON_REG_LIST(id)\
244}
245
246static const struct dce_audio_registers audio_regs[] = {
247 audio_regs(0),
248 audio_regs(1),
249 audio_regs(2),
250 audio_regs(3),
251 audio_regs(4),
252 audio_regs(5),
253 audio_regs(6)
254};
255
256#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
257 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
258 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
259 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
260
261static const struct dce_audio_shift audio_shift = {
262 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
263};
264
265static const struct dce_audio_mask audio_mask = {
266 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
267};
268
269#define vpg_regs(id)\
270[id] = {\
271 VPG_DCN3_REG_LIST(id)\
272}
273
274static const struct dcn30_vpg_registers vpg_regs[] = {
275 vpg_regs(0),
276 vpg_regs(1),
277 vpg_regs(2),
278 vpg_regs(3),
279 vpg_regs(4),
280 vpg_regs(5),
281 vpg_regs(6),
282};
283
284static const struct dcn30_vpg_shift vpg_shift = {
285 DCN3_VPG_MASK_SH_LIST(__SHIFT)
286};
287
288static const struct dcn30_vpg_mask vpg_mask = {
289 DCN3_VPG_MASK_SH_LIST(_MASK)
290};
291
292#define afmt_regs(id)\
293[id] = {\
294 AFMT_DCN3_REG_LIST(id)\
295}
296
297static const struct dcn30_afmt_registers afmt_regs[] = {
298 afmt_regs(0),
299 afmt_regs(1),
300 afmt_regs(2),
301 afmt_regs(3),
302 afmt_regs(4),
303 afmt_regs(5),
304 afmt_regs(6),
305};
306
307static const struct dcn30_afmt_shift afmt_shift = {
308 DCN3_AFMT_MASK_SH_LIST(__SHIFT)
309};
310
311static const struct dcn30_afmt_mask afmt_mask = {
312 DCN3_AFMT_MASK_SH_LIST(_MASK)
313};
314
315#define stream_enc_regs(id)\
316[id] = {\
317 SE_DCN3_REG_LIST(id)\
318}
319
320static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
321 stream_enc_regs(0),
322 stream_enc_regs(1),
323 stream_enc_regs(2),
324 stream_enc_regs(3),
325 stream_enc_regs(4),
326 stream_enc_regs(5)
327};
328
329static const struct dcn10_stream_encoder_shift se_shift = {
330 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
331};
332
333static const struct dcn10_stream_encoder_mask se_mask = {
334 SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
335};
336
337
338#define aux_regs(id)\
339[id] = {\
340 DCN2_AUX_REG_LIST(id)\
341}
342
343static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
344 aux_regs(0),
345 aux_regs(1),
346 aux_regs(2),
347 aux_regs(3),
348 aux_regs(4),
349 aux_regs(5)
350};
351
352#define hpd_regs(id)\
353[id] = {\
354 HPD_REG_LIST(id)\
355}
356
357static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
358 hpd_regs(0),
359 hpd_regs(1),
360 hpd_regs(2),
361 hpd_regs(3),
362 hpd_regs(4),
363 hpd_regs(5)
364};
365
366#define link_regs(id, phyid)\
367[id] = {\
368 LE_DCN3_REG_LIST(id), \
369 UNIPHY_DCN2_REG_LIST(phyid), \
370 DPCS_DCN2_REG_LIST(id), \
371 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
372}
373
374static const struct dce110_aux_registers_shift aux_shift = {
375 DCN_AUX_MASK_SH_LIST(__SHIFT)
376};
377
378static const struct dce110_aux_registers_mask aux_mask = {
379 DCN_AUX_MASK_SH_LIST(_MASK)
380};
381
382static const struct dcn10_link_enc_registers link_enc_regs[] = {
383 link_regs(0, A),
384 link_regs(1, B),
385 link_regs(2, C),
386 link_regs(3, D),
387 link_regs(4, E),
388 link_regs(5, F)
389};
390
391static const struct dcn10_link_enc_shift le_shift = {
392 LINK_ENCODER_MASK_SH_LIST_DCN30(__SHIFT),\
393 DPCS_DCN2_MASK_SH_LIST(__SHIFT)
394};
395
396static const struct dcn10_link_enc_mask le_mask = {
397 LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK),\
398 DPCS_DCN2_MASK_SH_LIST(_MASK)
399};
400
401
402static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
403 { DCN_PANEL_CNTL_REG_LIST() }
404};
405
406static const struct dce_panel_cntl_shift panel_cntl_shift = {
407 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
408};
409
410static const struct dce_panel_cntl_mask panel_cntl_mask = {
411 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
412};
413
414#define dpp_regs(id)\
415[id] = {\
416 DPP_REG_LIST_DCN30(id),\
417}
418
419static const struct dcn3_dpp_registers dpp_regs[] = {
420 dpp_regs(0),
421 dpp_regs(1),
422 dpp_regs(2),
423 dpp_regs(3),
424 dpp_regs(4),
425 dpp_regs(5),
426};
427
428static const struct dcn3_dpp_shift tf_shift = {
429 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
430};
431
432static const struct dcn3_dpp_mask tf_mask = {
433 DPP_REG_LIST_SH_MASK_DCN30(_MASK)
434};
435
436#define opp_regs(id)\
437[id] = {\
438 OPP_REG_LIST_DCN30(id),\
439}
440
441static const struct dcn20_opp_registers opp_regs[] = {
442 opp_regs(0),
443 opp_regs(1),
444 opp_regs(2),
445 opp_regs(3),
446 opp_regs(4),
447 opp_regs(5)
448};
449
450static const struct dcn20_opp_shift opp_shift = {
451 OPP_MASK_SH_LIST_DCN20(__SHIFT)
452};
453
454static const struct dcn20_opp_mask opp_mask = {
455 OPP_MASK_SH_LIST_DCN20(_MASK)
456};
457
458#define aux_engine_regs(id)\
459[id] = {\
460 AUX_COMMON_REG_LIST0(id), \
461 .AUXN_IMPCAL = 0, \
462 .AUXP_IMPCAL = 0, \
463 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
464}
465
466static const struct dce110_aux_registers aux_engine_regs[] = {
467 aux_engine_regs(0),
468 aux_engine_regs(1),
469 aux_engine_regs(2),
470 aux_engine_regs(3),
471 aux_engine_regs(4),
472 aux_engine_regs(5)
473};
474
475#define dwbc_regs_dcn3(id)\
476[id] = {\
477 DWBC_COMMON_REG_LIST_DCN30(id),\
478}
479
480static const struct dcn30_dwbc_registers dwbc30_regs[] = {
481 dwbc_regs_dcn3(0),
482};
483
484static const struct dcn30_dwbc_shift dwbc30_shift = {
485 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
486};
487
488static const struct dcn30_dwbc_mask dwbc30_mask = {
489 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
490};
491
492#define mcif_wb_regs_dcn3(id)\
493[id] = {\
494 MCIF_WB_COMMON_REG_LIST_DCN30(id),\
495}
496
497static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
498 mcif_wb_regs_dcn3(0)
499};
500
501static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
502 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
503};
504
505static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
506 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
507};
508
509#define dsc_regsDCN20(id)\
510[id] = {\
511 DSC_REG_LIST_DCN20(id)\
512}
513
514static const struct dcn20_dsc_registers dsc_regs[] = {
515 dsc_regsDCN20(0),
516 dsc_regsDCN20(1),
517 dsc_regsDCN20(2),
518 dsc_regsDCN20(3),
519 dsc_regsDCN20(4),
520 dsc_regsDCN20(5)
521};
522
523static const struct dcn20_dsc_shift dsc_shift = {
524 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
525};
526
527static const struct dcn20_dsc_mask dsc_mask = {
528 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
529};
530
531static const struct dcn30_mpc_registers mpc_regs = {
532 MPC_REG_LIST_DCN3_0(0),
533 MPC_REG_LIST_DCN3_0(1),
534 MPC_REG_LIST_DCN3_0(2),
535 MPC_REG_LIST_DCN3_0(3),
536 MPC_REG_LIST_DCN3_0(4),
537 MPC_REG_LIST_DCN3_0(5),
538 MPC_OUT_MUX_REG_LIST_DCN3_0(0),
539 MPC_OUT_MUX_REG_LIST_DCN3_0(1),
540 MPC_OUT_MUX_REG_LIST_DCN3_0(2),
541 MPC_OUT_MUX_REG_LIST_DCN3_0(3),
542 MPC_OUT_MUX_REG_LIST_DCN3_0(4),
543 MPC_OUT_MUX_REG_LIST_DCN3_0(5),
544 MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
545 MPC_RMU_REG_LIST_DCN3AG(0),
546 MPC_RMU_REG_LIST_DCN3AG(1),
547 MPC_RMU_REG_LIST_DCN3AG(2),
548 MPC_DWB_MUX_REG_LIST_DCN3_0(0),
549};
550
551static const struct dcn30_mpc_shift mpc_shift = {
552 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
553};
554
555static const struct dcn30_mpc_mask mpc_mask = {
556 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
557};
558
559#define optc_regs(id)\
560[id] = {OPTC_COMMON_REG_LIST_DCN3_0(id)}
561
562
563static const struct dcn_optc_registers optc_regs[] = {
564 optc_regs(0),
565 optc_regs(1),
566 optc_regs(2),
567 optc_regs(3),
568 optc_regs(4),
569 optc_regs(5)
570};
571
572static const struct dcn_optc_shift optc_shift = {
573 OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
574};
575
576static const struct dcn_optc_mask optc_mask = {
577 OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK)
578};
579
580#define hubp_regs(id)\
581[id] = {\
582 HUBP_REG_LIST_DCN30(id)\
583}
584
585static const struct dcn_hubp2_registers hubp_regs[] = {
586 hubp_regs(0),
587 hubp_regs(1),
588 hubp_regs(2),
589 hubp_regs(3),
590 hubp_regs(4),
591 hubp_regs(5)
592};
593
594static const struct dcn_hubp2_shift hubp_shift = {
595 HUBP_MASK_SH_LIST_DCN30(__SHIFT)
596};
597
598static const struct dcn_hubp2_mask hubp_mask = {
599 HUBP_MASK_SH_LIST_DCN30(_MASK)
600};
601
602static const struct dcn_hubbub_registers hubbub_reg = {
603 HUBBUB_REG_LIST_DCN30(0)
604};
605
606static const struct dcn_hubbub_shift hubbub_shift = {
607 HUBBUB_MASK_SH_LIST_DCN30(__SHIFT)
608};
609
610static const struct dcn_hubbub_mask hubbub_mask = {
611 HUBBUB_MASK_SH_LIST_DCN30(_MASK)
612};
613
614static const struct dccg_registers dccg_regs = {
615 DCCG_REG_LIST_DCN30()
616};
617
618static const struct dccg_shift dccg_shift = {
619 DCCG_MASK_SH_LIST_DCN3(__SHIFT)
620};
621
622static const struct dccg_mask dccg_mask = {
623 DCCG_MASK_SH_LIST_DCN3(_MASK)
624};
625
626static const struct dce_hwseq_registers hwseq_reg = {
627 HWSEQ_DCN30_REG_LIST()
628};
629
630static const struct dce_hwseq_shift hwseq_shift = {
631 HWSEQ_DCN30_MASK_SH_LIST(__SHIFT)
632};
633
634static const struct dce_hwseq_mask hwseq_mask = {
635 HWSEQ_DCN30_MASK_SH_LIST(_MASK)
636};
637#define vmid_regs(id)\
638[id] = {\
639 DCN20_VMID_REG_LIST(id)\
640}
641
642static const struct dcn_vmid_registers vmid_regs[] = {
643 vmid_regs(0),
644 vmid_regs(1),
645 vmid_regs(2),
646 vmid_regs(3),
647 vmid_regs(4),
648 vmid_regs(5),
649 vmid_regs(6),
650 vmid_regs(7),
651 vmid_regs(8),
652 vmid_regs(9),
653 vmid_regs(10),
654 vmid_regs(11),
655 vmid_regs(12),
656 vmid_regs(13),
657 vmid_regs(14),
658 vmid_regs(15)
659};
660
661static const struct dcn20_vmid_shift vmid_shifts = {
662 DCN20_VMID_MASK_SH_LIST(__SHIFT)
663};
664
665static const struct dcn20_vmid_mask vmid_masks = {
666 DCN20_VMID_MASK_SH_LIST(_MASK)
667};
668
669static const struct resource_caps res_cap_dcn3 = {
670 .num_timing_generator = 6,
671 .num_opp = 6,
672 .num_video_plane = 6,
673 .num_audio = 6,
674 .num_stream_encoder = 6,
675 .num_pll = 6,
676 .num_dwb = 1,
677 .num_ddc = 6,
678 .num_vmid = 16,
679 .num_mpc_3dlut = 3,
680 .num_dsc = 6,
681};
682
683static const struct dc_plane_cap plane_cap = {
684 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
685 .per_pixel_alpha = true,
686
687 .pixel_format_support = {
688 .argb8888 = true,
689 .nv12 = true,
690 .fp16 = true,
691 .p010 = true,
692 .ayuv = false,
693 },
694
695 .max_upscale_factor = {
696 .argb8888 = 16000,
697 .nv12 = 16000,
698 .fp16 = 16000
699 },
700
701 /* 6:1 downscaling ratio: 1000/6 = 166.666 */
702 .max_downscale_factor = {
703 .argb8888 = 167,
704 .nv12 = 167,
705 .fp16 = 167
706 },
707 16,
708 16
709};
710
711static const struct dc_debug_options debug_defaults_drv = {
712 .disable_dmcu = true, //No DMCU on DCN30
713 .force_abm_enable = false,
714 .timing_trace = false,
715 .clock_trace = true,
716 .disable_pplib_clock_request = true,
717 .pipe_split_policy = MPC_SPLIT_DYNAMIC,
718 .force_single_disp_pipe_split = false,
719 .disable_dcc = DCC_ENABLE,
720 .vsr_support = true,
721 .performance_trace = false,
722 .max_downscale_src_width = 7680,/*upto 8K*/
723 .disable_pplib_wm_range = false,
724 .scl_reset_length10 = true,
725 .sanity_checks = false,
726 .underflow_assert_delay_us = 0xFFFFFFFF,
727 .dwb_fi_phase = -1, // -1 = disable,
728 .dmub_command_table = true,
729 .use_max_lb = true,
730 .exit_idle_opt_for_cursor_updates = true,
731 .enable_legacy_fast_update = false,
732 .using_dml2 = false,
733};
734
735static const struct dc_panel_config panel_config_defaults = {
736 .psr = {
737 .disable_psr = false,
738 .disallow_psrsu = false,
739 .disallow_replay = false,
740 },
741};
742
743static void dcn30_dpp_destroy(struct dpp **dpp)
744{
745 kfree(TO_DCN20_DPP(*dpp));
746 *dpp = NULL;
747}
748
749static struct dpp *dcn30_dpp_create(
750 struct dc_context *ctx,
751 uint32_t inst)
752{
753 struct dcn3_dpp *dpp =
754 kzalloc(size: sizeof(struct dcn3_dpp), GFP_KERNEL);
755
756 if (!dpp)
757 return NULL;
758
759 if (dpp3_construct(dpp3: dpp, ctx, inst,
760 tf_regs: &dpp_regs[inst], tf_shift: &tf_shift, tf_mask: &tf_mask))
761 return &dpp->base;
762
763 BREAK_TO_DEBUGGER();
764 kfree(objp: dpp);
765 return NULL;
766}
767
768static struct output_pixel_processor *dcn30_opp_create(
769 struct dc_context *ctx, uint32_t inst)
770{
771 struct dcn20_opp *opp =
772 kzalloc(size: sizeof(struct dcn20_opp), GFP_KERNEL);
773
774 if (!opp) {
775 BREAK_TO_DEBUGGER();
776 return NULL;
777 }
778
779 dcn20_opp_construct(oppn20: opp, ctx, inst,
780 regs: &opp_regs[inst], opp_shift: &opp_shift, opp_mask: &opp_mask);
781 return &opp->base;
782}
783
784static struct dce_aux *dcn30_aux_engine_create(
785 struct dc_context *ctx,
786 uint32_t inst)
787{
788 struct aux_engine_dce110 *aux_engine =
789 kzalloc(size: sizeof(struct aux_engine_dce110), GFP_KERNEL);
790
791 if (!aux_engine)
792 return NULL;
793
794 dce110_aux_engine_construct(aux_engine110: aux_engine, ctx, inst,
795 timeout_period: SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
796 regs: &aux_engine_regs[inst],
797 mask: &aux_mask,
798 shift: &aux_shift,
799 is_ext_aux_timeout_configurable: ctx->dc->caps.extended_aux_timeout_support);
800
801 return &aux_engine->base;
802}
803
804#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }
805
806static const struct dce_i2c_registers i2c_hw_regs[] = {
807 i2c_inst_regs(1),
808 i2c_inst_regs(2),
809 i2c_inst_regs(3),
810 i2c_inst_regs(4),
811 i2c_inst_regs(5),
812 i2c_inst_regs(6),
813};
814
815static const struct dce_i2c_shift i2c_shifts = {
816 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
817};
818
819static const struct dce_i2c_mask i2c_masks = {
820 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
821};
822
823static struct dce_i2c_hw *dcn30_i2c_hw_create(
824 struct dc_context *ctx,
825 uint32_t inst)
826{
827 struct dce_i2c_hw *dce_i2c_hw =
828 kzalloc(size: sizeof(struct dce_i2c_hw), GFP_KERNEL);
829
830 if (!dce_i2c_hw)
831 return NULL;
832
833 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, engine_id: inst,
834 regs: &i2c_hw_regs[inst], shifts: &i2c_shifts, masks: &i2c_masks);
835
836 return dce_i2c_hw;
837}
838
839static struct mpc *dcn30_mpc_create(
840 struct dc_context *ctx,
841 int num_mpcc,
842 int num_rmu)
843{
844 struct dcn30_mpc *mpc30 = kzalloc(size: sizeof(struct dcn30_mpc),
845 GFP_KERNEL);
846
847 if (!mpc30)
848 return NULL;
849
850 dcn30_mpc_construct(mpc30, ctx,
851 mpc_regs: &mpc_regs,
852 mpc_shift: &mpc_shift,
853 mpc_mask: &mpc_mask,
854 num_mpcc,
855 num_rmu);
856
857 return &mpc30->base;
858}
859
860static struct hubbub *dcn30_hubbub_create(struct dc_context *ctx)
861{
862 int i;
863
864 struct dcn20_hubbub *hubbub3 = kzalloc(size: sizeof(struct dcn20_hubbub),
865 GFP_KERNEL);
866
867 if (!hubbub3)
868 return NULL;
869
870 hubbub3_construct(hubbub3, ctx,
871 hubbub_regs: &hubbub_reg,
872 hubbub_shift: &hubbub_shift,
873 hubbub_mask: &hubbub_mask);
874
875
876 for (i = 0; i < res_cap_dcn3.num_vmid; i++) {
877 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
878
879 vmid->ctx = ctx;
880
881 vmid->regs = &vmid_regs[i];
882 vmid->shifts = &vmid_shifts;
883 vmid->masks = &vmid_masks;
884 }
885
886 return &hubbub3->base;
887}
888
889static struct timing_generator *dcn30_timing_generator_create(
890 struct dc_context *ctx,
891 uint32_t instance)
892{
893 struct optc *tgn10 =
894 kzalloc(size: sizeof(struct optc), GFP_KERNEL);
895
896 if (!tgn10)
897 return NULL;
898
899 tgn10->base.inst = instance;
900 tgn10->base.ctx = ctx;
901
902 tgn10->tg_regs = &optc_regs[instance];
903 tgn10->tg_shift = &optc_shift;
904 tgn10->tg_mask = &optc_mask;
905
906 dcn30_timing_generator_init(optc1: tgn10);
907
908 return &tgn10->base;
909}
910
911static const struct encoder_feature_support link_enc_feature = {
912 .max_hdmi_deep_color = COLOR_DEPTH_121212,
913 .max_hdmi_pixel_clock = 600000,
914 .hdmi_ycbcr420_supported = true,
915 .dp_ycbcr420_supported = true,
916 .fec_supported = true,
917 .flags.bits.IS_HBR2_CAPABLE = true,
918 .flags.bits.IS_HBR3_CAPABLE = true,
919 .flags.bits.IS_TPS3_CAPABLE = true,
920 .flags.bits.IS_TPS4_CAPABLE = true
921};
922
923static struct link_encoder *dcn30_link_encoder_create(
924 struct dc_context *ctx,
925 const struct encoder_init_data *enc_init_data)
926{
927 struct dcn20_link_encoder *enc20 =
928 kzalloc(size: sizeof(struct dcn20_link_encoder), GFP_KERNEL);
929
930 if (!enc20)
931 return NULL;
932
933 dcn30_link_encoder_construct(enc20,
934 init_data: enc_init_data,
935 enc_features: &link_enc_feature,
936 link_regs: &link_enc_regs[enc_init_data->transmitter],
937 aux_regs: &link_enc_aux_regs[enc_init_data->channel - 1],
938 hpd_regs: &link_enc_hpd_regs[enc_init_data->hpd_source],
939 link_shift: &le_shift,
940 link_mask: &le_mask);
941
942 return &enc20->enc10.base;
943}
944
945static struct panel_cntl *dcn30_panel_cntl_create(const struct panel_cntl_init_data *init_data)
946{
947 struct dce_panel_cntl *panel_cntl =
948 kzalloc(size: sizeof(struct dce_panel_cntl), GFP_KERNEL);
949
950 if (!panel_cntl)
951 return NULL;
952
953 dce_panel_cntl_construct(panel_cntl,
954 init_data,
955 regs: &panel_cntl_regs[init_data->inst],
956 shift: &panel_cntl_shift,
957 mask: &panel_cntl_mask);
958
959 return &panel_cntl->base;
960}
961
962static void read_dce_straps(
963 struct dc_context *ctx,
964 struct resource_straps *straps)
965{
966 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
967 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), field_value: &straps->dc_pinstraps_audio);
968
969}
970
971static struct audio *dcn30_create_audio(
972 struct dc_context *ctx, unsigned int inst)
973{
974 return dce_audio_create(ctx, inst,
975 reg: &audio_regs[inst], shifts: &audio_shift, masks: &audio_mask);
976}
977
978static struct vpg *dcn30_vpg_create(
979 struct dc_context *ctx,
980 uint32_t inst)
981{
982 struct dcn30_vpg *vpg3 = kzalloc(size: sizeof(struct dcn30_vpg), GFP_KERNEL);
983
984 if (!vpg3)
985 return NULL;
986
987 vpg3_construct(vpg3, ctx, inst,
988 vpg_regs: &vpg_regs[inst],
989 vpg_shift: &vpg_shift,
990 vpg_mask: &vpg_mask);
991
992 return &vpg3->base;
993}
994
995static struct afmt *dcn30_afmt_create(
996 struct dc_context *ctx,
997 uint32_t inst)
998{
999 struct dcn30_afmt *afmt3 = kzalloc(size: sizeof(struct dcn30_afmt), GFP_KERNEL);
1000
1001 if (!afmt3)
1002 return NULL;
1003
1004 afmt3_construct(afmt3, ctx, inst,
1005 afmt_regs: &afmt_regs[inst],
1006 afmt_shift: &afmt_shift,
1007 afmt_mask: &afmt_mask);
1008
1009 return &afmt3->base;
1010}
1011
1012static struct stream_encoder *dcn30_stream_encoder_create(enum engine_id eng_id,
1013 struct dc_context *ctx)
1014{
1015 struct dcn10_stream_encoder *enc1;
1016 struct vpg *vpg;
1017 struct afmt *afmt;
1018 int vpg_inst;
1019 int afmt_inst;
1020
1021 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1022 if (eng_id <= ENGINE_ID_DIGF) {
1023 vpg_inst = eng_id;
1024 afmt_inst = eng_id;
1025 } else
1026 return NULL;
1027
1028 enc1 = kzalloc(size: sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1029 vpg = dcn30_vpg_create(ctx, inst: vpg_inst);
1030 afmt = dcn30_afmt_create(ctx, inst: afmt_inst);
1031
1032 if (!enc1 || !vpg || !afmt) {
1033 kfree(objp: enc1);
1034 kfree(objp: vpg);
1035 kfree(objp: afmt);
1036 return NULL;
1037 }
1038
1039 dcn30_dio_stream_encoder_construct(enc1, ctx, bp: ctx->dc_bios,
1040 eng_id, vpg, afmt,
1041 regs: &stream_enc_regs[eng_id],
1042 se_shift: &se_shift, se_mask: &se_mask);
1043
1044 return &enc1->base;
1045}
1046
1047static struct dce_hwseq *dcn30_hwseq_create(struct dc_context *ctx)
1048{
1049 struct dce_hwseq *hws = kzalloc(size: sizeof(struct dce_hwseq), GFP_KERNEL);
1050
1051 if (hws) {
1052 hws->ctx = ctx;
1053 hws->regs = &hwseq_reg;
1054 hws->shifts = &hwseq_shift;
1055 hws->masks = &hwseq_mask;
1056 }
1057 return hws;
1058}
1059static const struct resource_create_funcs res_create_funcs = {
1060 .read_dce_straps = read_dce_straps,
1061 .create_audio = dcn30_create_audio,
1062 .create_stream_encoder = dcn30_stream_encoder_create,
1063 .create_hwseq = dcn30_hwseq_create,
1064};
1065
1066static void dcn30_resource_destruct(struct dcn30_resource_pool *pool)
1067{
1068 unsigned int i;
1069
1070 for (i = 0; i < pool->base.stream_enc_count; i++) {
1071 if (pool->base.stream_enc[i] != NULL) {
1072 if (pool->base.stream_enc[i]->vpg != NULL) {
1073 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1074 pool->base.stream_enc[i]->vpg = NULL;
1075 }
1076 if (pool->base.stream_enc[i]->afmt != NULL) {
1077 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1078 pool->base.stream_enc[i]->afmt = NULL;
1079 }
1080 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1081 pool->base.stream_enc[i] = NULL;
1082 }
1083 }
1084
1085 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1086 if (pool->base.dscs[i] != NULL)
1087 dcn20_dsc_destroy(dsc: &pool->base.dscs[i]);
1088 }
1089
1090 if (pool->base.mpc != NULL) {
1091 kfree(TO_DCN20_MPC(pool->base.mpc));
1092 pool->base.mpc = NULL;
1093 }
1094 if (pool->base.hubbub != NULL) {
1095 kfree(objp: pool->base.hubbub);
1096 pool->base.hubbub = NULL;
1097 }
1098 for (i = 0; i < pool->base.pipe_count; i++) {
1099 if (pool->base.dpps[i] != NULL)
1100 dcn30_dpp_destroy(dpp: &pool->base.dpps[i]);
1101
1102 if (pool->base.ipps[i] != NULL)
1103 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1104
1105 if (pool->base.hubps[i] != NULL) {
1106 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1107 pool->base.hubps[i] = NULL;
1108 }
1109
1110 if (pool->base.irqs != NULL) {
1111 dal_irq_service_destroy(irq_service: &pool->base.irqs);
1112 }
1113 }
1114
1115 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1116 if (pool->base.engines[i] != NULL)
1117 dce110_engine_destroy(engine: &pool->base.engines[i]);
1118 if (pool->base.hw_i2cs[i] != NULL) {
1119 kfree(objp: pool->base.hw_i2cs[i]);
1120 pool->base.hw_i2cs[i] = NULL;
1121 }
1122 if (pool->base.sw_i2cs[i] != NULL) {
1123 kfree(objp: pool->base.sw_i2cs[i]);
1124 pool->base.sw_i2cs[i] = NULL;
1125 }
1126 }
1127
1128 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1129 if (pool->base.opps[i] != NULL)
1130 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1131 }
1132
1133 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1134 if (pool->base.timing_generators[i] != NULL) {
1135 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1136 pool->base.timing_generators[i] = NULL;
1137 }
1138 }
1139
1140 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1141 if (pool->base.dwbc[i] != NULL) {
1142 kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1143 pool->base.dwbc[i] = NULL;
1144 }
1145 if (pool->base.mcif_wb[i] != NULL) {
1146 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1147 pool->base.mcif_wb[i] = NULL;
1148 }
1149 }
1150
1151 for (i = 0; i < pool->base.audio_count; i++) {
1152 if (pool->base.audios[i])
1153 dce_aud_destroy(audio: &pool->base.audios[i]);
1154 }
1155
1156 for (i = 0; i < pool->base.clk_src_count; i++) {
1157 if (pool->base.clock_sources[i] != NULL) {
1158 dcn20_clock_source_destroy(clk_src: &pool->base.clock_sources[i]);
1159 pool->base.clock_sources[i] = NULL;
1160 }
1161 }
1162
1163 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1164 if (pool->base.mpc_lut[i] != NULL) {
1165 dc_3dlut_func_release(lut: pool->base.mpc_lut[i]);
1166 pool->base.mpc_lut[i] = NULL;
1167 }
1168 if (pool->base.mpc_shaper[i] != NULL) {
1169 dc_transfer_func_release(dc_tf: pool->base.mpc_shaper[i]);
1170 pool->base.mpc_shaper[i] = NULL;
1171 }
1172 }
1173
1174 if (pool->base.dp_clock_source != NULL) {
1175 dcn20_clock_source_destroy(clk_src: &pool->base.dp_clock_source);
1176 pool->base.dp_clock_source = NULL;
1177 }
1178
1179 for (i = 0; i < pool->base.pipe_count; i++) {
1180 if (pool->base.multiple_abms[i] != NULL)
1181 dce_abm_destroy(abm: &pool->base.multiple_abms[i]);
1182 }
1183
1184 if (pool->base.psr != NULL)
1185 dmub_psr_destroy(dmub: &pool->base.psr);
1186
1187 if (pool->base.dccg != NULL)
1188 dcn_dccg_destroy(dccg: &pool->base.dccg);
1189
1190 if (pool->base.oem_device != NULL) {
1191 struct dc *dc = pool->base.oem_device->ctx->dc;
1192
1193 dc->link_srv->destroy_ddc_service(&pool->base.oem_device);
1194 }
1195}
1196
1197static struct hubp *dcn30_hubp_create(
1198 struct dc_context *ctx,
1199 uint32_t inst)
1200{
1201 struct dcn20_hubp *hubp2 =
1202 kzalloc(size: sizeof(struct dcn20_hubp), GFP_KERNEL);
1203
1204 if (!hubp2)
1205 return NULL;
1206
1207 if (hubp3_construct(hubp2, ctx, inst,
1208 hubp_regs: &hubp_regs[inst], hubp_shift: &hubp_shift, hubp_mask: &hubp_mask))
1209 return &hubp2->base;
1210
1211 BREAK_TO_DEBUGGER();
1212 kfree(objp: hubp2);
1213 return NULL;
1214}
1215
1216static bool dcn30_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1217{
1218 int i;
1219 uint32_t pipe_count = pool->res_cap->num_dwb;
1220
1221 for (i = 0; i < pipe_count; i++) {
1222 struct dcn30_dwbc *dwbc30 = kzalloc(size: sizeof(struct dcn30_dwbc),
1223 GFP_KERNEL);
1224
1225 if (!dwbc30) {
1226 dm_error("DC: failed to create dwbc30!\n");
1227 return false;
1228 }
1229
1230 dcn30_dwbc_construct(dwbc30, ctx,
1231 dwbc_regs: &dwbc30_regs[i],
1232 dwbc_shift: &dwbc30_shift,
1233 dwbc_mask: &dwbc30_mask,
1234 inst: i);
1235
1236 pool->dwbc[i] = &dwbc30->base;
1237 }
1238 return true;
1239}
1240
1241static bool dcn30_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1242{
1243 int i;
1244 uint32_t pipe_count = pool->res_cap->num_dwb;
1245
1246 for (i = 0; i < pipe_count; i++) {
1247 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(size: sizeof(struct dcn30_mmhubbub),
1248 GFP_KERNEL);
1249
1250 if (!mcif_wb30) {
1251 dm_error("DC: failed to create mcif_wb30!\n");
1252 return false;
1253 }
1254
1255 dcn30_mmhubbub_construct(mcif_wb30, ctx,
1256 mcif_wb_regs: &mcif_wb30_regs[i],
1257 mcif_wb_shift: &mcif_wb30_shift,
1258 mcif_wb_mask: &mcif_wb30_mask,
1259 inst: i);
1260
1261 pool->mcif_wb[i] = &mcif_wb30->base;
1262 }
1263 return true;
1264}
1265
1266static struct display_stream_compressor *dcn30_dsc_create(
1267 struct dc_context *ctx, uint32_t inst)
1268{
1269 struct dcn20_dsc *dsc =
1270 kzalloc(size: sizeof(struct dcn20_dsc), GFP_KERNEL);
1271
1272 if (!dsc) {
1273 BREAK_TO_DEBUGGER();
1274 return NULL;
1275 }
1276
1277 dsc2_construct(dsc, ctx, inst, dsc_regs: &dsc_regs[inst], dsc_shift: &dsc_shift, dsc_mask: &dsc_mask);
1278 return &dsc->base;
1279}
1280
1281enum dc_status dcn30_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
1282{
1283
1284 return dcn20_add_stream_to_ctx(dc, new_ctx, dc_stream);
1285}
1286
1287static void dcn30_destroy_resource_pool(struct resource_pool **pool)
1288{
1289 struct dcn30_resource_pool *dcn30_pool = TO_DCN30_RES_POOL(*pool);
1290
1291 dcn30_resource_destruct(pool: dcn30_pool);
1292 kfree(objp: dcn30_pool);
1293 *pool = NULL;
1294}
1295
1296static struct clock_source *dcn30_clock_source_create(
1297 struct dc_context *ctx,
1298 struct dc_bios *bios,
1299 enum clock_source_id id,
1300 const struct dce110_clk_src_regs *regs,
1301 bool dp_clk_src)
1302{
1303 struct dce110_clk_src *clk_src =
1304 kzalloc(size: sizeof(struct dce110_clk_src), GFP_KERNEL);
1305
1306 if (!clk_src)
1307 return NULL;
1308
1309 if (dcn3_clk_src_construct(clk_src, ctx, bios, id,
1310 regs, cs_shift: &cs_shift, cs_mask: &cs_mask)) {
1311 clk_src->base.dp_clk_src = dp_clk_src;
1312 return &clk_src->base;
1313 }
1314
1315 kfree(objp: clk_src);
1316 BREAK_TO_DEBUGGER();
1317 return NULL;
1318}
1319
1320int dcn30_populate_dml_pipes_from_context(
1321 struct dc *dc, struct dc_state *context,
1322 display_e2e_pipe_params_st *pipes,
1323 bool fast_validate)
1324{
1325 int i, pipe_cnt;
1326 struct resource_context *res_ctx = &context->res_ctx;
1327
1328 DC_FP_START();
1329 dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
1330 DC_FP_END();
1331
1332 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1333 if (!res_ctx->pipe_ctx[i].stream)
1334 continue;
1335
1336 pipes[pipe_cnt++].pipe.scale_ratio_depth.lb_depth =
1337 dm_lb_16;
1338 }
1339
1340 return pipe_cnt;
1341}
1342
1343void dcn30_populate_dml_writeback_from_context(
1344 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)
1345{
1346 DC_FP_START();
1347 dcn30_fpu_populate_dml_writeback_from_context(dc, res_ctx, pipes);
1348 DC_FP_END();
1349}
1350
1351unsigned int dcn30_calc_max_scaled_time(
1352 unsigned int time_per_pixel,
1353 enum mmhubbub_wbif_mode mode,
1354 unsigned int urgent_watermark)
1355{
1356 unsigned int time_per_byte = 0;
1357 unsigned int total_free_entry = 0xb40;
1358 unsigned int buf_lh_capability;
1359 unsigned int max_scaled_time;
1360
1361 if (mode == PACKED_444) /* packed mode 32 bpp */
1362 time_per_byte = time_per_pixel/4;
1363 else if (mode == PACKED_444_FP16) /* packed mode 64 bpp */
1364 time_per_byte = time_per_pixel/8;
1365
1366 if (time_per_byte == 0)
1367 time_per_byte = 1;
1368
1369 buf_lh_capability = (total_free_entry*time_per_byte*32) >> 6; /* time_per_byte is in u6.6*/
1370 max_scaled_time = buf_lh_capability - urgent_watermark;
1371 return max_scaled_time;
1372}
1373
1374void dcn30_set_mcif_arb_params(
1375 struct dc *dc,
1376 struct dc_state *context,
1377 display_e2e_pipe_params_st *pipes,
1378 int pipe_cnt)
1379{
1380 enum mmhubbub_wbif_mode wbif_mode;
1381 struct display_mode_lib *dml = &context->bw_ctx.dml;
1382 struct mcif_arb_params *wb_arb_params;
1383 int i, j, dwb_pipe;
1384
1385 /* Writeback MCIF_WB arbitration parameters */
1386 dwb_pipe = 0;
1387 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1388
1389 if (!context->res_ctx.pipe_ctx[i].stream)
1390 continue;
1391
1392 for (j = 0; j < MAX_DWB_PIPES; j++) {
1393 struct dc_writeback_info *writeback_info = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j];
1394
1395 if (writeback_info->wb_enabled == false)
1396 continue;
1397
1398 //wb_arb_params = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j].mcif_arb_params;
1399 wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe];
1400
1401 if (writeback_info->dwb_params.cnv_params.fc_out_format == DWB_OUT_FORMAT_64BPP_ARGB ||
1402 writeback_info->dwb_params.cnv_params.fc_out_format == DWB_OUT_FORMAT_64BPP_RGBA)
1403 wbif_mode = PACKED_444_FP16;
1404 else
1405 wbif_mode = PACKED_444;
1406
1407 DC_FP_START();
1408 dcn30_fpu_set_mcif_arb_params(wb_arb_params, dml, pipes, pipe_cnt, cur_pipe: j);
1409 DC_FP_END();
1410 wb_arb_params->time_per_pixel = (1000000 << 6) / context->res_ctx.pipe_ctx[i].stream->phy_pix_clk; /* time_per_pixel should be in u6.6 format */
1411 wb_arb_params->slice_lines = 32;
1412 wb_arb_params->arbitration_slice = 2; /* irrelevant since there is no YUV output */
1413 wb_arb_params->max_scaled_time = dcn30_calc_max_scaled_time(time_per_pixel: wb_arb_params->time_per_pixel,
1414 mode: wbif_mode,
1415 urgent_watermark: wb_arb_params->cli_watermark[0]); /* assume 4 watermark sets have the same value */
1416
1417 dwb_pipe++;
1418
1419 if (dwb_pipe >= MAX_DWB_PIPES)
1420 return;
1421 }
1422 if (dwb_pipe >= MAX_DWB_PIPES)
1423 return;
1424 }
1425
1426}
1427
1428static struct dc_cap_funcs cap_funcs = {
1429 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1430};
1431
1432bool dcn30_acquire_post_bldn_3dlut(
1433 struct resource_context *res_ctx,
1434 const struct resource_pool *pool,
1435 int mpcc_id,
1436 struct dc_3dlut **lut,
1437 struct dc_transfer_func **shaper)
1438{
1439 int i;
1440 bool ret = false;
1441 union dc_3dlut_state *state;
1442
1443 ASSERT(*lut == NULL && *shaper == NULL);
1444 *lut = NULL;
1445 *shaper = NULL;
1446
1447 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {
1448 if (!res_ctx->is_mpc_3dlut_acquired[i]) {
1449 *lut = pool->mpc_lut[i];
1450 *shaper = pool->mpc_shaper[i];
1451 state = &pool->mpc_lut[i]->state;
1452 res_ctx->is_mpc_3dlut_acquired[i] = true;
1453 state->bits.rmu_idx_valid = 1;
1454 state->bits.rmu_mux_num = i;
1455 if (state->bits.rmu_mux_num == 0)
1456 state->bits.mpc_rmu0_mux = mpcc_id;
1457 else if (state->bits.rmu_mux_num == 1)
1458 state->bits.mpc_rmu1_mux = mpcc_id;
1459 else if (state->bits.rmu_mux_num == 2)
1460 state->bits.mpc_rmu2_mux = mpcc_id;
1461 ret = true;
1462 break;
1463 }
1464 }
1465 return ret;
1466}
1467
1468bool dcn30_release_post_bldn_3dlut(
1469 struct resource_context *res_ctx,
1470 const struct resource_pool *pool,
1471 struct dc_3dlut **lut,
1472 struct dc_transfer_func **shaper)
1473{
1474 int i;
1475 bool ret = false;
1476
1477 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {
1478 if (pool->mpc_lut[i] == *lut && pool->mpc_shaper[i] == *shaper) {
1479 res_ctx->is_mpc_3dlut_acquired[i] = false;
1480 pool->mpc_lut[i]->state.raw = 0;
1481 *lut = NULL;
1482 *shaper = NULL;
1483 ret = true;
1484 break;
1485 }
1486 }
1487 return ret;
1488}
1489
1490static bool is_soc_bounding_box_valid(struct dc *dc)
1491{
1492 uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev;
1493
1494 if (ASICREV_IS_SIENNA_CICHLID_P(hw_internal_rev))
1495 return true;
1496
1497 return false;
1498}
1499
1500static bool init_soc_bounding_box(struct dc *dc,
1501 struct dcn30_resource_pool *pool)
1502{
1503 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_0_soc;
1504 struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_0_ip;
1505
1506 DC_LOGGER_INIT(dc->ctx->logger);
1507
1508 if (!is_soc_bounding_box_valid(dc)) {
1509 DC_LOG_ERROR("%s: not valid soc bounding box\n", __func__);
1510 return false;
1511 }
1512
1513 loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator;
1514 loaded_ip->max_num_dpp = pool->base.pipe_count;
1515 loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk;
1516 dcn20_patch_bounding_box(dc, bb: loaded_bb);
1517 DC_FP_START();
1518 patch_dcn30_soc_bounding_box(dc, dcn3_0_ip: &dcn3_0_soc);
1519 DC_FP_END();
1520
1521 return true;
1522}
1523
1524static bool dcn30_split_stream_for_mpc_or_odm(
1525 const struct dc *dc,
1526 struct resource_context *res_ctx,
1527 struct pipe_ctx *pri_pipe,
1528 struct pipe_ctx *sec_pipe,
1529 bool odm)
1530{
1531 int pipe_idx = sec_pipe->pipe_idx;
1532 const struct resource_pool *pool = dc->res_pool;
1533
1534 *sec_pipe = *pri_pipe;
1535
1536 sec_pipe->pipe_idx = pipe_idx;
1537 sec_pipe->plane_res.mi = pool->mis[pipe_idx];
1538 sec_pipe->plane_res.hubp = pool->hubps[pipe_idx];
1539 sec_pipe->plane_res.ipp = pool->ipps[pipe_idx];
1540 sec_pipe->plane_res.xfm = pool->transforms[pipe_idx];
1541 sec_pipe->plane_res.dpp = pool->dpps[pipe_idx];
1542 sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst;
1543 sec_pipe->stream_res.dsc = NULL;
1544 if (odm) {
1545 if (pri_pipe->next_odm_pipe) {
1546 ASSERT(pri_pipe->next_odm_pipe != sec_pipe);
1547 sec_pipe->next_odm_pipe = pri_pipe->next_odm_pipe;
1548 sec_pipe->next_odm_pipe->prev_odm_pipe = sec_pipe;
1549 }
1550 if (pri_pipe->top_pipe && pri_pipe->top_pipe->next_odm_pipe) {
1551 pri_pipe->top_pipe->next_odm_pipe->bottom_pipe = sec_pipe;
1552 sec_pipe->top_pipe = pri_pipe->top_pipe->next_odm_pipe;
1553 }
1554 if (pri_pipe->bottom_pipe && pri_pipe->bottom_pipe->next_odm_pipe) {
1555 pri_pipe->bottom_pipe->next_odm_pipe->top_pipe = sec_pipe;
1556 sec_pipe->bottom_pipe = pri_pipe->bottom_pipe->next_odm_pipe;
1557 }
1558 pri_pipe->next_odm_pipe = sec_pipe;
1559 sec_pipe->prev_odm_pipe = pri_pipe;
1560
1561 if (!sec_pipe->top_pipe)
1562 sec_pipe->stream_res.opp = pool->opps[pipe_idx];
1563 else
1564 sec_pipe->stream_res.opp = sec_pipe->top_pipe->stream_res.opp;
1565 if (sec_pipe->stream->timing.flags.DSC == 1) {
1566 dcn20_acquire_dsc(dc, res_ctx, dsc: &sec_pipe->stream_res.dsc, pipe_idx);
1567 ASSERT(sec_pipe->stream_res.dsc);
1568 if (sec_pipe->stream_res.dsc == NULL)
1569 return false;
1570 }
1571 } else {
1572 if (pri_pipe->bottom_pipe) {
1573 ASSERT(pri_pipe->bottom_pipe != sec_pipe);
1574 sec_pipe->bottom_pipe = pri_pipe->bottom_pipe;
1575 sec_pipe->bottom_pipe->top_pipe = sec_pipe;
1576 }
1577 pri_pipe->bottom_pipe = sec_pipe;
1578 sec_pipe->top_pipe = pri_pipe;
1579
1580 ASSERT(pri_pipe->plane_state);
1581 }
1582
1583 return true;
1584}
1585
1586static struct pipe_ctx *dcn30_find_split_pipe(
1587 struct dc *dc,
1588 struct dc_state *context,
1589 int old_index)
1590{
1591 struct pipe_ctx *pipe = NULL;
1592 int i;
1593
1594 if (old_index >= 0 && context->res_ctx.pipe_ctx[old_index].stream == NULL) {
1595 pipe = &context->res_ctx.pipe_ctx[old_index];
1596 pipe->pipe_idx = old_index;
1597 }
1598
1599 if (!pipe)
1600 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
1601 if (dc->current_state->res_ctx.pipe_ctx[i].top_pipe == NULL
1602 && dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe == NULL) {
1603 if (context->res_ctx.pipe_ctx[i].stream == NULL) {
1604 pipe = &context->res_ctx.pipe_ctx[i];
1605 pipe->pipe_idx = i;
1606 break;
1607 }
1608 }
1609 }
1610
1611 /*
1612 * May need to fix pipes getting tossed from 1 opp to another on flip
1613 * Add for debugging transient underflow during topology updates:
1614 * ASSERT(pipe);
1615 */
1616 if (!pipe)
1617 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
1618 if (context->res_ctx.pipe_ctx[i].stream == NULL) {
1619 pipe = &context->res_ctx.pipe_ctx[i];
1620 pipe->pipe_idx = i;
1621 break;
1622 }
1623 }
1624
1625 return pipe;
1626}
1627
1628noinline bool dcn30_internal_validate_bw(
1629 struct dc *dc,
1630 struct dc_state *context,
1631 display_e2e_pipe_params_st *pipes,
1632 int *pipe_cnt_out,
1633 int *vlevel_out,
1634 bool fast_validate,
1635 bool allow_self_refresh_only)
1636{
1637 bool out = false;
1638 bool repopulate_pipes = false;
1639 int split[MAX_PIPES] = { 0 };
1640 bool merge[MAX_PIPES] = { false };
1641 bool newly_split[MAX_PIPES] = { false };
1642 int pipe_cnt, i, pipe_idx, vlevel;
1643 struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
1644
1645 ASSERT(pipes);
1646 if (!pipes)
1647 return false;
1648
1649 context->bw_ctx.dml.vba.maxMpcComb = 0;
1650 context->bw_ctx.dml.vba.VoltageLevel = 0;
1651 context->bw_ctx.dml.vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_vactive;
1652 dc->res_pool->funcs->update_soc_for_wm_a(dc, context);
1653 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
1654
1655 if (!pipe_cnt) {
1656 out = true;
1657 goto validate_out;
1658 }
1659
1660 dml_log_pipe_params(mode_lib: &context->bw_ctx.dml, pipes, pipe_cnt);
1661
1662 if (!fast_validate || !allow_self_refresh_only) {
1663 /*
1664 * DML favors voltage over p-state, but we're more interested in
1665 * supporting p-state over voltage. We can't support p-state in
1666 * prefetch mode > 0 so try capping the prefetch mode to start.
1667 */
1668 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
1669 dm_allow_self_refresh_and_mclk_switch;
1670 vlevel = dml_get_voltage_level(mode_lib: &context->bw_ctx.dml, pipes, num_pipes: pipe_cnt);
1671 /* This may adjust vlevel and maxMpcComb */
1672 if (vlevel < context->bw_ctx.dml.soc.num_states)
1673 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
1674 }
1675 if (allow_self_refresh_only &&
1676 (fast_validate || vlevel == context->bw_ctx.dml.soc.num_states ||
1677 vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported)) {
1678 /*
1679 * If mode is unsupported or there's still no p-state support
1680 * then fall back to favoring voltage.
1681 *
1682 * We don't actually support prefetch mode 2, so require that we
1683 * at least support prefetch mode 1.
1684 */
1685 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
1686 dm_allow_self_refresh;
1687
1688 vlevel = dml_get_voltage_level(mode_lib: &context->bw_ctx.dml, pipes, num_pipes: pipe_cnt);
1689 if (vlevel < context->bw_ctx.dml.soc.num_states) {
1690 memset(split, 0, sizeof(split));
1691 memset(merge, 0, sizeof(merge));
1692 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
1693 }
1694 }
1695
1696 dml_log_mode_support_params(mode_lib: &context->bw_ctx.dml);
1697
1698 if (vlevel == context->bw_ctx.dml.soc.num_states)
1699 goto validate_fail;
1700
1701 if (!dc->config.enable_windowed_mpo_odm) {
1702 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1703 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1704 struct pipe_ctx *mpo_pipe = pipe->bottom_pipe;
1705
1706 if (!pipe->stream)
1707 continue;
1708
1709 /* We only support full screen mpo with ODM */
1710 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled
1711 && pipe->plane_state && mpo_pipe
1712 && memcmp(p: &mpo_pipe->plane_state->clip_rect,
1713 q: &pipe->stream->src,
1714 size: sizeof(struct rect)) != 0) {
1715 ASSERT(mpo_pipe->plane_state != pipe->plane_state);
1716 goto validate_fail;
1717 }
1718 pipe_idx++;
1719 }
1720 }
1721
1722 /* merge pipes if necessary */
1723 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1724 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1725
1726 /*skip pipes that don't need merging*/
1727 if (!merge[i])
1728 continue;
1729
1730 /* if ODM merge we ignore mpc tree, mpo pipes will have their own flags */
1731 if (pipe->prev_odm_pipe) {
1732 /*split off odm pipe*/
1733 pipe->prev_odm_pipe->next_odm_pipe = pipe->next_odm_pipe;
1734 if (pipe->next_odm_pipe)
1735 pipe->next_odm_pipe->prev_odm_pipe = pipe->prev_odm_pipe;
1736
1737 pipe->bottom_pipe = NULL;
1738 pipe->next_odm_pipe = NULL;
1739 pipe->plane_state = NULL;
1740 pipe->stream = NULL;
1741 pipe->top_pipe = NULL;
1742 pipe->prev_odm_pipe = NULL;
1743 if (pipe->stream_res.dsc)
1744 dcn20_release_dsc(res_ctx: &context->res_ctx, pool: dc->res_pool, dsc: &pipe->stream_res.dsc);
1745 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));
1746 memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));
1747 repopulate_pipes = true;
1748 } else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) {
1749 struct pipe_ctx *top_pipe = pipe->top_pipe;
1750 struct pipe_ctx *bottom_pipe = pipe->bottom_pipe;
1751
1752 top_pipe->bottom_pipe = bottom_pipe;
1753 if (bottom_pipe)
1754 bottom_pipe->top_pipe = top_pipe;
1755
1756 pipe->top_pipe = NULL;
1757 pipe->bottom_pipe = NULL;
1758 pipe->plane_state = NULL;
1759 pipe->stream = NULL;
1760 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));
1761 memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));
1762 repopulate_pipes = true;
1763 } else
1764 ASSERT(0); /* Should never try to merge master pipe */
1765
1766 }
1767
1768 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
1769 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1770 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1771 struct pipe_ctx *hsplit_pipe = NULL;
1772 bool odm;
1773 int old_index = -1;
1774
1775 if (!pipe->stream || newly_split[i])
1776 continue;
1777
1778 pipe_idx++;
1779 odm = vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled;
1780
1781 if (!pipe->plane_state && !odm)
1782 continue;
1783
1784 if (split[i]) {
1785 if (odm) {
1786 if (split[i] == 4 && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe)
1787 old_index = old_pipe->next_odm_pipe->next_odm_pipe->pipe_idx;
1788 else if (old_pipe->next_odm_pipe)
1789 old_index = old_pipe->next_odm_pipe->pipe_idx;
1790 } else {
1791 if (split[i] == 4 && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe &&
1792 old_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
1793 old_index = old_pipe->bottom_pipe->bottom_pipe->pipe_idx;
1794 else if (old_pipe->bottom_pipe &&
1795 old_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
1796 old_index = old_pipe->bottom_pipe->pipe_idx;
1797 }
1798 hsplit_pipe = dcn30_find_split_pipe(dc, context, old_index);
1799 ASSERT(hsplit_pipe);
1800 if (!hsplit_pipe)
1801 goto validate_fail;
1802
1803 if (!dcn30_split_stream_for_mpc_or_odm(
1804 dc, res_ctx: &context->res_ctx,
1805 pri_pipe: pipe, sec_pipe: hsplit_pipe, odm))
1806 goto validate_fail;
1807
1808 newly_split[hsplit_pipe->pipe_idx] = true;
1809 repopulate_pipes = true;
1810 }
1811 if (split[i] == 4) {
1812 struct pipe_ctx *pipe_4to1;
1813
1814 if (odm && old_pipe->next_odm_pipe)
1815 old_index = old_pipe->next_odm_pipe->pipe_idx;
1816 else if (!odm && old_pipe->bottom_pipe &&
1817 old_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
1818 old_index = old_pipe->bottom_pipe->pipe_idx;
1819 else
1820 old_index = -1;
1821 pipe_4to1 = dcn30_find_split_pipe(dc, context, old_index);
1822 ASSERT(pipe_4to1);
1823 if (!pipe_4to1)
1824 goto validate_fail;
1825 if (!dcn30_split_stream_for_mpc_or_odm(
1826 dc, res_ctx: &context->res_ctx,
1827 pri_pipe: pipe, sec_pipe: pipe_4to1, odm))
1828 goto validate_fail;
1829 newly_split[pipe_4to1->pipe_idx] = true;
1830
1831 if (odm && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe
1832 && old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe)
1833 old_index = old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe->pipe_idx;
1834 else if (!odm && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe &&
1835 old_pipe->bottom_pipe->bottom_pipe->bottom_pipe &&
1836 old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
1837 old_index = old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->pipe_idx;
1838 else
1839 old_index = -1;
1840 pipe_4to1 = dcn30_find_split_pipe(dc, context, old_index);
1841 ASSERT(pipe_4to1);
1842 if (!pipe_4to1)
1843 goto validate_fail;
1844 if (!dcn30_split_stream_for_mpc_or_odm(
1845 dc, res_ctx: &context->res_ctx,
1846 pri_pipe: hsplit_pipe, sec_pipe: pipe_4to1, odm))
1847 goto validate_fail;
1848 newly_split[pipe_4to1->pipe_idx] = true;
1849 }
1850 if (odm)
1851 dcn20_build_mapped_resource(dc, context, stream: pipe->stream);
1852 }
1853
1854 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1855 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1856
1857 if (pipe->plane_state) {
1858 if (!resource_build_scaling_params(pipe_ctx: pipe))
1859 goto validate_fail;
1860 }
1861 }
1862
1863 /* Actual dsc count per stream dsc validation*/
1864 if (!dcn20_validate_dsc(dc, new_ctx: context)) {
1865 vba->ValidationStatus[vba->soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE;
1866 goto validate_fail;
1867 }
1868
1869 if (repopulate_pipes)
1870 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
1871 context->bw_ctx.dml.vba.VoltageLevel = vlevel;
1872 *vlevel_out = vlevel;
1873 *pipe_cnt_out = pipe_cnt;
1874
1875 out = true;
1876 goto validate_out;
1877
1878validate_fail:
1879 out = false;
1880
1881validate_out:
1882 return out;
1883}
1884
1885static int get_refresh_rate(struct dc_state *context)
1886{
1887 int refresh_rate = 0;
1888 int h_v_total = 0;
1889 struct dc_crtc_timing *timing = NULL;
1890
1891 if (context == NULL || context->streams[0] == NULL)
1892 return 0;
1893
1894 /* check if refresh rate at least 120hz */
1895 timing = &context->streams[0]->timing;
1896 if (timing == NULL)
1897 return 0;
1898
1899 h_v_total = timing->h_total * timing->v_total;
1900 if (h_v_total == 0)
1901 return 0;
1902
1903 refresh_rate = ((timing->pix_clk_100hz * 100) / (h_v_total)) + 1;
1904 return refresh_rate;
1905}
1906
1907#define MAX_STRETCHED_V_BLANK 500 // in micro-seconds
1908/*
1909 * Scaling factor for v_blank stretch calculations considering timing in
1910 * micro-seconds and pixel clock in 100hz.
1911 * Note: the parenthesis are necessary to ensure the correct order of
1912 * operation where V_SCALE is used.
1913 */
1914#define V_SCALE (10000 / MAX_STRETCHED_V_BLANK)
1915
1916static int get_frame_rate_at_max_stretch_100hz(struct dc_state *context)
1917{
1918 struct dc_crtc_timing *timing = NULL;
1919 uint32_t sec_per_100_lines;
1920 uint32_t max_v_blank;
1921 uint32_t curr_v_blank;
1922 uint32_t v_stretch_max;
1923 uint32_t stretched_frame_pix_cnt;
1924 uint32_t scaled_stretched_frame_pix_cnt;
1925 uint32_t scaled_refresh_rate;
1926
1927 if (context == NULL || context->streams[0] == NULL)
1928 return 0;
1929
1930 /* check if refresh rate at least 120hz */
1931 timing = &context->streams[0]->timing;
1932 if (timing == NULL)
1933 return 0;
1934
1935 sec_per_100_lines = timing->pix_clk_100hz / timing->h_total + 1;
1936 max_v_blank = sec_per_100_lines / V_SCALE + 1;
1937 curr_v_blank = timing->v_total - timing->v_addressable;
1938 v_stretch_max = (max_v_blank > curr_v_blank) ? (max_v_blank - curr_v_blank) : (0);
1939 stretched_frame_pix_cnt = (v_stretch_max + timing->v_total) * timing->h_total;
1940 scaled_stretched_frame_pix_cnt = stretched_frame_pix_cnt / 10000;
1941 scaled_refresh_rate = (timing->pix_clk_100hz) / scaled_stretched_frame_pix_cnt + 1;
1942
1943 return scaled_refresh_rate;
1944}
1945
1946static bool is_refresh_rate_support_mclk_switch_using_fw_based_vblank_stretch(struct dc_state *context)
1947{
1948 int refresh_rate_max_stretch_100hz;
1949 int min_refresh_100hz;
1950
1951 if (context == NULL || context->streams[0] == NULL)
1952 return false;
1953
1954 refresh_rate_max_stretch_100hz = get_frame_rate_at_max_stretch_100hz(context);
1955 min_refresh_100hz = context->streams[0]->timing.min_refresh_in_uhz / 10000;
1956
1957 if (refresh_rate_max_stretch_100hz < min_refresh_100hz)
1958 return false;
1959
1960 return true;
1961}
1962
1963bool dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, struct dc_state *context)
1964{
1965 int refresh_rate = 0;
1966 const int minimum_refreshrate_supported = 120;
1967
1968 if (context == NULL || context->streams[0] == NULL)
1969 return false;
1970
1971 if (context->streams[0]->sink->edid_caps.panel_patch.disable_fams)
1972 return false;
1973
1974 if (dc->debug.disable_fams)
1975 return false;
1976
1977 if (!dc->caps.dmub_caps.mclk_sw)
1978 return false;
1979
1980 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching_shut_down)
1981 return false;
1982
1983 /* more then 1 monitor connected */
1984 if (context->stream_count != 1)
1985 return false;
1986
1987 refresh_rate = get_refresh_rate(context);
1988 if (refresh_rate < minimum_refreshrate_supported)
1989 return false;
1990
1991 if (!is_refresh_rate_support_mclk_switch_using_fw_based_vblank_stretch(context))
1992 return false;
1993
1994 if (!context->streams[0]->allow_freesync)
1995 return false;
1996
1997 if (context->streams[0]->vrr_active_variable && dc->debug.disable_fams_gaming)
1998 return false;
1999
2000 context->streams[0]->fpo_in_use = true;
2001
2002 return true;
2003}
2004
2005/*
2006 * set up FPO watermarks, pstate, dram latency
2007 */
2008void dcn30_setup_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, struct dc_state *context)
2009{
2010 ASSERT(dc != NULL && context != NULL);
2011 if (dc == NULL || context == NULL)
2012 return;
2013
2014 /* Set wm_a.pstate so high natural MCLK switches are impossible: 4 seconds */
2015 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 4U * 1000U * 1000U * 1000U;
2016}
2017
2018void dcn30_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)
2019{
2020 DC_FP_START();
2021 dcn30_fpu_update_soc_for_wm_a(dc, context);
2022 DC_FP_END();
2023}
2024
2025void dcn30_calculate_wm_and_dlg(
2026 struct dc *dc, struct dc_state *context,
2027 display_e2e_pipe_params_st *pipes,
2028 int pipe_cnt,
2029 int vlevel)
2030{
2031 DC_FP_START();
2032 dcn30_fpu_calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);
2033 DC_FP_END();
2034}
2035
2036bool dcn30_validate_bandwidth(struct dc *dc,
2037 struct dc_state *context,
2038 bool fast_validate)
2039{
2040 bool out = false;
2041
2042 BW_VAL_TRACE_SETUP();
2043
2044 int vlevel = 0;
2045 int pipe_cnt = 0;
2046 display_e2e_pipe_params_st *pipes = kzalloc(size: dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
2047 DC_LOGGER_INIT(dc->ctx->logger);
2048
2049 BW_VAL_TRACE_COUNT();
2050
2051 DC_FP_START();
2052 out = dcn30_internal_validate_bw(dc, context, pipes, pipe_cnt_out: &pipe_cnt, vlevel_out: &vlevel, fast_validate, allow_self_refresh_only: true);
2053 DC_FP_END();
2054
2055 if (pipe_cnt == 0)
2056 goto validate_out;
2057
2058 if (!out)
2059 goto validate_fail;
2060
2061 BW_VAL_TRACE_END_VOLTAGE_LEVEL();
2062
2063 if (fast_validate) {
2064 BW_VAL_TRACE_SKIP(fast);
2065 goto validate_out;
2066 }
2067
2068 DC_FP_START();
2069 if (dc->res_pool->funcs->calculate_wm_and_dlg)
2070 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);
2071 DC_FP_END();
2072
2073 BW_VAL_TRACE_END_WATERMARKS();
2074
2075 goto validate_out;
2076
2077validate_fail:
2078 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
2079 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
2080
2081 BW_VAL_TRACE_SKIP(fail);
2082 out = false;
2083
2084validate_out:
2085 kfree(objp: pipes);
2086
2087 BW_VAL_TRACE_FINISH();
2088
2089 return out;
2090}
2091
2092void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
2093{
2094 unsigned int i, j;
2095 unsigned int num_states = 0;
2096
2097 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0};
2098 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0};
2099 unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0};
2100 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0};
2101
2102 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200};
2103 unsigned int num_dcfclk_sta_targets = 4;
2104 unsigned int num_uclk_states;
2105
2106 struct dc_bounding_box_max_clk dcn30_bb_max_clk;
2107
2108 memset(&dcn30_bb_max_clk, 0, sizeof(dcn30_bb_max_clk));
2109
2110 if (dc->ctx->dc_bios->vram_info.num_chans)
2111 dcn3_0_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans;
2112
2113 DC_FP_START();
2114 dcn30_fpu_update_dram_channel_width_bytes(dc);
2115 DC_FP_END();
2116
2117 if (bw_params->clk_table.entries[0].memclk_mhz) {
2118
2119 for (i = 0; i < MAX_NUM_DPM_LVL; i++) {
2120 if (bw_params->clk_table.entries[i].dcfclk_mhz > dcn30_bb_max_clk.max_dcfclk_mhz)
2121 dcn30_bb_max_clk.max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
2122 if (bw_params->clk_table.entries[i].dispclk_mhz > dcn30_bb_max_clk.max_dispclk_mhz)
2123 dcn30_bb_max_clk.max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
2124 if (bw_params->clk_table.entries[i].dppclk_mhz > dcn30_bb_max_clk.max_dppclk_mhz)
2125 dcn30_bb_max_clk.max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
2126 if (bw_params->clk_table.entries[i].phyclk_mhz > dcn30_bb_max_clk.max_phyclk_mhz)
2127 dcn30_bb_max_clk.max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;
2128 }
2129
2130 DC_FP_START();
2131 dcn30_fpu_update_max_clk(dcn30_bb_max_clk: &dcn30_bb_max_clk);
2132 DC_FP_END();
2133
2134 if (dcn30_bb_max_clk.max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
2135 // If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array
2136 dcfclk_sta_targets[num_dcfclk_sta_targets] = dcn30_bb_max_clk.max_dcfclk_mhz;
2137 num_dcfclk_sta_targets++;
2138 } else if (dcn30_bb_max_clk.max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
2139 // If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates
2140 for (i = 0; i < num_dcfclk_sta_targets; i++) {
2141 if (dcfclk_sta_targets[i] > dcn30_bb_max_clk.max_dcfclk_mhz) {
2142 dcfclk_sta_targets[i] = dcn30_bb_max_clk.max_dcfclk_mhz;
2143 break;
2144 }
2145 }
2146 // Update size of array since we "removed" duplicates
2147 num_dcfclk_sta_targets = i + 1;
2148 }
2149
2150 num_uclk_states = bw_params->clk_table.num_entries;
2151
2152 // Calculate optimal dcfclk for each uclk
2153 for (i = 0; i < num_uclk_states; i++) {
2154 DC_FP_START();
2155 dcn30_fpu_get_optimal_dcfclk_fclk_for_uclk(uclk_mts: bw_params->clk_table.entries[i].memclk_mhz * 16,
2156 optimal_dcfclk: &optimal_dcfclk_for_uclk[i], NULL);
2157 DC_FP_END();
2158 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) {
2159 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz;
2160 }
2161 }
2162
2163 // Calculate optimal uclk for each dcfclk sta target
2164 for (i = 0; i < num_dcfclk_sta_targets; i++) {
2165 for (j = 0; j < num_uclk_states; j++) {
2166 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) {
2167 optimal_uclk_for_dcfclk_sta_targets[i] =
2168 bw_params->clk_table.entries[j].memclk_mhz * 16;
2169 break;
2170 }
2171 }
2172 }
2173
2174 i = 0;
2175 j = 0;
2176 // create the final dcfclk and uclk table
2177 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) {
2178 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) {
2179 dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
2180 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
2181 } else {
2182 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= dcn30_bb_max_clk.max_dcfclk_mhz) {
2183 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
2184 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
2185 } else {
2186 j = num_uclk_states;
2187 }
2188 }
2189 }
2190
2191 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) {
2192 dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
2193 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
2194 }
2195
2196 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES &&
2197 optimal_dcfclk_for_uclk[j] <= dcn30_bb_max_clk.max_dcfclk_mhz) {
2198 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
2199 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
2200 }
2201
2202 dcn3_0_soc.num_states = num_states;
2203 DC_FP_START();
2204 dcn30_fpu_update_bw_bounding_box(dc, bw_params, dcn30_bb_max_clk: &dcn30_bb_max_clk, dcfclk_mhz, dram_speed_mts);
2205 DC_FP_END();
2206 }
2207}
2208
2209static void dcn30_get_panel_config_defaults(struct dc_panel_config *panel_config)
2210{
2211 *panel_config = panel_config_defaults;
2212}
2213
2214static const struct resource_funcs dcn30_res_pool_funcs = {
2215 .destroy = dcn30_destroy_resource_pool,
2216 .link_enc_create = dcn30_link_encoder_create,
2217 .panel_cntl_create = dcn30_panel_cntl_create,
2218 .validate_bandwidth = dcn30_validate_bandwidth,
2219 .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg,
2220 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
2221 .populate_dml_pipes = dcn30_populate_dml_pipes_from_context,
2222 .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
2223 .release_pipe = dcn20_release_pipe,
2224 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
2225 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
2226 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
2227 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
2228 .set_mcif_arb_params = dcn30_set_mcif_arb_params,
2229 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
2230 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
2231 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
2232 .update_bw_bounding_box = dcn30_update_bw_bounding_box,
2233 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
2234 .get_panel_config_defaults = dcn30_get_panel_config_defaults,
2235};
2236
2237#define CTX ctx
2238
2239#define REG(reg_name) \
2240 (DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
2241
2242static uint32_t read_pipe_fuses(struct dc_context *ctx)
2243{
2244 uint32_t value = REG_READ(CC_DC_PIPE_DIS);
2245 /* Support for max 6 pipes */
2246 value = value & 0x3f;
2247 return value;
2248}
2249
2250static bool dcn30_resource_construct(
2251 uint8_t num_virtual_links,
2252 struct dc *dc,
2253 struct dcn30_resource_pool *pool)
2254{
2255 int i;
2256 struct dc_context *ctx = dc->ctx;
2257 struct irq_service_init_data init_data;
2258 struct ddc_service_init_data ddc_init_data = {0};
2259 uint32_t pipe_fuses = read_pipe_fuses(ctx);
2260 uint32_t num_pipes = 0;
2261
2262 if (!(pipe_fuses == 0 || pipe_fuses == 0x3e)) {
2263 BREAK_TO_DEBUGGER();
2264 dm_error("DC: Unexpected fuse recipe for navi2x !\n");
2265 /* fault to single pipe */
2266 pipe_fuses = 0x3e;
2267 }
2268
2269 DC_FP_START();
2270
2271 ctx->dc_bios->regs = &bios_regs;
2272
2273 pool->base.res_cap = &res_cap_dcn3;
2274
2275 pool->base.funcs = &dcn30_res_pool_funcs;
2276
2277 /*************************************************
2278 * Resource + asic cap harcoding *
2279 *************************************************/
2280 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
2281 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
2282 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
2283 dc->caps.max_downscale_ratio = 600;
2284 dc->caps.i2c_speed_in_khz = 100;
2285 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/
2286 dc->caps.max_cursor_size = 256;
2287 dc->caps.min_horizontal_blanking_period = 80;
2288 dc->caps.dmdata_alloc_size = 2048;
2289 dc->caps.mall_size_per_mem_channel = 8;
2290 /* total size = mall per channel * num channels * 1024 * 1024 */
2291 dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576;
2292 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
2293
2294 dc->caps.max_slave_planes = 2;
2295 dc->caps.max_slave_yuv_planes = 2;
2296 dc->caps.max_slave_rgb_planes = 2;
2297 dc->caps.post_blend_color_processing = true;
2298 dc->caps.force_dp_tps4_for_cp2520 = true;
2299 dc->caps.extended_aux_timeout_support = true;
2300 dc->caps.dmcub_support = true;
2301
2302 /* Color pipeline capabilities */
2303 dc->caps.color.dpp.dcn_arch = 1;
2304 dc->caps.color.dpp.input_lut_shared = 0;
2305 dc->caps.color.dpp.icsc = 1;
2306 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
2307 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
2308 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
2309 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
2310 dc->caps.color.dpp.dgam_rom_caps.pq = 1;
2311 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
2312 dc->caps.color.dpp.post_csc = 1;
2313 dc->caps.color.dpp.gamma_corr = 1;
2314 dc->caps.color.dpp.dgam_rom_for_yuv = 0;
2315
2316 dc->caps.color.dpp.hw_3d_lut = 1;
2317 dc->caps.color.dpp.ogam_ram = 1;
2318 // no OGAM ROM on DCN3
2319 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
2320 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
2321 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
2322 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
2323 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
2324 dc->caps.color.dpp.ocsc = 0;
2325
2326 dc->caps.color.mpc.gamut_remap = 1;
2327 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //3
2328 dc->caps.color.mpc.ogam_ram = 1;
2329 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
2330 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
2331 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
2332 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
2333 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
2334 dc->caps.color.mpc.ocsc = 1;
2335
2336 dc->caps.dp_hdmi21_pcon_support = true;
2337 dc->caps.max_v_total = (1 << 15) - 1;
2338
2339 /* read VBIOS LTTPR caps */
2340 {
2341 if (ctx->dc_bios->funcs->get_lttpr_caps) {
2342 enum bp_result bp_query_result;
2343 uint8_t is_vbios_lttpr_enable = 0;
2344
2345 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
2346 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
2347 }
2348
2349 if (ctx->dc_bios->funcs->get_lttpr_interop) {
2350 enum bp_result bp_query_result;
2351 uint8_t is_vbios_interop_enabled = 0;
2352
2353 bp_query_result = ctx->dc_bios->funcs->get_lttpr_interop(ctx->dc_bios,
2354 &is_vbios_interop_enabled);
2355 dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled;
2356 }
2357 }
2358
2359 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
2360 dc->debug = debug_defaults_drv;
2361
2362 // Init the vm_helper
2363 if (dc->vm_helper)
2364 vm_helper_init(vm_helper: dc->vm_helper, num_vmid: 16);
2365
2366 /*************************************************
2367 * Create resources *
2368 *************************************************/
2369
2370 /* Clock Sources for Pixel Clock*/
2371 pool->base.clock_sources[DCN30_CLK_SRC_PLL0] =
2372 dcn30_clock_source_create(ctx, bios: ctx->dc_bios,
2373 id: CLOCK_SOURCE_COMBO_PHY_PLL0,
2374 regs: &clk_src_regs[0], dp_clk_src: false);
2375 pool->base.clock_sources[DCN30_CLK_SRC_PLL1] =
2376 dcn30_clock_source_create(ctx, bios: ctx->dc_bios,
2377 id: CLOCK_SOURCE_COMBO_PHY_PLL1,
2378 regs: &clk_src_regs[1], dp_clk_src: false);
2379 pool->base.clock_sources[DCN30_CLK_SRC_PLL2] =
2380 dcn30_clock_source_create(ctx, bios: ctx->dc_bios,
2381 id: CLOCK_SOURCE_COMBO_PHY_PLL2,
2382 regs: &clk_src_regs[2], dp_clk_src: false);
2383 pool->base.clock_sources[DCN30_CLK_SRC_PLL3] =
2384 dcn30_clock_source_create(ctx, bios: ctx->dc_bios,
2385 id: CLOCK_SOURCE_COMBO_PHY_PLL3,
2386 regs: &clk_src_regs[3], dp_clk_src: false);
2387 pool->base.clock_sources[DCN30_CLK_SRC_PLL4] =
2388 dcn30_clock_source_create(ctx, bios: ctx->dc_bios,
2389 id: CLOCK_SOURCE_COMBO_PHY_PLL4,
2390 regs: &clk_src_regs[4], dp_clk_src: false);
2391 pool->base.clock_sources[DCN30_CLK_SRC_PLL5] =
2392 dcn30_clock_source_create(ctx, bios: ctx->dc_bios,
2393 id: CLOCK_SOURCE_COMBO_PHY_PLL5,
2394 regs: &clk_src_regs[5], dp_clk_src: false);
2395
2396 pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL;
2397
2398 /* todo: not reuse phy_pll registers */
2399 pool->base.dp_clock_source =
2400 dcn30_clock_source_create(ctx, bios: ctx->dc_bios,
2401 id: CLOCK_SOURCE_ID_DP_DTO,
2402 regs: &clk_src_regs[0], dp_clk_src: true);
2403
2404 for (i = 0; i < pool->base.clk_src_count; i++) {
2405 if (pool->base.clock_sources[i] == NULL) {
2406 dm_error("DC: failed to create clock sources!\n");
2407 BREAK_TO_DEBUGGER();
2408 goto create_fail;
2409 }
2410 }
2411
2412 /* DCCG */
2413 pool->base.dccg = dccg30_create(ctx, regs: &dccg_regs, dccg_shift: &dccg_shift, dccg_mask: &dccg_mask);
2414 if (pool->base.dccg == NULL) {
2415 dm_error("DC: failed to create dccg!\n");
2416 BREAK_TO_DEBUGGER();
2417 goto create_fail;
2418 }
2419
2420 /* PP Lib and SMU interfaces */
2421 init_soc_bounding_box(dc, pool);
2422
2423 num_pipes = dcn3_0_ip.max_num_dpp;
2424
2425 for (i = 0; i < dcn3_0_ip.max_num_dpp; i++)
2426 if (pipe_fuses & 1 << i)
2427 num_pipes--;
2428
2429 dcn3_0_ip.max_num_dpp = num_pipes;
2430 dcn3_0_ip.max_num_otg = num_pipes;
2431
2432 dml_init_instance(lib: &dc->dml, soc_bb: &dcn3_0_soc, ip_params: &dcn3_0_ip, project: DML_PROJECT_DCN30);
2433
2434 /* IRQ */
2435 init_data.ctx = dc->ctx;
2436 pool->base.irqs = dal_irq_service_dcn30_create(init_data: &init_data);
2437 if (!pool->base.irqs)
2438 goto create_fail;
2439
2440 /* HUBBUB */
2441 pool->base.hubbub = dcn30_hubbub_create(ctx);
2442 if (pool->base.hubbub == NULL) {
2443 BREAK_TO_DEBUGGER();
2444 dm_error("DC: failed to create hubbub!\n");
2445 goto create_fail;
2446 }
2447
2448 /* HUBPs, DPPs, OPPs and TGs */
2449 for (i = 0; i < pool->base.pipe_count; i++) {
2450 pool->base.hubps[i] = dcn30_hubp_create(ctx, inst: i);
2451 if (pool->base.hubps[i] == NULL) {
2452 BREAK_TO_DEBUGGER();
2453 dm_error(
2454 "DC: failed to create hubps!\n");
2455 goto create_fail;
2456 }
2457
2458 pool->base.dpps[i] = dcn30_dpp_create(ctx, inst: i);
2459 if (pool->base.dpps[i] == NULL) {
2460 BREAK_TO_DEBUGGER();
2461 dm_error(
2462 "DC: failed to create dpps!\n");
2463 goto create_fail;
2464 }
2465 }
2466
2467 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
2468 pool->base.opps[i] = dcn30_opp_create(ctx, inst: i);
2469 if (pool->base.opps[i] == NULL) {
2470 BREAK_TO_DEBUGGER();
2471 dm_error(
2472 "DC: failed to create output pixel processor!\n");
2473 goto create_fail;
2474 }
2475 }
2476
2477 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2478 pool->base.timing_generators[i] = dcn30_timing_generator_create(
2479 ctx, instance: i);
2480 if (pool->base.timing_generators[i] == NULL) {
2481 BREAK_TO_DEBUGGER();
2482 dm_error("DC: failed to create tg!\n");
2483 goto create_fail;
2484 }
2485 }
2486 pool->base.timing_generator_count = i;
2487 /* PSR */
2488 pool->base.psr = dmub_psr_create(ctx);
2489
2490 if (pool->base.psr == NULL) {
2491 dm_error("DC: failed to create PSR obj!\n");
2492 BREAK_TO_DEBUGGER();
2493 goto create_fail;
2494 }
2495
2496 /* ABM */
2497 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2498 pool->base.multiple_abms[i] = dmub_abm_create(ctx,
2499 regs: &abm_regs[i],
2500 abm_shift: &abm_shift,
2501 abm_mask: &abm_mask);
2502 if (pool->base.multiple_abms[i] == NULL) {
2503 dm_error("DC: failed to create abm for pipe %d!\n", i);
2504 BREAK_TO_DEBUGGER();
2505 goto create_fail;
2506 }
2507 }
2508 /* MPC and DSC */
2509 pool->base.mpc = dcn30_mpc_create(ctx, num_mpcc: pool->base.mpcc_count, num_rmu: pool->base.res_cap->num_mpc_3dlut);
2510 if (pool->base.mpc == NULL) {
2511 BREAK_TO_DEBUGGER();
2512 dm_error("DC: failed to create mpc!\n");
2513 goto create_fail;
2514 }
2515
2516 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2517 pool->base.dscs[i] = dcn30_dsc_create(ctx, inst: i);
2518 if (pool->base.dscs[i] == NULL) {
2519 BREAK_TO_DEBUGGER();
2520 dm_error("DC: failed to create display stream compressor %d!\n", i);
2521 goto create_fail;
2522 }
2523 }
2524
2525 /* DWB and MMHUBBUB */
2526 if (!dcn30_dwbc_create(ctx, pool: &pool->base)) {
2527 BREAK_TO_DEBUGGER();
2528 dm_error("DC: failed to create dwbc!\n");
2529 goto create_fail;
2530 }
2531
2532 if (!dcn30_mmhubbub_create(ctx, pool: &pool->base)) {
2533 BREAK_TO_DEBUGGER();
2534 dm_error("DC: failed to create mcif_wb!\n");
2535 goto create_fail;
2536 }
2537
2538 /* AUX and I2C */
2539 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2540 pool->base.engines[i] = dcn30_aux_engine_create(ctx, inst: i);
2541 if (pool->base.engines[i] == NULL) {
2542 BREAK_TO_DEBUGGER();
2543 dm_error(
2544 "DC:failed to create aux engine!!\n");
2545 goto create_fail;
2546 }
2547 pool->base.hw_i2cs[i] = dcn30_i2c_hw_create(ctx, inst: i);
2548 if (pool->base.hw_i2cs[i] == NULL) {
2549 BREAK_TO_DEBUGGER();
2550 dm_error(
2551 "DC:failed to create hw i2c!!\n");
2552 goto create_fail;
2553 }
2554 pool->base.sw_i2cs[i] = NULL;
2555 }
2556
2557 /* Audio, Stream Encoders including DIG and virtual, MPC 3D LUTs */
2558 if (!resource_construct(num_virtual_links, dc, pool: &pool->base,
2559 create_funcs: &res_create_funcs))
2560 goto create_fail;
2561
2562 /* HW Sequencer and Plane caps */
2563 dcn30_hw_sequencer_construct(dc);
2564
2565 dc->caps.max_planes = pool->base.pipe_count;
2566
2567 for (i = 0; i < dc->caps.max_planes; ++i)
2568 dc->caps.planes[i] = plane_cap;
2569
2570 dc->cap_funcs = cap_funcs;
2571
2572 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
2573 ddc_init_data.ctx = dc->ctx;
2574 ddc_init_data.link = NULL;
2575 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
2576 ddc_init_data.id.enum_id = 0;
2577 ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
2578 pool->base.oem_device = dc->link_srv->create_ddc_service(&ddc_init_data);
2579 } else {
2580 pool->base.oem_device = NULL;
2581 }
2582
2583 DC_FP_END();
2584
2585 return true;
2586
2587create_fail:
2588
2589 DC_FP_END();
2590 dcn30_resource_destruct(pool);
2591
2592 return false;
2593}
2594
2595struct resource_pool *dcn30_create_resource_pool(
2596 const struct dc_init_data *init_data,
2597 struct dc *dc)
2598{
2599 struct dcn30_resource_pool *pool =
2600 kzalloc(size: sizeof(struct dcn30_resource_pool), GFP_KERNEL);
2601
2602 if (!pool)
2603 return NULL;
2604
2605 if (dcn30_resource_construct(num_virtual_links: init_data->num_virtual_links, dc, pool))
2606 return &pool->base;
2607
2608 BREAK_TO_DEBUGGER();
2609 kfree(objp: pool);
2610 return NULL;
2611}
2612

source code of linux/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c